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A novel high resolution delay locked loop

University of British Columbia

With the rapid advances in semiconductor technology, modern digital systems operated at GHz frequency have been successfully developed for many years. As the chip size gets progressively bigger, and the number of logic gates and chip operating frequencies increase, the clock skew becomes increasingly more important in ensuring the proper functioning of VLSI chips. With a synchronous methodology, it is impossible to increase the clock speed further without reducing the clock skew on the chip. The Phase Locked Loops (PLLs) and Delay Locked Loops (DLLs) have been widely adopted to solve the clock skew problem. In recent years, Delay Locked Loops (DLL's) have been widely used for clock alignment due to their lower phase-error accumulation and faster locking time. In this thesis a novel high resolution DLL with less than 10 ps is proposed which combines the coarse and fine delay line into an efficient hybrid delay line. Consequently, it saves power and area.

Text

2009-12-15

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http://hdl.handle.net/2429/16709

Electrical and Computer Engineering

University of British Columbia

UBCV

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