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Product-term based synthesizable embedded programmable logic cores

University of British Columbia

As integrated circuits become increasingly complex, the ability to make post-fabrication changes will become more important and attractive. This ability can be realized using programmable logic cores. Currently, such cores are available from vendors in the form of "hard" macro layouts. Previous work has suggested an alternative approach: vendors supply a synthesizable version of their programmable logic core and the integrated circuit designer synthesizes the programmable logic fabric using standard cells. Although this technique suffers increased delay, area, and power, the task of integrating such cores is far easier than the task of integrating "hard" cores into an ASIC or SoC. When implementing small amount of logic, this case of use may be more important than the increased overhead. This thesis presents a new family of architectures for these "synthesizable" cores; unlike previous architectures which were based on lookup-tables, the new family of architectures is based on a collection of product-term arrays. Compared to lookup-table based architectures, the new architectures result in density improvements of 35% and speed improvements of 72% on standard benchmark circuits. In addition, we describe novel architectural designs to enhance synthesizable architectures to support sequential logic. We show that directly embedding flipflops as is done in stand-alone programmable cores will not suffice. Consequently, we present two novel architectures employing our solution and optimize and compare them. Finally, we describe a proof-of-concept chip employing one of our proposed architectures.

Text

2009-12-11

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http://hdl.handle.net/2429/16574

Electrical and Computer Engineering

University of British Columbia

UBCV

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