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Detailed routing architectures for embedded programmable IP cores Hallschmid, Peter

Abstract

As the complexity of integrated circuits increases, the ability to make postfabrication changes to fixed ASIC chips will become increasingly attractive. This ability can be realized using programmable logic cores. These cores are blocks of programmable logic that can be embedded into a fixed-function ASIC or a custom chip. Such cores differ from stand-alone FPGAs in that they can take on a variety of shapes and sizes. With this in mind, we investigate the detailed routing characteristics of rectangular programmable logic cores. We quantify the effects of having different X and Y channel capacities, and show that the optimum ratio between the X and Y channel widths for a rectangular core is between 1.2 and 1.5. We also present a new switch block family optimized for rectangular cores. Further, we quantify the effects of logic block pin placement. Comparing to a simple extension of an existing switch block, our new architecture leads to a density improvement of up to 11.9%. Finally, we show that if the channel width, switch block, and pin placement are chosen carefully then the penalty for using a rectangular core (compared to a square core with the same logic capacity) is small; for a core with an aspect ratio of 2:1, the area penalty is 1.6% and the speed penalty is 3.8%.

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