UBC Theses and Dissertations

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UBC Theses and Dissertations

A parallel algorithm for ASN.1 encoding/decoding Joseph, Carlton Charles Agnel


Computers differ in many ways: the characters may be coded in ASCII, EBCDIC or UNICODE; integers can vary in size; processors can operate in Big-Endian or Little-Endian format; and programming languages can use different memory representations for data. The International Standards Organization (ISO) provides an Open System Interconnection (OSI) seven-layer reference model[20] to facilitate heterogeneous inter-computer communication. Multimedia technology places new demands on inter-computer communication speeds because of the higher bandwidth requirements of voice and image data. Various implementations of high speed networks meet this demand at the lower layers. The presentation layer of the ISO reference model is the dominant component of the total protocol processing time[5].Hence, the presentation layer represents a bottleneck in communication systems that use high speeds networks. The presentation layer is traditionally implemented in software but now a combined parallel hardware/software approach is taken. Prior to this thesis, VASN.1[3][24][25] was the only parallel hardware/software combination that achieved high throughput in the presentation layer. The parallel algorithm ofVASN.1 limits the scalablity of hardware and hence the achievable parallelism. VASN.1users are expected to use the parallel data structure¹ that it uses. This limitation reduces the flexibility for VASN.1 users and incurs an additional overhead for handling the data structure. The parallel system presented in this thesis avoids the serious problems found in VASN.1.A new parallel algorithm has been developed which provides users with flexible serial datastructures². The encoding algorithm converts flexible serial data structures into parallel information which allow simultaneous processing. The conversion from a serial to a parallel information has not been previously explored in the literature. The decoding algorithm also provides maximum parallelism while providing a flexible serial data structure for applications to use. The algorithm has been designed in such a way that any changes in the ASN.1 specification can be easily incorporated into the system. The final advantage is that the hardware scales gracefully and allows for more parallelism than VASN.1. The initial simulations are promising and show that the throughput achievable by the parallel algorithm is five times greater than that achievable by a serial implementation. ¹A parallel data structure is a data structure that contains extra information required for a parallel algorithm. ²A serial data structure is a data structure that holds no extra information required for a parallel algorithm.

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