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Design and VLSI implementation of a convolutional encoder and majority logic decoder for forward error correction in intrabuilding power line communications

University of British Columbia

The need for simple and effective forward error correction (FEC) schemes for use in modern low-cost communication systems continues, especially for intrabuilding power line (IPL) communications. In particular, the use of short random error correcting convolutional codes with a moderate degree of interleaving has been shown to be a viable FEC option that enhances the performance of communications over the power line channel. In this thesis, a VLSI convolutional encoder and threshold decoder (codec) chip for use in intrabuilding power line communications was successfully designed, fabricated and tested. The chip implements the rate 1/2 (2, 1, 6) self-orthogonal convolutional code together with programmable degrees of interleaving = 1, 3, 5, 7). This code provides random and burst error correcting capabilities. Threshold or majority—logic decoding was selected as the algorithm to be used, due to the ease of its implementation and its appropriateness for burst error channels. Interleaving and deinterleaving can easily be included in the encoder and decoder, respectively. The codec is a semi-custom design that uses standard library cells, and was fabri cated using 1.2 1tm CMOS technology. A maximum throughput of 50 Mbps is feasible. Built-In Self-Test was incorporated into the design providing 100% single stuck-at fault coverage, with under 10% of silicon area overhead. To evaluate the effectiveness of the VLSI codec, the chip was integrated onto two existing power line modems. Performance tests were completed for coded and uncoded data transmissions under conditions of varying channel quality. This study successfully demonstrates that the use of this FEC chip is effective in increasing the error—free throughput of intrabuilding power line communications. The chip provides the possibility of maintaining reliable communications over channels that could otherwise not be used for data communications at 19.2 Kbps.

Thesis/Dissertation

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2009-02-20

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http://hdl.handle.net/2429/4879

Electrical and Computer Engineering

University of British Columbia

UBCV

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