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FPGA routing structures : a novel switch block and depopulated interconnect matrix architectures Masud, Muhammad Imran

Abstract

Field-Programmable Gate Arrays (FPGAs) are integrated circuits which can be programmed to implement virtually any digital circuit. This programmability provides a low-risk, low-turnaround time option for implementing digital circuits. This programmability comes at a cost, however. Typically, circuits implemented on FPGAs are three times as slow and have only one tenth the density of circuits implemented using more conventional techniques. Much of this area and speed penalty is due to the programmable routing structures contained in the FPGA. By optimizing these routing structures, significant performance and density improvements are possible. In this thesis, we focus on the optimization of two of these routing structures. First, we focus on a switch block, which is a programmable switch connecting fixed routing tracks. A typical FPGA contains several hundred switch blocks; thus optimization of these blocks is very important. We present a novel switch block that, when used in a realistic FPGA architecture, is more efficient than all previously proposed switch blocks. Through experiments, we show that the new switch block results in up to 13% fewer transistors in the routing fabric compared to the best previous switch block architectures, with virtually no effect on the speed of the FPGA. Second, we focus on the logic block Interconnect Matrix, which is a programmable switch connecting logic elements. We show that we can create smaller, faster Interconnect Matrix by removing switches from the matrix. We also show, however, that removing switches in this way places additional constraints on the other FPGA routing structures. Through experiments, we show that, after compensating for the reduced flexibility of the Interconnect Matrix, the overall effect on the FPGA density and speed is negligible.

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