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Testing for floating gates defects in CMOS circuits

University of British Columbia

This thesis studies the detectability of MOS floating gate transistor faults considering classical Static Voltage, Dynamic Voltage and Static Current testing strategies. The behavior of the defect depends on two classes of parameters: the predictable and unpredictable parameters. A floating gate fault can induce abnormal logic values, additional delays, or increased power supply current. Consequently, classical test strategies can only detect floating gate faults for a given range of the unpredictable parameter. Here, a new test scheme is proposed, which allows a considerable current to flow in the faulty logic gate in stable state, making the circuit with a floating gate IDDQ testable. It is shown that a combination of voltage and current testing can ensure complete detection of the floating gate defects, i.e., regardless of the unpredictable parameters. Analysis with increasing initial charge on the floating gate transistor shows how the detectability intervals become smaller for the voltage testing strategies and increase for the static current strategy. Keywords: Floating gate testing, IDDQ testing, gate opens, floating gate defect model.

Thesis/Dissertation

application/pdf

2009-05-26

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http://hdl.handle.net/2429/8227

Electrical and Computer Engineering

University of British Columbia

UBCV

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