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Built-in jitter test schemes for mixed-signal integrated circuits Dalmia, Kamal
Abstract
Recent years have seen an unparalleled growth in the speed and complexity of VLSI circuits. Analog and mixed-signal circuits are going through a resurgence and continue to pose new challenges to VLSI test engineers. The state-of-the-art in the mixed-signal and analog test domain is to use application-specific test methodologies to tackle individual problems. The same is true for testing the high-speed clock signals used in present day integrated circuits (ICs) for their analog attributes. Jitter is one of the ways of quantifying the accuracy of a clock signal. Present day digital automatic test equipment (ATE) does not possess enough resolution to be suitable for jitter tests of high-speed clock signals such as SONET's (Synchronous Optical Network) 155.52 MHz and 622.08 MHz. In this thesis, the jitter test problem of high-speed clocks is approached with a built-in self-test (BIST) perspective. A BIST scheme is presented for the jitter tolerance test of clock and data recovery units typically found in data transceiver ICs. A cost-effective scheme based on the utilization of existing components for test purposes is presented. Some possible variations of the presented scheme are discussed. A second BIST scheme, focused on jitter testing of clock signals in a sampling-based digital signal processing (DSP) environment, is presented. Again, the focus is on the re-use of typically existing blocks on such ICs.
Item Metadata
Title |
Built-in jitter test schemes for mixed-signal integrated circuits
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Creator | |
Publisher |
University of British Columbia
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Date Issued |
1996
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Description |
Recent years have seen an unparalleled growth in the speed and complexity of VLSI
circuits. Analog and mixed-signal circuits are going through a resurgence and continue
to pose new challenges to VLSI test engineers. The state-of-the-art in the mixed-signal
and analog test domain is to use application-specific test methodologies to tackle individual
problems. The same is true for testing the high-speed clock signals used in present day
integrated circuits (ICs) for their analog attributes. Jitter is one of the ways of quantifying
the accuracy of a clock signal. Present day digital automatic test equipment (ATE) does
not possess enough resolution to be suitable for jitter tests of high-speed clock signals such
as SONET's (Synchronous Optical Network) 155.52 MHz and 622.08 MHz. In this thesis,
the jitter test problem of high-speed clocks is approached with a built-in self-test (BIST)
perspective. A BIST scheme is presented for the jitter tolerance test of clock and data
recovery units typically found in data transceiver ICs. A cost-effective scheme based on the
utilization of existing components for test purposes is presented. Some possible variations
of the presented scheme are discussed. A second BIST scheme, focused on jitter testing of
clock signals in a sampling-based digital signal processing (DSP) environment, is presented.
Again, the focus is on the re-use of typically existing blocks on such ICs.
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Extent |
3955212 bytes
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Genre | |
Type | |
File Format |
application/pdf
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Language |
eng
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Date Available |
2009-04-30
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Provider |
Vancouver : University of British Columbia Library
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Rights |
For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use.
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DOI |
10.14288/1.0065081
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URI | |
Degree | |
Program | |
Affiliation | |
Degree Grantor |
University of British Columbia
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Graduation Date |
1996-05
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Campus | |
Scholarly Level |
Graduate
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Aggregated Source Repository |
DSpace
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Item Media
Item Citations and Data
Rights
For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use.