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UBC Theses and Dissertations

The Multi-Sampling Digital Tanlock Loop for tracking suppressed-carrier M-ary PSK signals Bisson, Joël A.


A Multi-Sampling Digital Tanlock Loop (MDTL) is proposed for tracking suppressed-carrier M-ary Phase-Shift Keyed signals. Unlike the conventional Digital Phase-Locked Loop (DPLL) which possesses a sinusoidal phase characteristic, the MDTL has a linear phase characteristic with a period of 2π/M. Consequently, the MDTL can be characterized by a linear difference equation which eliminates the approximations of nonlinearity seen in the conventional DPLL. The linear difference equation also provides many attractive features over the conventional DPLL. These include locking conditions which are insensitive to variations in signal power, enhanced noise immunity, wider lock range and reduced steady-state mean phase error for the first order loop when the received signal has a frequency offset. A first-order MDTL is analyzed in the noiseless case. Closed-form expressions were derived for the steady-state mean phase error, the region of stability, the lock range and the acquisition time. It is shown that the use of multi-sampling improves the performance of the MDTL over the conventional Digital Tanlock Loop by increasing the region of stability and consequently, the lock range, and by decreasing the steady-state mean phase error and the acquisition time. In the presence of noise, the task of modelling the MDTL is partitioned into a software testbed and a hardware testbed. Both the software and hardware testbed simulate the MDTL in the presence of noise. The hardware testbed, however, also includes other important impairments such as quantization effects and loop delay. The software testbed represents the reference model against which the hardware testbed can be compared and measured. The phase error, the acquisition time and the hold-in time are the three performance measures used to characterize the performance of the MDTL in the presence of noise. It is shown that multi-sampling can be used as an acquisition aid without increasing the standard deviation of the phase error distribution. For binary phase-shift keying, four bits of sampler quantization and 64 levels of numerically-controlled oscillator resolution are needed to provide negligible performance degradation compared to the infinite quantization case at a received signal-to-noise ratio of zero dB. The MDTL design is simple. Digital implementation of the MDTL provides an opportunity for enhanced system integration using Very Large Scale Integration techniques for high speed applications or Digital Signal Processing microprocessor techniques for slower speed applications.

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