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Efficient self-timed interfaces for crossing clock domains Chakraborty, Ajanta

Abstract

With increasing integration densities, large chip designs are commonly partitioned into multiple clock domains. While the computation within each individual domain may be synchronous, the interfaces between these domains often use asynchronous methods. One such approach is the STARI technique[Gre93, Gre95] where a self-timed FIFO compensates for clock-skew between the sender and receiver. This dissertation presents implementations of STARI where the FIFO consists of a single, handshaking stage. I start with the simplest case where the sender and receiver operate at exactly the same frequency with an unknown skew. I then generalize this design for links with clocks whose frequencies are rational multiples of each other, clocks whose frequencies are closely matched, and arbitrary clocks. In each of these cases, the STARI interface can exploit the stability of typical clocks to achieve low latencies and negligible probabilities of synchronization failure using very simple hardware. I have designed and tested a proof-of-concept chip fabricated with the TSMC 0.18μ CMOS process for the scenario where clocks of different domains are exactly matched in frequency. The tests have demonstrated our claims about the skew tolerance of the design and I am now in the process of designing the interface for further generalizations.

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