UBC Theses and Dissertations

UBC Theses Logo

UBC Theses and Dissertations

Automatic formal verification for scheduled VLIW code Feng, Xiushan

Abstract

VLIW processors are attractive for many embedded applications, but VLIW code scheduling, whether by hand or by compiler, is extremely challenging. In this paper, I extend previous work on automated verification of low-level software to handle the complexity of modern, aggressive VLIW designs, e.g., the exposed parallelism, pipelining, and resource constraints. I implement these ideas into two prototype tools for verifying short sequences of assembly code for TI's C62x family of VLIW DSPs and Fujitsu's FR500 VLIW processor, and demonstrate the effectiveness of the tools in quickly verifying, or finding bugs in, several difficult-to-analyze code segments.

Item Media

Item Citations and Data

Rights

For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use.

Usage Statistics