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An automatic layout generator for integrated circuit design

University of British Columbia

In integrated circuit design, one of the most tedious and time-consuming steps is the generation of the layout. During the last decade, considerable effort has been invested in the development of CAD tools dedicated to the automation of this step. This effort has been largely motivated by a need for alternatives to manual layout to greatly reduce the development time and cost. This thesis describes my contribution through the implementation of a flexible and automatic integrated circuit layout generator. With this tool, the designer only needs to depict the circuit at a high level, while the tool works out the details of the design and produces the final layout. In comparison with most of the current layout synthesis tools, my tool aims to realize the generality while still preserving most of the efficiency of the hand design, and facilitate greater reuse. The solution is based on constraint solving. The tool is written in Java. Two architectural styles are followed in the whole design, call-and-return and object-oriented. Experimental results demonstrate the effectiveness of the tool in generating layouts comparable to manual designs, with very quick turn-around time and no manual intervention.

Thesis/Dissertation

application/pdf

2009-08-06

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http://hdl.handle.net/2429/11828

Computer Science

University of British Columbia

UBCV

DSpace