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Abstract

As the number of devices on a silicon photonic (SiP) chip increases, SiP compact models, generated from simulations, need to be dependable, trustworthy, and quickly generated for circuit-level design. Codified SiP design recipes, inspired by principles in software development, aim to capture device design processes and build compact models in a maintainable, trustworthy, extensible, and modular fashion. These recipes enable recalling results, if available, by looking up results related to their recipe setup, thereby skipping numerous simulations and reducing redundant data. We demonstrate SiP design recipes for tapers and PN junction microring modulators (MRM) using Python, GDSFactory, and Lumerical. The recipes include convergence sweeps to ensure simulation settings and results are accurate. The SiP taper recipe aims to generate an optimal geometrical taper shape and length that reduces routing loss on chip. For a C-band taper targeting the fundamental TE mode and tapering from 0.5 𝝻m to 3 𝝻m width on a 220 nm Si core, SiO₂ and air clad process, the sinusoidal taper is the best taper geometry in simulations and experiments. The sinusoidal taper experimentally achieves 1.4 mdB insertion loss at a device length of 40 𝝻m. We demonstrate SiP design recipes for PN junction MRMs, showcasing electro-optic characteristics extracted from the flow including charge profile, optical free spectral range, optical extinction ratio, and MRM quality factor. The PN junction MRM recipe is applied to a neuromorphic photonic weightbank circuit to extract fabrication process parameters and tolerance. The PN junction MRM recipe extracts the waveguide width variation and dopant concentrations in a fabrication process that is not well reported. By developing codified SiP design recipes, these recipes enable rapid development of SiP devices for applications in data communication, sensing, quantum computing, and more. The recipes can be applied toward forward design processes where experimental data is unavailable or reverse design processes to extract fabrication process parameters. These design recipes signify an important advancement toward more robust and high-performance SiP circuit design.