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Mishra, Amit Kumar

University of British Columbia

The phenomenon of injection locking and phase interpolation find widespread applications in electronic systems. In this dissertation, these phenomena are utilized to provide solutions to some critical challenges for power amplifiers, ring oscillators, and phase interpolators through circuit techniques. Firstly, injection locking (IL) in switching power amplifiers (PAs) is studied. Traditionally, injection-locked PAs (ILPAs) have supported phase modulation, and the IL primarily contributes to improving the power-added efficiency (PAE) by reducing the ILPA driving power. In this dissertation, by scaling both the switching PA and the locked power oscillator, improvement in both the PAE and drain efficiency of an ILPA is achieved while also attaining amplitude modulation. The presented ILPA, implemented in 65 nm CMOS process, achieves a peak drain efficiency of 42.7% and PAE of 40% at the highest output power of 23 dBm at 2.5 GHz in measurements. Secondly, IL is used to generate multiple phases using a multi-path ring oscillator with high phase accuracy, required for sampling clocks in a serial link receiver. A waveform balanced technique is proposed and implemented for the multi-path ring oscillators to prevent phase errors due to differential signal injection. The method ensures signal symmetry at all oscillator nodes during injection, thereby improving the phase accuracy to < 1.5° in the oscillator outputs at 7 GHz operation in the 65 nm CMOS process. Thirdly, phase interpolation techniques are explored to obtain high resolution and high phase linearity for the large operating frequencies. An integrating-mode phase interpolator (IMPI) architecture is proposed and implemented, where the voltage slopes with high phase linearity are generated through the integration of phase-shifted weighted current sources. This phase interpolator (PI) technique supports high-speed and low-power operation and achieves dual-edge interpolation with improved duty-cycle distortion characteristics. Two IMPI designs, in the 65 nm CMOS and the 5 nm finFET process, are implemented to provide proof of concept. The 5 nm PI achieves 9 bits of resolution and a peak-to-peak integral nonlinearity (INLₚₚ) and peak-to-peak differential nonlinearity (DNLₚₚ) of 2.4° and 1.4°, respectively, at 13.3 GHz with quadrature clock inputs in measurements.

Text

2025-01-31

Attribution-NonCommercial-NoDerivatives 4.0 International

http://hdl.handle.net/2429/83424

Electrical and Computer Engineering

University of British Columbia

UBCV

http://creativecommons.org/licenses/by-nc-nd/4.0/