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Hardware implementation of a multicarrier faster-than-Nyquist decoder Saeidi, Mehdi
Abstract
Efficient utilization of time and frequency resources in communication networks is crucial to meet the demands of the fast growing global internet traffic. The concept of packing data more densely in time and frequency via so-called Fasterthan- Nyquist (FTN) transmission, originally proposed in the 1970’s, has therefore regained popularity. This faster, more bandwidth-efficient transmission of data results in interference between symbols adjacent in time and frequency, which must be mitigated in the receiver. Hence, computational complexity of FTN receivers is generally higher than for non-FTN receivers and constitutes a bottleneck for practical adoption. Although there have been significant advances in algorithm design for reducing the computational complexity of state-of-the-art FTN decoders, research on efficient hardware acceleration has only been sporadic. In particular, hardware implementations of different components that constitute the FTN decoder have been investigated in isolation. As a result, the only hardware FTN decoder proposed to date utilizes the hardware resources extremely inefficiently (its hardware utilization is on the order of 54.1%). In this thesis, we offer algorithmic and architectural insights for efficient implementation of complete FTN decoder systems. We identify convergence properties and parallelism opportunities unique to how the computational blocks operate and communicate with each other when combined in an FTN decoder, and describe how to leverage the insights for speed and area-efficiency. Our proof-of-concept field-programmable gate-array (FPGA) implementation reduces memory and logic footprints to within 26% and 4% of an idealized FTN hardware decoder, and achieves a throughput of 1.46 Gbps.
Item Metadata
Title |
Hardware implementation of a multicarrier faster-than-Nyquist decoder
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Creator | |
Supervisor | |
Publisher |
University of British Columbia
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Date Issued |
2022
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Description |
Efficient utilization of time and frequency resources in communication networks
is crucial to meet the demands of the fast growing global internet traffic. The
concept of packing data more densely in time and frequency via so-called Fasterthan-
Nyquist (FTN) transmission, originally proposed in the 1970’s, has therefore
regained popularity. This faster, more bandwidth-efficient transmission of data
results in interference between symbols adjacent in time and frequency, which must
be mitigated in the receiver. Hence, computational complexity of FTN receivers is
generally higher than for non-FTN receivers and constitutes a bottleneck for practical
adoption.
Although there have been significant advances in algorithm design for reducing
the computational complexity of state-of-the-art FTN decoders, research on efficient
hardware acceleration has only been sporadic. In particular, hardware implementations
of different components that constitute the FTN decoder have been investigated
in isolation. As a result, the only hardware FTN decoder proposed to date utilizes
the hardware resources extremely inefficiently (its hardware utilization is on the
order of 54.1%).
In this thesis, we offer algorithmic and architectural insights for efficient implementation
of complete FTN decoder systems. We identify convergence properties
and parallelism opportunities unique to how the computational blocks operate and
communicate with each other when combined in an FTN decoder, and describe
how to leverage the insights for speed and area-efficiency. Our proof-of-concept
field-programmable gate-array (FPGA) implementation reduces memory and logic
footprints to within 26% and 4% of an idealized FTN hardware decoder, and achieves
a throughput of 1.46 Gbps.
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Genre | |
Type | |
Language |
eng
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Date Available |
2022-11-21
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Provider |
Vancouver : University of British Columbia Library
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Rights |
Attribution-NonCommercial-NoDerivatives 4.0 International
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DOI |
10.14288/1.0422011
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URI | |
Degree | |
Program | |
Affiliation | |
Degree Grantor |
University of British Columbia
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Graduation Date |
2023-05
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Campus | |
Scholarly Level |
Graduate
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Rights URI | |
Aggregated Source Repository |
DSpace
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Rights
Attribution-NonCommercial-NoDerivatives 4.0 International