UBC Theses and Dissertations

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UBC Theses and Dissertations

Circuit generation for machine learning-enhanced field programmable gate array architecture exploration Roorda, Esther


Recent years have seen an explosion of machine learning applications implemented on Field-Programmable Gate Arrays (FPGAs). FPGA vendors and researchers have responded by updating and optimizing their fabrics to more efficiently implement machine learning accelerators, including innovations such as enhanced Digital Signal Processing (DSP) blocks and hardened systolic arrays. Evaluating these architectural proposals is difficult however due to the lack of publicly available benchmark circuits. This thesis presents an open-source benchmark circuit generator that maps DNN layers onto a proposed FPGA architecture to generate circuits that are appropriate for use in FPGA architecture studies. Our circuits are constructed based on a set of nested loops that is characteristic of DNN and other machine learning applications, but differ in the size, shape and unrolling factors for various loops. Unlike previous generators, which create circuits that are agnostic of the underlying FPGA fabric, our circuits contain explicit instantiations of embedded computation blocks, allowing for meaningful comparison of recent architectural proposals without the need for a complete inference computer-aided design (CAD) flow. Our circuits are compatible with the VTR experimental CAD suite, allowing for architecture studies that investigate routing congestion, impact on place and route, and other low-level architectural implications. The framework also contains two levels of simulation support allowing for validation of the generated circuits. Our benchmark circuit generator is demonstrated through three case studies which show how realistic benchmark circuits can be generated to target actual different embedded blocks. We use these benchmark circuits to examine how FPGA architecture decisions affect DNN accelerator performance, and how different types of DNN have different performance bottlenecks.

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Attribution 4.0 International