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UBC Theses and Dissertations

Design exploration of faster than Nyquist equalizer system Matar, Mohamed

Abstract

Improving the spectral efficiency is a key challenge to meet the increasing demand for higher capacity over communication channels. Faster than Nyquist (FTN) signaling (first proposed in 1970s) has recently regained popularity due to its ability to improve signal’s spectral efficiency. FTN can achieve a symbol rate faster than Nyquist rate; therefore, it has been widely investigated in high-capacity wireless and optical communications. FTN signaling comes at the cost of intersymbol interference (ISI), which requires complex decoder at the receiver to recover the received symbol from ISI noise. This decoder is a bottleneck of the system throughput since it is on the critical path of receiving a noise free signal. Several decoders have been proposed in the literature to mitigate the ISI noise, however, these systems require a significant computational complexity to equalize the received frames. In this thesis, we propose a hardware architecture that implement an FTN decoder system. This system consists of a Maximum A-posteriori (MAP) equalizer and low-density parity (LDPC) decoder that work together iteratively to mitigate ISI noise and channel noise. The MAP equalizer is mainly responsible for equalizing ISI noise, while the LDPC decoder uses parity checks to remove random channel noise. We study the design trade-offs for each block, evaluate it separately, and propose a high-throughput hardware architecture for the FTN decoder system. We evaluate this architecture on Xilinx UltraScale+ (xcvu13p) device. Our MAP equalizer achieves a throughput up to 602 Mbps per processing element (PE). We also design an LDPC decoder that achieves a throughput of up to 520 Mbps per PE. The FTN decoder architecture achieves a throughput of up to 2.16 Gbps.

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Attribution-NonCommercial-NoDerivatives 4.0 International

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