UBC Theses and Dissertations
An FPGA overlay architecture supporting software-like compile times during on-chip debug of high-level synthesis designs Jamal, Al-Shahna
High-Level Synthesis (HLS) promises improved designer productivity by allowing designers to create digital circuits targeting Field-Programmable Gate Arrays (FPGAs) using a software program. Widespread adoption of HLS tools is limited by the lack of an on-chip debug ecosystem that bridges the software to the generated hardware, and that addresses the challenge of long FPGA compile times. Recent work has presented an in-system debug framework that provides a software-like debug experience by allowing the designer to debug in the context of the original source code. However, like commercial on-chip debug tools, any modification to the on-chip debug instrumentation requires a system recompile that can take several hours or even days, severely limiting debug productivity. This work proposes a flexible debug overlay family that provides software-like debug turn-around times for HLS generated circuits (on the order of hundreds of milliseconds). This overlay is added to the design at compile time, and at debug time can be configured many times to implement specific debug scenarios without a recompilation. We propose two sets of debug capabilities, and their required architectural and CAD support. The first set form a passive overlay, the purpose of which is to provide observability into the underlying circuit and not change it. In this category, the cheapest overlay variant allows selective variable tracing with only a 1.7\% increase in area overhead from the baseline debug instrumentation, while the deluxe variant offers 2x-7x improvement in trace buffer memory utilization with conditional buffer freeze support. The second set of capabilities is control-based, where the overlay is leveraged to make rapid functional changes to the design. Supported functional changes include applying small deviations in the control flow of the circuit, or the ability to override signal assignments to perform efficient "what if'" tests. Our overlay is specifically optimized for designs created using an HLS flow; by taking advantage of information from the HLS tool, the overhead of the overlay can be kept low. Additionally, all the proposed capabilities require the designer to only interact with their original source code.
Item Citations and Data
Attribution-NoDerivatives 4.0 International