UBC Theses and Dissertations
Design and analysis of supply-noise-insensitive all-digital phase-locked loops Yuan, Chen
Phase-locked loops (PLLs) are widely used in communication and digital systems to generate high frequency clocks by multiplying a low-frequency reference clock. Scaling of complementary metal-oxide-semiconductor (CMOS) technology over the last decade has benefitted digital circuits by shrinking their size and reducing their power consumption. On the other hand, it has posed challenges for analog design because of the decreasing power supply voltage and output impedance of transistors. Therefore, an all-digital PLL (ADPLL) becomes increasingly preferable over its conventional analog counterparts in terms of area and design flexibility. PLLs employ an oscillator locked to the phase and frequency of the reference clock. An LC oscillator utilizes an inductor (L) to filter noise, but on-chip inductors require large area and need specific thick metal layers for low loss. Compared to LC oscillators, ring oscillators are more suitable for ADPLL implementation since they occupy smaller area and are compatible to digital CMOS processes without a thick-metal layer option. However, the oscillation frequency of a ring oscillator is determined by the propagation delay of the delay-cells, and thereby very susceptible to power supply noise. In fully-integrated systems, switching of large-scale digital circuits can create large supply ripples and degrade the noise performance of the PLL output. Low dropout (LDO) regulators as well as some cancellation techniques have been adopted in prior-art to mitigate the supply sensitivity of ring-oscillator based ADPLLs. However, these techniques suffer from supply voltage headroom, noise penalty, and design complexity. In this thesis, a low-complexity supply-noise-insensitive ADPLL is proposed that does not degrade the supply voltage headroom, and operates over a wide range of supply-noise amplitude. Fabricated in a 65nm CMOS process, the ADPLL achieves ~ 45 mV of tunable supply-noise-insensitive range where the frequency pushing is less than 10%, operating at 850 mV supply. With the tuning range from 1 GHz to 1.4 GHz, the ADPLL achieves 16 ps integrated jitter at 1.25 GHz output frequency and consumes 2.73 mW of power.
Item Citations and Data
Attribution-NonCommercial-NoDerivatives 4.0 International