UBC Theses and Dissertations
Analysis and design of analog interface circuits for capacitive detector readout systems Beikahmadi, Mohammad
Advances in sub-micron complimentary metal-oxide semiconductor (CMOS) technologies have enabled implementation of ultra-low-power circuits and systems for variety of applications including readout systems for capacitive radiation detectors. As state-of-the-art readout systems may integrate thousands of electronic channels on chip, designing low-power and low-noise interface circuits is of great interest. The focus of this work is on developing a design methodology for such readout circuits with an emphasis on interfacing with capacitive sensors, in general, and solid-state radiation detectors, in particular. The critical aspects of the design from analyzing the specifications to noise optimization and circuit design are taken into account and the proposed circuits offer improved performance for the readout system. To facilitate the noise analysis of modern readout systems, the equivalent noise charge equations of the system are derived analytically. The analysis takes into account the stringent requirements of modern readout systems as well as the noise sources associated with deep submicron CMOS technologies. The analysis is based on the EKV (Enz, Krummenacher, and Vittoz) model of MOS transistors which is a model valid for all regions of operation. As a proof of concept, the analysis and design of three low-power and low-noise interface circuits are presented. The proposed circuits are fabricated in a 0.13 um CMOS process. The first interface circuit consists of a novel charge-sensitive amplifier (CSA), a pole-zero cancellation (PZC) circuit, and a 2nd-order programmable pulse shaper. The proposed CSA accepts signals of both polarities, exhibits 111 e-rms noise, and consumes only 37.5 uW. The second interface circuit consists of a CSA, a reset network, a 1st-order shaper, and a PZC circuit. The circuit consumes about 1 mW and exhibits 66 to 101 e-rms noise at different peaking times. The third interface circuit is a mixed-signal design and consists of a CSA with leakage compensation, a 5th-order programmable Gaussian shaper, a peak-detect and hold, a discriminator, and a novel Wilkinson-based digitizer. The circuit consumes 1.97 mW and exhibits 58 e-rms noise. The design performs favourably in terms of power consumption and noise behavior in comparison with similar works in the literature.
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