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Towards high-level leakage power reduction techniques for FPGAs

University of British Columbia

A field-programmable gate array (FPGA) is an integrated circuit (IC) which can be configured to implement any digital circuit. The speed and power-efficiency of an FPGA is better than general-purpose-processors (GPPs) and the flexibility, time-to-market, and low-volume costs of an FPGA are better than application-specific-integrated circuits (ASICs). As FPGAs are implemented using more advanced programming technologies, power, specifically leakage power, has become a first-class concern for many FPGA applications. Towards that end, the work in this thesis proposes software optimizations inside a high-level computer-aided-design (CAD) tool chain and a modeling technique that increases the effectiveness and accessibility of low-power architectural features, such as Dynamic Power Gating and Dynamic Partial Reconfiguration, in reducing the overall static leakage power in an FPGA. Three research contributions are presented. The first contribution is a high-level synthesis (HLS) based design methodology that targets an FPGA with dynamic power gating support. The proposed methodology automatically finds the coarse-grained (accelerator-level) power gating opportunities in a design expressed in C language and exploits the power-gating feature of the FPGA to minimize the static power dissipation. The second contribution demonstrates the impact of performing power gating at a finer granularity in which individual sub-accelerators within a parent accelerator are power-gated. Results reveal that for some applications, this finer granularity results in more effective power gating, thus providing more static power savings than just turning off the whole accelerator. Finally, the third contribution presents a model which aids in designing an FPGA-based dynamic partial reconfigurable system in which parts of the FPGA's functionality can be modified at run-time. The time-multiplexing of chip resources enables the use of a smaller FPGA device that helps in lowering the static power dissipation. A modeling approach is proposed that predicts the performance trends and bottlenecks in a reconfigurable datapath, without implementing the system on an FPGA device. This early prediction increases the ability to effectively explore the design space and experiment with various system parameters in less time.

Text

2015-07-16

Attribution-NonCommercial-NoDerivs 2.5 Canada

http://hdl.handle.net/2429/54082

Electrical Engineering

University of British Columbia

UBCO

http://creativecommons.org/licenses/by-nc-nd/2.5/ca/