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High speed and energy efficient hardware architectures for LTE-advanced systems

University of British Columbia

The explosive growth of internet traffic, fueled by an ever increasing availability of mobile wireless devices and demands of end users to be always connected, provides a challenge for cellular and broadband wireless access technologies. In this thesis, we present novel approaches of physical layer architectures Orthogonal Wavelet Division Multiple Access (OWDMA) & Fast Inverse Square Root based Matrix Inverse (FISRMI) that is shown to substantially improve bit error rate (BER), increase data rate, accommodating more number of users, low power consumption and cover dead zones effectively. The work presented in this thesis consists of basically two parts which provides solutions to different problems in the Long Term Evolution (LTE) networks. In LTE-Advanced (LTE-A), heterogeneous networks (HetNet) concept using centralized coordinated multipoint (CoMP) transmitting Radio resources over optical fibers LTE-A Radio-Over-Fiber (ROF) has provided a feasible way of satisfying user demands. A OWDMA processor architecture is proposed and evaluated. To validate the architecture, circuit is designed and synthesized on a Xilinx vertex-6 Field Programmable Gate Array (FPGA). We compare our architecture with similar available architectures for resource utilization & timing and provide performance comparison with OFDMA for different quality metrics of communication systems. The OWDMA architecture is found to perform better than OFDMA for BER performance versus signal to noise ratio (SNR) in ROF media. It also gives higher throughput and mitigates the bad effect of Peak to Average Power ratio (PAPR) and Inter carrier interference (ICI). Secondly, a low complexity and high speed matrix inversion algorithm FISRMI using fast inverse square root based on QR-decomposition and systolic array was designed. Matrix operations are costliest computational module within multiple input multiple output (MIMO)-LTE receivers. The capital expenditure (CAPEX) is reduced by implementing a 4x4 matrix inverse in Xilinx Virtex-6 FPGA by optimizing the module for speed and power by pipelining. The results are compared with state of art techniques of Coordinate Rotation Digital Computer (CORDIC) based algorithms and the various Minimum Mean Squared Error channel matrices of size 4x4 and 8x8 are inverted at different bit precision on a BER plot.

Text

2013-10-24

Attribution-NonCommercial-NoDerivatives 4.0 International

http://hdl.handle.net/2429/45376

Electrical and Computer Engineering

University of British Columbia

UBCV

http://creativecommons.org/licenses/by-nc-nd/4.0/