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On the use of body biasing to improve the performance of CMOS RF front-end building blocks Rashtian, Hooman


Body biasing is commonly used in digital and low-power analog integrated circuits to adjust the threshold voltage of complementary metal-oxide-semiconductor (CMOS) transistors and to lower the supply voltage. In this work, the application of body biasing to improve the performance of four of the main building blocks of CMOS radio-frequency (RF) front-ends is explored. Here, the body-biasing technique is used in conjunction with other design techniques and provides an extra degree of freedom in the design of CMOS RF front-end building blocks including low-noise amplifiers (LNAs), active down-conversion mixers, voltage-controlled oscillators (VCOs), and power amplifiers (PAs). The performance improvements are mainly related to noise and linearity of these building blocks and have been achieved through adjusting the values of the bulk-source transconductance, the source-bulk capacitance, and the threshold voltage of the MOS transistors. Body biasing is applied in multi-stage LNAs to improve their noise figure and linearity as well as to adjust the gain. Body biasing is used to improve the linearity of active down-conversion mixers with gradual LO switching by enhancing the linearity of the LO stage. Body biasing is used in cross-coupled LC VCOs to improve their phase noise performance by forward body biasing of core transistors which lowers the duty cycle in class-C mode of operation. In active-inductor-based LC VCOs, body biasing is used to increase the tuning range of active inductors and thus the oscillation frequency. Finally, body biasing is in the predistortion stage of class-AB PAs to improve the linearity by compensating for the voltage-dependent nonlinear gate-source capacitance of the input transistor of the PA. In all cases, these improvements are achieved with minimal overhead on circuit-level complexity and power consumption of the overall system. The proposed applications of body-biasing technique are validated through measurements on different proof-of-concept prototypes fabricated in 0.13-µm, 90-nm, and 65-nm CMOS technologies.

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