UBC Theses and Dissertations
A study of two wideband CMOS LC-VCO structures Yu, Ge
Phase-locked loops (PLLs) are widely used in telecommunication, radio, and computer applications. This thesis focuses on the study of wide-band PLLs, as they are a critical building block of many wireless and wireline systems. In particular, wide tuning range, low phase noise, and low power are desirable attributes for multi-standard and multi-band communication systems. One of the most critical components in a PLL is the voltage-controlled oscillator (VCO). In this work, two techniques for implementing a wide-tuning-range LC-VCO are presented. As a proof of concept, the techniques are used to design and layout two 13-GHz LC-VCOs, which are fabricated in a 90-nm CMOS technology and successfully tested. One design (Design A) uses two VCO cores and has an extra source-follower buffer while the other (Design B) uses one VCO core with a bank of switched capacitors. The 90-nm CMOS prototypes operate from a supply of 1.2 V. The Design A prototype has a 28.20% tuning range and a phase noise of ‒90.98 dBc/Hz at 1 MHz offset from the carrier, while the Design B prototype has a 24.42% tuning range and a phase noise of ‒94.20 dBc/Hz at 1 MHz offset. This measured performance is comparable with state-of-the-art wide-tuning-range VCOs. The total chip size, excluding pads, is 0.335 × 0.750 mm² and 0.316 × 0.425 mm² for Designs A and B, respectively. It was found that the addition of the source-follower buffer allows the VCO to function at a higher frequency, while the presence of the switched capacitor tends to deteriorate phase noise.
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