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Design and analysis of active and passive decoupling capacitors for on-chip power supply noise management Meng, Xiongfei

Abstract

On-chip decoupling capacitors (decaps) in the form of MOS transistors are widely used to reduce power supply noise in both standard-cell blocks and white spaces between blocks. This research provides guidelines for layouts of decaps that properly tradeoff high-frequency response, electrostatic discharge (ESD) reliability and gate tunneling leakage for use within standard-cell blocks in ASIC designs in 90nm and 65nm CMOS technologies. A simple but effective metric is developed to determine the optimal decap layout based on the frequency response. Novel active designs are also presented. If an JR-drop violation (hot spot) is found after the physical design is completed, it is usually difficult to implement a quick fix to the problem. In this dissertation, the use of an active decap in white-space areas as a drop-in replacement for passive decaps is investigated to provide noise reduction for these “hot-spot” problems found late in the design process. A modified active decap design is proposed for ASIC applications operating up to 1GHz, and the use of latch-based comparators provides a better power-delay trade-off. Measurement results from a test chip show that the noise reduction using active decaps improves as operating frequency increases, and provides between 10%-20% noise reduction at 200MHz-1GHz over its passive counterpart. The concept of active decap is further extended to achieve lower supply noise. It is found that an active decap with a stack height of three (i.e., number of pieces switching) provides the best noise reduction if the supply noise level is between 7%-14%, but a stack height of two is best if the noise level is between 14%-16%. In addition, a novel charge-borrowing decap circuit is introduced which outperforms all forms of active decaps for a fixed area in terms of removing local hot spots.

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Attribution-NonCommercial-NoDerivatives 4.0 International

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