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Practical considerations for post-silicon debug using backspace Gort, Marcel
Abstract
With the ever-increasing complexity of integrated circuits, the elimination of all design errors before fabrication is becoming more difficult. This increases the need to find design errors in chips after fabrication. This task, termed post-silicon debug, can be made easier if it is possible to obtain a trace of states that leads to a known state. BackSpace, a proposal for a new debug infrastructure which provides such a trace has been recently presented. BackSpace combines formal analysis with on-chip instrumentation. In this thesis, we show that BackSpace can be made practical by modifying the architecture and debug flow to address the area overhead, and also by addressing on-chip realities such as non-determinism and signal propagation delay. Additionally, this thesis describes a proof-of-concept implementation of a complex processor instrumented with the debug architecture and shows that BackSpace can produce traces hundreds of cycles long. Our results indicate that the area overhead of the breakpoint circuit, a main component of the debug architecture, can be reduced to 5% for our prototype, while still allowing the debug flow to create state-accurate traces.
Item Metadata
Title |
Practical considerations for post-silicon debug using backspace
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Creator | |
Publisher |
University of British Columbia
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Date Issued |
2009
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Description |
With the ever-increasing complexity of integrated circuits, the elimination of all design errors before fabrication is becoming more difficult. This increases the need to find design errors in chips after fabrication. This task, termed post-silicon debug, can be made easier if it is possible to obtain a trace of states that leads to a known state. BackSpace, a proposal for a new debug infrastructure which provides such a trace has been recently presented. BackSpace combines formal analysis with on-chip instrumentation. In this thesis, we show that BackSpace can be made practical by modifying the architecture and debug flow to address the area overhead, and also by addressing on-chip realities such as non-determinism and signal propagation delay. Additionally, this thesis describes a proof-of-concept implementation of a complex processor instrumented with the debug architecture and shows that BackSpace can produce traces hundreds of cycles long. Our results indicate that the area overhead of the breakpoint circuit, a main component of the debug architecture, can be reduced to 5% for our prototype, while still allowing the debug flow to create state-accurate traces.
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Extent |
695351 bytes
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Genre | |
Type | |
File Format |
application/pdf
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Language |
eng
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Date Available |
2009-08-26
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Provider |
Vancouver : University of British Columbia Library
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Rights |
Attribution-NonCommercial-NoDerivatives 4.0 International
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DOI |
10.14288/1.0067636
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URI | |
Degree | |
Program | |
Affiliation | |
Degree Grantor |
University of British Columbia
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Graduation Date |
2009-11
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Campus | |
Scholarly Level |
Graduate
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Rights URI | |
Aggregated Source Repository |
DSpace
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Item Media
Item Citations and Data
Rights
Attribution-NonCommercial-NoDerivatives 4.0 International