Applied Science, Faculty of
Electrical and Computer Engineering, Department of
DSpace
UBCV
Duan, Yingran
2009-06-16T19:26:36Z
1999
Master of Applied Science - MASc
University of British Columbia
With the advance of microprocessors/DSP, digital control is increasingly used in
various applications of switchmode power converter systems because of its advantages
over analog control. The disadvantages, however, include limited signal resolution due to
finite word length of processor and A/D converter; sampling time delay and limited computation
power and control loop bandwidth. Adequate performance is difficult to realize
by the current digital controllers with cost consideration. In order to achieve a good system
performance, digital controller design becomes an important issue. Many digital
design methods are available right now, and using different design methods results in different
digital control performance. Choosing a better digital control design approach or
method to improve the performance of the digital controlled power converter system is
currently under consideration in this thesis.
Digital controllers with different design methods are designed for a power inverter.
A thorough and systematic evaluation on these methods is provided by comparing the performance
of the digital controlled system. The performance of each approach is compared
in terms of both the bandwidth and the phase margin of the control loop as well as the performance
at nonlinear load condition. Furthermore, the difference of these design
approaches under different sampling rates is studied. The best digital design approach for
power converter system applications is identified based on the comparison results. Such a
result is useful since, the control sampling rate can be several times lower than the converter
switching frequency due to the limited computation power of low-cost processors.
A modified direct digital design method is proposed for practicing engineers who
are mostly familiar with the continuous domain design approach. Some other issues
related to digital control design for switchmode power converter system, including digital
controller implementation and delay modelling are discussed as well.
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Digital Control Loop Design for Power Converter Systems by Yingran Duan B.A.Sc, The Shanghai Jiao Tong University, 1993 A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS OR THE DEGREE OF MASTER OF APPLIED SCIENCE TN ELECTRICAL ENGINEERING in THE FACULTY OF GRADUATE STUDIES (Department of Electrical and Computer Engineering) We accept this thesis as conforming to the required standar/i| THE UNIVERSITY OF BRITISH COLUMBIA June 1999 © Yingran Duan, 1999 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department of b-befo-i t*J fi^^xd^^ The University of British Columbia Vancouver, Canada Date DE-6 (2/88) Abstract With the advance of microprocessors/DSP, digital control is increasingly used in various applications of switchmode power converter systems because of its advantages over analog control. The disadvantages, however, include limited signal resolution due to finite word length of processor and A/D converter; sampling time delay and limited com-putation power and control loop bandwidth. Adequate performance is difficult to realize by the current digital controllers with cost consideration. In order to achieve a good sys-tem performance, digital controller design becomes an important issue. Many digital design methods are available right now, and using different design methods results in dif-ferent digital control performance. Choosing a better digital control design approach or method to improve the performance of the digital controlled power converter system is currently under consideration in this thesis. Digital controllers with different design methods are designed for a power inverter. A thorough and systematic evaluation on these methods is provided by comparing the per-formance of the digital controlled system. The performance of each approach is compared in terms of both the bandwidth and the phase margin of the control loop as well as the per-formance at nonlinear load condition. Furthermore, the difference of these design approaches under different sampling rates is studied. The best digital design approach for power converter system applications is identified based on the comparison results. Such a result is useful since, the control sampling rate can be several times lower than the con-verter switching frequency due to the limited computation power of low-cost processors. ii A modified direct digital design method is proposed for practicing engineers who are mostly familiar with the continuous domain design approach. Some other issues related to digital control design for switchmode power converter system, including digital controller implementation and delay modelling are discussed as well. iii Table of Contents Abstract ii Table of Contents iv List of Figures vi List of Tables viii Acknowledgements ix 1. Introduction 1 1.1 Background 1 1.2 Digital Controller Designs 3 1.3 Thesis Objective and Outline 5 2. Digital Design Approaches 7 2.1 Introduction 7 2.2 Modeling of the Digital Control Time Delay 7 2.3 Digital Redesign Approach 9 2.3.1 Backward Euler Method 11 2.3.2 Bilinear Method 14 2.3.3 Pole/Zero Match Method 17 2.3.4 Step Invariant Method 19 2.4 Direct Digital Design Approach 21 2.4.1 Frequency Response Method 22 2.4.2 Root Locus Method 24 2.4.3 Deadbeat Control Method 25 2.4.4 Modified Direct Digital Design Method 27 2.5 Summary 31 3. Digital Controller Design for Single-Phase Power Inverter Systems 32 3.1 Introduction 32 3.2 Switchmode Power Inverter 32 3.3 Controllers Based on Digital Redesign Methods 35 3.4 Controllers Based on the Modified Direct Digital Design Method 37 3.5 Summary 41 4. Implementation of the Digital Controllers 43 4.1 Introduction 43 4.2 Hardware Design 44 4.2.1 Power Stage 45 4.2.2 Current and Voltage Sensors 45 4.2.3 DSP Evaluation Board 48 4.2.4 PWM Generator 50 4.3 Software Design 51 4.3.1 Numeric Representation and Calculation 51 4.3.2 Program Structure 53 4.4 Summary 55 5. Simulation and Experiment Results 56 5.1 Introduction 56 5.2 System Bandwidth Comparison 57 iv 5.3 Nonlinear Load Performance 75 5.4 Modeling of the digital controller delay 77 5.5 Summary 79 6. Conclusions 81 Bibliography 83 Appendix A: Schematic of the DSP Controlled Power Inverter System 87 Appendix B: Controller Software of the DSP 90 V List of Figures Fig. 1.1 A switchmode power converter system diagram 1 Fig. 1.2 Delay of the digital controller in switchmode power converter systems 3 Fig. 2.1 Bode plot of HZOH(s), Hc(s) and Hdelay(s), assuming Tc = Ts 9 Fig. 2.2 Block diagram of (a) an analog system; (b) an analog system with time delay 10 Fig. 2.3 Mapping of Backward Euler transformation between s-plane and z-plane 11 Fig. 2.4 Comparison of the amplitude and phase angle difference in the continuous and discrete domain for G(s)= - using the Backward Euler transformation 12 s Fig. 2.5 A digital controlled single-loop system 13 Fig. 2.6 Mapping of Bilinear transformation between s-plane and z-plane 15 Fig. 2.7 Comparison of the amplitude and phase angle difference in the continuous and discrete domain for G(s)= - using the Bilinear transformation 16 Fig. 2.8 Comparison of the amplitude and phase angle difference in the continuous and discrete domain for G(s)= - using the Step Invariant transformation 20 s Fig. 2.9 Discrete control system diagram 21 Fig. 2.10 Relationship between co and v 23 Fig. 2.11 Loci of constant damping ratio C and constant natural frequency a>„ of a second-order system 25 Fig. 2.12 Discrete step response of the close-loop system using the frequency response method 29 Fig. 2.13 Root locus plot of the digital control system designed by the root locus method 30 Fig. 2.14 Discrete step response of the digital control system designed by the root locus method 31 Fig. 3.1 Circuit diagram of a power inverter system 33 Fig. 3.2 Double-loop analog PI controlled power inverter system 34 Fig. 3.3 Double-loop digital controlled power inverter system 35 Fig. 3.4 Double-loop control system diagram for digital redesign approach 36 Fig. 3.5 Double-loop control system diagram for the direct digital design approach 38 Fig. 3.6 Discrete step response of the output voltage of the double-loop system by the frequency response method 40 Fig. 3.7 Root locus plot of (a) the current loop and (b) the voltage loop with the root locus method 42 Fig. 3.8 Discrete step response of the output voltage of the double-loop system by the root locus method 42 Fig. 4.1 Simplified schematic diagram of the inverter system 44 Fig. 4.2 Inductance current sensing circuit 47 Fig. 4.3 Output voltage sensing circuit 47 Fig. 4.4 Simplified block diagram of the F240 DSP 49 Fig. 4.5 PWM generation in DSP 50 Fig. 4.6 Time diagram of one sampling period 52 Fig. 4.7 Flowchart of the main program 53 Fig. 4.8 Flowchart of the interrupt service routine 54 Fig. 5.1 Double-loop digitally controlled system diagram 58 Fig. 5.2 Test circuit for system loop bandwidth measurement 59 vi Fig. 5.3 Current and voltage loop bandwidth measurement points 59 Fig. 5.4 Simulated Current loop Bode plot at the sampling rate of 10 kHz 60 Fig. 5.5 Simulated voltage loop Bode plot at the sampling rate of 10 kHz 61 Fig. 5.6 Current loop Bode plot provided by the system analyzer at the sampling rate of 10 kHz 62 Fig. 5.7 Voltage loop Bode plot provided by the system analyzer at the sampling rate of 10 kHz 63 Fig. 5.8 Current loop Bode plot provided by the system analyzer at the sampling rate of 20 kHz 67 Fig. 5.9 Voltage loop Bode plot provided by the system analyzer at the sampling rate of 20 kHz 68 Fig. 5.10 Simulated current loop Bode plot at the sampling rate of 40 kHz 72 Fig. 5.11 Simulated voltage loop Bode plot at the sampling rate of 40 kHz 73 Fig. 5.12 Nonlinear load for the inverter system 75 Fig. 5.13 Experimental nonlinear load output waveform 76 Fig. 5.14 Brief schematic of the power inverter model 78 vii List of Tables Table 3.1. Digital controllers for current and voltage loops using different redesign methods at 20 kHz sampling rate 37 Table 4.1. Features of the TMS320F240 DSP 48 Table 5.1. Current and voltage controllers with different methods at 10 kHz sampling rate 59 Table 5.2. Simulated current loop bandwidth and phase margin with different digital controllers at 10 kHz sampling rate 64 Table 5.3. Simulated voltage loop bandwidth and phase margin with different digital controllers at 10 kHz sampling rate 65 Table 5.4. Measured current loop bandwidth and phase margin with different digital controllers at 10 kHz sampling rate 65 Table 5.5. Measured voltage loop bandwidth and phase margin with different digital controllers at 10 kHz sampling rate 65 Table 5.6. Current and voltage controllers with different methods at 20 kHz sampling rate 67 Table 5.7. Measured current loop bandwidth and phase margin with different digital controllers at 20 kHz sampling frequency 70 Table 5.8. Measured voltage loop bandwidth and phase margin with different digital controllers at 20 kHz sampling frequency 70 Table 5.9. Simulated current loop bandwidth and phase margin with different digital controllers at 20 kHz sampling frequency 70 Table 5.10. Simulated voltage loop bandwidth and phase margin with different digital controllers at 20 kHz sampling frequency 71 Table 5.11. Current and voltage controllers with different methods at 40 kHz sampling rate 72 Table 5.12. Simulated current loop bandwidth and phase margin with different digital controllers at 40 kHz sampling frequency 72 Table 5.13. Simulated loop voltage bandwidth and phase margin with different digital controllers at 40 kHz sampling frequency 75 Table 5.14. Total Harmonic Distortion comparison of the five design methods for the inverter system with nonlinear load at different sampling rate 77 Table 5.15. Current loop bandwidth and phase margin with different delay models at 20 kHz sampling frequency 80 Table 5.16. Voltage loop bandwidth with different delay models at 20 kHz sampling frequency 80 viii Acknowledgements First, I would like to give special thanks to Professor Hua Jin, my graduate super-visor at the University of British Columbia, who supported me throughout the project. This work would have not been completed without his helpful comments and advice. I also want to express my gratitude to all the students, faculty and staff in the Electrical and Computer Engineering Department of UBC, especially the power electronics group. Many thanks are to Anil Tuladhar, Stephane Bibian and Kenneth Wicks for the helpful discus-sions we had. I wish to acknowledge Statpower Technologies Corporation for providing experiment resources for this project; Mr. Tom Unger and Mr. Rob Cameron for their helps on the system setup. In addition, I would like to thank Dr. Li-Ming Wu who reviewed this manuscript and provided useful comments. Finally, I am grateful to my fam-ily and all my friends who have supported me for all these years. Chapter 1 Introduction 1.1 Background The development of switchmode power converter systems has been in constant demand for high performance power sources with smaller volume and lower cost. A switchmode power converter system normally consists of power source, switches, output filters, sensors and control circuitry. F ig . 1.1 shows the diagram of such a system. In prac-tical design, E M I filters w i l l be included in the input line and output line as well . Power Source o U Switch Network 7^ Output Filter PWM Generator Ti Controller Reference t-1 o &> o. Sensors Fig. 1.1 A switchmode power converter system diagram Traditionally, analog control has been used in the power converter applications. Analog control is inexpensive and reliable, and it has infinite resolution with no control delays. The downside of the analog control, however, is that analog component values can vary with the tolerance, and they can change subject to aging and working environment. Furthermore, it is difficult to implement advanced control techniques and monitoring functions with analog controllers. The design of controllers using microprocessor/DSP is a changing and fast grow-ing subject. It has been introduced to switchmode power converter system applications as well in recent years. Digital control has more flexibility in implementing advanced control algorithms. It can handle multiple functions and add "intelligence" features to the system. The control of the whole system can be implemented using only a few components, which makes the system very easy to handle. In addition, most digital controllers are reprogram-mable, and modifications can be made by changing control programs. The working status is also very stable, and the environment condition has few effects on the performance of the digital controllers. Digital control, however, has a number of disadvantages. The first main disadvan-tage of digital control is the delay introduced to the system by the digital controller. The time delay comes from the fact that, in one sampling period, digital controller obtains input samples, finishes all the computation, and updates the control signal. In power con-verter systems, the control signal remains the same in one sampling period, and is updated at the beginning of the next period. Therefore, the delay of the digital controller is at least one sampling period. Fig. 1.2 shows the introduced delay. The second main disadvantage of digital control is the quantization error. Digital controllers can only deal with numbers in binary form, which must be represented by a binary word composed of a finite number of binary digits or bits. The limited word length in the representations of these numbers, therefore, introduces errors to some degree. Carrier Signal Co"rripu7ation| Finished 1—A/D Update Control Update Control Input to Output Delay Fig. 1.2 Delay of the digital controller in switchmode power converter systems 1.2 Digital Controller Designs Because of the limited control loop performance, it becomes even more important to design the digital controller properly and achieve the best possible performance. The objective of this work, therefore, is to evaluate different digital control design approaches and identify the one that is best suited for power converter applications. Many digital design techniques have been proposed in recent years [8-18]. In gen-eral, all the design methods can be divided into two main approaches: digital redesign approach and direct digital design approach. In the digital redesign approach, the control-ler is designed first in the continuous domain, and discretized into the discrete form. In the direct digital design approach, on the other hand, the system plant in the continuous domain is first transformed into the z-domain, and the controller design is carried out directly in the z-domain. Some efforts have been made in developing new techniques to realize optimal dig-ital redesign from existing analog controllers. In [11], a redesign method is presented based on optimal matching the continuous time close-loop step response of both the ana-log and the discretized system. In [13], an extrapolation integration technique is applied in developing a discrete representation for integration and differentiation that is less depen-dent on the sampling interval. They all require extra calculation to obtain the digital con-troller from the analog one. A good match is accomplished by increasing the order of the digital controller, which also increases the amount of calculation of the digital controller. In direct digital design approach, a modified root locus method is proposed in [16], which uses the sampling period as a parameter in the root locus plot. This method is suit-able only in the systems where the sampling period is a dominant factor of the stability. That is, the gain is set and the variable is the sampling rate in the root locus plot. Another robust controller is designed in [17], by minimizing the deviation of the frequency response of a perturbed plant at selected frequencies. The plant perturbations are gener-ated by uncertainty in the coefficients of the plant transfer function. This method increases the robustness at some frequencies, but may result in decrease of the stability at other fre-quencies. Practical digital controller design, for switchmode power converter system, is required to be simple and effective. Some studies are focused on the traditional digital control design methods. In [1], comparisons on very commonly used digital redesign methods and direct digital methods have been made. In digital redesign methods, the Bilinear method and the Pole/Zero Match method are discussed. It is found that the perfor-mance of the digital controller using the Bilinear transformation method is much closer to the analog controller than that of the Pole/Zero Match method. The root locus method in direct digital designs gives the best step response. The comparison is made only on the transient response of a single-loop system in this work. In [2], the Energy Resemblance Index (ERI) is introduced to compare three discretization methods. This ERI is mainly based on the pulse response difference between the analog system and discrete system. The results show that the Backward Euler method out-performs the Tustin (Bilinear) method, and the performance of the Step Invariant method varies in different systems. Similar comparisons of some other redesign approaches and direct digital approaches are presented in [3-5]. However, there is still a lack of thorough and systematic comparison of these methods. These studies, with the exception of [3], do not provide a quantitative com-parison of the performance in terms of control loop bandwidth, load disturbance rejection among different discretization methods, and between the digital redesign approach and the direct digital approach. All these works, including [3], are focused on the single-loop sys-tem. It is unclear that how the controller performance will vary in a two-loop structure or under different sampling rates. 1.3 Thesis Objective and Outline The objective of this thesis is to identify the best approach for power converter applications among the selected methods, and implement the design in a fixed-point digi-tal controller. Specific objectives include: • To compare various transformation techniques in digital redesign approach. • To compare the direct digital design approach with various digital redesign methods. • To develop a direct digital design method that is effective and easy to use in practical digital control designs. • To evaluate the effect of the sampling rate on the system performance. The thesis is organized as follows. Chapter 2 discusses the digital design approaches in detail. Digital controller design for a double-loop switchmode power inverter is described in Chapter 3. Chapter 4 is focused on the implementation of the digi-tal controlled system. Comparison of different design methods and approaches are pre-sented in Chapter 5, based on the simulation and experimental results. Conclusions and recommendations for future work are given in Chapter 6. Chapter 2 Digital Design Approaches 2.1 Introduction In this chapter, different digital controller design approaches are described. First, the time delay in the digital control loop is studied and the model for the time delay is dis-cussed. Second, digital redesign methods based on different transformations are presented. Finally, direct digital methods and the design procedure are provided. 2.2 Modeling of the Digital Control Time Delay The time lag introduced by the digital controller has to be taken into account dur-ing the controller design stage. In many industrial applications, only the delay due to the zero-order-hold (ZOH) of the A/D converter is considered in a digital control design. Rel-atively little attention has been paid to the effect of the computational delay in the digital controller. The computational delay includes the time needed to finish numerical calcula-tion and for A/D and D/A conversions. In those applications, the system dynamics is not very fast and the computation time is negligible as compared to the sampling period. The effect of a zero-order-hold can be expressed as: ~Tss HZOH^= X-^j— > (2-D 7 where T$ is the sampling period. The computational delay, on the other hand, can be described as: Hc(s)=e'c\ (2.2) where T£ is the computation time. Unlike zero-order-hold, the delay Hc(s) has no effect on the magnitude of the plant but adds large phase lag to the system. The total delay in the digital system is, therefore, -Tss _T Fig. 2.1 shows the Bode plot of HZ0H(s), Hc(s) and Hdeiay(s), assuming T = T . c s In power converter applications, however, computational delay must be included. This is because the computational delay is usually a significant portion of the sampling period. Also, in most of the cases, the new control variable is updated only at the begin-ning of the next period. There are different ways to model the delay. One way is to con-sider that the computational delay equals the sampling period. The delay will be -T s 1 - e s ~Tss • • ~Tss • e . Another way is to consider the total delay to be equal to e . Three s models of this time delay were presented and compared in Chapter V. Results show that g the model of Hdel (s)= e s gives the best results, and this model will be used in the remaining digital control designs in this project. 0.005 0.05 0.5 Frequency (pu), lunit equals £ 0.005 0.05 0.5 Frequency (pu), lunit equals fj Fig. 2.1 Bode plot of HZQH(s) , Hc(s) and Hdelay{s), assuming TQ - Ts 2.3 Digital Redesign Approach The methodology of analog control design has been well developed over the last few decades. By extending it to the digital system, we have the so called digital redesign approach. Digital redesign approach obtains digital controller by discretizing an analog controller. All the available transformation methods are approximate methods. Accuracy of the discretization depends on the sampling frequency. The fidelity and accuracy of the discretized expression are decreased when the sampling rate is reduced. Let the block diagram of an analog system be shown in Fig. 2.2(a), where H(s) is the plant transfer function and G(s) is the analog controller. The procedure to design a digital controller based on the redesign approach can be outlined as follows: (a) Include the time delay Hdelay(s) in the analog system, as shown in Fig. 2.2(b), and design the analog controller G(s) . (b) Discretize the analog controller G(s) into G(z) using one of the discretization methods. (c) Convert G(z) into a difference equation for implementation. Fig. 2.2 Block diagram of (a) an analog system; (b) an analog system with time delay There are several methods to discretize an analog function. In this section, four commonly used methods are discussed: Backward Euler, Bilinear, Pole/Zero Match and Step Invariant. 10 2.3.1 Backward Euler Method The Backward Euler method uses the Backward Euler transformation to discretize the analog control function. In this transformation, all derivatives are replaced by a first dx n^ ^ ft 1 order approximation. That is — = , where x and x , are the current and at 1' last samples, and T is the sampling time. The z-transform expression is: 1-z' 1 s = - J - • (2-4) Fig. 2.3 shows three typical points mapping from the s-plane to the z-plane. We can see the left side of the s-plane is mapping into the 0.5 radian circle with the center at 0.5 in the z-plane. s-plane <=> z-plane Fig. 2.3 Mapping of Backward Euler transformation between s-plane and z-plane This transformation does not preserve the frequency response. The distortion can be seen in the frequency domain by replacing s with /co, and z with e . If we use the integrator G(s)= - as an example, the difference of the frequency response between the s s-domain and z-domain is shown in Fig. 2.4. 0.005 0.05 Frequency (pu), lunit equals f. 0.005 0.05 Frequency (pu), lunit equals f, Fig. 2.4 Comparison of the amplitude and phase angle difference in the continuous and discrete domain for G(s)= - using the Backward Euler transformation s The upper plot shows that the Backward Euler method has relatively higher gain and phase lead than the analog one. When the frequency approaches the Nyquist fre-quency (1/2 sampling frequency), the phase difference can reach up to 90°. Although the Backward Euler method is not a very accurate transformation method because of the mag-nitude and phase difference with the analog counterpart in the high frequency, the higher 12 amplitude will provide a wider bandwidth, and the phase lead will contribute to the increase of the system phase margin. To illustrate the procedure of the digital controller design, a simple single-loop system as shown in Fig. 2.5 is used as an example. Yref, Digital Controller Sample Holder H's) Fig. 2.5 A digital controlled single-loop system The system is based on the inner current loop of the power inverter which will be discussed in Chapter III. The transfer function of the plant is: H's) = 12 1.58e 5+1 1.27e V + 8.48e *s+ 16.3 (2.5) The sample frequency of the digital controller is 20 kHz, and the delay of the dig-ital controller is modeled by one sample T delay. Equation (2.6) is the linear approxima-2 3 x XX tion of the delay function, where e =1 + x + — + — + 2! 3! 1+* has been used. 1 - ' Hdelay^ = e -Se Ss ^ -Se 5s + 2 5e~5s + 2 (2.6) 13 With the delay function included in the system, we can design the analog control-ler using the Bode plot method. Assuming a gain-cross-over frequency of 2.88 kHz and a phase margin 50°, the analog controller, in the PI structure, is obtained as: s 0.8(9.26e s + I) G(s)= — i 1. (2.7) 9.26e s Substituting equation (2.4) into equation (2.7), we have the digital controller using the Backward Euler transformation method as: G(z)= 0-852(z-0.950) z - l In difference equation form, equation (2.8) becomes: u(t) = 0.852e(t)-0.S04e(t-Ts) + u(t-Ts). (2.9) 2.3.2 Bilinear Method The Bilinear method uses the Bilinear transformation to discretize an analog con-troller function. The Bilinear transformation is also called Tustin transformation or trape-zoid integration method. In this transformation, all derivatives are replaced by a first order dx 2 •*"/ ~xi- l approximation: — = — • . The z-transform expression is: dt Ts xi + xi_l 2 1-z"1 Js l+z 14 Fig. 2.6 shows the three typical points mapping from the s-plane to the z-plane. From this, we can see that the left side of the s-plane is mapping into the unit circle in the z-plane. Fig. 2.6 Mapping of Bilinear transformation between s-plane and z-plane This transformation does not preserve the frequency response either. If we use the integrator G(s)= - as an example, the difference of the frequency response between the s s-domain and the z-domain is shown in Fig. 2.7. From the plot, the amplitude of the integration after Bilinear transformation drops to 0 at Nyquist frequency, although the phase plot matches very well to the analog one. The Bilinear transformation is an accurate transformation method at frequency up to 1/5 of the Nyquist frequency. In the high frequency range, since the amplitude drops quickly, the system bandwidth will be limited. 0.005 0.05 Frequency (pu), lunit equals fs 0.005 0.05 Frequency (pu), lunit equals fs 0.5 0.5 Fig. 2.7 Comparison of the amplitude and phase angle difference in the continuous and discrete domain for G(s)= - using the Bilinear transformation S The design procedure of the digital controller is the same as for the Backward Euler method, except that the transformation method is different. Taking the system in Fig. 2.5 as an example, we have the digital controller as: G(z)= Q-830(z-0.947) ? z-1 (2.11) when the analog controller in equation (2.7) and the Bilinear transformation defined in equation (2.10) are used. The difference equation of the controller is then: 16 u(t) = 0.830e(t)-0J86e(t-Ts) + u(t-Ts). (2.12) 2.3.3 Pole/Zero Match Method The Pole/Zero Match method uses the Pole/Zero Match transformation to dis-cretize the analog control function. The Pole/Zero Match transformation maps poles and zeros of the analog function from the s-plane to poles and zeros in the z-plane. Typical transformations are as follows: This transform maps the left side of the s-plane into the unit circle as well, as shown in Fig. 2.6. The Pole/Zero Match method requires the number of poles to equal the number of zeros. If the number of poles of the analog function is larger than the number of zeros, artificial zeros of -1 are added in the digital function. The gain of the z-domain function is different from that of the analog function, using the transformations in (2.13) and (2.14). It should be scaled to be equal to the gain of the analog function. The differ-ence of the frequency response for G(s)= - with this transformation is the same as the s Bilinear method, as shown in Fig. 2.7. The reason for the similarity is that the pole of the integrator is equal to 0, which is a very special case. For a more general case like 1 ~aTs G(s)= ——, Pole/Zero Match represents the pole a as e , while using Bilinear trans-(2.13) <s + a±jb)o(l+2z le ° scos(bTs) + z 2e (2.14) s + a 17 aTs 1 — s - r 2 ~a s formation it becomes , which is a linear approximation of function e s . The aT. 2 difference between them is small when the aT$ is small. But the difference can be signifi-cant when the sampling period T or parameter a is large. Since G(s)= —— is a low-s + a 1 - e~aTs pass filter, a scaling factor of is used to make the gain of the discrete function 2a equal to that of the analog function at lowband. The Bilinear transformation of T G(s)= has a gain of — , which is very close to the gain of the Pole/Zero s + a 2 + aTs Match transformation when sampling period T and parameter a are small. The differ-ence will increase when either Ts or a becomes large. The digital controller discretized from the analog controller, equation (2.7), with Pole/Zero Match method is: G(z)= ° - 8 3 0 ^ - , 0 - 9 4 7 > . (2.15) z-1 The Pole/Zero Match method and the Bilinear method are so similar that the parameters of the digital controllers from these two methods are the same to the third digit of decimal point. 18 2.3.4 Step Invariant Method Step Invariant method uses the Step Invariant transformation to discretize an ana-log controller function. Step Invariant transformation is the Impulse Invariant transforma-tion with addition of an artificial zero-order-hold. The Impulse Invariant approximation is accomplished by making a unit pulse response sequence of the digital function propor-tional to samples of a continuous time pulse response function. The major problem encountered in this transformation is that high frequencies are folded into the desired bandwidth. It maps only the poles of the analog filter to digital filter, as shown in Fig. 2.6. The zeros may remain outside of the unit circle in the z-plane. To solve this basing prob-lem, a low-pass filter should be used in cascade with the analog function. The Step Invari-ant transformation uses a zero-order-hold as the low-pass filter. The transformation is then expressed as: H(z) = Z r -Tss \ 1 6 H(s) v s (2.16) This transformation preserves the step response of the analog function, but the fre-quency response is distorted. The difference of the frequency response for the integrator function G(s)= - in the s-domain and z-domain is shown in Fig. 2.8. s From the Bode plot in Fig. 2.8, we can see that the transformation introduces a large phase lag to the controller, which reaches 90° at the Nyquist frequency. The ampli-tude increases with frequency, similar to the Backward Euler, which compensates the phase lag a bit. 19 The digital controller discretized from the analog controller equation (2.7) with the Step Invariant method is: G ( z ) = 0.808(z-0.946) z - l (2.17) The difference equation of the controller is: u(t) = 0.80Se(t)-0.764e(t-Ts) + u(t-Ts). (2.18) 0.005 0.05 Frequency (pu), lunit equals f. 0.005 0.05 Frequency (pu), lunit equals f, Fig. 2.8 Comparison of the amplitude and phase angle difference in the continuous and discrete domain for G(s)= - using the Step Invariant transformation s 20 2.4 Direct Digital Design Approach Besides the digital redesign approach, the other design approach in digital control is called direct digital design approach. The controlled plant in this approach is repre-sented by a discrete model. A continuous plant H(s) should first be transformed into the discrete domain, as illustrated in Fig. 2.9. H(z) G(z) Lag H's) W Fig. 2.9 Discrete control system diagram The methods of direct digital design assume that the compensation network is in the discrete domain. The functions in z-domain only show the relationship of sample inter-vals, but not the sampling rate. Theoretically, the behavior of the close-loop system is not dependent on the initial choice of the sampling frequencies. This can be contrasted with digital redesign approach, where an increasing of sampling interval changes the dynamics and may lead to destabilization of the close-loop system. Therefore, direct digital design methods are sometimes called exact methods. Obviously, the exactness is valid only in the linear domain and at the sampling points. Saturation of the controller in practical systems and inter-sample behavior, which are not detected by z-transfer analysis, will degrade the performance if a reasonable sampling rate is not chosen. The procedure of the direct digital design approach can be outlined as follows: 21 (a) Discretize the continuous plant into z-domain using Step Invariant transforma-tion. Time delay is included through the transformation. (b) Design a digital controller in the z-domain using one of the direct digital design methods. (c) Convert the digital controller into a difference equation for implementation. There are several direct digital design methods available, and three commonly used methods are discussed in this work. Based on the features of these methods, a modi-fied method is proposed. 2.4.1 Frequency Response Method The frequency response method uses the same technique as the continuous design method in the frequency domain. The same concepts of gain-cross-over frequency and gain/phase margin can still be used. The difference is that the discrete plant transfer func-tion has to be converted to the w-plane by z = * + w , which is in a form of bilinear trans-1 - w formation. It transforms the unit circle in the z-domain to the left-hand-side of the w-plane, which has the similar feature as the s-domain. A practical transformation method was proposed by Whiter Back and Hofmann [32] which scaled the transformation with a 9 factor of T /2, that is, w' = —w. The major benefit is that w'-plane has not only a geo-s metrical resemblance to the s-plane, but the actual quantities are also similar, which is, W approaches s when the sampling period T approaches 0. This property is useful as it helps to reduce the numerical error through the design process and give better insight to 22 the system. Therefore, the w'-plane, also called as w-plane, is normally used in the digital frequency response method. As mentioned in the section 2.3.2, a bilinear transformation distorts the frequency 7l/2Ts tt/Ts co (rad/sec) Fig. 2.10 Relationship between CO and v Therefore, v «co is true only at frequency much lower than the sampling fre-quency. There is a basic difference between the Bode plots of a continuous system and the corresponding system sampled and transformed from the s-plane to the z-plant, and even-tually to the w-plane. The w-plane transfer function usually has the same number of poles as zeros. When the number of poles is higher than that of the zeros, additional zeros are 23 added to make them equal in the w-plane. In transforming G(z) = KzG'(z) to G(w) = KwG'(w) , the value of the gain Kw can be positive or negative. The sign of Kw is determined by the coefficient of G(z) which in turn is a function of T. Conse-quently, the amplitude response of the G(w) can converge to a value totally away from the original G(s) in continuous system. Due to these features, the sampling frequency is required to be much higher than the desired bandwidth to have a satisfactory design. Usually a sampling frequency of 10 times higher than the bandwidth is recommended. 2.4.2 Root Locus Method Root locus is a plot of the roots of the control system characteristic equation as a function of the gain constant. The underlying principle is that the close-loop poles which mainly decide the system characteristics are related to the zeros and poles of the open-loop function and the gain. From the root locus plot, it is easy to find the trend of the close-loop poles when the parameters of the controller are changing. Since the z-plane is the mapping of the s-plane by means of z = e . The fea-tures of the poles and zeros in the s-plane can be applied to the z-plane. Fig. 2.11 is the plot of the z-plane loci of a constant damping ratio £\, and natural frequency cow for a sec-2 2 ond-order system, with the characteristic expression of s + 2t,Gins + a>n. The concept of the damping ratio and natural frequency in discrete system is similar to the analog system. 24 t=0 C=0.2 0=0.4 Real Fig. 2.11 Loci of constant damping ratio L\ and constant natural frequency (&n of a second-order system The root locus method is a direct way of designing the digital controller. However the transient behavior and the frequency response are strongly influenced by the location of the zeros as well. For this reason, the zeros, poles and the gain of the controller need to be selected properly. 2.4.3 Deadbeat Control Method Deadbeat control is a control technique developed for sampled data control sys-tems. The method is based on the formulation of the desired behavior of the plant and gives an algebraic solution for the controller. The output of the system is forced to move to the expected value after a finite number of intervals. To illustrate the concept, the close-loop transfer function of a single-input-single-output system can be expressed as G(z)H(z) 5 where H(z) is the discrete transfer 1 + G(z)H(z) 25 function plant, and G(z) is the digital controller. If the desired close-loop function is K(z), the controller can be obtained by solving the equation G(z) = —— • . It H(z) 1 - K(z) should be noted that, when choosing K(z), unstable zeros or poles in the plant should not be compensated by cancelling the original zeros or poles through placing additional poles or zeros at the same locations. This is because it is unrealizable to locate an unstable com-pensation pole exactly on the right place and to keep it there practically. Any errors can make the system diverge and cause instability. Deadbeat control requires K(z) to be a polynomial in z 1 . For example, if we wish a second-order system to settle to the desired value after two sample intervals, we can set l_K(z) = ( l - z -y , ( z ) (2.19) to obtain a zero steady state error to a step input. We can also set K(z) = Numerator of the plant transfer function • F2(z) (2.20) to avoid cancellation of the zeros of H(z). Function F, (z) and F2(z) are user defined polynomials. In order to realize the deadbeat control after two sample intervals, Fj (z), F2(z) and K(z) can be in the following forms: -2 -1 Fj(z) = C q Z + C j Z +c 2 , (2.21) 26 F2(z) = dQz 2 + dxz 1 + d-•2> (2.22) K(z) = eQz +gjZ + e2z + e3 . (2.23) Using the definition of Fj(z), F2(z) and iC(z), one can solve equation (2.19) and (2.20) for K(z) and D(z). In some cases, the number of equations can be less than the number of parameters. To have a solution for these systems, some of the parameters must be set initially. Iterations with different initial values and digital simulation are needed to obtain the optimum design. The procedure of this method is straightforward, although more calculation is needed during the design stage. However, the final performance of the resulting controller may not work well as expected. There are two main reasons. First, the controller design is heavily dependent on the system transfer function. However, the transfer function, which normally only reflects the main dynamics of the system, can not fully represent the sys-tem. Furthermore, the system dynamics may be subject to change at different working conditions. Another reason is that deadbeat control usually requires a large control signal which in general can not be implemented in real applications. Therefore, the advantage of this control technique is hard to realize in practical applications. 2.4.4 Modified Direct Digital Design Method As discussed previously, the frequency response method needs additional transfor-mation from the z-domain to the w-domain in order to complete the final design. The approximation in the transformation makes it difficult to achieve optimal design. It is nev-27 ertheless a intuitive method and very easy to use. The root locus method is a real direct design method. No further transformation that may introduce inaccuracy is needed. The main disadvantage of this method, however, is that the relationship of the poles and zeros in the z-plane is not directly related to the system performance, and the tuning of parame-ters can be time-consuming. A modified design method is proposed that combines the advantages of the fre-quency response method and the root locus method. The method proceeds as follows: first, an initial design using the frequency response method is obtained, then the root locus and digital simulation are used to fine tune the controller. In this way, a few iterations will be sufficient to achieve a good digital controller design. The following example with the system shown in Fig. 2.5 illustrates the modified design procedure. The discrete transfer function of the plant can be obtained by discretizing the s-domain plant transfer function with time delay. The corresponding digital transfer function is: H(z) = 0.71z-0.51 . (2.24) z 2 - 1.45z + 0.72 The sampling frequency is 20 kHz in this case. There is one sampling period delay between the plant input and output from the difference equation of H(z) ; y(t) = 0.7\e(t-Ts)-0.5\e(t-2Ts)+\A5y(t-Ts)-0.72y(t-2Ts). (2.25) The digital controller design starts with the digital frequency response method. The discrete transfer function H(z) in equation (2.24) is converted to the w-plane: 28 „ , , -0.39w2+1.29e4w + 9.9e7 n ~~ H(w) = — . (2.26) w2 + 7.\8e3w+\.34e 2 z-1 where w = — • has been used. Ts z+1 A digital controller is designed in the w-plane with a control loop bandwidth of 2.8 kHz and a phase margin of 60° : 0.63(1 + 1.41^) G(w) = — . (2.27) 1.41e w The z-plane expression of this controller is: G(z) = Q - 7 5 z ~ ° - 5 2 . (2.28) z-1 The step response of the close-loop system is shown in Fig. 2.12. 1.0 0.2 -0 U . 1 . . . 0 10 20 30 4 0 50 60 Time (samples) Fig. 2.12 Discrete step response of the close-loop system using the frequency response method 29 Next, the root locus method will be used to fine tune the controller. If the controller is expressed in the form of K • , there will be two parameters in the digital controller z-1 to be tuned: K, the gain and a, the zero of the controller. As we can see from the step response in Fig. 2.12, it takes several sample intervals to reach the first peak value, and around 60 steps to get settled at the steady state value. Therefore, the gain can be higher and the zero of the controller can be adjusted to make the close-loop poles closer to the origin. After a few iterations, one can finalize the digital controller as: G(z) = L 4 z ~ ° - 9 1 . (2.29) z-1 The difference equation of the controller is: u(t) = \A0e(t)-0.9\e(t-Ts) + u(t-Ts). (2.30) The root locus plot is shown in Fig. 2.13, and the step response is shown in Fig. 2.14. 0.8 0.6 0.4 0.2 TO £ 0.2 -0.4 •0.6 -0.8 -1 -1 -0.5 0 0.5 1 1.5 2 Real Fig. 2.13 Root locus plot of the digital control system designed by the root locus method 30 1 1 X Poles O Zeros i 1 i 1 z-plane to (~Y~) v «V o L J , , , , , _J 0 5 10 15 20 25 30 Time (samples) Fig. 2.14 Discrete step response of the digital control system designed by the root locus method 2.5 Summary In this chapter, two different digital controller design approaches and their design procedures are described and analyzed in theory. In digital redesign methods, features of four transformation methods are discussed, especially in their frequency responses. Three commonly used direct digital design methods are analyzed as well. Based on the charac-teristics of these methods, a modified direct digital design method which is more suitable for practical applications is proposed. A simple design example is provided for each design method to clarify the design procedure. The five digital design methods: four digi-tal redesign methods and one modified direct digital design method, will be used in a power inverter controller design in the next chapter. 31 Chapter 3 Digital Controller Design for Single-Phase Power Inverter Systems 3.1 Introduction In this chapter, the digital design methods discussed in the Chapter 2 will be applied to the controller design of a signal-phase inverter system. Section 3.2 presents the model of the inverter system first, and then describes the control structure of that system. As mentioned in Chapter 2, we have discussed two different digital design approaches and five different methods. Digital controller design using these methods for the inverter sys-tem will be described in details in section 3.3 and 3.4. In order to evaluate which method is better for inverter application, and to test the effect of different sampling frequency on the inverter performance, three different sample frequencies are selected: f = 40kHz, f = 20kHz, and fs = \0kHz. To avoid duplication, only fs = 20kHz is discussed in this chapter. 3.2 Switchmode Power Inverter In this project, digital controller design and implementation practice will be applied to a PWM single-phase inverter system. Fig. 3.1 shows the circuit diagram of the system. The inverter uses full bridge topology which consists of four switches. The induc-tance and capacitor after the switches act as low-pass filter to filter out the high switching frequency. Bipolar PWM scheme is used to turn on and turn off switches. During each conduction cycle, either the upper left (Tl) and the lower right (T2) switches or the upper right (T3) and lower left (T4) switches are turned on. To avoid conduction of switches on one-leg of the full bridge inverter, dead times are added in the gating signals. (Dv, J dc T l JI&T4 T3 pT2 C t Switch driver 1 Switch driver 2 Fig. 3.1 Circuit diagram of a power inverter system The relationship of the inductance current to the duty ratio d is [33]: ¥ Hi(*) = 5 — — = a RQCLs +(RLR0C + L)s + R0 + RL (3.1) where R is the load of the inverter, M is the modulation index of the sinusoidal PWM, and RL is the ESR of the inductor L. The relationship of the output voltage to the duty ratio d is: 33 7 " H ( s ) M-Vdc.RQ RoCLs +(RLR0C + L)s + R0 + RL (3.2) The relationship of the output voltage to the inductance current is: (3.3) The double-loop structure, as shown in Fig. 3.2, is used for inverter control. The inner loop controls the inductance current, while the outer loop controls the output volt-age. PI controllers are used for both the current loop and the voltage loop. Double-loop PI Controller Fig. 3.2 Double-loop analog PI controlled power inverter system The objective of this thesis is to replace the analog controller with the digital con-troller, implemented in a microprocessor or DSP. The DSP which used in this project, has the function of PWM embedded with deadtime feature. Detailed implementation issues of 34 the DSP will be discussed in Chapter 4. Fig. 3.3 is the block diagram of the DSP con-trolled inverter system. Digital PI controllers are used in the design. ±)V d c o U 'act 5 VSI P W M Generator i A/D DSP *~ A/D Reference T C Ro V Fig. 3.3 Double-loop digital controlled power inverter system 3.3 Controllers Based on Digital Redesign Methods The power inverter we used in this research has the following system parameters: Vdc = 200V, RL = 0.3Q, L = 800p#, C = 9.9pF. The nominal output voltage of the inverter is 120 VAC, the modulation index is assigned as 0.6, and the load R is set to 16Q. Substituting these values into equation (3.1) and equation (3.3), we obtain H;(s) and H~v(s) as follows: -4 Ht(s) = 120 }fe S + ] , (3.4) 1.27e V + 8.48e 5+16.3 35 The continuous double-loop control system diagram with the time delay is shown in Fig. 3.4. Vo.ref, •( Voltage Controller Current Controller V, Kv o Fig. 3.4 Double-loop control system diagram for digital redesign approach Kt and Kv are the gains of the current sensor and voltage sensor. In this study, Kt = 0.1, and Ky = 0.013 have been used respectively. The current loop design using digital redesign methods have been done in the last chapter, as seen in equations (2.8), (2.11), (2.15) and (2.17). The outer voltage loop transfer function is the product of the cur-rent close-loop transfer function and Hy(s). The voltage loop controller is designed by using Bode plot as well. The analog PI controller with a bandwidth of 0.9 kHz and a phase margin of 50° is given by: 0.12(1.56^+1) G c v ^ = is • (3-6> l.56e s 36 Using the transformation methods discussed in section 2.3, the corresponding dig-ital controllers for the voltage loop can be obtained. Table 3.1 lists the current and voltage controllers with different redesign methods. Simulation and experiment results on the inverter system with different digital controllers will be presented in Chapter 5. Table 3.1. Digital controllers for current and voltage loops using different redesign methods at 20 kHz sampling rate Methods Current Loop controller Voltage loop controller Backward Euler n ( v 0.852z- 0.809 C l z-1 r ( x 0.475z-0.113 G - ( Z ) _ z-1 Bilinear n f v 0.830z-0.786 C l z-1 n , x 0.294z + 0.068 G - ( Z ) " z-1 Pole/Zero Match n ( v 0.830z-0.786 C l z-1 GCVV = ° -3 7 7 z - 0 - 0 1 5 Step Invariant n , , 0.808z-0.764 G « ( 2 ) " z-1 G c v ( z ) = 0.113z + 0.249 3.4 Controllers Based on Direct Digital Design Method Fig. 3.5 shows the block diagram of the direct digital design method. In this method, the continuous plant transfer functions H~t(s) and H (s) are discretized first. The transfer function H^s) is discretized as: m . 7.07,-5.11 t ( 3 ? ) z -1.45z + 0.72 37 with the sampling frequency of 20 kHz. Unlike the H{(s), Hv(z) is not discretized directly from Hy(s), because one sample delay from inductance current to the output volt-age will produce total delay of two-sample period. Since we know the relationship of out-put voltage and the duty ratio as: a{<s) \21e V + 8.48e $+16.3 by discretizing this function, we have: H ( Z ) = V ^ 1 = 16.55Z+ 14.79 ( 3 9 ) d ^ z2-1.45z + 0.72 The discrete function Hv(z) is then obtained by f^f^ , or = 2.34Z + 2.09 ( 3 1 0 ) Vo,re^_ Voltage Controller Current Controller H,(z) Kv "o Fig. 3.5 Double-loop control system diagram for the direct digital design approach 3 8 The w-plane transfer function of H((z) is: „ ( , -3.85w2+ 1.29e5w + 9.9e8 m n Ht(w) = — . (5.11) w + 7.18e w+ l.34e The function Hv(w) is not obtained from transformation of Hv(z), but rather from the multiplication of the inner close-loop function T{(z) and Hv(z), or H'(z) = Tt(z)-Hv(z). The digital controller is then designed in the w-plane with a bandwidth of 2.8 kHz and a phase margin of 60° for the current loop; and a bandwidth of 0.9 kHz and a phase margin of 60° for the voltage loop. The current and voltage controllers are: 0.63(1 + \A\e~\) Gci(w) , (3.12) 1.41e w „ , , 0.52(1 +9.66e 5w) ... 9.66e w After transformation, the z-plane expressions of equation (3.12) and (3.13) are: 0^^052 ^ ( 3 1 4 ) 0 1 z-1 G ( w W _ 0 6 ^ 0 3 9 ( 3 1 5 ) The step response of this double-loop system is shown in Fig. 3.6. 39 20 10 0 L J , , , , , _ J , , . 0 5 10 15 20 25 30 35 4 0 Time (samples) Fig. 3.6 Discrete step response of the output voltage of the double-loop system by the frequency response method To proceed with the direct digital design method, the root locus method is used to fine tune the controller parameters. Since the controller has a double-loop structure, the current loop poles and zeros placement will also affect the voltage loop design. As we can see from Fig. 3.6, the output takes several sample intervals to reach the peak value and even longer to get to the steady state. This means that the gains of the current and voltage controllers can be further increased, and the zeros of the current and voltage controllers need to be adjusted to make the close-loop poles closer to the origin of the z-plane. Since the gain and the zero position of the current controller will affect the positions of the volt-age loop poles, attention should be paid to the voltage loop pole/zero movement, when making parameter changes on the current loop controller. There are usually several poles in the voltage loop on the z-plane, as seen in Fig. 3.7. Dominant poles which are closer to the unit circle on the right side of the plane deserve more attention. In the current loop root locus, the zero of the controller has been moved closer to the pole at point 1, the influence 40 of this pole/zero pair on the system is very small. The response speed of the current loop will increase, when the gain of the current controller is adjusted to make the two dominant poles "a" and "b" closer to the origin. One of the voltage loop root loci shows the tendency of going directly to the outside of the unit circle. Moving the zero of the voltage controller to the origin will slow the tendency. The gain of the voltage controller is also modified to finalize the positions of the dominate poles "c" and "d". After a few iterations, we obtain current and voltage controllers as: Gci(z) = 1 ^ 1 3 2 , (3.16) C l z - l Gcv(z) = 0-^-0-13 (3.17) The root locus plot of the system is shown in Fig. 3.7, while the step response is depicted in Fig. 3.8. As compared to Fig. 3.6, the step response in Fig. 3.8 shows that the controller performance has been improved in terms of response time and overshoot mag-nitude. 3.5 Summary In this chapter, a real PWM single-phase inverter system was introduced. Different digital design methods discussed in chapter 2 are used to control a single-phase inverter system. The current and voltage loop controllers we derived in this chapter will be imple-mented in a DSP controller which will be discussed in the next chapter. The simulation and experiment on the digital controlled inverter system will be performed in Chapter 5. 41 60 03 1 0 .8 0 .6 0 .4 ) 2 0 3.2 - 0 . 4 - 0 6 - 0 -1 X Poles O Zeros z-plane ,-a . I. Pc o -K: m—( ?\ \J7 4> DO s 1.5 • .5 -0.5 Real fa) X Poles O Zeros z-plane Fig. 3.7 Root locus plot of (a) the current loop and (b) the voltage loop with the root locus method 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 40 Time (samples) Fig. 3.8 Discrete step response of the output voltage of the double-loop system by the root locus method 42 Chapter 4 Implementation of the Digital Controllers 4.1 Introduction A good control algorithm is only the first step towards a satisfactory digital con-trolled system. A lot of effort must be made in order to achieve appropriate implementa-tion of the numerical algorithm. Using a fixed-point finite word length DSP, for example, various arithmetic errors can be encountered which may cause system degradation. Basically, arithmetic errors can be classified into three types. One is errors from analog-to-digital or digital-to-analog conversion where an analog signal is represented by a finite length binary word. These errors, also called as quantization errors, can be handled as random "noise". The second are multiplication errors, where the product of two finite-length binary words must be represented by another word of the same length. These errors can be treated as random "white" noise as well. The last category of errors is the parameter errors in which control algorithm coefficients must be truncated and stored as finite-length words. Since pole location and frequency response of controller are very sensitive to the variation of coefficient values in the transfer function, the parameter errors therefore can cause significant alterations in the system dynamic behavior. No matter what kind of digi-tal control algorithm is used, these three errors always exist in the system and must be carefully handled in order to obtain a satisfactory controller performance. 43 In this chapter, a DSP-based power inverter is implemented. The hardware compo-nents of the inverter such as power stage, current and voltage sensors, signal condition components, PWM signal and power supplies are discussed in section 4.2, while the soft-ware implementation is described in section 4.3. 4.2 Hardware Design In this section, a power system consisting of an inverter and a TMS320F240 DSP control board is constructed. Fig. 4.1 shows the simplified schematic diagram of the power system. A complete circuit schematic is shown in Appendix A. ACin + Cc Cl Optocoupler — 1 IGBT LI Ei rwnrYA/vVrr ri Optocoupler Optocoupler H C4 Optocoupler L2 l i n r w C5 'C6 ACout r m Y V ^ A A / v n l u r m L-Current Signal Conditioning Voltage Signal Conditioning ADCIN6 ADCIN14 PWM1 DSP TMS320F240 PWM2 Fig. 4.1 Simplified schematic diagram of the inverter system The power system consists of five different parts: DC power supply, single-phase power inverter, switch driver circuit, current and voltage sensor, and the DSP board. They are described as follows. 44 4.2.1 Power Stage The input DC power source of the inverter is a simple AC to DC diode bridge. In order to provide a low ripple DC source to the inverter, a capacitor of \QmF is used. Due to its large size, this bulky capacitor can not be placed very close to the hardware circuit. In order to suppress the switching spikes produced by the parasitic inductance of the long connection wires, another three small capacitors of 650pF are placed just before the switching network. The power stage of the inverter is based on the commercial product of a 1.8 kW inverter from Statpower Technologies Corporation. To minimize the ESR, three output capacitors of the inverter are placed in parallel with an equivalent of 9.9 pi 7. IGBTs (Insu-lated Gate Bipolar Transistor) IRG4PC40UD from International Rectifier are used as switching devices. The optimized operating frequency of this device is from 8 kHz to 40 kHz. With ultrafast, ultra-soft-recovery anti-parallel diodes included in the module, the switching characteristic of the IGBT are as follows: 57ns rise time, 54ns turn-on delay, 130ns fall time, 200ns turn-off delay, and 120ns diode reverse recovery time. Based on these characteristics and the load condition, the dead time is set to be 1.5ps to avoid shoot-through. Optocouplers HCPL-3150 from Hewlett Packard are used to isolate the control circuit from the power stage. With 0.5A output current operating at a DC voltage of 15V to 30V, the optocouplers also work as gate drivers for IGBTs. 4.2.2 Current and Voltage Sensors The output voltage of power inverter is 120VAC and the output inductance current can go up to 15 A. While considering the transient overshoot, the possible voltage peak-to-45 peak value is set to be 380V, and the possible current peak-to-peak value is 50A. Since the DSP A/D converter accepts signals only from 0 ~ 5 V, signals sensed from the output stage of the power inverter must be processed before they are transmitted to the A/D con-verter. Fig. 4.2 shows the current sensing circuit. The inductance current is sensed by a small resistor, Rt = 5mQ, which is connected in serial with the inductor. The voltage across the resistor is 200 times smaller than the current value flowing through it. Circuit of Stage 1 in Fig. 4.2 amplifies the signal 20 times larger to make the output at "vl" to be lOOmv/A, where Rx = R3 = 50kQ and R4 = R5 = 100&Q. The resistor R2, with the value of 10Q, is to provide a small input signal to the current controller to stabilize the current loop temporarily in case there is a problem on the current sensing resistor Ri. Circuit of Stage 2 is to shift the current signal to be within the 0 ~ 5 V range, so that 2.5V corresponds to OA in the circuit. In order to prevent the A/D channel from being damaged due to the excessive voltage, a 5-V zener is used at the output. Fig. 4.3 is the voltage sensing circuit. In circuit of stage 1, the output voltage is R-y + R-i measured by a voltage divider: , where R^ = lMQ,i? 2 = 10&Q,i?3 is an adjustable resistor of 0 ~ 5kQ.. The purpose of 7?3 is to adjust the voltage at "v2" 76 times smaller than the inverter output voltage. Circuit of Stage 2 is the same as the current sens-ing circuit in Fig. 4.2. 46 i L „ L Ri o i A A / T V A / v V Inverter • i • :RO / W V T >R2 = vi -15V pvvW-To A / D 5V Stage 1 Stage 2 Fig. 4.2 Inductance current sensing circuit L\AAr A A / V To A / D 5V Stage 1 Stage 2 Fig. 4.3 Output voltage sensing circuit 47 Resolution of the A/D converter is 10 bits, each level corresponds to 0.37V for the output voltage, and 0.37mA for the inductance current. This resolution loss will result in some steady state error and the controller-induced oscillations (or limit cycles). 4.2.3 DSP Evaluation Board The DSP used in this project is TI TMS320F240. This type of DSP is designed mainly for motor control applications. Besides the high performance of the DSP core, it also has many on-chip peripherals that are normally only available in microcontrollers. The main features of this DSP are listed in Table 4.1. Table 4.1. Features of the TMS320F240 DSP Parameter Name TMS320F240 MIPS 20 Cycle Time (ns) 50 Frequency (MHz) 20 RAM (words) 544 Flash (words) 16K Boot Loader Available Flash Timers 3 PWM channels 12 A/D channels 16 A/D resolution 10-bit Conversion Time (us) 6.6us Total Serial Ports 2 External Memory Interface Yes 48 The architecture of the F240 DSP is based on the modified Harward architecture, which supports separate bus structures for program space and data space. A third space, the input/output space, is also available and is accessible through an External Bus Inter-face. To support a large selection of peripherals, a peripheral bus is used. The peripheral bus is mapped to the data space and interfaced to the data bus through system module. Fig. 4.4 is the simplified block diagram of the DSP. A high-speed powerful CPU allows faster processing of algorithms. Wait External Bus Interface Program Bus Data Bus Event Manager Data Memory Program Memory System Module CPU 32-bit Input scaling Multiplication 16-bit x 16-bit v 32-bit CALU 32-bit Accumulator 32-bit Output scaling Peripheral Bus System Control WD/RTT/ PLL ADC Digital I/O External Interrupt Fig. 4.4 Simplified block diagram of the F240 DSP The evaluation board of the F240 DSP provides features that are very useful in the development stage. It provides hardware interfaces between the DSP and the peripherals. There are four 34-pin connectors that give access to all the relevant signals on the evalua-tion board. This board also provides the power supply and the oscillator for the DSP. The 49 A/D converter uses the same ground as the DSP which is grounded through the sensing circuit. 4.2.4 PWM Generator One of the key function of TMS320F240 is the generation of PWM pattern accord-ing to calculated duty cycle. The frequency, duty cycle, and deadtime of the PWM signals are programmable. The PWM signal is generated by comparing an internal counter with a specified value. The counter can be either symmetrical or asymmetrical, as shown in Fig. 4.5. i off On Symmetric PWM Asymmetric PWM Fig. 4.5 PWM generation in DSP If the PWM period T is fixed, the maximum value of the counter TV in a period of T„ is also fixed; that is N = T/tm, where tm is the cycle time of the DSP. Simulta-neously the highest resolution of the PWM can be determined as: Resolution = 1 /N for the asymmetric PWM, and Resolution - 2/N for the symmetric PWM. Since the asymmetric PWM can give 2 times higher resolution than the symmetric PWM, it is used in this digital controller application. 50 4.3 Software Design The digital control schemes are implemented in a C program. The following sec-tion describes the fixed-point implementation issues and the program structure. 4.3.1 Numeric Representation and Calculation In general, numeric data can be represented in floating-point or fixed-point for-mats. Since TMS320F240 is a 16-bit fixed-point DSP, it provides much faster operation speed on an integer than on a floating-point number. For example, it takes 24 cycles to fin-ish the calculation of '2.0 + 3.0', but only 10 cycles to finish '2 + 3 '. Similar speed dif-ference can be found in multiplications. In order to increase the computation speed, all the parameters are converted into integers before calculation is performed. The scaling values which are used to transform floating-point numbers to integer numbers are carefully selected to avoid overflow and to minimize the quantization effect. A digital PI controller a,z-a7 G(z)= — can be implemented in the form of difference equation, as z - l u(t) = a^e(t)- a2e(t- T ) + u(t- Ts). For voltage loop and current loop, there are two multiplications and two additions in each PI controller. Compared to addition, multiplica-tion has a larger possibility of overflow. To avoid overflow, multiplication results have been stored in long integer variables and limited to 16-bit for later computation. The scal-ing values are in the power of 2, so that the multiplication or division operations can be implemented as left or right shift. The value of e(t) feeding into the current controller is in the range of ±64 after A/D conversion. The parameters and a2 should not be larger than 512 to avoid overflow. For example, if the parameters and a2 are 1.4 and 1.39 in 51 the current controller, the scale factor of 256 can be used, and the parameters in the DSP will be 1.4 x 256 - 358.4^358 and 1.39x 256 = 355.8 « 356 respectively. The value of gains and zero positions can be changed slightly as compared to designed values because truncation has been made when the parameters are scaled from floating-point numbers to integers. To optimize the implementation of PI controller, the computation sequence has been modified. Basically, the calculation of a digital PI controller consists of two parts. One is the calculation on the previous data e(t - T ) and u(t - T), and the other is on the recent A/D input data e(t) = r(t)-y(t), where r(t) is the reference value and the y(t) is the input value. The first part can be precalculated before the new input is available. Then the calculation burden is reduced for the second part. The A/D converter of the F240 DSP needs 6 us minimum to finish a conversion. If some calculation can be performed in this period of time, instead of doing all the calculation after that, at least 6 us can be saved. The time diagram of the one sample period is shown in Fig. 4.6. Update P W M A/D values ready A/D conversion Computation 1 Computation 2 Obtain P W M pattern • DSP in Idle Start of one period End of one period Fig. 4.6 Time diagram of one sampling period The meaning of Fig. 4.6 is explained as follows. In the stage of Computation 1, the DSP is doing A/D conversion and some computations at the same time. Necessary calcu-52 lation variables from last sample interval are stored, those are, e(i) —> e(t— T ) and u(t) —» u(t — T ). The new reference value for a current sample period is obtained by checking the reference table which is prepared and stored in the DSP memory before exe-cution. The second terms of the digital controller • e(t- T ) can be calculated in the same period as well. All the other necessary calculations to generate new PWM pattern are finished in the stage of Computation 2. 4.3.2 Program Structure Fig. 4.7 is a flowchart of the overall control program. The first task of the program is to initiate the DSP status, cycle time, and wait cycles, etc. The main computation part is in Timer Tl interrupt procedure. After starting the timer, the program will be waiting for the interrupt to be requested. Initiate DSP Status t Initiate Timer, A/D, PWM, and Interrupt __t Start Timer and Enable Interrupt Wait for timer interrupt Fig. 4.7 Flowchart of the main program 53 When Timer Tl counter reaches the end of a switching period, the interrupt is trig-gered and program flow is redirected to the interrupt service routine. Fig. 4.8 is the flow diagram of the interrupt service routine with sampling frequency of 20 kHz. Timer interrupt triggered 1 Save registers 1 Start A/D conversion 1 A/D conversion is progress; Store previous value: e(t-Ts)=e(t); u(t-Ts)=u(t); Computation: a/*e(t-Ts) Get Reference value: r(t) 1 Get A/D result Calculation: e(t)=r(t)-y(t); u(t)=(a2*e(t)+ a! *e(t-Ts))/K+u(t-Ts) Set to the max value Yes H Generate PWM _t Return Fig. 4.8 Flowchart of the interrupt service routine 54 4.4 Summary In this chapter, the implementation of a digital controller through DSP is dis-cussed. Both respects of hardware and software designs are considered. In hardware design, a system with a inverter and a DSP evaluation board was constructed. Some efforts are made to improve the system performance. In software implementation, the numeric representation and calculation sequence in the fixed-point F240 DSP are issued. Some techniques used to reduce the computation time are developed. The experiment of the inverter system will be reported in the next chapter. 55 Chapter 5 Simulation and Experiment Results 5.1 Introduction In this chapter, performance comparison of five digital controller methods men-tioned in Chapter 3 is made based on experiment and simulation results of the switchmode power inverter. Bandwidth and nonlinear load condition are used to evaluate the system performance. In the frequency domain, bandwidth of the control loop gives information of the response speed of the system. Therefore, comparison of the bandwidth of the inverter with different controllers is made first. In the time domain, the performance of a control system can be observed from response to a nonlinear load. Therefore, the performance of the five methods with the nonlinear load condition is compared too. Their relationship with the control structure and the sampling frequency is studied as well. In general, the magnitude of the switching frequency has significant effect on the performance of an inverter. It influences not only the output voltage ripple, but also the steady state sinusoidal waveform as well. Theoretically, the higher the frequency is, the better the performance. Unfortunately, the frequency is limited by the availability of com-ponents and cost consideration. Due to the speed of the DSP, we can only realize the digi-tal control at 20 kHz switching and sampling frequency. In the following discussion, the waveforms and data measured from experiments are the results from using 20 kHz as switching frequency, 20 kHz & 10 kHz as sampling frequencies. The waveforms and data 56 obtained from simulation programs PSIM and MATLAB are results from using 40 kHz as the switching and sampling frequencies. The experimental output waveforms are mea-sured with a Tektronix TDS 240A digital real-time oscilloscope. The experimental band-width data and frequency responses are provided by a Venable Industries Model 260 system analyzer. Section 5.2 compares the system bandwidth of the current loop and the voltage loop with different digital controllers and different sampling frequencies. Nonlinear load performance is presented in 5.3. Additional comparison of the digital controller delay models was made in section 5.4. 5.2 System Bandwidth Comparison In this section, five design methods are compared based on system bandwidth measurements. The system bandwidth is measured from a frequency response plot (Bode plot). This frequency response plot can be obtained from the Matlab simulation and from experiment. Bandwidth obtained from simulation is a little different with different calculation approaches. No matter which approach is used in the digital controller design, all systems share the same block diagram as in Fig. 5.1. Since calculation in Matlab has to be made in the same domain, either in the s-domain, or in the z-domain, transformation is needed because the plant transfer function is in the s-domain while the digital controller is in the z-domain. We either can convert the plant to the z-domain, and replace z in loop transfer function with e to see the fre-57 quency response, or convert the controller to the s-domain, and replace s in loop transfer function with /'co to obtain the frequency response. In this thesis, the first transformation is used, and the transformation of the plant is the same as that of direct digital design approach. The current loop bandwidth is measured in the Bode plot of Kt • Df(z) • H^z), and the voltage loop bandwidth is obtained from that of Kv • £>v(z) • Tt(z) • Hv(z), where is the current close-loop transfer function. Voltage Controller Current Controller Hv(s) Fig. 5.1 Double-loop digitally controlled system diagram Fig. 5.2 shows the experimental test circuit for the current loop and voltage loop bandwidth with Venable system analyzer. Channel 1 and channel 2 are the two terminals of the system analyzer used for signal injection and measurement. Two operational ampli-fiers connected as voltage followers are used to provide a high impedance for channel 1 and a low impedance for channel 2, as required by the system analyzer. A small resister of 22Q is added as well for the analyzer to inject and obtain signals. Fig 5.3 indicates the connection of the test circuit and the inverter system. The test circuit is believed not to have a large influence on the system dynamics. First, the comparison on the system bandwidth is made at 10 kHz sampling fre-quency and 20 kHz switching frequency. Following the same design procedure described 58 in Chapter 3, five different current loop and voltage loop controllers were constructed, and Table 5.1 lists all the controllers. Signal in Channel 2 22Q. L J W V Channel 1 Signal out T Y Y Y 1 System A n a l y z e r Fig. 5.2 Test circuit for system loop bandwidth measurement V, Voltage Controller Current Controller Voltage loop inject point His) Current loop inject point Kv Ki HJs) o Fig. 5.3 Current and voltage loop bandwidth measurement points Table 5.1. Current and voltage controllers with different methods at 10 kHz sampling rate Design Method Current Loop Controller Voltage Loop Controller Direct Digital n , x 0.8z-0.796 n , x z-0.18 ° * ( z ) z-1 Backward Euler 0.514z-0.489 Gj(z) ~ ' z-1 n , x 0.866z-0.156 G * ( Z ) = z-1 Bilinear r, f s 0.502z-0.477 G ' ( Z ) = z-1 „ t x 0.509z + 0.204 G ' ( Z ) = z-1 Pole/Zero Match 0.502z-0.477 r. , . 0.720z-0.072 ° ' ( Z ) z-1 Step Invariant 0.489z-0.464 G <- ( Z ) = z-1 n . . 0.153Z +0.562 G * ( Z ) z-1 59 Fig. 5.4 and 5.5 are the simulated Bode plot of the system current and voltage loops from Matlab. m w 1 Frequency (Hz) Fig. 5.4 Simulated Current loop Bode plot at the sampling rate of 10 kHz OQ w •a | -300 10 Frequency (Hz) 10* 2-10 Frequency (Hz) Fig. 5.5 Simulated voltage loop Bode plot at the sampling rate of 10 kHz The experimental frequency responses of the current and voltage loops obtained from analyzer are presented in Fig. 5.6 and Fig. 5.7. Frequency (Hz) Frequency (Hz) Fig. 5.6 Current loop Bode plot provided by the system analyzer at the sampling rate of 10 kHz 62 PQ -13 a "5. Frequency (Hz) -300 10' Frequency (Hz) 10 2-10 Fig. 5.7 Voltage loop Bode plot provided by the system analyzer at the sampling rate of 1 0 kHz 63 Table 5.2 to 5.5 list the bandwidth and the phase margin of the current and voltage loops from the simulated and experimental results. Table 5.2. Simulated current loop bandwidth and phase margin with different digital controllers at 10 kHz sampling rate Design Method Current Loop Bandwidth Current Loop Phase Margin Direct Digital 2.93 kHz 50° Backward Euler 2.23 kHz 70° Bilinear 2.20 kHz 70° Pole/Zero Match 2.20 kHz 70° Step Invariant 2.16 kHz 70° Table 5.3. Simulated voltage loop bandwidth and phase margin with different digital controllers at 10 kHz sampling rate Design Method Voltage Loop Bandwidth Voltage Loop Phase Margin Direct Digital 1.08kHz 70° Backward Euler 0.68kHz 75° Bilinear 0.64kHz 63° Pole/Zero Match 0.65kHz 71° Step Invariant 0.63kHz 53° Table 5.4. Measured current loop bandwidth and phase margin with different digital controllers at 10 kHz sampling rate Design Method Current Loop Bandwidth Current Loop Phase Margin Direct Digital 2.5kHz 48° Backward Euler 2.3kHz 48° Bilinear 2.3kHz 48° Pole/Zero Match 2.3kHz 48° Step Invariant 2.2kHz 40° Table 5.5. Measured voltage loop bandwidth and phase margin with different digital controllers at 10 kHz sampling rate Design Method Voltage Loop Bandwidth Voltage Loop Phase Margin Direct Digital 0.90kHz 70° Backward Euler 0.70kHz 70° Bilinear 0.65kHz 65° Pole/Zero Match 0.68kHz 70° Step Invariant 0.60kHz 55° As we can see from Fig. 5.5 to 5.7, the experimental and the simulated frequency response curves are very similar in shape. The bandwidth and phase margin obtained from these curves are close to each other as well. Between the two results, the experimental result is considered to be a better reflection of the real physical inverter system. However, the noise in the physical system makes it difficult to get a very accurate reading. The small variation of the simulation results, as seen in Fig. 5.5 to 5.7 and Table 5.2 to 5.5, is because of the following two reasons. First, the simulation is based on the system transfer function, which only represents the main dynamic of the system. Second, there is a system transformation in the simulation, and the transformation may introduce some errors. Although there are limitations on the method, the simulation results still display the sys-tem performance. From both the experimental and the simulation results, it is shown that the direct digital design approach gives a higher bandwidth than the redesign approach. In the exper-imental system, the bandwidth of the current loop is 8.7% higher than the Backward Euler method and 13.6% higher than the Step Invariant method. The improvement is even big-ger in voltage loop: it is 28.6% higher than the Backward Euler and 50% higher than the Step Invariant. In digital redesign methods, Backward Euler gives the highest bandwidth 65 in the voltage loop, Pole/Zero Match and Bilinear are second, Step Invariant gives the lowest. The bandwidth difference in the current loop among the Backward Euler, Pole/ Zero Match and Bilinear is not very clear in the experimental result, but their bandwidth are slightly better than that of Step Invariant method. The same conclusion on these rede-sign methods can be drawn from the simulated results, and from the data, we can see that the Backward Euler has higher bandwidth than the Pole/Zero Match even in the current loop. A similar comparison of the system bandwidth was made at a 20 kHz sampling frequency. Table 5.6 lists all the controllers with different design methods. Table 5.6. Current and voltage controllers with different methods at 20 kHz sampling rate Design Method Current Loop Controller Voltage Loop Controller Direct Digital ^ , , 1.4z-1.39 ' z - l n , v 0.55z-0.13 G V ( Z ) " Z - l Backward Euler n , v 0.852z-0.809 ° ' ( Z ) z - l r. , , 0.475Z-0.113 G * ( Z ) = z - l Bilinear n , , 0.830z- 0.786 ' z - l n ( v 0.294z + 0.068 G * ( Z ) - z - l Pole/Zero Match n , , 0.830z-0.786 ' z - l n , x 0.377z- 0.015 v z - l Step Invariant ^ . v 0.808z-0.764 G,(z)= z l r, < ^ 0.113z +0.249 ° ^ Z ) = z - l Fig. 5.8 and 5.9 are the experimental results of the current and voltage loops pro-vided by the system analyzer. Table 5.7 and 5.8 list the measured bandwidth and the phase margin of the current and voltage loops. Similar results are obtained from simulation as 66 well. Table 5.9 and 5.10 list the simulated bandwidth and the phase margin of the current and voltage loops. Frequency (Hz) Fig. 5.8 Current loop Bode plot provided by the system analyzer at the sampling rate of 20 kHz 67 Table 5.7. Measured current loop bandwidth and phase margin with different digital controllers at 20 kHz sampling frequency Design Method Current Loop Bandwidth Current Loop Phase Margin Direct Digital 3.1 kHz 50° Backward Euler 2.9 kHz 50° Bilinear 2.9 kHz 50° Pole/Zero Match 2.9 kHz 50° Step Invariant 2.9 kHz 50° Table 5.8. Measured voltage loop bandwidth and phase margin with different digital controllers at 20 kHz sampling frequency Design Method Voltage Loop Bandwidth Voltage Loop Phase Margin Direct Digital 1.2 kHz 65° Backward Euler 0.95 kHz 65° Bilinear 0.83 kHz 55° Pole/Zero Match 0.90 kHz 60° Step Invariant 0.82 kHz 50° Table 5.9. Simulated current loop bandwidth and phase margin with different digital controllers at 20 kHz sampling frequency Design Method Current Loop Bandwidth Current Loop Phase Margin Direct Digital 3.74 kHz 62° Backward Euler 2.94 kHz 65° Bilinear 2.90 kHz 65° Pole/Zero Match 2.90 kHz 65° Step Invariant 2.85 kHz 65° 69 Table 5.10. Simulated voltage loop bandwidth and phase margin with different digital controllers at 20 kHz sampling frequency Design Method Voltage Loop Bandwidth Voltage Loop Phase Margin Direct Digital 1.29 kHz 56° Backward Euler 0.93 kHz 63° Bilinear 0.89 kHz 55° Pole/Zero Match 0.90 kHz 58° Step Invariant 0.88 kHz 46° Qualitatively speaking, from observing the experimental and simulation results with 20 kHz sampling rate in Fig. 5.8 and 5.9 and Table 5.7 to 5.10, one can almost draw the same conclusion as that for 10 kHz sampling rate. However, the difference on the bandwidth among different methods becomes smaller compared to the case of 10 kHz sampling rate. In the experimental system, the current loop bandwidth of the direct digital controlled system is 6.9% higher than the redesign methods. The voltage loop bandwidth is 26.3% higher than the Backward Euler and 46.3% higher than the Step Invariant. Although there are some differences among the four redesign methods from the simula-tion results on current loop, the difference is so small that, in the real inverter system, it can not be differentiated from noise. On the other hand, the difference on the voltage loop is visible, especially on the phase plot. The Backward Euler gives the highest bandwidth and good phase margin, followed by Pole/Zero Match and Bilinear. The Step Invariant method is the worst, both in amplitude and phase response. From previous results, we can see that the difference among the different methods is larger in the double-loop than that of single-loop. The difference also increases when 70 the sampling frequency is lower. To verify the trends of variation of the bandwidth differ-ence among the five methods, a sampling frequency of 40 kHz was tried. Since it is diffi-cult to perform a experiment with such high switching and sampling frequency with the existing setup, the trend verification is done only by simulation. Table 5.11 lists the digital controllers designed with 40 kHz sampling rate. Fig. 5.10 and Fig. 5.11 are the simulated frequency responses of current and voltage loops. Table 5.12 and 5.13 list the bandwidth and the phase margin of the current and voltage loops. Table 5.11. Current and voltage controllers with different methods at 40 kHz sampling rate Design Method Current Loop Controller Voltage Loop Controller Direct Digital r, , \ 2z- 1.98 G,(z)- 2 l n t \ 0.75z-0.49 G ^ Z ) = z - l Backward Euler G ) = 1.73Z-1.67 z- 1 n t ^ 0.543z-0.323 G ^ Z ) - z - l Bilinear r,, , 1.70r-1.64 G ' ( Z ) = z - l n f , 0.433z- 0.213 v z - l Pole/Zero Match G 1.70Z-1.64 ' z - l n , , 0.446z-0.226 G * ( Z ) - z - l Step Invariant 1.67z-1.61 G <- ( Z ) = z - l r, , N 0.323z-0.103 Table 5.12. Simulated current loop bandwidth and phase margin with different digit controllers at 40 kHz sampling frequency Design Method Current Loop Bandwidth Current Loop Phase Margin Direct Digital 5.44 kHz 67° Backward Euler 4.78 kHz 68° Bilinear 4.71 kHz 68° Pole/Zero Match 4.71 kHz 68° Step Invariant 4.64 kHz 69° 71 CQ w 3 "a. E 20 15 10 u DO ii w <D t o 03 - C -10 10' i i i i i i • i 1 k^. \. 1 1 X 1 Direct Digital Backward Pole/Zero Match Bilinear Step Invariant / 1 / 1 / 1 1 1 1 1 1 1 1 1 1 1 1 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 10" 10 Frequency (Hz) \ \ i ^ Direct Digital V y L L - V V l \ v i K , L, Backward Pole/Zero Match Bilinear Step Invariant 1 1 1 10 Frequency (Hz) Fig. 5.10 Simulated current loop Bode plot at the sampling rate of 40 kHz m 3 T 3 3 S < 20 15 10 5 0 -5 -10 -15 -20 5-10 w • O H . Direct Digital Pole/Zero Match Bilinear Step Invariant 10' 5-10 Frequency (Hz) 5-10 Frequency (Hz) Fig. 5.11 Simulated voltage loop Bode plot at the sampling rate of 40 kHz 73 Table 5.13. Simulated loop voltage bandwidth and phase margin with different digital controllers at 40 kHz sampling frequency Design Method Voltage Loop Bandwidth Voltage Loop Phase Margin Direct Digital 1.76 kHz 58° Backward Euler 1.43 kHz 57° Bilinear 1.39kHz 54° Pole/Zero Match 1.39 kHz 52° Step Invariant 1.36 kHz 47° With the switching and sampling frequencies increasing to 40 kHz, the system bandwidth with different methods, in sequence from larger to smaller, are still in the same order as in the low frequency cases. However, the difference of the bandwidth with differ-ent controllers is reduced in the voltage loop. The bandwidth of the direct digital controller is 23.1% higher than the Backward Euler and 29.4% higher than the Step Invariant method. In the current loop, the bandwidth is 13.8% higher than that of Backward Euler method and 17.2% higher than that of Step Invariant. Although the difference seems larger than the results of low frequency experiment, it is reduced when compared with low fre-quency simulation results. In the comparison on the system bandwidth above, the direct digital design approach always gives the highest bandwidth on both the current loop and the voltage loop at all frequencies. The difference on double-loop system is bigger than single-loop. The four digital redesign approaches are comparable in terms of the bandwidth as well; that is, Backward Euler gives the largest bandwidth, followed by Pole/Zero Match and 74 Bilinear, and Step Invariant has the narrowest bandwidth. The difference on the bandwidth keeps increasing while the sampling rate is reduced. 5.3 Nonlinear Load Performance Performance at nonlinear load is another indication of the system. The perfor-mance can be measured by voltage distortion. The lower the distortion, the better the per-formance. In the system experiment and simulation, the nonlinear load shown in Fig. 5.12, wi thC 0 = 560pF, RQ = 26.67Q, is applied. Fig. 5.13 are typical output voltage and current waveforms from a nonlinear load. These waveforms represent big distortions in the output voltage and current. The perfor-mance difference of the five design methods will be listed in Table 5.14 by calculating the total harmonic voltage distortion from the experimental waveforms at sampling frequency of 10 kHz and 20 kHz. The total harmonic voltage distortion can be expressed as •0 Fig. 5.12 Nonlinear load for the inverter system V, H THD= , in which V, L-H is the fundamental A C line to neutral voltage; VH is the L-H 75 total line to neutral harmonic voltage VH 2 £ , the upper summation limitation A, =2 of h2 = 10 is chosen for calculation purposes. o > -150 Output Voltage XT i i i 0.2 0.3 Time (s) Fig. 5.13 Experimental nonlinear load output waveform Table 5.14. Total Harmonic Distortion comparison of the five design methods for the inverter system with nonlinear load at different sampling rate Design Method THD at 10 kHz sampling frequency THD at 20 kHz sampling frequency Direct Digital 15.1% 13.5% Backward Euler 15.7% 13.9% Bilinear 15.9% 14.1% Pole/Zero Match 15.9% 14.1% Step Invariant 16.9% 14.7% 76 The same comparison is made on the double-loop system with a switching and sampling frequency of 40 kHz. THDs are calculated from PSIM simulated waveforms, they are: 9.2% for direct digital, 9.6% for backward, 9.7% for Bilinear and Pole/zero Match, and 9.9% for Step Invariant. Direct digital approach has the lowest output voltage THD at all sample frequen-cies that have been tried. When the sampling rate is relatively low, the THD difference among methods increases a little. Backward Euler method has lower THD than other rede-sign methods, but the difference is small. Pole/zero Match method and Bilinear method give the same THD, which is between the Backward Euler and the Step Invariant. These results also verify the system bandwidth differences of the five digital design methods. 5.4 Modeling of the digital controller delay As discussed in Chapter 2, the model which represents the digital controller delay as in Fig. 2.2(b), has some effects on the digital controller design. Using different delay models on the same design method will generate different controllers. In this section, an experiment is performed on a hardware inverter model board to display the influence of the delay model on digital controller design. Fig. 5.14 is the brief schematic of the model board. The model board neglects the switching effect of the inverter while retaining the main dynamic characteristics. An LM3875 amplifier is used to realize the gain from con-trol signal to working voltage. The gain is obtained from taking the ratio of R2 and i?j. Because of the limitation on operating voltage of the amplifier, the model board can only work in a low voltage range. The values of output inductance, capacitor and the load have 77 been modified in order to obtain similar dynamic behavior as the inverter, and the current and voltage controllers are modified slightly to fit for this model board. The current and voltage loop bandwidth of this model system was measured at a sample frequency of 20 kHz with the same equipment. Table 5.15 and Table 5.16 list the designed current and voltage loop bandwidth and phase margin. The measured current and voltage loop bandwidth and phase margin are provided in these two tables for comparison purpose. Model 1 to 3 in Table 5.15 and 5.16 are explained as follows: Fig. 5.14 Brief schematic of the power inverter model Model 1: T delay only, H delay I (s) = e Model 2: Zero-order-hold and T /2 delay, H (*) = l-e 7 > / 2 delay! e s Model 3: Zero-order-hold and 7' delay, H delay3 l - e s 7 8 Table 5.15. Current loop bandwidth and phase margin with different delay models at 20 kHz sampling frequency Model Design Bandwidth Designed Phase Margin Measure Bandwidth Design Phase Margin Model 1 2.3 kHz 60° 2.2 kHz 50° Model 2 2.3 kHz 60° 2.2 kHz 40° Model 3 1.85 kHz 60° 1.8 kHz 40° Table 5.16. Voltage loop bandwidth with different delay models at 20 kHz sampling frequency Model Design Bandwidth Designed Phase Margin Measure Bandwidth Design Phase Margin Model 1 0.8 kHz 65° 0.8 kHz 76° Model 2 0.8 kHz 65° 0.8 kHz 70° Model 3 0.6 kHz 65° 0.6 kHz 73° As seen clearly from Table 5.15 and 5.16, the first two models give us much faster response than the last one. Using Model 1 or model 2 in the digital design not only gener-ates higher bandwidth but also shows reasonable phase margin. The amplitude responses of these two models are almost the same, while Model 1 gives more phase margin than that of Model 2. Model 3 adds dramatic delay to the system, and the system bandwidth is poorly limited. Based on the result we have obtained, model 1 has been used in this project. 5.5 Summary The simulation and experiment results of a DSP-controlled-inverter are presented in this chapter. The performance of five digital control design methods are tested and com-pared as well. From the presented results, some interesting points are as follows: 79 1) . The direct digital design method always gives higher bandwidth and smaller output voltage THD than the redesign methods. 2) . The system performance also varies with different digital redesigned control-lers, and the Backward Euler method is the best among the four discussed rede-sign methods. 3) . The difference in performance is bigger in a double-loop system than that of a single-loop. 4) . The difference also increases while the sampling rate is lower. In addition, the study on the influence of the delay model to the system perfor-mance shows that digital controller obtained with T delay as the delay model gives better performance than the other models. Further conclusions on the development of digital controlled inverter system will be stated in Chapter 6. 80 Chapter 6 Conclusions The work presented in this thesis describes five digital controller design methods for switchmode power converter system application. Design, implementation, and com-parison are made on these methods. The contribution and conclusions of the thesis can be summarized as follows: a) A systematic comparison of different digital controller design methods is car-ried out. Results show that: i) . the direct digital design method out-performs any of the digital redesign methods. The direct digital design method gives a higher bandwidth, and smaller Total Harmonic Distortion in nonlinear loads at all switching and sampling frequencies that have been applied. ii) . Among the digital redesign methods, the Backward Euler transforma-tion methods always gives a slightly better controller, followed by the Pole/ Zero Match and the Bilinear methods. The Step Invariant method is the worst. The Backward Euler also provides the smallest THD in nonlinear load condition among the digital redesign methods. The same results can be drawn at all applied switching and sampling frequencies. 81 iii). The difference of the performance among the design methods becomes greater for the outer loop in a double-loop system and when the sampling rate is lower. This result can be very useful in digital control design for switchmode power converter systems. In these applications, double-loop control structure is mostly used, and the sampling rate can be several times lower than the converter switching frequency, due to the availability of components. b) A modified direct digital design method is proposed. This method makes full use of the advantages of the frequency response method and the root locus method. It can still use the same concept of the gain-cross-over frequency and the gain/ phase margin as in the continuous s-domain, and at the same time achieve an near optimum design with fewer iterations using the root locus method. This method is particularly convenient for practicing engineers who are familiar with the tradi-tional s-domain design methods. Some future work related to this topic will be indicated. The control program in DSP is written in C right now. It is recommended to write the control program in assembly for a commercial product, so that more functions or features can be added, or a low-rate controller can be used. The model used to represent the delay introduced by the digital controller is helpful to get reasonable digital controller. Theoretical study on this issue will benefit the further digital control designs. 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Guidance and Control, Vol. I, No. 5, 1978 [33] M. Brown, "Practical Switching Power Supply", Academic Press, Inc. 1990. 86 Appendix A: Schematic of the DSP Controlled Power Inverter System 88 n *0 Z 75 > Z 3 a n c D O o 3 CL o ft 3 IK o ha r IK o r o D GO O o 3 Q -O o re C/3 C T3 T3 O O o o n s a D o n era + (5 00 3 Appendix B: Controller Software of the DSP The C program is made of five files. The main program is in "invl.c". There are two header files, "regis.h" and "invl.h". Another small assembly program "init.asm" is only for system initialization, "invl.cmd" defines the program and data memory address in F240 DSP. A) "invl.h" file /* invl.c */ /* the main c program for the DSP controlled switchmode power inverter system */ /* header file which defines the registers of the DSP */ #include "regis.h" /* header file which define the inverter system parameters */ #include "invl.h" /* set cpu interrupt vector */ /* two interrupts: timer T l interrupt and NMI interrupt */ asm(" .global _c_intO"); asm(" .sect V'.iniV "); asm(" b cintO "); asm(" retc "); asm(" retc "); asm(" b _c_int2 "); asm(" .sect V'.textV "); /* main program start from here */ mainfj { /* the initialization of the system and program */ init(); /* clear the A D C digital result registers */ bufferl=*ADCFIF01; bufferl=*ADCFIF02; bufferl=*ADCFIF01; buffer 1=*ADCFIF02; /* idle, waiting for timer interrupt */ while(l) { }; }; /* main program ends here */ 90 /* dsp initialization program */ void init() { /* define the system clock as 10MHz and the cpu clock as 20MHz */ /* the 'waitstate' is a system initialization function in init.asm program */ waitstate(); /* initial the status registers stO and stl */ /* enable all unmasked interrupts */ asm(" CLRC INTM"); /* reconfigurable dual-access RAM block are mapped to data space */ asm(" CLRC CNF "); /* enable timer INT2 interrupt and clear the interrupt pending flags */ *IMR=0x0002; *IFR=Oxffff; /* intial the PWM registers */ /*ACTR:0000011001100110=0x0666 */ /* set 3 pwm pares output polarity to be active high/low respectively */ *ACTR = 0x0666; /* DBTCON: 0001100100100000 =0x1920 */ /* enable deadband timer to be 1.25us */ * DBTCON = 0x1920; /* inital a pwm duty ratio to be 0.5 */ *CMPR1 = 500; /* enable full compare output, and set in pwm mode */ /* COMCON: 0000001000000111=0x0207 */ *COMCON = 0x0207; /* start the compar operation */ *COMCON = 0x8207; /* initial the timer T l registers */ /* enable timer T l underflow interrupt */ /*EVIMRA: 0000001000000000= 0x0200 */ *EVIMRA = 0x0200; /* no interrupt poriotity problem */ *EV1VRA= 0x0; /* reset all the pending interrupt flag */ *EVIFRA=0xffff; /* enable timer compare output and set output polarity to be active low */ /*GPTCON: 0000000001000001=0x0041 */ *GPTCON = 0x41; /* set the timer period to be 50us, the corresponding switching frquency is 20kHz */ *T1CMPR = 0; *T1PR = 999; /* enable timer and compare operation */ /* set the timer count mode to be continuous up/dowm count mode, */ /*and reset the counter */ /*TlCON: 0010100001000010 =0x2842*/ *TlCON = 0x1042; *TlCNT = 0x0; /* intial the AD converter registers */ /* enable two AD units, select channal 6 and 14, set the input clock prescler to 20 /* ADCTRL:1001100001011010=0xl85a*/ •ADCTRL1 =0x185a; *ADCTRL2 = 0x0006; /* reset the reference table vector and sample and flag for 10kHz sample rate*/ i=0; f=0; } /* the timer interrupt process */ /* the control algorithm is calculated here */ interrupt void c_int2() { /* just return at this switching period, for 10kHz sample rate */ /*if(f>0) { *PCDATDIR = 0x8080; f=0; *PCDATDIR = 0x8000; } else { f=i; */ /* set I/O port C7 to high, for testing purpose*/ •PCDATDIR = 0x8080; /* start A/D conversion */ *ADCTRL1 =0x385b; /* store the old controller data */ xil=xi0; xvl=xv0; yil=yi0; yvl=yv0; /* some control algorithm calculations, which do not need new AD values */ xil=xil*c4; xvl=xvl*c2; /* get the reference value for this time step */ if(i<167) vr=SIN[i]; else vr=-SIN[i-167]; if(i>333) i=0; /* check whether AD conversion is finished, if not wait for it. */ while(*ADCTRLl &0x80) { }; /* get the input AD result */ /* A/D input voltage range is 0->5v */ /* represents -25A->25A in inverter for current, */ /*-190V->190V for voltage in inverter */ /* the ad converter result -512->+512 after shifting */ buffer 1 = ((* ADCFIFO1 »6)&0x03 ff)-512; vv=bufferl; buffer2= ((*ADCFIFO2»6)&0x03ff)-512; ii=buffer2; /* controller calculations */ /* voltage PI controller, 512 is the parameter scaling effect */ xv0=(vr/4-vv); y vO=y v 1 +(xvO* c 1 -xv 1 )/512; /* set limitation */ if(yv0>16384) yv0=16384; if (yv0<-16384) yv0=-16384; /* current PI controller, 256 is the parameter scaling effect */ xiO=(yvO+ii); yi0=yil+(xi0*c3-xil)/256; /* generate pwm duty ratio, set limitation, and update the compare register vr=yi0/2*3; *CMPRl=vr+500; if(*CMPRl>970) {*CMPR1=970;} if(*CMPRl<30) {*CMPR1=30;} /* send out some important signal to D/A port, for testing */ DAC0_VAL=ii*4+2048; DACl_VAL=vv*4+2048; DAC2_VAL=vr+2048; DAC3_VAL=DAC0_VAL; asm(" OUT _DAC0_VAL,0000h"); asm(" OUT_DAC3_VAL,0001h"); asm(" OUT_DACl_VAL,0002h"); asm(" OUT_DAC2_VAL,0003h"); asm(" OUT_DACl_VAL,0004h"); /* clear the interrupt pending flag */ *EVIFRA=Oxffff; /* set I/O port C7 to low, for testing purpose*/ *PCDATDIR = 0x8000; /*}*/ } /* end of program */ B) "ini.asm" file .global meminit .global waitstate .include f240regs.h Variables Declartion for B2 .bssGPRO,l;General Purpose Register .text meminit ;Dummy function call for demo NOP NOP NOP RET _waitstate SETCINTM ;Disable interrupts LACCIFR;Read Interrupt flags SACLIFR;Clear all interrupt flags CLRCSXM;Clear Sign Extension Mode CLRCOVM;Reset Overflow Mode CLRCCNF;Config Block BO to Data mem LDP #00E0h;DP for addresses 7000h-707Fh SPLK#00BBh,CKCR 1 ;CLKIN(OSC)= 10MHz,CPUCLK=20MHz SPLK#00C3h,CKCR0 ;CLKMD=PLL Enable,SYSCLK=CPUCLK/2 SPLK#40C0h,SYSCR ; C L K O U T = C P U C L K SPLK#006Fh, WDCR;Disable WD if VCCP=5V (JP5 in pos. 2-3) KICK_DOG;Reset Watchdog R E T .end C) "invl.h" file /* invl.h */ /* this the header file that defines the globle constant parameter and varables.*/ /* the parameters of the digital controller */ /* voltage PI controller parameters */ const int c 1=282; /*0.55*512=282*/ const int c2=67; /*0.13*512=67*/ /* current PI controller parameters */ const int c3=358; /* 1.4*256=358*/ const int c4=356; /* 1.39*256=356*/ /* the variables that needed for the system */ int D A C O V A L ; /* data to D/A channal 0 */ int DAC 1_VAL; /* data to D/A channal 1 */ int D A C 2 V A L ; /* data to D/A channal 2 */ int DAC3_VAL; /* data to D/A channal 3 */ int i=0; /* for count purpose.*/ int f=0; /* flag for 10kHz sample rate, 20kHz switching frquency */ int buffer 1=0; /* temperary storage for AD value */ int buffer2=0; /* temperary storage for AD value */ int ii=0; /* the current input */ int vv=0; /* the voltage input */ int vr=0; /* the reference voltage for the system */ long int xv0=0,xvl=0; /* the input data for the voltage controller, xvl is the last data */ long int yv0=0,yvl=0; /* the output data for the voltage controller, yvl is the last value */ long int xi0=0,xil=0; /* the input data for the current controller, xii is the last data*/ long int yi0=0,yil=0; /* the output data for the current controller, y i l is the last data*/ /* sinasoidal reference waveform table, half period */ int SIN[168]={0,34,68,102,136,170,204,237,271,305,338,372,405,438,471,503,536,568, 601,633,664,696,727,758,789,819,850,879,909,938,967,996,1024,1052,1079,1106, 1133,1159,1185,1211,1236,1260,1284,1308,1331,1354,1377,1398, 1420,1440,1461,1481,1500,1519,1537,1554,1571,1588,1604,1619, 1634,1648,1662,1675,1687,1700,1711,1722,1732,1741,1750,1758, 1766,1773,1779,1785,1780,1795,1798,1802,1804,1806,1807,1808, 1808,1807,1806,1804,1802,1800,1795,1790,1785,1780,1773,1766, 1758,1750,1741,1732,1722,1711,1700,1688,1675,1662,1648,1634, 1619,1604,1588,1571,1554,1537,1519,1500,1481,1461,1440,1420, 1398,1377,1354,1331,1308,1284,1260,1236,1211,1185,1159,1133, 1106,1079,1052,1024,996,967,938,909,879,850,819,789,758, 727,696,664,633,601,568,536,503,471,438,405,372,338,305, 271,237,204,170,136,102,68,34,0}; D) "regis.h" file /* regis.h */ /* this is the header file that defines dsp registers */ /*Core Registers*/ int*lMR = (int *) 0x0004; int *GREG = (int *) 0x0005; int*IFR = (int *) 0x0006; /•System Module Registers*/ int *SYSCR = (int *) 0x7018; /* Watch-Dog / Real Time Interrupts / Phase Lock Loop (PLL) Registers int *RTICNTR = (int *) 0x7021; int *WDCNTR = (int *) 0x7023; int *WDKEY = (int *) 0x7025; int *RTICR = (int *) 0x7027; int *WDCR = (int *) 0x7029; int *CKCR0 = (int *) 0x702B; int *CKCR1 = (int *) 0x702D; /* Analog-to-Digital Converter Registers*/ int *ADCTRL1 = (int *) 0x7032; int *ADCTRL2 = (int *) 0x7034; int *ADCFIFOT= (int *) 0x7036; int *ADCFIF02= (int *) 0x7038; /•Digital I/O*/ int *PCDATDIR = (int *) 0x709C; /•General Purpose Timer Registers - Event Manager*/ int *GPTCON = (int *) 0x7400; int*TlCNT = (int *) 0x7401; int *T1CMPR = (int *) 0x7402; int*TlPR = (int *) 0x7403; int*TlCON = (int *) 0x7404; /•Full & Simple Compare Unit Registers - Event Manager*/ int *COMCON = (int *) 0x7411; int*ACTR = (int *) 0x7413; int *SACTR = (int *) 0x7414; int *DBTCON = (int *) 0x7415; int*CMPRl = (int*) 0x7417; int*CMPR2 = (int *) 0x7418; /•Interrupt Registers - Event Manager*/ int •EVIMRA = (int *) 0x742C; int *EVIFRA = (int *) 0x742F; int *EVIVRA = (int *) 0x7432; /*wait state registers */ int*WSGR =(int *) Oxffff; E) " i n v l . c m d " f i l e /* compile options */ -cr -1 rts2xx.lib -stack 256 -heap 256 -o invl.out -m invl.map MEMORY { PAGE0: P F L A S H : origin = 0x0000, length = 0x0040 PAGE 0: PPROGR : origin = 0x0040 length = 0x3 fbO PAGE 0: P E X T R A M : origin = 0x4000, length = OxbeOO PAGE 0: P_B0_RAM: origin = OxfeOO, length = 0x0100 /* If CNF=1 */ PAGE 1: D B 2 R A M : origin = 0x0060, length = 0x0020 PAGE 1: D B 0 R A M : origin = 0x0200, length = 0x0100 /* If CNF=0 */ PAGE 1: D B 1 R A M : origin = 0x0300, length = 0x0100 PAGE 1: D E X T R A M : origin = 0x8000, length = 0x8000 } SECTIONS { .ini: > P F L A S H , PAGE = 0 /* DEFINE THE INTERRUPT VECTORS */ .text : > PPROGR , PAGE = 0 /* initialized - executable code */ .cinit: > P E X T R A M , PAGE = 0 /* initialized - initialization tables */ .switch: > P E X T R A M , PAGE = 0 /* initialized - switch tables */ .const: > D B 2 R A M , PAGE = 1 /* initialized - constants */ .bss : > D B 0 R A M , PAGE = 1 /* uninitialized - global variables */ .stack : > D B 1 R A M , PAGE = 1 /* uninitialized - system stack */ .sysmem: > D_B1_RAM , PAGE = 1 /* uninitialized - sytem heap */ .data : > D E X T R A M , PAGE = 1 /* not needed for C programs */ }
Thesis/Dissertation
1999-11
10.14288/1.0064811
eng
Electrical and Computer Engineering
Vancouver : University of British Columbia Library
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Graduate
Digital control loop for power converter systems
Text
http://hdl.handle.net/2429/9304