Applied Science, Faculty of
Non UBC
Electrical and Computer Engineering, Department of
DSpace
Applied Sciences 12 (1): 89 (2022)
Chen, Ruiqi
Wu, Tianyu
Zheng, Yuchen
Ling, Ming
In Internet of Things (IoT) scenarios, it is challenging to deploy Machine Learning (ML) algorithms on low-cost Field Programmable Gate Arrays (FPGAs) in a real-time, cost-efficient, and high-performance way. This paper introduces Machine Learning on FPGA (MLoF), a series of ML IP cores implemented on the low-cost FPGA platforms, aiming at helping more IoT developers to achieve comprehensive performance in various tasks. With Verilog, we deploy and accelerate Artificial Neural Networks (ANNs), Decision Trees (DTs), K-Nearest Neighbors (k-NNs), and Support Vector Machines (SVMs) on 10 different FPGA development boards from seven producers. Additionally, we analyze and evaluate our design with six datasets, and compare the best-performing FPGAs with traditional SoC-based systems including NVIDIA Jetson Nano, Raspberry Pi 3B+, and STM32L476 Nucle. The results show that Lattice’s ICE40UP5 achieves the best overall performance with low power consumption, on which MLoF averagely reduces power by 891% and increases performance by 9 times. Moreover, its cost, power, Latency Production (CPLP) outperforms SoC-based systems by 25 times, which demonstrates the significance of MLoF in endpoint deployment of ML algorithms. Furthermore, we make all of the code open-source in order to promote future research.
Citation: Chen, R.; Wu, T.; Zheng, Y.;Ling, M. MLoF: Machine LearningAccelerators for the Low-Cost FPGAPlatforms. Appl. Sci. 2022, 12, 89.https://doi.org/10.3390/app12010089Academic Editors: Deliang Fan andZhezhi HeReceived: 2 November 2021Accepted: 16 December 2021Published: 22 December 2021Publisher’s Note: MDPI stays neutralwith regard to jurisdictional claims inpublished maps and institutional affil-iations.Copyright: © 2021 by the authors.Licensee MDPI, Basel, Switzerland.This article is an open access articledistributed under the terms andconditions of the Creative CommonsAttribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).applied sciencesArticleMLoF: Machine Learning Accelerators for the Low-CostFPGA PlatformsRuiqi Chen 1 , Tianyu Wu 1,2 , Yuchen Zheng 3 and Ming Ling 4,*1 VeriMake Innovation Lab, Nanjing Renmian Integrated Circuit Co., Ltd., Nanjing 210088, China;rickychen@verimake.com (R.C.); twu15@ece.ubc.ca (T.W.)2 Department of Electrical and Computer Engineering, University of British Columbia,Vancouver, BC V6T 1Z4, Canada3 Department of Computer Science, University of North Carolina at Chapel Hill, Chapel Hill, NC 27514, USA;felix02@email.unc.edu4 National ASIC System Engineering Technology Research Center, Southeast University, Nanjing 210096, China* Correspondence: trio@seu.edu.cnAbstract: In Internet of Things (IoT) scenarios, it is challenging to deploy Machine Learning (ML)algorithms on low-cost Field Programmable Gate Arrays (FPGAs) in a real-time, cost-efficient, andhigh-performance way. This paper introduces Machine Learning on FPGA (MLoF), a series of ML IPcores implemented on the low-cost FPGA platforms, aiming at helping more IoT developers to achievecomprehensive performance in various tasks. With Verilog, we deploy and accelerate ArtificialNeural Networks (ANNs), Decision Trees (DTs), K-Nearest Neighbors (k-NNs), and Support VectorMachines (SVMs) on 10 different FPGA development boards from seven producers. Additionally, weanalyze and evaluate our design with six datasets, and compare the best-performing FPGAs withtraditional SoC-based systems including NVIDIA Jetson Nano, Raspberry Pi 3B+, and STM32L476Nucle. The results show that Lattice’s ICE40UP5 achieves the best overall performance with lowpower consumption, on which MLoF averagely reduces power by 891% and increases performanceby 9 times. Moreover, its cost, power, Latency Production (CPLP) outperforms SoC-based systems by25 times, which demonstrates the significance of MLoF in endpoint deployment of ML algorithms.Furthermore, we make all of the code open-source in order to promote future research.Keywords: Internet of Things; machine learning; embedded system; FPGA; hardware accelerator1. IntroductionMachine Learning (ML) algorithms are effective and efficient in processing Internet ofThings (IoT) endpoint data with well robustness [1]. As data volumes grow, IoT endpointML implementations have become increasingly important. Compared to the traditionalcloud-based approaches, they can compute in real-time and reduce the communicationoverhead [2]. There are some researches deploying ML algorithms on System on Chip (SoC)based endpoint devices in industry and academia. For example, the TensorFlow Lite [3],X-CUBE-AI [4], and the Cortex Microcontroller Software Standard Neural Network (CMSIS-NN) [5] are three frameworks proposed by Google, STM, and ARM for pre-trained modelsin embedded systems. However, these solutions cannot achieve a balance among powerconsumption, cost-efficiency, and high-performance simultaneously for IoT endpoint MLimplementations.Field Programmable Gate Array (FPGA) devices have an inherently parallel archi-tecture that makes them suitable for ML applications [6]. Moreover, some FPGAs havesubstantially close costs and leakage power compared to those of Microcontroller Unit(MCU). Therefore, FPGA can be an ideal target platform for IoT endpoint ML implementa-tions. Nowadays, some researches and supports have been done for the deployment ofML algorithms on FPGAs. For instance, the ongoing AITIA, led by the Technical Univer-sity of Dresden, KUL, IMEC, VUB, etc. [7], is a preliminary project that investigated theAppl. Sci. 2022, 12, 89. https://doi.org/10.3390/app12010089 https://www.mdpi.com/journal/applsciAppl. Sci. 2022, 12, 89 2 of 27feasibility of ML implementations on FPGAs. On the other hand, in the industry, Xilinxand Intel have supported portions of the machine learning based Intellectual Property (IP)cores [8–11]. Unfortunately, these solutions are based on high-end FPGAs and requirehighly professional standards. It is difficult for many small and medium-sized corporationsand individual developers to deploy their hardware platforms. Therefore, an ML librarythat can run on any FPGA platform is needed [12], especially those low-cost FPGAs. Low-cost FPGAs do not mean they have the lowest absolute value among all FPGAs, instead,they refer to the lowest-priced FPGA series in the most representative manufacturers.Meanwhile, the lack of comprehensive comparisons makes it difficult to demonstrate thebenefits of FPGA ML implementations over conventional SoC-based solutions.Therefore, we introduce Machine Learning on FPGA (MLoF) with a series of IP coresdedicated to low-cost FPGAs. The MLoF IP-cores are developed in Verilog HardwareDescription Language (HDL) and can be used to implement popular machine learningalgorithms on FPGAs, including Support Vector Machines (SVMs), K-Nearest Neighbors(k-NNs), Decision Trees (DTs), and Artificial Neural Networks (ANNs). The performanceof seven FPGA producers (Anlogic *2, Gowin *1, Intel *2, Lattice *2, Microsemi *1, Pango*1, and Xilinx *1) is thoroughly evaluated using low-cost platforms. As far as we know,MLoF is the first case to implement machine learning algorithms on nearly every low-cost FPGA platform. Compared with the typical way of implementing machine learningalgorithms on embedded systems, including NVIDIA Jetson Nano, Raspberry Pi 3B+,and STM32L476 Nucle, the advantage of MLoF is that it balances the cost, performance,and power consumption. Moreover, these IP cores are open-source, assisting developersand researchers in more efficient implementation of machine learning algorithms on theirendpoint devices.The contributions of this paper are as follows:(1) To the best knowledge of the authors, this is the first time that four ML hardwareaccelerator IP-cores are generated using Verilog HDL, including SVM, k-NN, DTsand ANNs. The source code of all IP-cores is fully disclosed at github.com/verimake-team/MLonFPGA;(2) The proposed IP-cores are deployed and validated on 10 mainstream low-cost andlow-power FPGAs from seven producers to show its broad compatibility;(3) Our designs are comprehensively evaluated on FPGA boards and embedded systemplatforms. The results prove that low-cost FPGAs are ideal platforms for IoT endpointML implementations;The rest of this paper is organized as follows: Section 2 reviews prior work on thehardware implementations of machine learning algorithms. Section 3 introduces detailsof the proposed MLoF IP series. Section 4 provides a comparison of various FPGA devel-opment platforms. Section 5 contains experiments and analyses. Section 6 concludes theresearch results and future works.2. Related WorkFor decades, the implementations of machine learning algorithms on low-cost embed-ded systems have been vigorously investigated. Due to the limited computing resourceson embedded systems, these approaches tend to lack outstanding performance. However,FPGA is an effective solution for machine learning algorithms [13]. Saqib et al. [14] pro-posed a decision tree hardware architecture based on FPGA. It improves data throughputand resource utilization efficiency by utilizing parallel binary decision trees and a pipeline.A 3.5× computing speed is achieved while only 2952 Look-up Tables (LUTs) of resourcesare consumed via an 8-parallelism 4-stage pipeline. Nasrin Attaran et al. [15] proposed abinary classification architecture based on SVM and k-NN. Over 10× computing speed and200× power-delay are obtained as compared with ARM A53. Gracieth et al. [16] proposeda 4-stage, low-power SVM pipeline architecture capable of achieving 98% of accuracy onover 30 classification tasks. It consumes only 1315 LUTs of resources and operates at asystem frequency of 50 MHz. The aforementioned works introduce the deployment of MLAppl. Sci. 2022, 12, 89 3 of 27algorithms on FPGA platforms, but there are still deficiencies: 1. None of the works inte-grate the mainstream ML algorithms for FPGA deployment; 2. None of the works comparethe final results horizontally with other embedded platforms of various IoT terminals.Due to the high inherent parallelism in FPGAs, more advanced machine learningalgorithms, such as neural networks, are widely studied. Roukhami M et al. [17] proposeda Deep Neural Network (DNN) based architecture for classification tasks on low-powerFPGA platforms. They thoroughly compared the performance with STM32 ARM MCUand designed a general communication interface for accelerators, such as SPI and UART.The entire acceleration process consumes only 25.459 mW of power with a latency of 1.99 s.Chao Wang et al. [18] proposed a Deep Learning Accelerating Unit (DLAU) that acceleratesneural networks, e.g., DNN and CNN. Additionally, they developed an AXI-Lite interfacefor the acceleration unit to enhance its versatility. In general, the DLAU outperformsCortex-A7 by 67%. Fen Ge et al. [19] developed a resource-constrained CNN acceleratorfor IoT endpoint SoCs that does not require any DSP resources. With a total resourceoverhead of 4901 LUTs, the data throughput reaches 6.54 GOP (Giga Operation per second).The above works present neural network-based FPGA deployments, but none of them isdesigned for low-cost FPGAs, which are oftentimes the most prevalent platforms used forIoT endpoints.Although the previous works succeed in increasing the capability of endpoint com-puting by implementing only one or two machine learning algorithms on FPGAs, furtheranalyses and comprehensive comparisons across low-cost FPGA platforms, as well as theintegration of more commonly used machine learning algorithms are still required.3. Machine Learning Algorithms Implementation on Low-Cost FPGAsNormally, the post-process of IoT data mainly focuses on two tasks: Classificationsand regressions [20]. By exploiting the parallelism and low power consumption of FPGAs,MLoF offers a superior solution for these workloads. Drawn from past designs, MLoF isdesigned with lower computation resources, and it includes a variety of common machinelearning algorithms, namely ANN, DT, k-NN, and SVM. Details will be further presentedin this section.As shown in Figure 1, the system has consisted of the training and the MLoF modulesas most machine learning models are used for inferencing and evaluating within IoT deviceswithout requiring extensive training [21], all of the model training process is completedthrough PC. First, the IoT dataset is gained from the endpoints and will be sent to thetraining module. Then, an ML library (e.g., Scikit-Learn and TensorFlow Lite) [22] and anML algorithm should be chosen as the first level of parameters. Thereafter, a set range ofhyperparameters (the same set as in the MLoF module) are used to constrain the PC trainingprocess, as FPGA has limited local resources. Since hyperparameters are key features inML algorithms [23–25], users could set them to different values to find the best sets fortraining according to Table 1. Next, with all the labeled data and hyperparameters, the bestmodel and the best parameters (including the updated hyperparameters) are generatedand sent to the MLoF module. After receiving and storing the parameters into ROM orexternal Flash, the algorithm is deployed on an FPGA. The language of FPGA is mainlyVerilog HDL, thus the algorithms can literally be deployed on any known FPGA platform.Appl. Sci. 2022, 12, 89 4 of 27Figure 1. Block diagram of the MLoF system architecture.Table 1. Configurable parameters.ANN DT k-NN SVMData width (max = 13);Number of inputs(max = 16); Data width (max = 13); Data width (max = 13); Data width (max = 13);Number of hiddenlayers (max = 4);Number of depth(max = 6);Number of inputs(max = 16);Number of inputs(max = 16);Number of neurons ineach hidden layer(max = 8);Number of leaf nodes(max = 64);Number of neighbors(max = 16);Number of targets(max = 16)Number of targets(max = 16);Number of targets(max = 16)Number of targets(max = 16)Activation functionsIn this paper, we selected six datasets, the four most representative ML algorithms, anddeployed them on 10 low-cost FPGAs, with a total of 240 combinations. The experimentsand evaluations are described in detail in Section 5.3.1. Artificial Neural Networks (ANN)3.1.1. Overall Structure of ANNThe implementation of ANN, for example, with eight inputs and two hidden layers(eight neurons within each layer) is shown in Figure 2a. This ANN model includes aMemory Unit (Mem), a Finite State Machine (FSM), eight Multiplying Accumulator (MAC)computing units, Multiplexers (MUX), an Activation Function Unit (AF), and a Buffer Unit(BUFFER). The Memory Unit (Mem) stores the weights and biases after training. The FSMmanages the computation order and the data stream. The MAC units are designed withmultipliers, adders, and buffers for multiplying and adding operations within each neuron.Here, we implement eight MAC blocks to process in parallel the multiplication of the eightneurons. Initially, features are serially entered for registration. Then, the MAC is used tosequentially process the ANN from the first input feature to the eighth feature on the firstAppl. Sci. 2022, 12, 89 5 of 27hidden layer (Figure 2b). Next, the second hidden layer is sequentially processed from thefirst hidden neuron to the eighth neuron. Finally, we process the output by the activationfunction. As demonstrated in Figure 3, the multiplexers (MUX) allocate the data stream.The AF computes the activation functions, which will be discussed in Section 3.1.2. Thebuffer stores data computed from each neuron.Figure 2. ANN algorithm implementation. (a) Block diagram of ANN. (b) Scheduling of theANN processing.Figure 3. Block diagram of MAC.The entire procedure for performing a hardware-based ANN architecture is describedbelow. First, eight features are serially inputted to an ANN model. Each feature is enteredinto eight MAC units simultaneously and multiplications for eight neurons in the first layerare then completed. An inner buffer is used to store the multiplication results. Next, alleight results are added to a user-specified activation function. The output is further storedin the buffer unit as the input of the next hidden layer. Finally, the results are exportedfrom the output layer following the second hidden layer.3.1.2. Activation FunctionThe activation function is required within each neuron, which introduces non-linearityinto the ANN, resulting in better abstract capability. Three typical activation functionsinclude the Rectified Linear Unit (ReLU), the Hyperbolic Tangent Function (Tanh), andthe Sigmoid Function [26]. All of three activation functions listed above are developed inhardware, and details are described as follows.Rectified Linear Unit (ReLU)The mathematical representation of the ReLU is described as Equation (1):ReLU(x) ={x, x > 00, x ≤ 0 (1)Appl. Sci. 2022, 12, 89 6 of 27The hardware implementation is shown in Figure 4 with a comparator and a multi-plexer [27]:Figure 4. Block diagram of ReLU.Hyperbolic Tangent Function (Tanh)The mathematical representation of the Tanh function is described as Equation (2):Tanh(x) =ex − e−xex + e−x (2)This cannot be achieved directly in the hardware using HDL. Therefore, we fit thisfunctionality separately with five sub-intervals [28]. We divide the interval of [0, +∞] intofive sub-intervals: [0, 1], (1, 2], (2, 3], (3, 4], (4, +∞). Table 2 contains the heuristic functionsused to fit the Tanh function for each sub-interval. The performance of each sub-interval isshown in Figure 5 with an error kept within an acceptable range. The sub-intervals enablethe Tanh function to be implemented using only adders and multipliers.Table 2. Fitting function at different intervals.Numerical Interval Function Absolute Error[0, 1] y = −0.3275x2 + 1.0977x− 0.0038 0.0038(1, 2] y = −0.1690x2 + 0.7021x + 0.2324 0.0039(2, 3] y = −0.0282x2 + 0.1703x + 0.7370 0.0055(3, 4] y = −0.0039x2 + 0.0313x + 0.9363 0.0101(4, +∞ ) 1 /Sigmoid FunctionThe mathematical representation of the Sigmoid function is described as Equation (3):Sigmoid(x) =11 + e−x (3)Appl. Sci. 2022, 12, 89 7 of 27Similar to the Tanh function, the Sigmoid function cannot be implemented directlyin the hardware using HDL, as well. The Sigmoid function is equivalent to the tanhfunction [29] when the transformation in Equation (4) is applied:Sigmoid(x) =Tanh(x/2)+ 12(4)This transformation can be implemented easily on the hardware using a shift operationand an adder based on the tanh function.Figure 5. The images of the fitting effect of these functions. (a) Numerical interval [0, 1]. (b) Numericalinterval (1, 2]. (c) Numerical interval (2, 3]. (d) Numerical interval (3, 4].3.2. Decision Tree (DT)Figure 6 illustrates the implementation of DT with multiple inputs, a depth of four,and a maximum of eight nodes on each layer. The DT consists of a Memory Unit (Rom),a Finite State Machine (FSM), eight compare units, and a dispatcher. The memory unit isused to store nodes’ parameters from PC training. The FSM is used to determine whichinput node to use next based on the output. The compare unit serves as the selecting node.The distributor is used to distribute the input to each node.3.3. The k-Nearest Neighbors (k-NN)3.3.1. Overall Structure of k-NNThe k-NN method is used to classify the samples based on their distances. In this case,we use the squared Euclidean distance as defined in Equation (5). The structure of k-NN isdemonstrated in Figure 7 with an example of eight inputs and a k-value of 6. It consists ofa Memory Unit (Mem), a Finite State Machine (FSM), a subtractor, a multiplier, a buffer, anadder, and a Sorting Network and Label Finder (SNLF) module.d =8∑i=1(xi − yi)2 (5)Appl. Sci. 2022, 12, 89 8 of 27Figure 6. DT algorithm implementation. (a) The sample decision tree. (b) Block diagram of DT.(c) Scheduling of the DT processing.Figure 7. The k-NN algorithm implementation. (a) Block diagram of k-NN. (b) Scheduling of thek-NN processing.3.3.2. Structure of Sort Network and Label Finder ModuleThe Sorting Network and Label Finder (SNLF) is a key module that completes thesorting operation of distance and then outputs the classification or prediction results. Itbalances the pipeline and parallel execution with a ping-pong operation. As shown inFigure 8, this module consists of three parts, MUX, comparators, and cache registers. Themux was used to control di transmit in different clock cycles. The comparator was usedfor comparison with the new di and for storing dis in cache registers. There were 12 cacheregisters (Ox and Ex) used for storing di, as shown in Figure 7b. Specifically, Ox registerswere used to store the six smallest dis in ‘odd’ clock cycles. Ex registers were used to storeAppl. Sci. 2022, 12, 89 9 of 27the six smallest dis in ‘even’ clock cycles. The ping-pong cache was used to rank the di indifferent clock cycles for the SNLF. From those dis, six could be identified to be the smallest.Initially, we set the register’s value to the maximum. The di value was compared with eachOx’s value when the clock cycle was jth (j = 3,5 . . . ) period. If the di value was bigger thaneach Ox’s values in the next period, it would be dropped. Otherwise, the di value wasinserted into Ox and the biggest value in six Ox’s would be dropped. Similarly, the Ex’svalues were updated in (j + 1)th (j + 1 = 4,6 . . . ) period. The cycles were repeated until allof the 600 training samples had been calculated with input features. Finally, we compareall the 12 registers to get the smallest six values. The result was voted from the smallest sixvalue of registers.Figure 8. Block diagram of SNLF.3.4. Support Vector Machine (SVM)The SVM (with eight inputs) is composed of Memory Units (Mem), the Finite StateMachine (FSM), multipliers, adders, and multiplexers. The pre-trained support vectors arestored in the memory unit. The FSM controls the order of output data and the runningprocess. The FSM controlling process is mainly used in multi-class classification, where thesupport vector and bias are updated recursively within the structure shown in Figure 9.Multipliers and adders complete the support vector calculation in Equation (6), and themultiplexer is used for the sign function.f (x) = sign(8∑i=1(Si·Feature) + B)(6)Figure 9. SVM algorithm implementation. (a) Block diagram of SVM. (b) Scheduling of the SVM processing.4. Comparison of Development PlatformsThe specifications of 10 different FPGA platforms from seven different producers arethoroughly analyzed. The key features of these FPGA cores are listed in Table 3. It is worthAppl. Sci. 2022, 12, 89 10 of 27noting that Intel MAX and Xilinx Artix-7 FPGA have the richest LUTs and DSPs, whichare beneficial for the parallel implementation of multi-input machine learning algorithms.Additionally, on-chip Random Access Memory (RAM) resources are important. Otherwise,a large amount of pre-trained data must be pre-fetched from memory to the cache andlimited LUTs resources cannot be used as buffers to cache data during the calculation.Pango PGL12G, Lattice MachXO2, and Anlogic EG4S20 all have limited RAM capacitances.Anlogic EG4S20 has an internal SDRAM module that satisfies the need for additionalcaching. In addition, static power consumption is a critical metric for endpoint platforms,and Anlogic FPGAs, Intel Cyclone 10LP, and Microchip M2S010 perform well in this regard.Moreover, two Lattice FPGA platforms consume the least static power, which is quitecompetitive for endpoint implementations. Finally, both Anlogic EF2M45 and MicrochipMS010 are equipped with an internal Cortex-M3 core, which significantly improves theirgeneral performance in terms of driving external devices and communication.Table 3. The resource of 10 different FPGAs.Producer Device LUTs DSPs RAM Static Current(mA at 12 V, 25 ◦C) DistinctionAnlogicEF2M45 4480 15 700 Kb 5 Inside Cortex-M3 unitEG4S20 19,600 29 156.8 Kb 5 Inside SDRAM unitGowin GW2A 20,736 48 828 Kb 35 /IntelCyclone10LP10CL 6272 30 270 Kb 5 Low-power designMAX10M50DAF 49,760 144 1638 Kb 35 /LatticeICE40UP5 5280 8 128 Kb 0.075 Ultra low-powerdesignMachXO2 6864 / 92 Kb 0.08 Low-power designMicrochip M2S010 12,084 22 512 Kb 6.9 Inside Cortex-M3 unitPango PGL12G 12,480 20 85 Kb 13 /Xilinx Artix-7 33,280 240 1800 Kb 14 /On-board resources, external interfaces, and prices are the three main discriminativeFPGA features that the developers pay most attention to. Therefore, in Table 4, we presentthe features of 10 FPGAs from seven producers.Table 4. The specification of 10 different FPGA boards.Producer Device Manufacturer Board Name Memory Interface PriceAnlogicEF2M45 NanjingRenmianIntegratedCircuitSparkroad-M / / $25.9EG4S20 Sparkroad SPI Flash,microSDADC, VGA,DVP Arduino,Raspberry Pi$49.9Gowin GW2A MYMINIEYE Combat DDR3, SPIFlash, microSDRJ45, HDMI,MIPI $169IntelCyclone10LP10CL QMTECH Starter Kit SDRAM, SPIFlash ADC, MIPI $49.9MAX10M50DAF Terasic DE10-Lite SDRAM, VGA,Accelerometer $85LatticeICE40UP5 TinyFPGA TinyFPGA BX SPI Flash / $38MachXO2 STEPFPGA STEP-MXO2 / / $29.9Appl. Sci. 2022, 12, 89 11 of 27Table 4. Cont.Producer Device Manufacturer Board Name Memory Interface PriceMicrochip M2S010 Trenz electronic SMF2000 SDRAM, SPIFlash / $59.9Pango PGL12G ALINXPGL12GDevelopmentBoardSDRAM, SPIFlashADC, HDMI,MIPI $52Xilinx Artix-7 QMTECHArtix-7DevelopmentBoardSDRAM, SPIFlash ADC, MIPI $79.9All seven producers develop their own Electronic Design Automation (EDA) software,among which Lattice develops a completely different EDA software for different devices.In addition, the final resource consumption is determined by synthesis tools. Most of theseven producers use either their own synthesis tools or Synplify [30], but the latter requiresan individual supporting license. Table 5 summarizes the relative information of sevenproducers. It is worth noting that Lattice’s iCEcube2 and Lattice Diamond are for ICE40UP5and MachXO2 development respectively, and thus they cannot share the same EDA.Table 5. The specification of EDA software.Producer EDA Software Synthesis Tool AvailabilityAnlogic Tang Dynasty TD Integrated Synthesis CommercialGowin GOWIN EDA GowinSynthesis/Synplify CommercialIntel Quartus Prime Quartus IntegratedSynthesis Free License/CommercialLatticeiCEcube2 Synplify Pro Free License/CommercialLattice Diamond Lattice Synthesis Engine Free License/CommercialMicrochip Libero SoC Synplify Pro ME CommercialPango Pango Design Suite ADS/Synplify CommercialXilinx Vivado Xilinx SynthesisTechnology Free License/Commercial5. Experimental Analysis and ResultTo evaluate the performance of these IPs, we select six typical IoT endpoint datasets fordifferent parameter combinations and tests. As shown in Table 6, the datasets include binaryclassifications, multi-classifications, and regressions. The Gutter Oil dataset proposedby VeriMake Innovation Lab aims to detect gutter oils [31], and contains six input oilfeatures, including the pH value, refractive index, peroxide value, conductivity, pH valuedifferences under different temperatures, and conductivity value difference under differenttemperatures. This dataset can serve both in a dichotomous and a polytomous way. TheSmart Grid dataset for conducting research on electrical grid stability is from KarlsruherInstitut für Technologie, Germany [32,33]. This is a dichotomous dataset with 13 inputfeatures used to determine whether the grid is stable under different loads. The WineQuality dataset is proposed by the University of Minho [34] for classifying wine quality.This is a polytomous dataset, with 11 input dimensions (e.g., humidity, light, etc.), ratingwines on a scale of 0 to 10. The rain dataset by the Bureau of Meteorology, Australia, is basedon datasets of different weather stations for recording and forecasting the weather [35].This is a dataset for regression prediction, using eight input parameters, such as wind,humidity, and light intensity to predict the probability of rain. Power Consumption is anopen-source dataset created by the University of California, Irvine. It tracks the total energyconsumption of various devices within families [36].Appl. Sci. 2022, 12, 89 12 of 27Table 6. Dataset specifications.Dataset Number of Input Features TypeGutter Oil 6 Binary classificationSmart Grid 13 Binary classificationGutter Oil 6 Multiclass classification 6Wine Quality 11 Multiclass classification 11Rain 8 RegressionPower Consumption 7 RegressionWe use a desktop PC with a 2.59 GHz Core i7 processor to train various models on thesix datasets and export the best parameters with the best scores obtained during training.For binary classifications and multiclass classifications, the scores represent the classifica-tion accuracies. For linear regressions, the scores represent R2 [37]. Then, these trainedparameters are fed to our machine learning IPs and implemented on 10 different FPGAboards using EDAs from seven different candidate producers. Each EDA is configured tooperate in the balanced mode with identical constraints. As shown in Table 5, part of theEDAs is integrated with synthesis tools, such as Gowin and Pango. However, as Synplifyrequires an individual supporting license, in this paper, only their self-developed synthesistools (GowinSynthesis, ADS) are used for analyzing FPGA implementations. The analysisof FPGA implementations is not limited to the computing performance, but encompassesall aspects of the hardware. While Power Latency Production (PLP) [38] is a commonmetric for evaluating the results of FPGA implementations, it does not consider the cost,which is a critical factor in IoT endpoint device development. As a result, we introduce theCost Power Latency Production (CPLP) as an additional metric for evaluating the results.In addition, we realize the same machine learning algorithms and parameters to theNvidia Jetson Nano 2, the Raspberry Pi 3B+, and STM32L476 Nucleo, respectively [39], al-lowing for more comprehensive comparisons of the implementations within different FPGAs.5.1. ANN5.1.1. ANN Parameter AnalysisWe intend to find the best user-defined ANN parameters in six datasets, including thenumber of hidden layers, neurons within each layer, and activation functions. Differentcombinations of these parameters are used to train our ANN model on the desktop PCand their corresponding results are shown in Appendix A, Table A1. There are only minordifferences among all the combinations. We chose to apply parameters with the best scorefrom the software to our hardware implementation. The hyperparameter values associatedwith the best scores for these datasets processed using the ANN algorithm are shown inTable 7.Table 7. The highest-scoring parameters of ANN obtained in different datasets.Dataset Score ANNArchitecturesActivationFunctionBinaryclassificationGutter Oil 97.14% [4,4,4] SigmoidSmart Grid 98.73% [4,4,4] TanhMulticlassclassificationGutter Oil 97.09% [8,8,8] TanhWine Quality 73.01% [8,8,8,8] SigmoidRegressionRain 0.8583 (R2) [8,8,8,8] ReLUPowerConsumption 0.9979 (R2) [8,8] SigmoidAppl. Sci. 2022, 12, 89 13 of 275.1.2. Implementation and Analysis of ANN HardwareBased on the ANN architectures in Table 7, we use the corresponding EDA (with theBalanced Optimization Mode in Synthesis Settings) to implement ANN on 10 differentFPGA boards. The results are summarized in Appendix A, Table A2. In terms of com-puting performance (latency), Intel MAX10M50DAF outperforms the others in five out ofsix datasets, while PGL12G outperforms the competition in the Rain task. The performancedifferences in time delay between 10 FPGAs are all at the millisecond level, which canalmost be ignored. For the comprehensive comparisons, Lattice’s ICE40UP5 has achievedfirst place in most application scenarios for its extremely low power consumption andcost-effectiveness among most of the datasets (five out of six). One exception is that inthe Wine Quality task scenario, it was not implemented on ICE40UP5 due to the resourceconstraint. In addition, the device that performed the best on the Wine Quality task wasLattice MachXO2. The FPGA deployment results with the best comprehensive performanceunder each task are shown in Table 8.Table 8. ANN deployment results on the best CPLP-performing FPGAs.Dataset Device Score LUTs DSPs Latency/us Power/mW PLP CPLPBinaryclassificationGutter Oil ICE40UP5 97.14% 1898 8 11.12 140 1556.10 59,131.80Smart Grid ICE40UP5 98.73% 1855 8 11.12 140 1556.10 59,131.80MulticlassclassificationGutter Oil ICE40UP5 97.09% 3887 8 11 140 1540 58,520Wine Quality MachXO2 73.01% 6114 / 12.73 192 2444.54 73,091.87Regression Rain ICE40UP5 0.8583 (R2) 3553 8 8.73 135 1178.69 44,790.03PowerConsumption ICE40UP5 0.9979 (R2) 3653 8 11.98 140 1676.50 63,7075.2. DT5.2.1. Analysis of DT ParametersFor PC simulations, 12 different combinations of the maximum depth and the maxi-mum number of leaf nodes are chosen. The results are shown in Appendix A, Table A3.Different DT structures produce nearly identical results. Adding the maximum depth andthe maximum number of leaf nodes has no significant improvement on the score. Here, wechose the best results from various combinations for hardware deployment, and the resultswith the best scores for the six datasets are shown in Table 9.Table 9. The highest-scoring parameters of DT obtained in different datasets.Dataset Score Max Depth Max Leaf NodesBinaryclassificationGutter Oil 96.18% 5 16Smart Grid 97.98% 4 8MulticlassclassificationGutter Oil 96.85% 6 32Wine Quality 83.69% 4 16Regression Rain 0.8481 (R2) 4 8Power Consumption 0.9976 (R2) 6 645.2.2. Implementation and Analysis of DT HardwareBased on the DT architectures in Appendix A, Table A4, we use the appropriateEDA (with the Balanced Optimization Mode in Synthesis Settings) to implement DT on10 different FPGA boards. In terms of computing performance, Intel MAX10M50DAFoutperforms the competition in all six datasets. While in terms of comprehensiveness,Lattice’s ICE40UP5 came to first place again in most application scenarios for its extremelylow power consumption and cost-effectiveness. The FPGA DT deployment results with thebest comprehensive performance under each task are shown in Table 10.Appl. Sci. 2022, 12, 89 14 of 27Table 10. DT deployment results on the best CPLP-performing FPGAs.Dataset Device Score LUTs DSPs Latency/us Power/mW PLP CPLPBinaryclassificationGutter Oil ICE40UP5 96.18% 451 0 7.92 133.90 1060.76 3882.38Smart Grid ICE40UP5 97.98% 285 0 5.87 122 716.14 2873.01MulticlassclassificationGutter Oil ICE40UP5 96.85% 715 0 7.92 135 1069.47 3876.36Wine Quality ICE40UP5 83.69% 305 0 5.60 121 677 2740.86Regression Rain ICE40UP5 0.8481 (R2) 303 0 5.80 121 701.80 2838.75PowerConsumption ICE40UP5 0.9976 (R2) 765 0 9.65 128 1235.46 4723.105.3. K-NN5.3.1. Analysis of k-NN ParametersIn our k-NN model, the parameter k is user-defined. We experiment with variousk values when training our model on the PC, and the results are shown in Appendix A,Table A5. The increment of k has no significant effect on the score. In fact, on the contrary,it might decrease them. We deploy the architecture that is optimal in terms of k value forhardware deployment. The hyperparameter values associated with the best scores for thesedatasets processed using the k-NN algorithm are shown in Table 11.Table 11. The highest-scoring parameters of k-NN obtained in different datasets.Dataset Score k ValuesBinary classification Gutter Oil 99.36% 2Smart Grid 79.39% 16MulticlassclassificationGutter Oil 99.36% 2Wine Quality 81.23% 8Regression Rain 0.8527 (R2) 16Power Consumption 0.9960 (R2) 25.3.2. Implementation and Analysis of k-NNAccording to the k parameters analyzed in Section 5.3.1, we implement our modelon 10 FPGA boards (with the Balanced Optimization Mode in Synthesis Settings). Thecorresponding results are shown in Appendix A, Table A6. Gowin’s GW2A has the bestcomputing performance in all of the task scenarios. By relying on extremely low powerconsumption and cost-effectiveness, Lattice’s ICE40UP5 achieves the best comprehensiveperformance across all datasets.Additionally, two things are worth noting: Anlogic’s EF2M45 and Lattice’s MachXO2are unable to deploy k-NN in multiple mission scenarios due to resource constraints.Pango’s PGL12G is also incapable of deploying k-NN. In addition, the reason is that thesynthesis tool is unable to correctly recognize the current k-NN design, and thereforeignores the key path. This does not occur when using alternative development tools. TheFPGA k-NN deployment results with the best comprehensive performance under each taskare shown in Table 12.Table 12. The k-NN deployment results on the best CPLP-performing FPGAs.Dataset Device Score LUTs DSPs Latency/us Power/mW PLP CPLPBinary clas-sificationGutter Oil ICE40UP5 99.36% 979 6 7.81 134 1046.54 39,768.52Smart Grid ICE40UP5 79.39% 4949 8 9.32 135.79 1265.58 48,092.09Multiclassclassifica-tionGutter Oil ICE40UP5 99.36% 1077 6 7.81 135 1054.35 40,065.30Wine Quality MachXO2 81.23% 4348 / 7.18 186 1335.67 39,936.41Regression Rain Cyclone10LP10CL 0.8527 (R2) 5397 8 11.89 305.54 3633.79 181,325.98PowerConsumption ICE40UP5 0.9960 (R2) 1159 7 9.36 12.71 118.97 4520.69Appl. Sci. 2022, 12, 89 15 of 275.4. SVMIn the experiment, the linear SVM is chosen for training, and the results are shownin Table 13. Due to the function similarity between the linear SVM and ANN, theirsimulation scores are very similar. The SVM deployment results on 10 FPGA boards withthe best comprehensive performance under each task are shown in Table 14. The remainingimplementation results are provided in the Appendix A, Table A7.Table 13. The highest-scoring of SVM obtained in different datasets.Dataset ScoreBinary classification Gutter Oil 96.02%Smart Grid 98.35%Multiclass classificationGutter Oil 96.33%Wine Quality 72.68%Regression Rain 0.7932 (R2)Power Consumption 0.9979 (R2)Table 14. SVM deployment results on the best CPLP-performing FPGAs.Dataset Device Score LUTs DSPs Latency Power PLP CPLPBinaryclassificationGutter Oil ICE40UP5 96.02% 765 8 15.56 151 2349.41 89,277.54Smart Grid ICE40UP5 98.35% 955 8 15.90 154.98 2464.17 93,638.31MulticlassclassificationGutter Oil ICE40UP5 96.33% 765 8 14.90 152.99 2279.20 86,609.61Wine Quality ICE40UP5 72.68% 976 8 15.56 155.14 2413.89 91,727.65Regression Rain ICE40UP5 0.7932 (R2) 527 8 13.51 147.76 1996.77 75,877.43PowerConsumption ICE40UP5 0.9979 (R2) 516 8 13.47 148 1994.00 75,772.155.5. Comparisons with Embedded PlatformsTo provide a more accurate assessment of our implementation, we also compare MLoFwith three representative embedded platforms, namely Nvidia Jetson Nano, RaspberryPi3 B+, and STM32L476 Nucleo. The specification of each platform is listed in Table 15.Jetson Nano is powered by a Cortex-A57 core running at 1.43 GHz and a 128-core NvidiaMaxwell-based GPU [40], while Raspberry features a Cortex-A53 core running at 1.2 GHz.STM32L476 Nucleo is a typical IoT development platform with a Cortex-M4 core runningat 80 MHz [41]. Compared with Table 4, the prices of these three representative embeddeddevelopment platforms are similar to the FPGAs, which indicates that all of them arecomparable in terms of other indexes. Given the proper cost of FPGAs, they can beconsidered as competitive substitutes for past typical platforms.Table 15. The specification of three representative embedded development platforms.Platform Processor Clock PriceNvidia Jetson Nano Cortex-A57 1.43 GHz $89.00Raspberry Pi3 B+ Cortex-A53 1.2 GHz $54.99STM32L476 Nucleo Cortex-M4 80 MHz $31.99Based on the simulation results of previous desktop PCs, the Receiver OperatingCharacteristic (ROC) curve and Precision-Recall (PR) curve shown in Figure 10, we selectthe models with the highest score in each of the six task scenarios for deployment of theembedded platform [42]. The corresponding deployment models and architectures for eachtask are listed in Table 16. PyCuda is used for GPU parallel acceleration with fixed weightparameters on Jetson Nano. Moreover, we use the same Python code to implement it onthe Raspberry Pi, as well.Appl. Sci. 2022, 12, 89 16 of 27Figure 10. Comparison of the receiver operating characteristic curve and precision-recall curve forthe six typical IoT endpoint datasets with different algorithms. (a) Receiver Operating Characteristiccurve for Gutter Oil binary classification; (b) Receiver Operating Characteristic curve for SmartGrid binary classification; (c) Receiver Operating Characteristic curve for Gutter Oil multiclassclassification; (d) Receiver Operating Characteristic curve for Smart Grid multiclass classification;(e) Precision-Recall curve for Gutter Oil binary classification; (f) Precision-Recall curve for Smart Gridbinary classification; (g) Precision-Recall curve for Gutter Oil multiclass classification; (h) Precision-Recall curve for Smart Grid multiclass classification.Table 16. The highest-scoring model obtained in different datasets.Dataset Model Score ArchitectureBinaryclassificationGutter Oil k-NN 99.36% K = 2Smart Grid ANN 98.73% [4,4,4], TanhMulticlassclassificationGutter Oil k-NN 99.36% K = 2Wine Quality DT 83.69% Max depth = 4,Max node = 16Regression Rain ANN 0.8583 (R2) [8,8,8], ReLUPower Consumption SVM 0.9979 (R2) N/ATable 17 compares the performance of our FPGA and three embedded platformimplementations. Jetson Nano takes the lead in terms of computing performance. Onthe other hand, Nucleo consumes the lowest power. While the power consumption ofFPGA decreased by an average of 891%, and its performance improved by an average of9 times compared to typical IoT endpoint platforms. Moreover, FPGAs outperform allother platforms in terms of Energy Efficiency (PLP) and Cost Efficiency (CPLP).Appl. Sci. 2022, 12, 89 17 of 27Table 17. Breakdown of platform implemented results.Dataset and Type of Module The Best of FPGA Jetson Nano Raspberry NucleoBinaryclassificationGutter Oil(k-NN)Accuracy 99.36% 99.36% 99.36% 99.36%Latency 7.81 us 5.90 us 10.51 us 180.00 usPower 134 mW 2120 mW 1480 mW 102 mWPLP 1046.54 12,508 15,554.8 18,360CPLP 39,768.52 1,113,212 855,358.5 587,336.4Smart Grid(ANN)Accuracy 98.73% 98.73% 98.73% 98.73%Latency 11.12 us 5.97 us 18.77 us 300.00 usPower 140 mW 2110 mW 1470 mW 101 mWPLP 1556.8 12,596.7 27,591.9 30,300CPLP 59,158.4 1,121,106 1,517,279 969,297MulticlassclassificationGutter Oil(k-NN)Accuracy 99.36% 99.36% 99.36% 99.36%Latency 7.81 us 5.44 us 10.25 us 180.00 usPower 135 mW 2120 mW 1470 mW 102 mWPLP 1054.35 11,532.8 15,067.5 18,360CPLP 40,065.3 1,026,419 828,561.8 587,336.4WineQuality(DT)Accuracy 83.69% 83.69% 83.69% 83.69%Latency 5.60 us 1.37 us 5.82 us 84.00 usPower 121 mW 2060 mW 1350 mW 101 mWPLP 677.6 2822.2 7857 8484CPLP 25,748.8 251,175.8 432,056.4 271,403.2RegressionRain(ANN)R2 0.8583 0.8583 0.8583 0.8583Latency 8.73 us 7.81 us 35.77 us 261.00 usPower 135 mW 2140 mW 1480 mW 102 mWPLP 1178.55 16,713.4 52,939.6 26,622CPLP 44,784.9 1,487,493 2,911,149 851,637.8Power Con-sumption(SVM)R2 0.9979 0.9979 0.9979 0.9979Latency 13.47 us 7.94 us 43.73 us 364.00 usPower 148 mW 2610 mW 1530 mW 103 mWPLP 1993.56 20,723.4 66,906.9 37,492CPLP 75,755.28 1,844,383 3,679,210 1,199,369To demonstrate the benefits of FPGA implementation in IoT endpoint scenarios, wecompare embedded and FPGA platforms using six datasets in terms of performance(latency), power consumption, PLP, and CPLP, as shown in Figure 11 with the ordinate-axisin logarithmic scale. Jetson Nano exceeds the others in performance, but the second-best FPGA is not far behind, only 38% lower in average, 100% ahead of Raspberry, and2300% ahead of Nucleo. In terms of power consumption, Nucleo is quite competitiveas a low-power MCU with 102 mW on average, 30 mW lower than FPGA. These twoplatforms advanced well beyond Jetson Nano and Raspberry. It can be clearly seen thatin comparison to other platforms, FPGAs require significantly less PLP and CPLP on theordinate-axis in logarithmic scale. The smallest PLP and CPLP are critical for IoT endpointdevelopment and implementation, as response time, power consumption, and cost are allcritical factors in IoT endpoint tasks. Furthermore, the FPGA PLP is 17× better than theaverage for embedded platforms and the FPGA CPLP is 25× better than the average forembedded platforms.Appl. Sci. 2022, 12, 89 18 of 27Appl. Sci. 2022, 12, 89 17 of 27 CPLP 59,158.4 1,121,106 1,517,279 969,297 Multiclass clas‐sification Gutter Oil (k‐NN) Accuracy 99.36% 99.36% 99.36% 99.36% Latency 7.81 us 5.44 us 10.25 us 180.00 us Power 135 mW 2120 mW 1470 mW 102 mW PLP 1054.35 11,532.8 15,067.5 18,360 CPLP 40,065.3 1,026,419 828,561.8 587,336.4 Wine Quality (DT) Accuracy 83.69% 83.69% 83.69% 83.69% Latency 5.60 us 1.37 us 5.82 us 84.00 us Power 121 mW 2060 mW 1350 mW 101 mW PLP 677.6 2822.2 7857 8484 CPLP 25,748.8 251,175.8 432,056.4 271,403.2 Regression Rain (ANN) R2 0.8583 0.8583 0.8583 0.8583 Latency 8.73 us 7.81 us 35.77 us 261.00 us Power 135 mW 2140 mW 1480 mW 102 mW PLP 1178.55 16,713.4 52,939.6 26,622 CPLP 44,784.9 1,487,493 2,911,149 851,637.8 Power Con‐sumption (SVM) R2 0.9979 0.9979 0.9979 0.9979 Latency 13.47 us 7.94 us 43.73 us 364.00 us Power 148 mW 2610 mW 1530 mW 103 mW PLP 1993.56 20,723.4 66,906.9 37,492 CPLP 75,755.28 1,844,383 3,679,210 1,199,369 To demonstrate the benefits of FPGA implementation in IoT endpoint scenarios, we compare embedded and FPGA platforms using six datasets in terms of performance (la‐tency), power consumption, PLP, and CPLP, as shown in Figure 11 with the ordinate‐axis in logarithmic scale. Jetson Nano exceeds the others in performance, but the second‐best FPGA is not far behind, only 38% lower in average, 100% ahead of Raspberry, and 2300% ahead of Nucleo. In terms of power consumption, Nucleo is quite competitive as a low‐power MCU with 102 mW on average, 30 mW lower than FPGA. These two platforms advanced well beyond Jetson Nano and Raspberry. It can be clearly seen that in compar‐ison to other platforms, FPGAs require significantly less PLP and CPLP on the ordinate‐axis in logarithmic scale. The smallest PLP and CPLP are critical for IoT endpoint devel‐opment and implementation, as response time, power consumption, and cost are all crit‐ical factors in IoT endpoint tasks. Furthermore, the FPGA PLP is 17× better than the aver‐age for embedded platforms and the FPGA CPLP is 25× better than the average for em‐bedded platforms. (a) (b) 150LatencyFPGA Jetson NanoRaspberry Nucleo110100100010000PowerFPGA Jetson NanoRaspberry NucleoAppl. Sci. 2022, 12, 89 18 of 27 (c) (d) Figure 11. Comparison of performance (latency), power consumption, PLP, and CPLP for the six typical IoT endpoint datasets with different algorithms when implemented on FPGA and embedded platforms. (a) Comparison of performance (latency). (b) Comparison of power consumption. (c) Comparison of PLP. (d) Comparison of CPLP. 6. Conclusions In this paper, the Machine Learning on FPGA (MLoF), a series of ML hardware ac‐celerator IP cores for IoT endpoint devices was introduced to offer high‐performance, low‐cost, and low‐power. MLoF completes the process of making inferences on FPGAs based on the optimal parameter results from PC training. It implements four typical machine learning algo‐rithms (ANN, DT, k‐NN, and SVM) with Verilog HDL on 10 FPGA development boards from seven different manufacturers. The usage of LUTs, Power, Latency, Cost, PLP, as well as CPLP are used in comparisons and analyses of the MLoF deployment results with six typical IoT datasets. At the same time, we analyzed the synthesis results of different EDA tools under the same hardware design. Finally, we compared the best FPGA deploy‐ment results with typical IoT endpoint platforms (Jetson Nano, Raspberry, STM32L476). The results indicate that the FPGA PLP outperforms the IoT platforms by an average of 17× due to their superior parallelism capability. Meanwhile, FPGAs have 25× better CPLP compared to the IoT platforms. To our knowledge, this is the first paper that conducts hardware deployment, platform comparisons, and deployment result analysis. At the same time, it is also the first set of IP on open‐source FPGA machine learning algorithms, and has been verified on low‐cost FPGA platforms. MLoF still has room for further improvements: 1. The adaptability of MLoF could be enhanced, thus more complex algorithms (kNN with k > 16) could also be deployed on low‐cost FPGAs with few resources, such as MachXO2; 2. More options for user parame‐ters configuration could be added, including more ML algorithms, larger data bit width, and more hyperparameters; 3. Usability could be improved by further providing a script file or a user interface, to help the users generate the desired ML algorithm IP core more easily. These existing shortcomings of MLoF point out the direction of our future work. Author Contributions: Conceptualization, M.L. and R.C.; investigation, M.L. and R.C.; algorithm proposed, R.C.; hardware architecture, R.C.; data curation, R.C., T.W., and Y.Z.; validation, M.L. and R.C.; resources, M.L. and R.C.; supervision, M.L.; visualization, R.C., T.W., and Y.Z.; writing—original draft, M.L., R.C., and T.W.; writing—review and editing, M.L., R.C., T.W., and Y.Z. All au‐thors have read and agreed to the published version of the manuscript. Funding: This research was funded by the Innovation Funding of Agriculture Science and Technol‐ogy in Jiangsu Province, under grant CX(21)3121. Institutional Review Board Statement: Not applicable. Informed Consent Statement: Not applicable. 110010000PLPFPGA Jetson Nano1100100001000000CPLPFPGA Jetson NanoRaspberry NucleoFigure 11. Comparison of performance (latency), power consumption, PLP, and CPLP for the sixtypical IoT endpoint datasets with different algorithms when implemented on FPGA and embed-ded platforms. (a) Comparison of performance (latency). (b) Comparison of power consumption.(c) Comparison of PLP. (d) Comparison of CPLP.6. ConclusionsIn this paper, the Machine Learning on FPGA (MLoF), a series of ML hardwareaccelerator IP cores for IoT endpoint devices was introduced to offer high-performance,low-cost, and low-power.MLoF completes the process of making inferences on FPGAs based on the optimalparameter results from PC training. It implements four typical machine learning algorithms(ANN, DT, k-NN, and SVM) with Verilog HDL on 10 FPGA development boards fromseven different manufacturers. The usage of LUTs, Power, Latency, Cost, PLP, as wellas CPLP are used in comparisons a d a alyses of the MLoF deployment results it sixtypical IoT datasets. At the same time, w analyzed the synthesis results of different EDAtools under the same h rdw e design. Fi ally, we compared the b st FPGA deploymentresults with typ cal IoT endpoi t latforms (Jetson Nano, Raspberry, STM32L476). Theresults indicate th the FPGA PLP outperforms the IoT platforms by an average of 17×due to their superior pa allelism cap bility. Meanwhile, ave 25× b tter C LPcompared to the IoT platfor s. ledge, this is the first paper that conductshardware deployment, platform comparisons, and eployment result an lysis. At the sametime, it is also the first set of IP on open-source FPGA machine learning algorithms, andhas been verified on low-cost FPGA platforms.MLoF still has room for further improvements: 1. The adaptability of MLoF could beenhanced, thus more complex algorithms (kNN with k > 16) could also be deployed onlow-cost FPGAs with few resources, such as MachXO2; 2. More options for user parametersconfiguration could be added, including more ML algorithms, larger data bit width, andmore hyperparameters; 3. Usability could be improved by further providing a script file ora user interface, to help the users generate the desired ML algorithm IP core more easily.These existing shortcomings of MLoF point out the direction of our future work.Appl. Sci. 2022, 12, 89 19 of 27Author Contributions: Conceptualization, M.L. and R.C.; investigation, M.L. and R.C.; algorithmproposed, R.C.; hardware architecture, R.C.; data curation, R.C., T.W. and Y.Z.; validation, M.L. andR.C.; resources, M.L. and R.C.; supervision, M.L.; visualization, R.C., T.W. and Y.Z.; writing—originaldraft, M.L., R.C. and T.W.; writing—review and editing, M.L., R.C., T.W. and Y.Z. All authors haveread and agreed to the published version of the manuscript.Funding: This research was funded by the Innovation Funding of Agriculture Science and Technologyin Jiangsu Province, under grant CX(21)3121.Institutional Review Board Statement: Not applicable.Informed Consent Statement: Not applicable.Data Availability Statement: The following are available online at https://github.com/verimake-team/MLonFPGA, the source code and data.Acknowledgments: The authors would like to thank Jiangsu Academy of Agricultural Sciences for allthe support, and would also like to acknowledge the technical support from VeriMake Innovation Lab.Conflicts of Interest: The authors declare no conflict of interest.AbbreviationsANN Artificial Neural NetworkDT Decision TreeFSM Finite State MachineFPGA Field Programmable Gate ArrayGOP Giga Operation per SecondHDL Hardware Description LanguageIoT Internet of ThingIP Intellectual Propertyk-NN K-Nearest NeighborLUT Look-up TableMAC Multiplying AccumulatorMLoF Machine Learning on FPGAMCU Microcontroller UnitML Machine LearningRAM Random Access MemoryReLU Rectified Linear UnitSoC System on ChipSVM Support Vector MachineAppendix ATable A1. The score for different ANN architectures and activation functions.ActivationFunctionDatasetThe Score for ANN Architecture1.4 1.8 2.4 2.8 3.4 3.8 4.4 4.8ReLUGutter Oil 95.76 96.08 95.97 96.61 95.55 96.92 96.71 96.82Smart Grid 98.17 98.25 98.41 97.92 98.3 97.83 98.16 98.41Gutter Oil 95.28 96.55 96.46 96.28 96.28 96.97 93.1 96.19Wine Quality 70.84 71.58 63.01 71.45 70.22 71.36 70.7 72.29Rain 78.85 85.18 85.06 83.66 78.85 85.36 85.55 85.83Power Consumption 0.9976 0.9967 0.9894 0.997 0.9973 0.9964 0.9973 0.9973TanhGutter Oil 96.19 96.4 95.87 96.4 96.92 95.87 96.5 96.29Smart Grid 98.25 98.52 98.68 98.3 98.73 98.41 98.32 98.16Gutter Oil 95.73 96.46 96.37 96.82 96.37 96.91 96.53 96.55Wine Quality 71.85 70.44 71.76 72.95 72.02 72.29 72.46 72.94Rain 78.85 83.62 78.85 78.85 78.85 78.85 78.84 78.85Power Consumption 0.9948 0.995 0.9959 0.9965 0.9945 0.9956 0.9904 0.9958Appl. Sci. 2022, 12, 89 20 of 27Table A1. Cont.ActivationFunctionDatasetThe Score for ANN Architecture1.4 1.8 2.4 2.8 3.4 3.8 4.4 4.8SigmoidGutter Oil 96.29 96.4 96.19 96.4 97.14 97.14 97.03 96.92Smart Grid 98.07 98.07 98.52 98.03 98.64 98.26 97.87 97.56Gutter Oil 95.55 95.5 96.27 96.73 96.1 97.09 96.83 97Wine Quality 72.07 72.64 72.86 72.95 72.15 72.81 73 73.01Rain 78.85 85.14 85.12 85.17 78.85 85.46 78.85 84.37Power Consumption 0.9953 0.9966 0.9951 0.9979 0.9954 0.9956 0.9958 0.9964Table A2. ANN deployment results on the low-cost FPGAs.Dataset Device LUTs DSPs Latency Power PLP CPLPGutter OilEF2M45 1445 15 11.76 492.48 5789.10 149,937.75EG4S20 1165 25 11.40 371.82 4238.32 211,492.13GW2A 1833 12 11.45 451.47 5167.12 873,243.27Cyclone10LP10CL 1795 15 10.55 271.38 2863.87 142,907.27MAX10M50DAF 1400 25 10.17 312.53 3177.18 270,060.30ICE40UP5 1898 8 11.12 140 1556.10 59,131.80MachXO2 2717 / 11.48 190.98 2192.07 65,542.85M2S010 1398 22 11.63 292.47 3402.01 203,780.46PGL12G 1780 7 11.65 585.22 6820.15 354,648Artix-7 916 10 10.75 589 6331.75 505,906.83Smart GridEF2M45 1371 15 15.59 494.18 7704.24 199,539.69EG4S20 1091 25 11.40 381.85 4353.48 217,238.81GW2A 1779 12 12.30 419.11 5155.09 871,210.19Cyclone10LP10CL 1530 15 10.62 267.11 2837.24 141,578.40MAX10M50DAF 1335 21 9.58 311.08 2978.90 253,206.68ICE40UP5 1855 8 11.12 140 1556.10 59,131.80MachXO2 2696 / 11.48 191 2192.30 65,549.71M2S010 1263 22 11.79 300.44 3542.49 212,195.03PGL12G 1116 10 11.61 586 6802.87 353,749.45Artix-7 919 10 10.90 588 6409.20 512,095.08Gutter OilEF2M45 2651 15 12.44 542.82 6752.71 174,895.08EG4S20 1766 29 11.13 481.85 5360.60 267,494.11GW2A 3235 8 12.32 579.51 7136.70 1,206,102.74Cyclone10LP10CL 3069 15 10.36 272 2818.46 140,641.35MAX10M50DAF 2198 25 9.69 317 3072.05 261,124ICE40UP5 3887 8 11 140 1540 58,520MachXO2 5763 / 12.05 191 2301.17 68,804.92M2S010 2022 22 12 305 3658.78 219,160.92PGL12G 2546 7 11.97 585 7002.45 364,127.40Artix-7 2269 14 11 591 6501 519,429.90Wine QualityEF2M45 3139 15 16.37 622.83 10,195.78 264,070.60EG4S20 2231 29 12.31 491.84 6053.59 302,074.21GW2A 3696 16 14.27 682.89 9741.40 1,646,296.15Cyclone10LP10CL 3815 15 11.80 279 3290.81 164,211.17MAX10M50DAF 2895 33 9.66 322 3109.88 264,339.46ICE40UP5 / / / / / /MachXO2 6114 / 12.73 192 2444.54 73,091.87M2S010 2560 22 13.99 302.21 4226.41 253,161.77PGL12G 2929 7 15.61 586 9146.87 475,637.45Artix-7 2320 14 12.47 588 7332.36 585,855.56Appl. Sci. 2022, 12, 89 21 of 27Table A2. Cont.Dataset Device LUTs DSPs Latency Power PLP CPLPRainEF2M45 1426 15 11.84 542.85 6428.45 166,496.94EG4S20 1354 16 10.77 431.85 4650.61 232,065.65GW2A 3245 8 11.45 579.73 6634.96 1,121,308.93Cyclone10LP10CL 2263 15 9.39 273 2562.38 127,862.66MAX10M50DAF 2292 16 8.12 313 2542.50 216,112.42ICE40UP5 3553 8 8.73 135 1178.69 44,790.03MachXO2 4392 / 9.14 189 1728.03 51,668.01M2S010 2196 16 9.12 311 2836.63 169,914.20PGL12G 2055 7 4.72 584 2754.73 143,245.86Artix-7 1794 8 9.25 595 5503.75 439,749.63Power Con-sumptionEF2M45 2548 15 16.61 555.51 9227.56 238,993.80EG4S20 1614 29 14.61 454.12 6632.39 330,956.43GW2A 3245 8 14.45 561.69 8117 1,371,772.43Cyclone10LP10CL 2741 15 12.48 293 3657.23 182,495.58MAX10M50DAF 1832 33 11.67 344 4014.14 341,201.56ICE40UP5 3653 8 11.98 140 1676.50 63,707MachXO2 5621 / 12.80 209 2675.41 79,994.73M2S010 2323 22 12.21 322 3931.30 235,484.75PGL12G 2298 10 15.89 586 9309.78 484,108.66Artix-7 1110 14 12.12 588 7126.56 569,412.14Table A3. The score for different DT architectures.Number ofDepths DatasetNumber of Leaf Nodes8 16 32 644Gutter Oil 96.09 96.09 / /Smart Grid 97.98 97.98 / /Gutter Oil 96.46 96.46 / /Wine Quality 81.98 83.69 / /Rain 0.8481 0.848 / /PowerConsumption 0.98 0.992 / /5Gutter Oil 96.09 96.18 96.18 /Smart Grid 97.98 97.98 97.98 /Gutter Oil 96.46 96.63 96.7 /Wine Quality 81.98 83.21 83.51 /Rain 0.8481 0.8451 0.8404 /PowerConsumption 0.98 0.9928 0.9963 /6Gutter Oil 96.09 96.18 96.18 96.18Smart Grid 97.98 97.98 97.98 97.98Gutter Oil 96.46 96.63 96.85 96.85Wine Quality 81.98 82.5 83.51 83.25Rain 0.8481 0.8447 0.8366 0.839PowerConsumption 0.98 0.9928 0.9966 0.9976Appl. Sci. 2022, 12, 89 22 of 27Table A4. DT deployment results on the low-cost FPGAs.Dataset Device LUTs DSPs Latency Power PLP CPLPGutter OilEF2M45 681 / 12.28 416.85 5120.52 132,621.57EG4S20 661 / 11.52 325.63 3751.54 187,201.70GW2A 417 0 8.62 409.26 3528.20 596,265.12Cyclone10LP10CL 360 0 6.33 263 1664 83,033.65MAX10M50DAF 363 0 5.70 302 1722 146,370.34ICE40UP5 451 0 7.92 133.90 1060.76 40,309.02MachXO2 494 / 8.86 184.71 1635.83 48,911.23M2S010 396 0 9.87 279 2752.34 164,864.87PGL12G 271 0 9.77 548 5356.15 278,519.90Artix-7 264 0 9.40 587 5517.80 440,872.22Smart GridEF2M45 272 0 7.95 387.38 3081.21 79,803.41EG4S20 272 0 7.62 281.08 2142.35 106,903.45GW2A 313 0 7.86 400.69 3150.21 532,385.33Cyclone10LP10CL 284 0 5.93 261 1546.95 77,192.66MAX10M50DAF 287 0 5.38 301 1620.28 137,724.06ICE40UP5 285 0 5.87 122 716.14 27,213.32MachXO2 285 / 5.95 184 1095.17 32,745.52M2S010 291 0 6.38 293 1868.75 111,938.36PGL12G 307 0 6.33 543 3436.65 178,705.64Artix-7 188 0 8.02 588 4715.76 376,789.22Gutter OilEF2M45 1412 0 18.90 446.36 8436.73 218,511.20EG4S20 1463 0 17.63 374.87 6608.87 329,782.61GW2A 693 0 10.17 437.50 4450.69 752,166.19Cyclone10LP10CL 636 0 8.06 264 2128.10 106,192.39MAX10M50DAF 648 0 7.11 303 2153.72 183,066.54ICE40UP5 715 0 7.92 135 1069.47 40,639.86MachXO2 774 / 8.86 187 1656.07 49,516.55M2S010 685 0 9.35 316 2955.86 177,056.25PGL12G 679 0 12.82 553 7088.35 368,594.41Artix-7 655 0 10.20 590 6018 480,838.20Wine QualityEF2M45 266 0 8.26 387.38 3199.73 82,873.11EG4S20 266 0 8.39 286.44 2403.78 119,948.59GW2A 311 0 7.94 401.59 3187.39 538,668.59Cyclone10LP10CL 284 0 5.77 261.42 1507.09 75,203.61MAX10M50DAF 287 0 5.54 301.81 1670.82 142,019.71ICE40UP5 305 0 5.60 121 677.6 25,748.8MachXO2 304 / 5.54 179 991.66 29,650.63M2S010 301 0 6.72 291.47 1958.41 117,308.58PGL12G 316 0 7.22 443.83 3204.90 166,654.61Artix-7 177 0 8.20 488 4001.60 319,727.84RainEF2M45 269 0 7.65 382.18 2925.24 75,763.62EG4S20 269 0 7.79 281.84 2196.36 109,598.15GW2A 315 0 7.94 400.68 3180.23 537,458.69Cyclone10LP10CL 280 0 5.77 261.29 1508.69 75,283.55MAX10M50DAF 283 0 5.09 301.38 1533.12 130,315.21ICE40UP5 303 0 5.80 121 701.80 26,668.40MachXO2 301 / 5.94 174 1033.21 30,893.04M2S010 306 0 6.57 289.28 1900.28 113,826.79PGL12G 312 0 7.23 443.86 3210 166,919.77Artix-7 178 0 7.42 487 3613.54 288,721.85Appl. Sci. 2022, 12, 89 23 of 27Table A4. Cont.Dataset Device LUTs DSPs Latency Power PLP CPLPPower Con-sumptionEF2M45 1437 0 19.76 436.51 8625.48 223,399.86EG4S20 1424 0 17.51 365.56 6399.56 319,338.21GW2A 679 0 10.24 439.19 4495.09 759,670.07Cyclone10LP10CL 655 0 8.52 264.80 2256.10 112,579.19MAX10M50DAF 665 0 6.87 303.44 2083.72 177,116.41ICE40UP5 765 0 9.65 128 1235.46 46,947.33MachXO2 783 / 9.96 194 1932.82 57,791.38M2S010 709 0 10.47 313.76 3286.36 196,853.21PGL12G 668 0 15.50 454.35 7044.24 366,300.60Artix-7 716 0 8.35 492 4108.20 328,245.18Table A5. The score for different k-NN architectures.Datasetk Values (Number of Neighbors)2 4 8 16Gutter Oil 99.36 99.09 98.73 98.46Smart Grid 75.78 77.3 78.38 79.39Gutter Oil 99.36 99.07 98.73 98.46Wine Quality 77.93 77.41 81.23 74.9Rain 0.8366 0.8466 0.8494 0.8527Power Consumption 0.996 0.9954 0.9944 0.9915Table A6. The k-NN deployment results on the low-cost FPGAs.Dataset Device LUTs DSPs Latency Power PLP CPLPGutter OilEF2M45 1251 15 17.26 446.36 7703.32 199,515.87EG4S20 942 18 16.08 315.81 5077.64 253,374.31GW2A 991 6 5.18 397.25 2059.34 348,029.14Cyclone10LP10CL 984 6 10.63 282.49 3001.74 149,786.76MAX10M50DAF 985 6 9.33 335.91 3135.05 266,479.08ICE40UP5 979 6 7.81 134 1046.54 39,768.52MachXO2 1062 / 8.84 185.47 1638.63 48,994.96M2S010 990 6 13.32 325.57 4337.50 259,816.40PGL12G / / / / / /Artix-7 592 18 11.92 597 7116.24 568,587.58Smart GridEF2M45 / / / / / /EG4S20 10,757 29 18.07 1371.32 24,783.83 1,236,713.13GW2A 5708 13 7.84 888.16 6960.47 1,176,319.55Cyclone10LP10CL 4810 13 11.89 304.67 3621.31 180,703.25MAX10M50DAF 4847 13 9.90 369.19 3653.14 310,516.48ICE40UP5 4949 8 9.32 135.79 1265.58 48,092.09MachXO2 / / / / / /M2S010 5078 13 13.41 327.23 4386.45 262,748.42PGL12G / / / / / /Artix-7 3231 39 12.05 594 7157.70 571,900.23Appl. Sci. 2022, 12, 89 24 of 27Table A6. Cont.Dataset Device LUTs DSPs Latency Power PLP CPLPGutter OilEF2M45 1361 15 16.92 452.82 7663.01 198,471.83EG4S20 1058 18 16.62 331.42 5507.27 274,812.90GW2A 1047 6 5.18 406.45 2107.04 356,089.22Cyclone10LP10CL 1076 6 10.63 282.79 3005.77 149,988.17MAX10M50DAF 1088 6 8.83 335.66 2964.55 251,986.68ICE40UP5 1077 6 7.81 135 1054.35 40,065.30MachXO2 1241 / 7.62 185.47 1414.02 42,279.30M2S010 1117 6 12.94 325.72 4213.81 252,407.44PGL12G / / / / / /Artix-7 673 18 11.57 597 6907.29 551,892.47Wine QualityEF2M45 / / / / / /EG4S20 4435 29 18.96 672.69 12,752.20 636,334.94GW2A 3415 11 6.46 578.87 3739.51 631,977.72Cyclone10LP10CL 3073 11 11.10 194.79 2162.56 107,911.67MAX10M50DAF 3067 11 9.27 354 3280.87 278,874.12ICE40UP5 3848 8 9.13 135 1232.42 46,831.77MachXO2 4348 / 7.18 186 1335.67 39,936.41M2S010 3568 11 13.35 235.65 3145.95 188,442.66PGL12G / / / / / /Artix-7 2037 33 12.10 511 6183.10 494,029.69RainEF2M45 / / / / / /EG4S20 11,767 24 18 1491.21 26,843.27 1,339,479.23GW2A 6297 8 7.76 886.53 6882.98 1,163,223.64Cyclone10LP10CL 5397 8 11.89 305.54 3633.79 181,325.98MAX10M50DAF 5412 8 10.09 362.04 3651.17 310,349.74ICE40UP5 / / / / / /MachXO2 / / / / / /M2S010 6218 8 12.94 471.37 6097.62 365,247.23PGL12G / / / / / /Artix-7 3754 24 11.50 509 5853.50 467,694.65Power Con-sumptionEF2M45 1735 15 17.75 485.83 8625.01 223,387.78EG4S20 1071 21 15.30 365.83 5598.36 279,358.05GW2A 1095 7 5.18 321.68 1667.57 281,819.93Cyclone10LP10CL 1160 7 9.07 288.61 2617.40 130,608.46MAX10M50DAF 1173 7 10.54 339.08 3573.90 303,781.77ICE40UP5 1159 7 9.36 127 1188.21 45,152.06MachXO2 1864 / 8.81 195.09 1719.12 51,401.82M2S010 1232 7 11.86 212.88 2524.48 151,216.63PGL12G / / / / / /Artix-7 734 21 11.95 534 6381.30 509,865.87Table A7. SVM deployment results on the low-cost FPGAs.Dataset Device LUTs DSPs Latency Power PLP CPLPGutter OilEF2M45 829 8 13.81 426.67 5890.66 152,568.13EG4S20 853 8 13.45 365.11 4909.28 244,973.20GW2A 671 8 6.51 329.78 2145.52 362,592.23Cyclone10LP10CL 740 8 10.59 274.36 2906.30 145,024.14MAX10M50DAF 741 8 10.06 342.58 3447.04 292,998.40ICE40UP5 765 8 15.56 151 2349.41 89,277.54MachXO2 2663 / 15.57 217 3378.91 101,029.32M2S010 766 8 12.66 315.13 3988.89 238,934.52PGL12G 663 8 11.73 589.16 6910.26 359,333.40Artix-7 416 8 9.12 590 5380.80 429,925.92Appl. Sci. 2022, 12, 89 25 of 27Table A7. Cont.Dataset Device LUTs DSPs Latency Power PLP CPLPSmart GridEF2M45 950 8 13.69 456.22 6245.71 161,763.80EG4S20 1000 8 14.01 355.15 4976.29 248,316.96GW2A 890 8 6.75 361.03 2437.66 411,964.72Cyclone10LP10CL 963 8 11.33 307.44 3484.22 173,862.45MAX10M50DAF 964 8 10.46 364.08 3809.00 323,765.42ICE40UP5 955 8 15.90 154.98 2464.17 93,638.31MachXO2 3752 / 15.21 216 3284.71 98,212.89M2S010 975 8 13.48 325.74 4390.70 263,003.13PGL12G 775 8 11.22 587.97 6596.44 343,014.64Artix-7 482 8 8.78 589 5171.42 413,196.46Gutter OilEF2M45 829 8 13.81 426.67 5890.66 152,568.13EG4S20 853 8 13.45 365.11 4909.28 244,973.20GW2A 671 8 6.51 329.78 2145.52 362,592.23Cyclone10LP10CL 740 8 10.59 274.36 2906.30 145,024.14MAX10M50DAF 741 8 10.06 362.58 3648.28 310,103.80ICE40UP5 765 8 14.90 152.99 2279.20 86,609.61MachXO2 2667 / 15.19 217.11 3297.02 98,580.82M2S010 766 8 12.07 319.07 3851.48 230,703.77PGL12G 663 8 11.73 569.16 6675.68 347,135.24Artix-7 416 0 9.12 487 4441.44 354,871.06Wine QualityEF2M45 918 8 13.52 444.32 6005.85 155,551.42EG4S20 994 8 13.72 355.15 4873.65 243,195.38GW2A 858 8 6.68 354.76 2369.78 400,493.40Cyclone10LP10CL 932 8 10.96 276.47 3030.39 151,216.34MAX10M50DAF 933 8 10.52 362.87 3817.76 324,509.20ICE40UP5 976 8 15.56 155.14 2413.89 91,727.65MachXO2 3070 / 15.91 217.11 3454.24 103,281.66M2S010 966 8 12.44 320.80 3990.75 239,046.04PGL12G 743 8 12.10 569.60 6891.02 358,333.08Artix-7 465 8 9.20 490 4508.00 360,189.20RainEF2M45 523 8 13.27 400.72 5317.57 137,725.00EG4S20 533 8 12.95 312.13 4041.45 201,668.17GW2A 541 8 5.91 316.57 1869.98 316,027.45Cyclone10LP10CL 502 8 9.83 275.69 2710.86 135,271.90MAX10M50DAF 503 8 9.95 320.90 3193.92 271,483.00ICE40UP5 527 8 13.51 147.76 1996.77 75,877.43MachXO2 864 15.21 217.43 3307.55 98,895.60M2S010 570 8 11.38 184.51 2100.12 125,797.09PGL12G 540 8 12.50 567.52 7095.14 368,947.02Artix-7 344 8 8.92 490 4370.80 349,226.92Power Con-sumptionEF2M45 523 8 13.85 397.72 5509.19 142,688.01EG4S20 533 8 12.66 315.82 3997.32 199,466.32GW2A 534 8 5.91 314.48 1857.63 313,939.04Cyclone10LP10CL 504 8 10.02 275.91 2765.72 138,009.52MAX10M50DAF 507 8 9.59 321.22 3081.14 261,897.09ICE40UP5 516 8 13.47 148 1994.00 75,772.15MachXO2 851 / 15.21 216.43 3292.33 98,440.76M2S010 519 8 12.53 193.70 2427.30 145,395.56PGL12G 531 8 10.86 467.43 5078.16 264,064.30Artix-7 342 8 8.66 490 4243.40 339,047.66References1. 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Internet of Things
machine learning
embedded system
FPGA
hardware accelerator
MLoF: Machine Learning Accelerators for the Low-Cost FPGA Platforms
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