Shared load-store unit for instruction-based accelerators : case study with soft multicore and multithreaded RISC-V vector processors
department or school: Applied Science, Faculty of
department or school: Electrical and Computer Engineering, Department of
data provider: DSpace
degree campus: UBCV
creator: Maheshe, Joseph
issued: 2025-01-09T23:59:53Z
issued: 2024
related degree: Master of Applied Science - MASc
degree grantor: University of British Columbia
description: The end of Moore's Law and Dennard Scaling has shifted computing systems toward specialized accelerators to increase performance and lower power-per-operation. Accelerators are special-purpose hardware optimized to perform specific functions within general-purpose computing systems, and modern SoCs combine many general-purpose processors with a growing number of accelerators. Accelerators achieve higher performance and power efficiency by prioritizing specialization and heterogeneity over generality and homogeneity. When specialization reduces the cost of processing low enough, accelerators become memory-limited. High-performance accelerators typically access memory directly or through caches to circumvent throughput bottlenecks from accessing data only through the processor's register file. However, direct access to shared memory introduces coherence and consistency issues, both challenging aspects of modern processor design. As accelerators proliferate in shared-memory heterogeneous SoCs, ensuring coherence and consistency in each accelerator adds significant design complexity. This thesis proposes a novel shared load-store unit (LSU) to address these challenges collectively for all accelerators. The shared LSU specifically targets instruction-based accelerators integrated into the processor's instruction set architecture. Sharing an LSU consolidates LSU logic, buffering, multiple memory access ports, and coherence and consistency logic into a single unit. It can also enable automatic dependence checking, leading to improved performance. The shared LSU aims to alleviate the burden on designers who typically create accelerator-specific LSUs. Its platform-independent design is written in standard SystemVerilog HDL and uses open-source communication protocols to facilitate hardware reuse. It also offers programmers a simplified programming model featuring custom, accelerator-based, fine-grain fences. A case study demonstrates a shared LSU that replaces individual vec…
aggregated CHO: https://circle.library.ubc.ca/rest/handle/2429/90088
note: Shared Load-Store Unit forInstruction-based AcceleratorsCase Study with Soft Multicore and MultithreadedRISC-V Vector ProcessorsbyJoseph MahesheB.Eng. Electrical Engineering, Polytechnique Montréal, 2022A THESIS SUBMITTED IN PARTIAL FULFILLMENT OFTHE REQUIREMENTS FOR THE DEGREE OFMASTER OF APPLIED SCIENCEinThe Faculty of Graduate and Postdoctoral Studies(Electrical and Computer Engineering)THE UNIVERSITY OF BRITISH COLUMBIA(Vancouver)December 2024© Joseph Maheshe 2024The following individuals certify that they have read, and recommend tothe Faculty of Graduate and Postdoctoral Studies for acceptance, the thesisentitled:Shared Load-Store Unit for Instruction-based Accelerators: CaseStudy with Soft Multicore and Multithreaded RISC-V VectorProcessorssubmitted by Joseph Maheshe in partial fulfillment of the requirements forthe degree of Master of Applied Science in Electrical and ComputerEngineering.Examining Committee:Guy Lemieux, Professor, Electrical and Computer Engineering, UBCSupervisorSteve Wilton, Professor, Electrical and Computer Engineering, UBCSupervisory Committee MemberPrashant Nair, Professor, Electrical and Computer Engineering, UBCSupervisory Committee MemberiiAbstractThe end of Moore’s Law and Dennard Scaling has shifted computing systemstoward specialized accelerators to increase performance and lower power-per-operation. Accelerators are special-purpose hardware optimized to performspecific functions within general-purpose computing systems, and modernSoCs combine many general-purpose processors with a growing number ofaccelerators. Accelerators achieve higher performance and power efficiency byprioritizing specialization and heterogeneity over generality and homogeneity.When specialization reduces the cost of processing low enough, accelera-tors become memory-limited. High-performance accelerators typically accessmemory directly or through caches to circumvent throughput bottlenecksfrom accessing data only through the processor’s register file. Howe…
has type: Thesis/Dissertation
date issued: 2025-05
is shown at: 10.14288/1.0447717
language: eng
degree discipline: Electrical and Computer Engineering
provider: Vancouver : University of British Columbia Library
publisher: University of British Columbia
rights: Attribution-NonCommercial-NoDerivatives 4.0 International
rights URI: http://creativecommons.org/licenses/by-nc-nd/4.0/
scholar level: Graduate
contributor: Lemieux, Guy
type: Text
identifier URI: http://hdl.handle.net/2429/90088