Applied Science, Faculty of
Electrical and Computer Engineering, Department of
DSpace
UBCV
Min, Jun
Doctor of Philosophy - PhD
University of British Columbia
This thesis investigates the development of efficient bidirectional chargers, an integral component for advancing e-mobility. Electric vehicles (EVs), energized by renewable sources, could mitigate the power grid instability by returning stored energy when renewables are less available. Battery voltage in EVs, however, can vary widely based on the EV's application and its battery's State of Charge (SoC). This necessitates employing various bidirectional charger techniques that can handle a broad range of EV battery voltages when connected to the renewable energy grid. Three innovative techniques are proposed. Firstly, this work introduces the Asymmetric Parameters Methodology (APM), a technique that enables the design of asymmetric resonant tanks in bidirectional resonant CLLC DC/DC stages. APM, optimized through a statistical Design of Experiments (DoE) approach, results in a narrower bidirectional switching frequency range, reduced component current stress, and smaller transformer size. The second technique is a unified bidirectional resonant frequency tracking method for the CLLC DC/DC stage of battery chargers, which decreases bidirectional resonance tracking costs and complexity while enhancing efficiency under parameter deviations. It is based on the discovery of two interesting features of the CLLC converters: one, the maximum efficiency for charging and discharging modes occurs at a variable but bidirectionally identical resonant frequency. Two, the voltages at both ends of the resonant tank remain in phase at this frequency for bidirectional operations. This thesis introduces a third technique: a cascaded half-bridge-based multi-level multi-port bridgeless PFC rectifier for the AC/DC stage of chargers. Suitable for low-voltage battery charging, this technique divides high-voltage DC bus voltage into multiple low-voltage ports for the following CLLC DC/DC converter stage. This allows the transformer ratio of the DC/DC converter stage to be designed close to 1. Compared to cascaded full-bridge multi-level PFC, this approach cuts the number of switches per cell by half, while maintaining the same output ports. It also reduces input current ripple due to the reduction in volt-seconds on the boost inductor.
Bidirectional Resonant Chargers for E-MobilitybyJun MinM. Eng., Hunan University, 2018B. Eng., Hunan Institute of Engineering, 2014A THESIS SUBMITTED IN PARTIAL FULFILLMENTOF THE REQUIREMENTS FOR THE DEGREE OFDoctor of PhilosophyinTHE FACULTY OF GRADUATE AND POSTDOCTORAL STUDIES(Electrical & Computer Engineering)The University of British Columbia(Vancouver)June 2023© Jun Min, 2023The following individuals certify that they have read, and recommend to the Faculty of Graduateand Postdoctoral Studies for acceptance, the thesis entitled:Bidirectional Resonant Chargers for E-Mobilitysubmitted by Jun Min in partial fulfillment of the requirements forthe degree of Doctor of Philosophyin Electrical and Computer EngineeringExamining Committee:Dr. Martin Ordonez, Professor, Electrical and Computer Engineering, UBCSupervisorDr. Juri Jatskevich, Professor, Electrical and Computer Engineering, UBCSupervisory Committee MemberDr. Navid Shafiei, Senior Power Supply Design Engineer, EnerSysSupervisory Committee MemberDr. Shahriar Mirabbasi, Professor, Electrical and Computer Engineering, UBCUniversity ExaminerDr. Curtis Berlinguette, Professor, Chemical and Biological Engineering, UBCUniversity ExamineriiAbstractThis thesis investigates the development of efficient bidirectional chargers, an integral componentfor advancing e-mobility. Electric vehicles (EVs), energized by renewable sources, could mitigatethe power grid instability by returning stored energy when renewables are less available. Batteryvoltage in EVs, however, can vary widely based on the EV’s application and its battery’s State ofCharge (SoC). This necessitates employing various bidirectional charger techniques that can handlea broad range of EV battery voltages when connected to the renewable energy grid.Three innovative techniques are proposed. Firstly, this work introduces the Asymmetric Pa-rameters Methodology (APM), a technique that enables the design of asymmetric resonant tanks inbidirectional resonant CLLC DC/DC stages. APM, optimized through a statistical Design of Ex-periments (DoE) approach, results in a narrower bidirectional switching frequency range, reducedcomponent current stress, and smaller transformer size.The second technique is a unified bidirectional resonant frequency tracking method for theCLLC DC/DC stage of battery chargers, which decreases bidirectional resonance tracking costsand complexity while enhancing efficiency under parameter deviations. It is based on the discoveryof two interesting features of the CLLC converters: one, the maximum efficiency for chargingand discharging modes occurs at a variable but bidirectionally identical resonant frequency. Two,the voltages at both ends of the resonant tank remain in phase at this frequency for bidirectionaloperations.This thesis introduces a third technique: a cascaded half-bridge-based multi-level multi-portbridgeless PFC rectifier for the AC/DC stage of chargers. Suitable for low-voltage battery charging,this technique divides high-voltage DC bus voltage into multiple low-voltage ports for the followingCLLC DC/DC converter stage. This allows the transformer ratio of the DC/DC converter stage toiiibe designed close to 1. Compared to cascaded full-bridge multi-level PFC, this approach cuts thenumber of switches per cell by half, while maintaining the same output ports. It also reduces inputcurrent ripple due to the reduction in volt-seconds on the boost inductor.ivLay SummaryE-mobility focuses on using electric power for a variety of Electric Vehicles (EVs), promotinggreener transportation. This research seeks to connect EVs with renewable energy sources in abidirectional manner. By deploying EVs extensively, they can store substantial electricity and sta-bilize the renewable energy grid during peak demand by feeding energy back into it. This not onlyfosters eco-friendly transportation but also ensures the stability of the renewable energy system.The key for this concept is the use of bidirectional chargers, acting as intermediaries between therenewable energy system and EV batteries. Presently, the voltage levels of EV batteries can sig-nificantly vary based on their usage and charging state, leading to design hurdles and inefficienciesfor conventional chargers. This thesis addresses these problems, introducing three innovative tech-niques to efficiently manage the charging and discharging processes for both high and low voltageEV batteries.vPrefaceThis work is based on the research performed at the Department of Electrical and Computer Engi-neering of the University of British Columbia by Jun Min, under the supervision of Prof. MartinOrdonez.Chapter 1 contains modified portions of text from all below-listed publications. Portions ofChapter 2 are published in IEEE Transactions on Power Electronics. Some other portions arepublished in 2020 IEEE Energy Conversion Congress and Exposition (ECCE) [1, 2]:• J. Min and M. Ordonez, ”Bidirectional Resonant CLLC Charger for Wide Battery VoltageRange: Asymmetric Parameters Methodology,” in IEEE Transactions on Power Electronics,vol. 36, no. 6, pp. 6662-6673, June 2021.• J. Min and M. Ordonez, ”Asymmetric Parameters Design for Bidirectional Resonant CLLCBattery Charger,” 2020 IEEE Energy Conversion Congress and Exposition (ECCE), 2020,pp. 5375-5379.Portions of Chapter 3 have been published in IEEE Transactions on Power Electronics, and2021 IEEE Energy Conversion Congress and Exposition (ECCE) [3, 4]:• J. Min and M. Ordonez, “Unified bidirectional resonant frequency tracking for CLLC con-verters,” IEEE Transactions on Power Electronics, vol. 37, no. 5, pp. 5637-5649, 2022.• J. Min and M. Ordonez, ”Bidirectional resonant frequency tracking for CLLC convertersbased on voltage falling edges,” in 2021 IEEE Energy Conversion Congress and Exposition(ECCE), 2021, pp. 1793-1797.viPortions of Chapter 4 have been published in 2023 IEEE Applied Power Electronics Confer-ence & Exposition (APEC) [5], and submitted to a peer-reviewed journal in the field of powerelectronics.• J. Min and M. Ordonez, ”Cascaded Half-bridge Multi-Level Multi-Outputs Bridgeless PFC,”2023 IEEE Applied Power Electronics Conference and Exposition (APEC), Orlando, FL,USA, 2023, pp. 2027-2031.• J. Min and M. Ordonez, ”Title Withheld...,” under review.As the first author of the above-mentioned publications, the author of this thesis developed thetheoretical concepts and wrote the manuscripts, developed simulation and experimental platforms,and received advice and technical support from Prof. Martin Ordonez and his research team.viiTable of ContentsAbstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiiLay Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vPreface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viTable of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiiList of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiiList of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xivList of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxviAcknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxix1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.3 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.3.1 The DC/DC Stage of Bidirectional Chargers . . . . . . . . . . . . . . . . . 101.3.2 The AC/DC PFC Stage of Bidirectional Chargers . . . . . . . . . . . . . . 171.4 Contributions of the Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231.4.1 Asymmetric CLLC tank parameters method for wide battery voltage range . 241.4.2 Unified Bidirectional Resonant Frequency Tracking for CLLC Converters . 25viii1.4.3 Cascaded Half-bridge Based PFC for low battery voltage applications . . . 271.5 Dissertation Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Bidirectional Resonant CLLC Converter for Wide Battery Voltage Range: Asym-metric Parameters Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302.1 Mathematical Model of Asymmetric Designed CLLC Converters . . . . . . . . . . 312.1.1 Equivalent Circuit Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 312.1.2 Gain Formulas Derivation . . . . . . . . . . . . . . . . . . . . . . . . . . 332.1.3 Ranges of Quality Factors . . . . . . . . . . . . . . . . . . . . . . . . . . 372.1.4 Ranges of Resonant Inductance Ratios . . . . . . . . . . . . . . . . . . . . 422.2 Statistical Design of Experiments for APM . . . . . . . . . . . . . . . . . . . . . . 432.2.1 Initial Factor Ranges and Responses . . . . . . . . . . . . . . . . . . . . . 442.2.2 Design Simulations and Obtain Responses . . . . . . . . . . . . . . . . . . 452.2.3 Obtain Models and Analyze Responses . . . . . . . . . . . . . . . . . . . 472.2.4 Selection and Verification of Factor Values . . . . . . . . . . . . . . . . . . 572.3 Experimental Verification of the Proposed APM . . . . . . . . . . . . . . . . . . . 592.3.1 Experiments of Proposed APM Design . . . . . . . . . . . . . . . . . . . . 602.3.2 Design Trade-offs for Turn-off Currents . . . . . . . . . . . . . . . . . . . 652.3.3 Comparison of Proposed APM Design and Conventional Symmetric Design 672.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 Unified Bidirectional Resonant Frequency Tracking for CLLC Converters . . . . . 723.1 The Bidirectional Resonant Frequency (BRF) . . . . . . . . . . . . . . . . . . . . 733.1.1 Bidirectional Short-circuit Resonant Frequencies . . . . . . . . . . . . . . 753.1.2 Bidirectional Open-circuit Resonant Frequencies . . . . . . . . . . . . . . 793.2 Phase Shift Analysis of Resonant Tank Voltage Vab and Vcd . . . . . . . . . . . . . 813.2.1 Phase Shift Analysis of Voltages . . . . . . . . . . . . . . . . . . . . . . . 813.2.2 Parameter Deviation Analysis for Phase Shift of Voltages . . . . . . . . . . 843.2.3 Gain Curves Slope Analysis for Phase Shift of Voltages . . . . . . . . . . . 87ix3.3 The Unified Bidirectional Resonant Frequency Tracking Algorithm . . . . . . . . . 893.4 Experiment Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933.4.1 Implementation Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . 933.4.2 Experimental Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . 953.5 Comparison with Conventional Tracking Methods . . . . . . . . . . . . . . . . . . 1023.5.1 Compare with Voltage-sensing based Unidirectional Tracking Methods . . 1033.5.2 Compare with Current-sensing based Unidirectional Tracking Methods . . 1133.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144 Cascaded Half-bridge Based Bidirectional Multi-level Bridgeless PFC with MultiOutput Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154.1 Operation Principles and Steady State Model of Proposed Cascaded Half-bridge PFC1164.1.1 Operation Mode Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174.1.2 Steady State Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1214.2 Comparison with Conventional PFC Topologies . . . . . . . . . . . . . . . . . . . 1254.2.1 Switching Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264.2.2 Conduction Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274.2.3 Current Ripple and Required Inductance . . . . . . . . . . . . . . . . . . . 1284.3 Control strategy for the proposed Cascaded Half-bridge PFC . . . . . . . . . . . . 1294.3.1 Analysis of Parameter Mismatch . . . . . . . . . . . . . . . . . . . . . . . 1294.3.2 Control and Modulation Strategy for the Proposed Cascaded Half-bridge PFC1334.4 Design and Experimental verifications . . . . . . . . . . . . . . . . . . . . . . . . 1364.4.1 Design of Proposed PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364.4.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1374.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1465 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1475.1 Conclusions and Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147x5.1.1 Bidirectional Resonant CLLC Converter for Wide Battery Voltage Range:Asymmetric Parameters Methodology . . . . . . . . . . . . . . . . . . . . 1475.1.2 Unified Bidirectional Resonant Frequency Tracking for CLLC Converters . 1485.1.3 Cascaded Half-bridge Based Bidirectional Multi-level Bridgeless PFC withMulti Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495.2 Specific Academic Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495.3 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153xiList of TablesTable 2.1 Case Studies for FC1 (k1) ≥ 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Table 2.2 Case Studies for FC2 (k1)≤ 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Table 2.3 Normalized Parameter Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Table 2.4 Simulation run points composed of different combinations of factors (Q1, Q2,and k1) are selected between the high and low factor levels. The minimum fre-quency response in charging mode ( fcmin) for every run is recorded. . . . . . . . 48Table 2.5 Simulation run points composed of different combinations of factors (Q1, Q2,and k1) are selected between the high and low factor levels. The maximumfrequency response in charging mode ( fcmax) for every run is recorded. . . . . . 49Table 2.6 Simulation run points composed of different combinations of factors (Q1, Q2,and k2) are selected between the high and low factor levels. The minimum fre-quency response in discharging mode ( fdmin) for every run is recorded. . . . . . 50Table 2.7 Simulation run points composed of different combinations of factors (Q1, Q2,and k2) are selected between the high and low factor levels. The maximumfrequency response in discharging mode ( fdmax) for every run is recorded. . . . . 51Table 2.8 Fit statistics of DoE model for minimum switching frequency fCmin in the charg-ing mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Table 2.9 Model errors analysis for minimum switching frequency fCmin in the chargingmode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Table 2.10 Parameters of CLLC Converter Prototype . . . . . . . . . . . . . . . . . . . . . 62Table 2.11 CLLC Resonant Tank Parameters of Conventional Symmetrical Design . . . . . 67xiiTable 3.1 Parameters of CLLC Converter Prototype . . . . . . . . . . . . . . . . . . . . . 95Table 3.2 Comparisons of bidirectional operations with unidirectional tracking methods . 103Table 4.1 Operation Modes of the Proposed PFC . . . . . . . . . . . . . . . . . . . . . . 120Table 4.2 Comparison of conventional 3-level totem-pole PFC, cascaded full-bridges PFC,and the Proposed PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125Table 4.3 Parameters of the proposed PFC prototype . . . . . . . . . . . . . . . . . . . . 138xiiiList of FiguresFigure 1.1 E-mobility (Electromobility) refers to the use of electric propulsion for a widerange of Electric Vehicle (EV) types including scooters, e-bikes, e-cars, e-trucks and e-buses. These EVs have diverse battery voltage levels dependingon their specific applications. On large scale, the widespread adoption of EVscould help mitigate the intermittency of renewable energy sources by returningexcess energy stored in the batteries back to the grid during times of low re-newable energy availability. Bidirectional chargers, acting as the link betweenthe renewable power grid and the batteries in e-mobility, are crucial in makingthis a reality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Figure 1.2 Block diagram of a typical two-stage EV battery charger: AC/DC stage andDC/DC stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Figure 1.3 An EV is powered by thousands of 18650 lithium-ion battery cells in series andparallel connection. But rather than arranging all the cells to build a single bigbattery, manufacturers use multiple smaller batteries called the battery moduleto make the final battery pack. This is to facilitate manufacturing and mainte-nance while achieving high voltage and high capacity. It is because of differentseries/parallel connections that lead to various battery pack voltage levels fordiverse EVs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Figure 1.4 A three-dimensional response surface-based battery model showing that theOpen-circuit Voltage (OCV) of batteries drops as their State of Charge (SoC)decreases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8xivFigure 1.5 The figure illustrates the CC/CV (Constant Current/Constant Voltage) chargingprofile for a Lithium-ion battery. To maintain a constant charging current inCC mode as the battery state of charge increases, the charger voltage mustadapt to the wide range of battery voltages. This can present design challengesfor bidirectional chargers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Figure 1.6 Circuit topology of Dual Active Bridge (DAB) DC/DC converter . . . . . . . . 10Figure 1.7 Circuit topology of LLC DC/DC converter . . . . . . . . . . . . . . . . . . . . 11Figure 1.8 Circuit topology of bidirectional resonant CLLC DC/DC converter . . . . . . . 12Figure 1.9 The control system diagram of AC/DC and DC/DC stages. The power flowdirection is controlled by regulating the DC bus voltage V1 through the PFC stage. 14Figure 1.10 Circuit topology of totem pole bridgeless PFC converter . . . . . . . . . . . . 18Figure 1.11 Circuit topology of interleaved totem pole bridgeless PFC converter . . . . . . 18Figure 1.12 Circuit topology of Neutral Point Clamped (NPC) PFC converter . . . . . . . . 19Figure 1.13 Circuit topology of Flying Capacitor (FC) clamped PFC converter . . . . . . . 20Figure 1.14 Circuit topology of Single Phase 5-level Active Neutral Point Clamped (ANPC)PFC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Figure 1.15 Circuit topology of Cascaded H-Bridges (CHB) multi-level PFC converter . . . 22Figure 1.16 Gain curves comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Figure 1.17 As Vab and Vcd are always bidirectionally in phase at BRF ( fBRF) Ê, fBRF istracked with the proposed unified tracking algorithm Ë by aligning the fallingedges of Vab and Vcd . Therefore, the bidirectional efficiency improvement isachieved even with parameter deviations for unregulated bidirectional CLLCconverters Ì. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26xvFigure 1.18 The proposed half-bridge based bidirectional multi-level PFC showing the fol-lowing benefits: ¶ Multi DC output ports via half bridges (maintaining thesame DC out ports with half MOSFETs compared with cascaded full bridgePFC); · Lower voltage and lower Rdson MOSFETs for lower conduction loss;¸ Volt-second reduction for smaller current ripple with same boost inductance;¹ Switching loss reduction for the same equivalent fs. . . . . . . . . . . . . . 27Figure 2.1 Circuit topology of CLLC converter . . . . . . . . . . . . . . . . . . . . . . . 32Figure 2.2 Equivalent circuit of CLLC resonant tank . . . . . . . . . . . . . . . . . . . . 34Figure 2.3 Response surfaces of statistical DoE in charge mode . . . . . . . . . . . . . . 54Figure 2.4 Response surfaces of statistical DoE in discharge mode . . . . . . . . . . . . . 55Figure 2.5 Design flowchart for the proposed APM . . . . . . . . . . . . . . . . . . . . . 56Figure 2.6 Simulation gain curves to compare proposed APM and conventional design . . 57Figure 2.7 AC/DC and DC/DC converters are the main EMI noise sources. Differentialmode noise and common mode noise can have different pathways. . . . . . . . 59Figure 2.8 The bidirectional resonant CLLC converter prototype . . . . . . . . . . . . . . 60Figure 2.9 Experiments in the charging mode . . . . . . . . . . . . . . . . . . . . . . . . 61Figure 2.10 Experiments in the discharging mode . . . . . . . . . . . . . . . . . . . . . . 63Figure 2.11 Predicted frequency ranges comparison of statistical DoE and FHA model. Sta-tistical DoE shows higher accuracy in predicting max. and min. frequenciesthan FHA to simulations and experiments in (a) charging mode (b) dischargingmode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Figure 2.12 Experiments in charging mode of proposed APM designed CLLC (a) At res-onance (b) Above resonance, showing that φ decreases as the switching fre-quency increases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65xviFigure 2.13 Experiment results of conventional symmetric designed CLLC in chargingmode with different switching frequencies. (a) below resonance, and (b) aboveresonance. Compared with the proposed APM, the conventional symmetricdesign operating in a wide voltage range has the disadvantages of a larger fre-quency range and higher peak current. . . . . . . . . . . . . . . . . . . . . . . 68Figure 2.14 Experiment results of conventional symmetric designed CLLC in dischargingmode with different switching frequencies. (a) below resonance, and (b) aboveresonance. Compared with the proposed APM, the conventional symmetricdesign operating in a wide voltage range has the disadvantages of a larger fre-quency range and higher peak current. . . . . . . . . . . . . . . . . . . . . . . 69Figure 2.15 Measured Efficiency Comparison of Proposed APM and Traditional SymmetricDesign. Proposed APM shows higher efficiency in both charging mode anddischarging mode than conventional symmetric design. . . . . . . . . . . . . . 70Figure 3.1 Gain curves for CLLC resonant converters with different load conditions in(a) forward mode; (b) backward mode. CLLC converters have up to 3 reso-nant frequencies (Ê - Ì) in each mode: fr, f 1, fr, f 2, fr, f 3 in forward mode, andfr,b1, fr,b2, fr,b3 in backward mode. . . . . . . . . . . . . . . . . . . . . . . . . 74Figure 3.2 Equivalent circuits of short-circuit condition for CLLC resonant tank in (a)forward mode (b) backward mode . . . . . . . . . . . . . . . . . . . . . . . . 77Figure 3.3 Equivalent circuits of open-circuit condition for CLLC resonant tank in (a) for-ward mode (b) backward mode . . . . . . . . . . . . . . . . . . . . . . . . . . 79Figure 3.4 In the forward mode, the phase shift ϕ f varies with the switching frequencyfs(= 1/Ts). (a) ϕ f is less than 0 when fs > fBRF; (b) ϕ f is greater than 0 whenfs < fBRF; (c) ϕ f is equal to 0 when fs = fBRF(= 1/TBRF). . . . . . . . . . . . 82Figure 3.5 Equivalent circuit of CLLC resonant tank in (a) forward mode, (b) backwardmode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83xviiFigure 3.6 Phase shift between Vab and Vcd in forward mode ϕ f is always 0 when ωs =ωBRF∗, although ωBRF∗ changes with different resonant tanks parameter varia-tion cases: ω∗e = ω∗emax , Qe = Qemax (¶), ω∗e = 1, Qe = 1 (·), and ω∗e =ω∗emin, Qe = Qemin (¸). Moreover, ϕ f > 0 when ωs < ωBRF∗; ϕ f < 0 whenωs > ωBRF∗ regardless of parameter variation cases. These two characteristicsenable the tracking of ωBRF∗. . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Figure 3.7 Phase shift between Vab and Vcd in backward mode ϕb is always 0 when ωs =ωBRF∗, although ωBRF∗ changes with different resonant tanks parameter varia-tion cases: ω∗e = ω∗emax , Qe = Qemax (¶), ω∗e = 1, Qe = 1 (·), and ω∗e =ω∗emin, Qe = Qemin (¸). Moreover, ϕb < 0 when ωs < ωBRF∗; ϕb > 0 whenωs > ωBRF∗ regardless of parameter variation cases. These two characteristicsenable the tracking of ωBRF∗. . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Figure 3.8 The proposed BRF tracking algorithm can tune the switching frequency to trackthe fBRF for both positive and negative voltage gain slopes. . . . . . . . . . . . 88Figure 3.9 The switching frequency tuning strategy of the proposed unified bidirectionalresonant frequency tracking algorithm, where the switching frequency is tunedbased on converter operation modes Ê and time difference ∆t f e of voltagefalling edges Ë. By aligning the falling edge of Vab with the falling edge ofVcd , the bidirectional efficient fBRF is tracked Ì. . . . . . . . . . . . . . . . . . 89Figure 3.10 The flowchart for the proposed unified bidirectional resonance tracking algo-rithm, shows how the proposed algorithm tunes fs online according to ∆t f e andoperation modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Figure 3.11 Although Vab and Vcd are synchronized for ensuring BRF tracking, the directionof power flow across the CLLC resonant tank is still controllable by regulatingthe amplitude of port voltage V1. . . . . . . . . . . . . . . . . . . . . . . . . . 92Figure 3.12 Two symmetric sampling channels (¶ and ·) are implemented to obtain thetime difference ∆t f e of voltage falling edges. Propagation delay skew of tab andtcd is minimized due to this symmetric structure and synchronized eCaps. . . . 93xviiiFigure 3.13 The bidirectional resonant CLLC converter prototype for verifying the perfor-mance of the unified bidirectional resonant frequency tracking algorithm . . . . 95Figure 3.14 Frequency tracking process in the forward mode of the proposed bidirectionalresonant frequency tracking algorithm starting with fs > fBRF. ∆t f e increasesfrom less than 0 to equal to 0, which indicates that the CLLC converter is work-ing at fBRF after frequency tracking. (a) Overall tracking transit waveforms(b) Zoomed-in view showing before frequency tracking. (c) Zoomed-in viewshowing after frequency tracking. . . . . . . . . . . . . . . . . . . . . . . . . 96Figure 3.15 Frequency tracking process in the forward mode of the proposed bidirectionalresonant frequency tracking algorithm starting with fs < fBRF. ∆t f e increasesfrom greater than 0 to equal to 0, which indicates that the CLLC converter isworking at fBRF after frequency tracking. (a) Overall tracking transit wave-forms (b) Zoomed-in view showing before frequency tracking. (c) Zoomed-inview showing after frequency tracking. . . . . . . . . . . . . . . . . . . . . . . 97Figure 3.16 Frequency tracking process in the backward mode of the proposed bidirectionalresonant frequency tracking algorithm starting with fs > fBRF. ∆t f e drops fromgreater than 0 to equal to 0, which indicates that the CLLC converter is work-ing at fBRF after frequency tracking. (a) Overall tracking transit waveforms(b) Zoomed-in view showing before frequency tracking. (c) Zoomed-in viewshowing after frequency tracking. . . . . . . . . . . . . . . . . . . . . . . . . 98Figure 3.17 Frequency tracking process in the backward mode of the proposed bidirectionalresonant frequency tracking algorithm starting with fs < fBRF. ∆t f e increasesfrom less than 0 to equal to 0, which indicates that the CLLC converter is work-ing at fBRF after frequency tracking. (a) Overall tracking transit waveforms(b) Zoomed-in view showing before frequency tracking. (c) Zoomed-in viewshowing after frequency tracking. . . . . . . . . . . . . . . . . . . . . . . . . 99xixFigure 3.18 In forward mode, the proposed tracking algorithm tracks fBRF of differentpower levels, so better efficiency has been achieved compared with the con-ventional method of fixed switching frequency (98kHz). Measured with inputvoltage V1 varies while output voltage V2 is fixed at 182V. . . . . . . . . . . . . 100Figure 3.19 In backward mode, the proposed tracking algorithm tracks fBRF of differentpower levels, so better efficiency has been achieved compared with the con-ventional method of fixed switching frequency (98kHz). Measured with inputvoltage V2 varies while output voltage V1 is fixed at 182V. . . . . . . . . . . . . 100Figure 3.20 In forward mode with 10% resonant tank parameter deviations, the proposedtracking algorithm shows up to 0.27% efficiency improvement compared withthe conventional fixed switching frequency (98kHz) in different power levels.Measured with input voltage V1 varies while output voltage V2 is fixed at 182V. 100Figure 3.21 In backward mode with 10% resonant tank parameter deviations, the proposedtracking algorithm shows up to 0.3% efficiency improvement compared withthe conventional fixed switching frequency (98kHz) in different power levels.Measured with input voltage V2 varies while output voltage V1 is fixed at 182V. 101Figure 3.22 With the help of this chapter’s proposed BRF and voltage shift analysis, theconventional voltage-sensing based PWLL technique could be applied to bidi-rectional tracking. However, extra stages, highlighted in red, are required toadd for PWLL, which is more complicated than the proposed BRF trackingmethod in bidirectional operations. . . . . . . . . . . . . . . . . . . . . . . . . 104Figure 3.23 The implementation diagram for the proposed BRF tracking algorithm. It canwork with/without SR. Therefore, it is more flexible and simpler than adoptingconventional unidirectional tracking methods for forward and backward modesseparately. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105xxFigure 3.24 This figure shows the effect of parasitic on adaptive SR, which is used in con-ventional PWLL tracking methods: in the case of the reduced load a capacitivecurrent spike should trigger the turn-on, there would be a current inversion(flowing from the output capacitor toward the SR MOSFET). This current in-version would cause a discharge of the output capacitor and consequently anincrease of the rectified current RMS value, in order to balance that discharge;this in turn would affect the converter efficiency. Therefore, the adaptive turn-on delay will cause the propagation delay skew to conventional PWLL trackingmethods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106Figure 3.25 The turn-on at the full load with minimum delay (TD On min) and at the reducedload with increased delay (up to TD On max equal to 40% of the clock cycle). . . 107Figure 3.26 The measuring and latching of the duty of VAB and VCD in (a) Forward mode (b)Backward mode. It is showing that the correct duty of VAB and VCD is latched,and it is not affected by voltage oscillations. . . . . . . . . . . . . . . . . . . . 108Figure 3.27 High frequency tests for optocouplers at (a) 500kHz (b) 1MHz. High-speedoptocouplers are showing stable propagation delay and propagation delay skewfor both 500kHz and 1MHz input. Therefore, optocouplers will not be thebottleneck for high frequency applications. The AC voltages of VAB and VCDare converted to DC signals by optocouplers before sending to eCaps in theDSP controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109Figure 3.28 The proposed BRF tracking method tracks the resonance based on falling edgestime difference of VAB and VCD. Therefore, the propagation delay may notdirectly reduce the accuracy of resonant frequency tracking, but the skew of thepropagation delay of the two signals is the source of tracking error. . . . . . . . 110Figure 3.29 The propagation delay skew comparison of (a) the proposed BRF tacking; (b)the PWLL method in references. As the proposed BRF tacking method hassymmetric measuring channels for VAB and VCD, the propagation delay skew ofthe two channels is lower than the references. . . . . . . . . . . . . . . . . . . 111xxiFigure 3.30 Same input voltage Vin opto = ±200V , 100kHz is applied to two BroadcomACPL-071L used in this work’s prototype. (a) this figure is showing the mea-sured propagation delay is 26.8ns, but this propagation delay will not directlycause accuracy degradation for this work. (b) this figure is showing the de-lay skew of two optocouplers is only 2.75ns, which only can cause the trackedresonant frequency to vary from 100kHz within [99.97kHz,100.03kHz]. . . . . 112Figure 3.31 Extra stages (highlighted in red) are required to add for current-sensing-basedunidirectional tracking methods for bidirectional operations. Two current sen-sors are required, which are unfavorable due to the high cost, and low powerdensity. The proposed BRF tracking method is lower cost, simpler, and hashigher power density in bidirectional operations. . . . . . . . . . . . . . . . . 113Figure 4.1 Operation modes of the proposed PFC. Sub figs (a)-(d) show the 4 differentoperation modes during the positive half cycles of the grid voltage us> 0. . . . 117Figure 4.2 Operation modes of the proposed PFC. Sub figs (a)-(d) show the 4 differentoperation modes during the negative half cycles of the grid voltage us6 0. . . . 119Figure 4.3 Operation waveforms diagram of the proposed PFC. It is showing that multi-level switching node voltage usw changes sinusoidally with the grid voltage us.Switches K1 and K2 operate alternately with grid frequency. S3a and S4a switchduring positive gird cycle, while S1a and S2a work during negative gird cycle.The width of the gate driving signals of S1a to S4a varies sinusoidally duringtheir working time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120Figure 4.4 Equivalent circuits for the proposed PFC in (a) Positive us Cycles (b) Negativeus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122Figure 4.5 The steady-state model for the proposed cascaded half-bridge based multi-levelmulti-port PFC. It can be regarded as two sub-systems for the positive andnegative grid cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124xxiiFigure 4.6 Circulating current analysis of the proposed cascaded half-bridge based multi-level multi-port PFC: (a) the proposed PFC with 2n cells in ISOP application(b) AC equivalent circuit of the proposed PFC in ISOP application, where thecascaded half bridges in proposed PFC can be modeled as controlled currentsources. (c) Assuming only DC link capacitor of the first cell (ZC1) has pa-rameter mismatch from other (2n− 1) cells (ZC). By using Norton Theorem,the simplified equivalent circuit for the negative grid cycle can be obtained. (d)Norton equivalent circuit for the positive grid cycle. . . . . . . . . . . . . . . 130Figure 4.7 The control diagram of the proposed cascaded half-bridge based multi-levelmulti-port PFC, which consists of four parts: output voltage loop, current loop,feed-forward and modulation. The DC link voltages for upper and lower cellsare controlled separately. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134Figure 4.8 Prototype of the proposed cascaded half-bridge based multi-level multi-portPFC with 6 cells according to Table 4.3. (a) the experimental setup consistsof the proposed PFC board, control board, loads, and AC power source. (b)Close-up view of the proposed PFC board. The size of the boost inductor hasbeen significantly reduced by the application of multi-level voltage. . . . . . . 139Figure 4.9 The experimental captures of the proposed PFC. (a) Boost inductor current iLsand switching node multi-level voltage usw are following the sinusoidal gridvoltage us. (b) Zoomed in view of iLs showing low current ripple (300kHz,2.1A) at 0.5 duty ratio. This is because the reduced volt-second is applied tothe boost inductor from usw. Due to the multi cell feature of the proposedPFC topology: ¶ usw voltage step is reduced to Udc/2n (33V); · iLs ripplefrequency (300kHz) is n times faster than cell gate driving signals (S1b, S2b andS3b, 100kHz, 120◦ phase shifted). . . . . . . . . . . . . . . . . . . . . . . . . 140xxiiiFigure 4.10 Experimental results of the conventional totem pole PFC with the same induc-tance as the proposed PFC. (a) The measured results of the converter inputvoltage us, switching node voltage usw, and the boost inductor current iLs. (b)Zoomed-in view of the totem pole converter current ripple. The current hasmaximum ripple when us reaches its peak. Although the switching frequencyis increased to the same as the proposed PFC equivalent switching frequency(300kHz)·, the maximum current ripple is still as high as 12.7A, which isaround 6 times higher than the ripple of the proposed PFC shown in Fig. 4.9(b). This is a consequence of the 6 times higher ∆usw for the totem pole PFC ¶. 141Figure 4.11 The experimental capture showing the output DC voltage ripple of Cell(1) andCell(6) in the positive (us > 0) and negative grid (us ≤ 0) cycles. Gate driv-ing signals are showing upper arm cells (Cell(1) to Cell(3)) and lower armcells (Cell(4) to Cell(6)) are charged by iLs alternately. The cell voltage rippleduring the full grid cycle is 7V. . . . . . . . . . . . . . . . . . . . . . . . . . 141Figure 4.12 Experimental results demonstrate the ability of multiple DC output ports to dis-tribute output power evenly, despite ±20% mismatches in output capacitanceparameters of Cells(1) and Cells(5). The results show stable and evenly dis-tributed power among Cells(1), Cells(2), Cells(5), and Cells(6) with calculatedvalues of 81.5W, 80.5W, 81W, and 81.3W respectively, despite differences involtage and current ripple amplitudes. . . . . . . . . . . . . . . . . . . . . . . 142Figure 4.13 Experimental results of proposed PFC converter for 20% input voltage (us)step-down. (a) overall waveforms demonstrating steady operation before andafter the step-down transition. (b) zoomed-in view before the input voltagestep-down, with a power factor of 0.993. (c) zoomed-in view after the inputvoltage step-down, with a power factor of 0.996. . . . . . . . . . . . . . . . . 143xxivFigure 4.14 Experimental results of proposed PFC converter for 20% input voltage (us)step-up. (a) overall waveforms demonstrating steady operation before and afterthe step-up transition. (b) zoomed-in view before the input voltage step-up,with a power factor of 0.996. (c) zoomed-in view after the input voltage step-up, with a power factor of 0.993. . . . . . . . . . . . . . . . . . . . . . . . . . 144Figure 4.15 Measured and estimated efficiency of the proposed half-bridge based multi-level multi-port PFC. The estimation of losses is based on equations presentedin this paper and simulations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 145Figure 4.16 The figure shows the power loss breakdown of the proposed PFC topologybased on experimental results at 500W. MOSFETs switching and conductionlosses account for 47.67% of the total loss, while the DC-link capacitors con-tribute to 29.94% of the total loss. The boost inductance and other factorsaccount for 8.28% and 19.11% of the total loss, respectively. . . . . . . . . . . 145xxvList of AbbreviationsAC Alternating CurrentAh Ampere hourANOVA Analysis of VarianceANPC Active Neutral Point ClampedAPM Asymmetric Parameters MethodologyBRF Bidirectional Resonant FrequencyCHB Cascaded H-BridgesCLLC Capacitor(C)-Inductor(L)-Inductor(L)-Capacitor(C)DAB Dual Active BridgeDC Direct CurrentDoE Design of ExperimentsDSP Digital Signal ProcessoreCap enhanced Capture ModuleEMI Electromagnetic InterferenceEMS Energy Management SystemePWM Enhanced Pulse Width Modulator ModuleEV Electric VehiclexxviFC Flying CapacitorFET Field Effect TransistorFHA First Harmonic ApproximationGaN Gallium NitrideIC Integrated CircuitIEA International Energy AgencyISR Interrupt Service RoutineKCL Kirchhoff’s Current LawKVL Kirchhoff’s Voltage LawLC Inductor(L)-Capacitor(C)LGA Land Grid ArrayLi-ion Lithium-ionLLC Inductor(L)-Inductor(L)-Capacitor(C)MOSFET Metal Oxide Semiconductor Field Effect TransistorNPC Neutral Point ClampedPFC Power Factor CorrectionPHEV Plug-in Hybrid Electric VehiclePI Proportional IntegratorPWLL Pulsewidth Locked LoopPWM Pulsed Width ModulationRMS Root Mean SquaredSIC Silicon CarbidexxviiSoC State of ChargeSR Synchronous RectificationV2G Vehicle-to-GridZCS Zero Current SwitchingZVS Zero Voltage SwitchingxxviiiAcknowledgmentsI would like to express my deep appreciation to my advisor Prof. Martin Ordonez, for his guidanceand support throughout my research process. His expertise and insights have been invaluable inhelping me to develop my ideas and complete this work. I cannot thank him enough for his patienceand encouragement, and his unwavering commitment to my development as a researcher.I am grateful to my committee members, Prof. William Dunford, Prof. Juri Jatskevich, and Dr.Navid Shafiei, for their feedback on my research progress and their valuable contributions to thiswork.I would also like to thank my lab colleagues, Dr. Ion Isbasescu, Dr. Ignacio Galiano, Dr. Fran-cisco Paz, Dr. Mohammad Ali Saket, Dr. Hamed Valipour, Dr. Daniel Hsu, Franco Degioanni, JanHammer and German Nahuel Bogado, for their informative discussions. Their technical supporthas been crucial in helping me to complete this work. I would also like to thank the rest of the labmembers for creating a supportive and collaborative environment that has enabled me to thrive.I am deeply grateful to my parents for their love and support throughout my academic journey.Their encouragement and belief in me have been a constant source of strength.Finally, I would like to thank the reader for taking the time to engage with this work. Yourinterest and attention are greatly appreciated.xxixChapter 1Introduction1.1 Motivation   Charge Discharge36V48V800V400V200VFigure 1.1: E-mobility (Electromobility) refers to the use of electric propulsion for a widerange of Electric Vehicle (EV) types including scooters, e-bikes, e-cars, e-trucks ande-buses. These EVs have diverse battery voltage levels depending on their specific ap-plications. On large scale, the widespread adoption of EVs could help mitigate theintermittency of renewable energy sources by returning excess energy stored in the bat-teries back to the grid during times of low renewable energy availability. Bidirectionalchargers, acting as the link between the renewable power grid and the batteries in e-mobility, are crucial in making this a reality.1Transportation is one of the key sectors of the global economy and has the highest relianceon fossil fuels of any sector, according to the International Energy Agency (IEA) [6]. Vehicleemissions generated in transportation are causing air pollution and climate change. Besides, fossilfuels, such as crude oil, take thousands of years to form naturally and cannot be replenished asfast as they are consumed. Growing energy consumption by conventional vehicles will lead toa shortage of fossil fuels in the coming decades. In contrast, e-mobility uses different types ofEVs that are powered by rechargeable batteries, resulting in zero tailpipe emissions. This is whye-mobility is seen as one of the most promising technologies for reducing emissions in globaltransportation.E-mobility could not be fully green in transport unless the electricity powering EVs is clean. IfEVs are charged primarily with fossil fuel-generated power, they may lead to a stronger relianceon fossil fuels and generate more greenhouse gas emissions as EV ownership rates go up. Infact, a recent study from Tsinghua University (China) and Argonne National Laboratory (US) [7]showed that the electricity charging EVs in China mainly comes from coal-fired power plants,which contribute two to five times as much particulate matter and chemicals as gas-engine cars. Toachieve a safer and greener future for everyone, it is crucial to charge EVs with renewable energygenerated from solar, wind, geothermal, hydropower, and ocean resources.E-mobility and renewable energy are an ideal match. Renewable energy, such as wind andsolar, cannot be turned on and off at load demands, as they come and go with the weather andtime of day. Consequently, lots of power plants in the grid are built purely to satisfy some briefwindows of possible highest peak loads, which causes both economic and efficiency losses. Energystorage batteries, especially those with high power density, bring an alternative perspective to thisproblem by storing excess energy for high-demand usage. Over the past 10 years, lithium-ion (Li-ion) battery energy densities have almost tripled [8], so most EVs today are powered by Li-ionbatteries. This is paving the way for a highly cost-efficient option for clean energy storage sinceubiquitous EV batteries can be used with few additional hardware investments. Moreover, a studyreveals that cars sit idle 95% of the year [9]. That means car owners are behind the wheel forjust around 400 hours per year on average while cars are parked for the remaining 8,360 hours2annually. Therefore, energy planners are looking at ways to utilize this dead time to solve oneof the biggest problems for scaling up renewable grids: stability. EVs at scale can provide a vastelectricity storage capacity while ensuring cost savings.This could be achieved through vehicle-to-grid (V2G) technology. Different from conventionalEVs that just take power from the grid, V2G technology enables energy to be pushed back tothe power grid from the batteries of EVs during peak power load. This unlocks a virtuous circlewhere EVs support the stability of the renewable grid, while renewable energy makes transporta-tion cleaner [10]. With delicate strategies and appropriate infrastructure, EVs could lower gasemissions, obsolete polluting vehicles, and increase the penetration of renewable energy. More-over, EVs can act as battery banks, when they are idle and plugged in, to stabilize the renewableenergy power grid. For renewable energy suppliers, this also creates opportunities to provide hugeamounts of clean energy to the ever-growing demands in the e-mobility sector.Bidirectional chargers are the key to implementing V2G technology: they act as the bridge link-ing the renewable power grid and batteries in various EVs. However, battery voltage levels vary fordifferent categories of EVs as shown in Fig. 1.1, resulting in challenges in pushing energy back tothe grid. On one hand, some EVs have battery voltage lower than 60V, such as golf carts and Ebikes,for low cost and touching safe. On the other hand, high-end EV makers are embracing 800V sys-tems today to satisfy the urges for longer vehicle mileage and faster charging. Furthermore, batteryvoltage also varies in a wide range with its State of Charge (SoC) even for the same battery pack.It remains challenging for bidirectional chargers to convert these various battery voltage levels toa standard grid voltage level. In-depth investigation into bidirectional chargers supporting vari-ous battery voltages can augment the application of idle EV batteries for grid stability and excessrenewable energy storage. Specifically, this leverages the V2G technology, where idle EVs cansupply power during peak demand, reducing grid strain, and storing surplus renewable energy forlater use, thus ensuring a more balanced and reliable power grid. Altogether, studying bidirectionalchargers for e-mobility can integrate large-scale EVs into the renewable energy grid, enabling thebidirectional power interaction between the electricity network and distributed batteries on EVs,and ultimately bringing considerable economic benefits to our society.31.2 ObjectivesThe objective of this thesis is to bidirectionally connect the renewable energy grid to EVs with di-verse battery voltages. Nowadays, the voltages required for e-mobility vary a lot to satisfy differentfunctions/purposes. As shown in Fig. 1.1, common battery pack voltages in current EVs rangefrom 24V-48V for small-size vehicles (golf carts, scooters, and electric bikes), 100V-200V forhybrid/plug-in hybrid vehicles, 400V for passenger EVs, and 800V for EVs needing higher trans-port power (sports cars, trucks, and electric buses). Apart from this, battery voltage also changeswith its SoC, even within the same battery pack. Taking passenger EVs as an example, their batterypack is around 400V at 100% indicated SoC but the voltage is only about 260V when the SoC is0%. Different bidirectional charger techniques are required to accommodate these batteries withdiverse voltage specs to renewable energy grid efficiently. Unfortunately, there is currently onlya very small number of EVs that are capable of two-way charging in the market, due to technicalchallenges in bidirectional chargers. Therefore, the main goal of this thesis is to overcome the ex-isting difficulties in bidirectional chargers by providing novel insights, models, methodologies, andtechniques.ACDC DCDCBidirectional EV ChargerBidirectional AC/DC stageBidirectional DC/DC stageChargeDischargeChargeDischargeAC DCDC BusFigure 1.2: Block diagram of a typical two-stage EV battery charger: AC/DC stage andDC/DC stage.A bidirectional EV charger requires a bidirectional AC/DC converter (i.e., power factor cor-rection (PFC)) followed by an isolated bidirectional DC/DC converter, as shown in Fig. 1.2. Thebattery voltage can be regulated by either AC/DC or DC/DC stage. If the battery voltage is con-trolled by DC/DC stage, the PFC on the AC/DC stage converts the AC power of the grid into a fixedDC bus voltage and minimizes the harmonics and reactive power, while the DC/DC stage regulates4the voltage or current required by batteries. Another way to regulate battery voltage is based onAC/DC stage by controlling DC bus voltage while the DC/DC stage tracks maximum efficiencyand provides galvanic isolation.The first aim of this thesis is to achieve wide battery range voltage regulation through theDC/DC stage. As one of the core parts of a bidirectional charger, bidirectional DC/DC convert-ers have different topologies. Among them, the CLLC resonant converter is one of the promisingtopologies due to its bidirectional boost/buck capability and high efficiency. The battery voltagelevel varies widely with the SoC, so the CLLC resonant converter is required to provide a widerange of bidirectional gain. In addition, the bidirectional CLLC resonant converter has a higherorder resonant tank than the conventional LLC converter, which complicates the converter design.Therefore, the bidirectional CLLC converter requires a systematic parameter design method toconsider the wide gain range, soft switching characteristics, and switching frequency range re-quirements for both forward and reverse operation. Meanwhile, to facilitate the optimization of theCLLC converter, it is necessary to research the impact of each parameter on the converter and itstrade-offs. Therefore, this work aims to propose a novel CLLC resonant tank design methodologyto find solutions to these challenges.The second aim is to solve the problem of efficiency loss caused by DC/DC converter resonancefrequency drifting. In some EV charger applications, battery voltages could also be controlled byAC/DC stage. This is realized by PFC converters to regulate wide battery voltage via controllingthe intermediate DC bus voltage as shown in Fig. 1.2. As a result, the CLLC resonant DC/DCconverter works as an unregulated isolation stage, and always operates at the designed resonant fre-quency where the maximum efficiency is achieved theoretically. In practical applications, however,the resonant frequency of CLLC converters deviates due to parameter variations in the temperature,operating frequency, load, and manufacturing tolerances. As a result of this deviation, an unreg-ulated CLLC converter with a fixed switching frequency cannot always operate in its optimumoperating condition. To address this issue, this work dedicates to modeling the frequencies of mul-tiple resonance points in the CLLC DC/DC converter, and track the drifted resonance frequencypoint bidirectionally via a tracking algorithm.5The third aim of this thesis is to further expand the applications of bidirectional chargers tolow-voltage EVs. For example, some golf cart batteries in low SoC could be 36V or 48V. Thislow-voltage battery voltage introduces design challenges for the two-stage bidirectional chargers.For a PFC with a single phase input voltage of 277VAC, for instance, the minimum intermediateDC bus voltage from AC/DC stage is about 400VDC (277*√2 VDC). Then, the DC/DC stageconverts the high DC bus voltage to a lower DC voltage with a high current, such as 36V and25A. This may bring two problems to the bidirectional DC/DC stage. Firstly, the power switches’voltage stress on the input side of the DC/DC stage is high. Higher voltage rating devices usuallyimply more losses and lower efficiency than low voltage devices. Secondly and more importantly,the conversion from high voltage bus to low voltage bus requires a high transformer ratio (ntrans),which introduces resonant tank design challenges to the DC/DC stage. Taking the bidirectionalCLLC DC/DC converter as an example, the leakage inductance on the secondary side is generallydesigned as n2trans smaller than the primary side leakage inductance. If the transformer ratio istoo high, the secondary leakage inductance would tend to be very low (nano Henry (nH) level).This low-level leakage inductance is hard to precisely obtain in a transformer, and variation in theinductance may also lead to non-monotonic bidirectional gain curves. Therefore, it is better tofind solutions from AC/DC PFC stage than from DC/DC stage for these challenges. This thesisaims to propose a novel PFC topology to tackle the challenging problems in low battery voltageapplications.Accomplishing the aforementioned objectives would result in three novel techniques for bidi-rectional resonant chargers. By selecting suitable combinations of the proposed techniques, bidi-rectional chargers could be utilized across various categories of EVs in the near future. Theseproposed techniques represent a crucial stepping stone for the economical and efficient populariza-tion of Vehicle-to-Grid (V2G) in e-mobility.1.3 Literature ReviewBattery storage is the most common large-scale option today, mainly because of the ubiquity oflithium-ion batteries and their increasing energy density [11]. In the EV industry, 18650 batteries,6one of the lithium-ion rechargeable batteries, have gained great popularity due to their reliability,long run times, and ability to be recharged hundreds of times over [12, 13]. The first 4 digits of thedesignation “18650” indicate the physical dimensions while the 5th digit shows it is a cylinder cell:the standard 18650 battery is 18mm in diameter by 65mm long, which is larger than daily usedAAA batteries (10.5mm x 44.5mm). 18650 battery cells may have a voltage range between 2.8volts and 4.2 volts, or a charging voltage of 4.2 volts, but the nominal voltage of a standard 18650is 3.7 volts. To power an EV, these battery cells need to be packed together to achieve high voltageand high capacity. There are two ways to connect battery cells to form a pack: series connectionand parallel connection [14, 15]. Connecting batteries in series could increase the amount of theirvoltage. Higher voltage normally means a lower system current, so thinner wires with less voltagedrop can be used; putting batteries in parallel brings high battery capacity (Ampere hour, Ah)while maintaining the same level of voltage. Depending on the application’s required voltage andcapacity, a combination of series and parallel connections are usually used in the EV industry tobuild battery modules and/or battery packs, as shown in Fig. 1.3. It is because of these differentseries/parallel connections that lead to various battery pack voltage levels for diverse EVs.Accordingly, battery voltage levels vary from EVs to EVs. The battery pack voltage level forEbikes is usually much lower than the voltage of electric passenger cars out of touching safe andlow-cost considerations. Most commercially available Ebike batteries are 36V 10Ah, which consistof 10-series 5-parallel 18650 cells (3.7V 2Ah each cell) [16]. In contrast, electric passenger carscommonly have a battery pack of around 400V for charging speed and capacity considerations. Forexample, Tesla Model S P85’s battery pack has a capacity of 90 kWh, which are 7104 of 18650cells [17]. Instead of combining all the cells and making a single big battery pack, Tesla utilizesmultiple smaller batteries, i.e., the battery modules, to make the final battery pack. Each modulehas a 6-series 74-parallel configuration. There are a total of 16 modules in series for each batterypack to achieve the rated high battery voltage level.Apart from this, the EV battery voltages can vary as the SoC of the battery changes. As shownin Fig. 1.4, the relationship between open-circuit battery voltage and SoC is not linear and can varydepending on the specific battery chemistry and design [18]. In general, however, the voltage of a7A 18650 Lithium-ionBattery CellModule ofLithium-ionBatteriesMultiple modulesmake up a battery packfor practical EV useFigure 1.3: An EV is powered by thousands of 18650 lithium-ion battery cells in series andparallel connection. But rather than arranging all the cells to build a single big battery,manufacturers use multiple smaller batteries called the battery module to make the finalbattery pack. This is to facilitate manufacturing and maintenance while achieving highvoltage and high capacity. It is because of different series/parallel connections that leadto various battery pack voltage levels for diverse EVs.Figure 1.4: A three-dimensional response surface-based battery model showing that theOpen-circuit Voltage (OCV) of batteries drops as their State of Charge (SoC) decreases.8lithium-ion battery will tend to decrease as the SoC decreases and will tend to increase as the SoCincreases. As an example, consider the Tesla Model S P85’s battery pack again, which is composedof 6 series cells per module and a total of 16 modules in series. The voltage of the battery packcan vary from around 269V (2.8V ×6×16) to 400V (4.2V ×6×16) as the SoC changes from 0%(2.8V per cell) to 100% (4.2V per cell).The varying battery voltages resulting from EV applications and State of Charge (SoC) neces-sitate the use of bidirectional chargers capable of adjusting their charging voltage accordingly. Asillustrated by the typical CC/CV (Constant Current/Constant Voltage) charging profile in Fig. 1.5[19], the charger voltage must adapt to the wide range of battery voltages to maintain a constantcharging current in CC mode as the battery SoC increases. Due to the diverse battery voltages,different bidirectional charger techniques are necessary to handle them, making it a significantchallenge to accommodate these various voltage levels to the renewable power grid. Because ofthis, the technology of V2G is still in its infancy. Currently, Nissan Leaf ZE1 and MitsubishiOutlander PHEVs (Plug-in hybrid EVs) are the only two mass-production EVs on the market thatenable V2G charging [20]. Bidirectional chargers capable of V2G for low voltage EVs, such asEbikes and golf carts, are even rare in the market. Therefore, there is an urgent need to developbidirectional chargers to cope with such various battery voltage levels. This work will further studyboth the DC/DC stage and AC/DC stage of bidirectional chargers in the following subsections withrelated literature.TimeCharging CurrentCharging VoltagetState of Charge(SoC)Figure 1.5: The figure illustrates the CC/CV (Constant Current/Constant Voltage) chargingprofile for a Lithium-ion battery. To maintain a constant charging current in CC modeas the battery state of charge increases, the charger voltage must adapt to the wide rangeof battery voltages. This can present design challenges for bidirectional chargers.91.3.1 The DC/DC Stage of Bidirectional ChargersFor safety reasons, electrical isolation is generally required for battery chargers. The electrical iso-lation for bidirectional DC/DC converters between the input and output ports is typically achievedby high-frequency transformers, which have the advantage of small profiles. At present, the com-mon isolated bidirectional DC/DC converters mainly include flyback, forward, push-pull, half-bridge, and full-bridge. The following will focus on the review and comparison of full-bridgebidirectional DC/DC converters.The Topology Review for Bidirectional DC/DC ConvertersVSS5 S7S8S6S1 S3LrILr1VP VABn:1S4S2VCD ILr2Figure 1.6: Circuit topology of Dual Active Bridge (DAB) DC/DC converterDue to its simple structure and bidirectional power flow capability, the Dual Active Bridge(DAB) converters have attracted researchers’ attention. Its topology is shown in Fig. 1.6. TheDAB converter consists of two full bridges, one inductor Lr, and a high-frequency transformer.By adjusting the phase shift on the primary and secondary sides of the inductor Lr, the magnitudeand direction of the transmitted power can be controlled. There are different phase shift controlmethods: traditional Single Phase Shift control (SPS) [21–23], Extended Phase Shift control (EPS)[24–26], Dual Phase Shift Control (DPS) [27–30] and Triple Phase Shift Control (TPS) [31–35].They all increase the degree of controllability by shifting the phase angle, thereby expanding thesoft switching range. However, it is challenging for DAB converters to achieve soft switching forall load conditions when the voltage is not matching. [36–38] summarizes some improved controlmethods to improve the performance of the DAB converter, but it cannot completely solve theproblems of circulation loss, and soft switching range.How to reduce the power loss and expand the soft switching range are the key to further im-10proving the efficiency of the DC/DC converter, which also are research hotspots of the isolatedbidirectional DC/DC converter. Among isolated DC/DC converter topologies, resonant convertersare good alternatives for their high efficiency. In [39–41], the unidirectional LLC resonant converteris extended to a bidirectional resonant converter by replacing the secondary diodes with MOSFETs,as shown in Fig. 1.7. When the energy is forwardly transmitted, the MOSFETs of the secondaryside operate in a synchronous rectification mode, and the output characteristics of the converterare the same as those of the unidirectional LLC resonant converter. When the energy is reverselytransmitted, the resonant tank is composed only of the resonant inductor and the capacitor, and theoutput characteristics are similar to those of the series LC resonant converter [42, 43]. The gaincurve of the LC resonant converter reaches a peak at the resonant frequency point, and the peakgain is low, which is very different from the output characteristics of the LLC resonant converter[44, 45]. Therefore, it is difficult to achieve the same voltage gain when the power is bidirectional.VSS5 S7S8S6S1 S3LrLmILr1VP VABCrS4S2VCD ILr2Figure 1.7: Circuit topology of LLC DC/DC converterTo solve the backward mode gain issues of the LLC converter, the CLLC bidirectional resonantconverter is proposed in [46–48]. Two LC resonant tanks are added to the primary and secondarysides of the transformer, as shown in Fig. 1.8. Therefore, resonant CLLC converters can boost andbuck bidirectionally. The converter can realize soft switching in the full working range, which notonly improves the conversion efficiency but also is beneficial to the operating frequency improve-ment. When the CLLC converter is running in charging mode (forward mode), driving signalsare given to the switches S1∼S4 to invert the input voltage V1 into a high-frequency square wave-form VAB. The switches S5∼S8 are in the rectification state. When the CLLC converter operatesin the discharging mode (backward mode), the switches S5∼S8 receive driving signals, while theswitches S1∼S4 are used for rectification. The power transfer direction is regulated by controlling11the amplitudes or phase shift of tank voltages VAB and VCD. Thus, the CLLC bidirectional resonantconverter is an ideal topology for high-power bidirectional DC/DC converters.VSS5 S7S8S6S1 S3Lr1Lm1 Lm2ILr1VP VABCr1 Cr2n:1S4S2 Lr2VCD ILr2Figure 1.8: Circuit topology of bidirectional resonant CLLC DC/DC converterAs stated, the voltage variation range of batteries is wide between high and low SoC, whichrequires bidirectional chargers to have a wide range of voltage regulation ability. This voltageregulation can be realized by the bidirectional resonant CLLC DC/DC converters or by the PFC inthe AC/DC stage. Depending on these two situations, the role of the CLLC DC/DC converters inthe charger will be discussed below.Wide Voltage Regulation by the DC/DC StageThe first option is to achieve wide battery voltage regulation via the bidirectional resonant CLLCDC/DC converters, while the AC/DC stages provide a steady DC bus voltage. There has beenan increasing number of papers regarding wide voltage operation for CLLC converters. A three-level CLLC converter is proposed to expand the output voltage range and reduce the voltage stress[49]. For applications with a wide input voltage, an integrated-half-bridge CLLC converter ispresented[50]. The ZVS for all switches is realized. To reduce voltage ripple, a novel inverter/rec-tifier leg is added to the CLLC converter and its operating principles are discussed [51]. Someinteresting work about control of bidirectional CLLC converter has been done [52–56]. A time-domain model of CLLC converter is adopted to accelerate steady-state analysis[52]. This modelcan be used for both frequency modulation control and phase-shift control. As parameter variationscould undermine the performance of the CLLC converter, the sliding mode control is proposed toimprove the converter dynamics and robustness to disturbances[53]. A novel dual-control mod-ulation is presented for CLLC converters in battery charging applications[54], where phase shift12between the primary and secondary is utilized as a control variable to reduce the power loss. Tofurther improve efficiency, Synchronous Rectification (SR) control is introduced [57, 58]. The onand off timing is determined by the phase difference between the primary gate pulse and secondaryresonant current[57]. For a more accurate estimate of the phase of its secondary side current, anovel extended harmonics approximation modeling approach is adopted for SR of CLLC resonantconverters[58].As the design of the CLLC resonant tank has significant impacts on bidirectional voltage reg-ulation, it has received much attention recently [59]. To ensure uniform characteristics for bidi-rectional operation, secondary LC resonant tank components are designed to equal the primaryLC components after reflection (Lr1=n2Lr2, Cr1=Cr2/n2) [60]. This design method is regarded assymmetric design, and it is commonly used for applications where wide voltage regulation is not re-quired, such as CLLC DC transformers [61–65]. As the resonant frequency of the DC transformeris sensitive to parameter variations, a robust design scheme is proposed to solve the parameter de-viation problems [61]. Artificial Intelligent algorithms can also be adopted to find high efficiencyand robust parameters [62, 63]. A switching frequency selection criteria approach is proposed tooptimize active power transmission in CLLC DC transformers, as multiple resonant frequenciesexist[64, 65].However, compared with symmetric designed CLLC DC transformer applications in [61–63],the main concern of bidirectional charger applicants is wide battery voltage regulation. If thetraditional symmetric design was applied to battery chargers, the bidirectional switching frequencyrange would be undesirable large, especially those frequencies for the minimum gain, becauseof asymmetric gain requirements in charging and discharging mode. Therefore, the conventionalsymmetrical design method cannot meet the demanding requirements of bidirectional chargers inthe full operating region. Although capacitors ratio has been adopted for monotonic gain curves[66], detailed asymmetric design methodology, the relationship among coupled parameters, andaccurate switching frequency models are lacking in the literature.13Cr1LmLr1 Lr2Forward ModeBackward ModeCr2V1V1V1refV1refPFCGridForward/Backward modeV2V2I2I2PFC controlEnergy ManagementSystem (EMS)Vab VcdResonanceTracking AlgorithmFigure 1.9: The control system diagram of AC/DC and DC/DC stages. The power flowdirection is controlled by regulating the DC bus voltage V1 through the PFC stage.Resonant Frequency Tracking by the DC/DC StageThe second option is for CLLC DC/DC converter stage to be fixed at the efficient resonant fre-quency for galvanic isolation and high-efficiency operation, while battery voltage regulation isrealized by varying the intermediate DC bus voltage V1 via AC/DC PFC stages, as shown in Fig.1.9. The bidirectional power flow is managed by the upper-level Energy Management System [67–69] via two operations: 1). calculating V1re f for the PFC stage, and 2). giving operating modecommand to CLLC converter stage [70–72]. The EMS can calculate the reference V1re f accordingto the targeted power direction, power requirement, V2, and I2. Then, the error of V1re f and V1,the grid phase, and the grid current are sent to the PFC controller to regulate the amplitude of V1.Meanwhile, the CLLC converter tracks the BRF with the proposed tracking algorithm based onthe targeted operation mode command (forward or backward mode) from the EMS. The reason foradopting this two-stage structure of the PFC stage + CLLC stage is that CLLC resonant convertershave a limited bidirectional voltage regulation range. The wider range voltage regulation is realizedby varying the DC bus voltage V1 via the PFC stage, so the CLLC converter stage can work at theBRF for galvanic isolation and high-efficiency operation [73, 74]. In this case, the CLLC converteris regarded as the unregulated bidirectional resonant converter.14To obtain maximum efficiency, the ideal operation case is that the unregulated bidirectionalCLLC converters work perfectly at resonant frequency[75]. Resonant frequencies are determinedby five resonant components in CLLC resonant tank. However, in engineering applications, thesefive components may deviate from designed values due to component tolerances, temperature andaging[76, 77]. These parameter deviations may cause the actual CLLC resonant tank to be asym-metric from symmetric design [1, 2], thereby leading to the resonant frequencies of the CLLCconverter to drift from the designed values in forward and backward operations. Consequently, thebidirectional efficiency of unregulated CLLC converters decreases.Impedance analysis of the CLLC resonant tank is fundamental for solving the resonant fre-quency drifting issue. Some interesting work about the impedance of bidirectional CLLC converterhas been published[78–81]. An optimal design methodology based on multiple simulations is pro-posed, where input impedance is analyzed to determine the ZVS for the MOSFETs [78]. The outputimpedance is obtained for the resonant parameter design stability analysis of CLLC converter [79],and the swarm intelligence is used to locate the global peak point of output impedance accuratelyand fast in the proposed design approach [80]. The whole CLLC secondary part, instead of justload resistance, is represented with an equivalent impedance [81], so design criteria incorporatedwith the soft switching and gain requirements could be developed easier for key parameters of theconverter.However, the resonant frequency analysis mentioned in the above literature is based on twoassumptions: Lm is infinite (Lm → +∞), so it can be omitted in the resonant frequency equa-tions; secondary LC resonant tank components are dependent on the primary LC components(Lr1 = n2Lr2,Cr1 =Cr2/n2, where n is the transformer ratio). However, actual resonant tank com-ponents deviate from nominal values. These parameter deviations break the design dependency andcause bidirectional resonant frequencies to drift from the designed values. Tracking the resonantfrequency calculated by equations with assumptions may lead to inaccurate tracking of resonancefor unregulated CLLC converters. It is still an open research opportunity for the generalized anal-ysis of CLLC converters’ bidirectional resonant frequencies without these assumptions.Once the equation for generalized bidirectional resonant frequency is obtained for CLLC con-15verters, a bidirectional tracking method is also needed to keep the CLLC converter working at thisfrequency. Resonant frequency tracking methods published so far are only for the conventional uni-directional LLC converters to solve the resonant frequency drifting problem [82–88]. These pub-lished techniques can be categorized as current-based methods [82–84] and voltage-based methods[85–88]. An online harmonics analyzing and minimizing for resonant current has been presentedto track resonant frequency [82]. It is based on the fact that the harmonic components of resonantcurrent at the resonance frequency are minimized, but online harmonics analysis involves a heavycomputation burden for signal processors. Similarly, the zero-current duration of the secondarydiode could also be measured and minimized to track the resonant frequency in LLC converters[83, 84]. Notwithstanding, if these unidirectional current-based tracking methods are applied tobidirectional converters, two costly current sensors are required, where one sensor is for forwardmode and the other is for backward mode. For unidirectional converters with synchronous recti-fication (SR), resonant frequency tracking can be achieved by the pulse width locked loop [85].In this method, synchronous rectification signals are used to minimize body diode conduction ofsecondary MOSFETs, while the pulse width locked loop is adopted to track resonant frequency byeliminating the pulse width differences between primary switch driving signals and secondary SRsignals [86]. Nevertheless, this method also requires additional control circuits for SR in backwardmode to track the resonant frequency bidirectionally, and it is not applicable for applications with-out SR. A resonant frequency tracking method for resonant converters was published [87], wherefrequency tracking is realized by monitoring the gain relationship between an exclusive electricalvariable pair[88]. Extra calculations and components need to be added for the backward mode toenable tracking bidirectionally. However, all the tracking methods mentioned above are designedfor conventional unidirectional LLC converters, so they cannot be applied for bidirectional track-ing directly. Bidirectional resonant frequency tracking for CLLC converters is an interesting newtopic, which requires different considerations. Compared with these conventional unidirectionalLLC converters, CLLC converters are bidirectional and have multiple different resonant frequen-cies in both forward and backward modes [66, 89]. The generalized resonant frequency equationscharacteristics and bidirectional resonant frequency tracking have not been derived and researched16in published papers yet.So far, the literature tackles this parameter deviation problem for unregulated CLLC convertersby using the concept of robust design. The robustness to parameter deviations is improved by con-sidering the worst-case deviation range and parasitic parameters [61, 65]. Since design complexitymay increase as the design factors rise for robust design methods, some artificial intelligence al-gorithms are adopted to simplify robust design [90, 91]. Moreover, a robust design idea is alsoimplemented to determine the fixed resonant switching frequency for unregulated CLLC convert-ers [64]. With this method, unregulated CLLC DC transformers can achieve robust power trans-mission ability against the resonant parameter variation. However, the concept of robust designcannot ensure unregulated CLLC converters work at efficient resonant frequencies bidirectionallyunder parameter deviations. Therefore, although unidirectional tracking methods (LLC) and robustdesign concepts show interesting results, a resonant frequency tracking method, which is bidirec-tional, low cost and has larger immunity against noise for CLLC converters, remains a researchopportunity.1.3.2 The AC/DC PFC Stage of Bidirectional ChargersFor the bidirectional battery chargers, the basic requirements for AC-DC stage converters are:• the ability to transfer power bidirectionally;• the ability to provide required DC bus voltage;• the capability of power factor correction (PFC);• high power density;• high efficiency;Conventional boost-type PFCs can no longer meet these demanding requirements as their highpower loss on the rectification diode bridge and they can only operate unidirectionally. Therefore,bridgeless PFC topologies, as shown in Fig. 1.10, have garnered wide interest [92–94]. The currentonly flows through two semiconductor switches during operations, so the conduction loss is reduced17CoS1 S3usS4S2LDC/DCstageFigure 1.10: Circuit topology of totem pole bridgeless PFC converterCoL1L2S1 S3usS4S2S5S6DC/DCstageFigure 1.11: Circuit topology of interleaved totem pole bridgeless PFC convertercompared with boost-type PFCs. S1 and S2 operate at high switching frequency while S3 and S4work at grid frequency. During the positive half cycle of input voltage, current passes through S2and S4; when S2 is off, current flows through S1 and S4. During the negative grid half-cycle, currentgoes via S1 and S3 to charge the boost inductor; when S1 is turned off, the grid power and energystored in the boost inductor go to load via the body diode of S2 and S3. This topology has theadvantages of a low number of components, low conduction loss of semiconductor devices, highefficiency, and low common-mode noise. However, the gate driving of two high side switches S1and S3 needs to be isolated from S2 and S4. In addition, hard switching transitions rule out the useof Super Junction MOSFETs in the continuous operation mode for totem pole PFCs, because oftheir long reverse recovery time trr and high reverse recovery charge Qrr [95]. Therefore, totempole PFCs with high-voltage Super Junction MOSFETs usually work in discontinuous mode or inthe critical mode for high-power applications where the inductor current ripple is large. This canbe solved if wide band gap switching devices are used [96]. Interleaved totem-pole PFC, shown in18Fig. 1.11, can also mitigate ripple issues in high-power applications [97–99]. The input currents ofthe two phases are interleaved by 180 degrees, and the inductor current ripple cancels each otherout. Therefore, the power level of the system has also been improved. However, the large volumeof the boost inductor of bridgeless PFC remained the dominant challenge for further improvingpower density.To reduce the size of the boost inductor, bridgeless multi-level PFC rectifiers are proposed[100, 101]. This is because the volt-second of the boost inductor decreases significantly with theincrease of voltage levels [102], [103]. Multi-level PFC rectifier topologies can be categorizedinto Neutral Point Clamped (NPC) [104–106], Flying Capacitor (FC) clamped [107, 108], hybrid[109–111], and Cascaded H-Bridges (CHB) [112, 113].C1LS1D1D2S5S6S3usS4S2C2DC/DCstageFigure 1.12: Circuit topology of Neutral Point Clamped (NPC) PFC converterThe neutral point clamped topology was first introduced by Nabae, et at., in 1981 [114]. It hasbeen widely adopted because of its high capability in medium voltage and high efficiency [115–117]. It adopts multiple capacitors in series to provide multiple DC voltage levels by dividingthe total DC voltage into a set of equal voltages as shown in Fig. 1.12. Because of this, lowervoltage rating switches with better conduction and switching loss performance can be applied inNPC. Another benefit of the NPC is brought by the added zero-voltage level, which can reduce theharmonic contents of the multi-level voltages. NPC can achieve more voltage levels by increasing19the number of switching devices, clamping diodes, and capacitors. However, it has an unbalancedvoltage issue on DC link capacitors if the multi-level voltage is higher than three.C1C3LS1S5S6S3usS4S2C2DC/DCstageFigure 1.13: Circuit topology of Flying Capacitor (FC) clamped PFC converterAnother classic topology is Flying Capacitor (FC) multilevel PFC, which is introduced by Mey-nard et al. in 1992 [118]. It has a similar topology to NPC PFC but Flying Capacitor clamped PFCreplaces the clamping diodes with capacitors as shown in Fig. 1.13. It outputs the required outputvoltage levels by summing the flying capacitor and DC-link voltages [119, 120]. FC multilevelPFC has a considerable number of flying capacitors which can supply short backup power duringhold-up time. As the increased number of capacitors at higher voltage levels, a complex controlmethod is required to balance the voltages of both DC-link capacitors and FCs. The higher switch-ing frequency to balance the capacitor voltages and a large number of balancing capacitors havelimited the industrial penetration of FC-type multilevel PFC.Hybrid multilevel PFC topologies, which combine features of both NPC and FC types, enablepossibilities to use the benefits of both topologies. One of the application issues of NPC PFC is theunequal distribution of power loss on the MOSFETs, which is caused by the non-identical voltagestress on the semiconductors. This leads to different temperatures and asymmetrical heat sinks forpower switches [121]. The loss distribution issues can be tackled with the Active Neutral PointClamped (ANPC) PFC converter [122]. By replacing clamping diodes with active power switches,20usC1LS1S3S4S2C2S5S6S7S8C3 DC/DCstageFigure 1.14: Circuit topology of Single Phase 5-level Active Neutral Point Clamped (ANPC)PFC converterthe ANPC controls the current flowing through the power switches and the neutral point. A five-level ANPC converter is shown in Fig. 1.14. The ANPC realizes modularity, which is missing inthe NPC topology, by adding FC to reach higher voltage levels. Besides, the complexity of DC linkcapacitor voltage balancing is reduced, as there are only two capacitors in the DC link [123]. Incontrast, the NPC and FC-type PFC topologies require four capacitors. The redundant switchingstates in ANPC converters also allow the voltage across FC to be regulated. Five-level ANPCconverters use at least eight active power switches, but it only has one DC output port.Providing multiple DC output ports is one of the essential features for multi-level PFCs, espe-cially when the application scenario is low-voltage batteries. As stated previously, multi-level PFCswork with isolated resonant DC/DC converters as a two-stage power supply solution [96], wherethe PFC stage provides a high DC voltage bus to the following DC/DC converters stage. For a PFCwith a three-phase line input voltage of 380VAC, for instance, the input DC bus voltage for DC/DCstage could be as high as 1000VDC. Then, the DC/DC stage converts the high DC input voltage to alower DC voltage bus with high current, such as 15V, 440A in battery formation applications[124].This solution may bring two problems to the bidirectional DC/DC stage. Firstly, the power switchvoltage stress on the input side of DC/DC stage is high. Higher voltage rating devices usuallyimply more losses and lower efficiency than low voltage devices. Secondly and more importantly,21the conversion from high voltage bus to low voltage bus requires a high transformer ratio (ntrans),which introduces resonant tank design challenges to the DC/DC stage. Taking the bidirectionalCLLC DC/DC converter [1, 2] as an example, the leakage inductance on the secondary side is gen-erally designed as n2trans smaller than the primary side leakage inductance [3, 4]. If the transformerratio is too high, the secondary leakage inductance would tend to be very low (nH level) [125].This low-level leakage inductance is challenging to precisely obtain in a transformer, and variationin the inductance may also lead to non-monotonic bidirectional gain curves [126].VDC,1VoVDC,2VDC,nusLDC/DCstage 1DC/DCstage 2DC/DCstage nFigure 1.15: Circuit topology of Cascaded H-Bridges (CHB) multi-level PFC converterCascaded full-bridge multi-level PFC [127] (also termed cascaded H-Bridges, CHB) couldsolve this challenge, as the DC link capacitors in each CHB cell can serve as an output port tofeed the DC/DC converters [128], as shown in Fig. 1.15. Therefore, high DC bus voltage is sharedamong multiple DC/DC converters, and the transformer ratio of each DC/DC converter is reduced.It can be found form Fig. 1.15 that the total high DC link voltage VDC is split into n low voltages,VDC,1 ∼ VDC,n, to provide for the subsequent DC/DC stage. The AC/DC CHB PFC converters have22the following advantages [129]:• As high DC voltage is shared among the multi H-bridge cells, the low-voltage switches withlower conduction resistances can be used. Therefore, conduction loss is reduced, and thermalis distributed to multiple H-bridge cells symmetrically;• Current and voltage ripples are dropped. This is because the effective switching frequency ofCHB PFC is multiple times of the switching frequency of a single cell, which is realized byinterleaving the operation of H-bridge cells. Combined with the reduced voltage levels, thecurrent ripple is further reduced;• Switching losses are also reduced. The switching loss is defined by the overlapping area ofcurrent and voltage during the transition. By splitting the high-power system into severallow-power cells, the total power loss is dropped (assuming the same di/dt and dv/dt ratesfor single cell and multi-cell systems);• The heat sink volume can also benefit from the CHB PFC. To begin with, both the conductionand switching loss are reduced, so smaller heat sinks are required. Besides, the thermal is dis-tributed among multiple power cells, which shrinks the heat sink volume or even eliminatesthe heat sinks.Although CHB PFCs bring these benefits, each CHB cell requires four power switches, whichincreases the costs and losses. From the industrial application point of view, it would be worthwhileto develop a novel cascaded multilevel PFC topology that realizes the same CHB PFC features butuses fewer power switches.1.4 Contributions of the WorkThis work makes significant contributions to bidirectional battery chargers in the areas of topolo-gies, modeling, and designing. The main contribution of this thesis fulfills the objective of accom-modating batteries with various voltage specs for the renewable energy power grid bidirectionallyand efficiently. Batteries with different voltage levels are charged/discharged with novel ideas on23both the DC/DC stage and AC/DC stage. The specific aspects of this work to advance the state-of-the-art bidirectional charging technology are the following:1.4.1 Asymmetric CLLC tank parameters method for wide battery voltagerange Overlapping Charge and Dischargefrequency range of APMAPM reduced range➋DischargeMDmaxMDminChargeMCmaxMCminf*f*Proposed asymmetric design (APM)Conventional symmetric design(Lr1≠n2Lr2, Cr1≠Cr2/n2)(Lr1=n2Lr2, Cr1=Cr2/n2)Proposed asymmetric design (APM)Conventional symmetric design(Lr1≠n2Lr2, Cr1≠Cr2/n2)(Lr1=n2Lr2, Cr1=Cr2/n2)Charge Mode Discharge ModeCr1 Cr2LmLr1 Lr2➋➋➋➊Figure 1.16: Comparison of gain curves for conventional symmetric design and proposedAPM design. APM design is showing advantages of more overlapping (¶) and re-duced (·) bidirectional switching frequency range compared with conventional sym-metric design.The first contribution of this work involves an asymmetric resonant tank design method forthe CLLC DC/DC converters, which is named Asymmetric Parameters Methodology (APM). Itenables CLLC resonant converters to operate in a wide battery voltage variation range introduced24by the high and low State of Charge (SoC). This design method can be used in both high batteryvoltage EVs and low battery voltage EVs. A conceptual comparison of the proposed idea andconventional symmetric design is illustrated in Fig. 1.16.To meet the multivariate optimization challenge of CLLC, the statistical Design of Experiments(DoE) has been adopted. It can obtain accurate models for multivariate systems with a few mea-surements. As indicated by ¶ in Fig. 1.16, the extra parameter design freedom, introduced by theasymmetric resonant tank (Lr1 6=n2Lr2, Cr1 6=Cr2/n2), can be used to successfully design gain curvesfor charging and discharging separately. Therefore, the proposed APM switching frequency rangeof charging (turquoise area) can be designed to overlap with discharging (green area). Besides,both the maximum and minimum switching frequencies of the proposed APM have been reducedfor charging and discharging (indicated by ·). The reduced parts are shown by the red areas inFig. 1.16. This means that the bidirectional switching frequencies of the proposed APM design arenarrower than the traditional symmetrical design, therefore optimizing the efficiency and currentstress of components. Moreover, since the minimum switching frequency is higher, the size of thetransformer can be smaller. The design of the Electromagnetic Interference (EMI) filters will alsobe more optimal due to the uniform and reduced bidirectional switching frequency.1.4.2 Unified Bidirectional Resonant Frequency Tracking for CLLCConvertersAnother contribution of this work is the proposed unified bidirectional resonant frequency trackingfor the CLLC DC/DC converter. The bidirectional efficiency of both high and low battery voltageapplications can benefit from the proposed tacking technique if the AC/DC stage regulates the DCbus voltage to control the output charging voltage. Fig. 1.17 is demonstrating the proposed ideaand advantages.With the proposed tracking algorithm, the forward mode (charging) and backward mode (dis-charging) resonant frequencies tracking are unified and simplified, and therefore the cost and com-plexity are reduced compared with using unidirectional tracking methods in forward and backwardmodes separately. These advantages are achieved with the help of two interesting features of theBidirectional Resonant Frequency (BRF or fBRF). To begin with, by the analysis of generalized25Cr1±ε%±ε%LmLr1 Lr2Forward ModeBackward ModeVab VcdCr2V1PFCGrid V2±ε%±ε%Parameter DeviationsWith the Proposed BidirectionalTracking AlgorithmIn phaseWithout frequency tracking(Fixed switching frequency)Out of phase➊➊➋VabVcd VabVcd1/fBRF1/ffixedIdentical frequency to obtainmax efficiency for forwardand backward modesfBRF fBRFffixed ffixed Real resonant frequencydrifting with deviations➊ Tracking fBRFWithout trackingEfficiencyLoad➌Figure 1.17: As Vab and Vcd are always bidirectionally in phase at BRF ( fBRF) Ê, fBRF istracked with the proposed unified tracking algorithm Ë by aligning the falling edgesof Vab and Vcd . Therefore, the bidirectional efficiency improvement is achieved evenwith parameter deviations for unregulated bidirectional CLLC converters Ì.resonant frequency equations, one of the features is discovered: forward mode and backward modeachieve maximum efficiency at an identical (but not constant) resonant frequency under parameterdeviations. Therefore, this unique resonant frequency is defined as the BRF in this work. With thisfeature, the resonant frequencies tracking is unified into tracking one specific frequency, namelyBRF. Another feature is derived from the analysis of the phase shift of voltages at both sides of theCLLC resonant tank (i.e., Vab and Vcd , which are shown in Fig. 1.17): Vab and Vcd are always inphase at fBRF for bidirectional operations regardless of parameter deviations. With this feature, thebidirectional tracking is further unified into tuning switching frequency online to keep Vab and Vcdin phase. Once Vab and Vcd are in phase as shown in Fig. 1.17, the maximum efficiency is achievedin both modes, regardless of the deviation of resonant tank parameters compared with conventionalfixed switching frequency for unregulated CLLC converters.26uPiPuPUdc UdcUdc UdcΔu=Proposed PFC with 2n Cells switching freuqncy fs, cell=fs /n, Ploss,s=Ps /2nConventional totem pole PFC, switching freuqncy fs, Ploss,s=Ps 20 ttiPDC/DCDC/DCDC/DCDC/DC2n02-Udc-UdcUnUn+1usususvacS1aS1bSnaSnbS(n+1)aS(n+1)bS(2n)aS(2n)bU1K1U2nK2NegativeCyclesuNiNuswusw(=uP-uN)iNPositiveCyclesLs is➊➊➊➊➋➌➌➍➍➍usw_conv Δu=-uNFigure 1.18: The proposed half-bridge based bidirectional multi-level PFC showing the fol-lowing benefits: ¶ Multi DC output ports via half bridges (maintaining the same DCout ports with half MOSFETs compared with cascaded full bridge PFC); · Lowervoltage and lower Rdson MOSFETs for lower conduction loss; ¸ Volt-second reduc-tion for smaller current ripple with same boost inductance;¹ Switching loss reductionfor the same equivalent fs.1.4.3 Cascaded Half-bridge Based PFC for low battery voltage applicationsThe third contribution of this thesis is the proposed cascaded half-bridge based multi-level multi-port bridgeless PFC rectifier as shown in Fig. 1.18. It is particularly suitable for low voltage batterycharging applications, as the high voltage DC bus is divided into multiple low voltage ports thatcan be utilized by the following CLLC DC/DC converters. This allows for the transformer ratioof the CLLC converters to be designed closer to 1, thus mitigating the design challenges of lowsecondary inductance for the CLLC resonant tank in low battery voltage applications.Compared with cascaded full-bridge multi-level PFC, the number of switches per cell for theproposed topology is significantly reduced by half while maintaining the same output ports. Theadded two switches, K1 and K2, are just working at grid frequency, and they can be simply replacedby two diodes if this proposed topology only works unidirectionally. Thanks to the volt-secondreduction on the boost inductor brought by multi-level voltage, the input current ripple drops re-markably with the same boost inductance as compared with conventional totem pole PFC rectifiers.The switching loss can also benefit from the proposed cascaded half-bridge topology. Compared27with cascaded full-bridge PFC with n full bridge cells, the proposed PFC can have 2n half bridgecells. Therefore, the switching voltage for each cell is lower than the cascaded full-bridge PFC,thereby leading to lower switching loss. Moreover, the conduction losses can also benefit from theproposed rectifier as the lower voltage switches with smaller Rds on are adopted in half-bridge cellscompared with conventional totem pole PFC rectifiers.1.5 Dissertation OutlineThe rest of this thesis is organized as follows:• In Chapter 2, the Asymmetric Parameters Methodology (APM) is introduced to design theresonant tank of bidirectional CLLC DC/DC converters for a wide battery voltage range.The equivalent circuit model and bidirectional gain formulas of asymmetric CLLC resonantconverter are derived. Precise maximum and minimum switching frequency models of theCLLC converter are presented by the statistical Design of Experiments (DoE) first. Andthen, a set of asymmetrical resonant tank parameters is obtained by analyzing statistical DoEresults. Optimization of wide voltage range operation of these resonant tank parameters isverified by experiments.• In Chapter 3, a unified bidirectional resonant frequency tracking method is proposed forunregulated CLLC DC/DC converters, which enables the unregulated CLLC converters withparameter deviations to operate at high efficiency bidirectionally. Bidirectional Resonant Fre-quency (BRF, fBRF) formula is derived based on generalized CLLC resonant tank models.Then, the proposed unified bidirectional tracking algorithm is analyzed and demonstrated.The technical challenges and their solutions in implementing the unified bidirectional reso-nance tracking algorithm will be discussed, and then efficiency improvement will be verifiedby experiments.• In Chapter 4, a cascaded half-bridge based bidirectional multi-level multi-port bridgelessPFC has been proposed for the AC/DC stage of the battery charger. Detailed operation princi-ples of the proposed cascaded half-bridge multi-level PFC are analyzed, and the steady-statemodel is proposed. To show the advantages of the proposed PFC topology, it is compared28with conventional boost PFC and cascaded full-bridge PFC topologies. Then, the parame-ter mismatch is analyzed, and the control strategy is presented for the proposed PFC. Theeffectiveness and performance are verified by experiments.• Chapter 5 concludes this thesis by summarizing contributions and planning the future workareas. This work contributes significantly to the bidirectional battery chargers. With theproposed techniques, EV batteries with various voltage levels can bidirectionally connectto the renewable energy grid efficiently and effectively. The contributions are publishedin relevant publications in IEEE Transactions journals and international IEEE conferencepapers.29Chapter 2Bidirectional Resonant CLLC Converter forWide Battery Voltage Range: AsymmetricParameters Methodology1The CLLC bidirectional resonant converter has significant potential in battery chargers, due toits bidirectional power transfer capability. To ensure uniform characteristics for bidirectional op-eration, secondary LC resonant tank components are usually designed to equal the primary LCcomponents after reflection. This conventional design method is regarded as the symmetric design.It is used in applications where wide voltage regulation is not required, such as CLLC DC trans-formers. However, for bidirectional battery charger applications, the battery has a wide voltagerange variation as the SoC changes. The gain requirements during charging and discharging aredifferent as well. These asymmetric characteristics could lead to an undesirable large switching fre-quency range if a conventional symmetric CLLC design is employed. As shown by the two red gaincurves in Fig. 1.16, the switching frequencies of conventional symmetric design, especially thosefrequencies for the minimum gain, are very different and far away from resonance. Therefore, theconventional symmetrical design method cannot meet the demanding requirements of bidirectionalchargers in the full operating region.Motivated by these problems, a detailed Asymmetric Parameters Methodology (APM) design1Portions of this chapter have been published in [1, 2]30is proposed in this chapter. To meet the multivariate optimization challenge of CLLC, the statisticalDesign of Experiments (DoE) has been adopted. It can obtain accurate models for multivariablesystems with a few measurements. A conceptual comparison of the proposed APM and conven-tional symmetric design is shown in Fig. 1.16. As indicated by ¶, the extra parameter designfreedom, introduced by the asymmetric resonant tank (Lr1 6=n2Lr2, Cr1 6=Cr2/n2), can be used tosuccessfully design gain curves for charging and discharging separately. Therefore, the proposedAPM switching frequency range of charging (turquoise area) can be designed to overlap with dis-charging (green area). Besides, both the maximum and minimum switching frequencies of the pro-posed APM have been reduced for charging and discharging (indicated by ·). The reduced partsare shown by the red areas in Fig. 1.16. This means that the bidirectional switching frequenciesof the proposed APM design are narrower than the traditional symmetrical design, therefore opti-mizing the efficiency and current stress of components. Moreover, since the minimum switchingfrequency is higher, the size of the transformer can be smaller[130]. The design of Electromag-netic Interference (EMI) filters filter will also be more optimal due to the uniform and reducedbidirectional switching frequency.The rest of this chapter is organized as follows. The equivalent circuit model and bidirectionalgain formulas of asymmetric CLLC resonant converter are derived in Section 2.1. In Section 2.2,precise maximum and minimum switching frequency models of the CLLC converter are presentedby the statistical Design of Experiments (DoE) at first. And then, a set of asymmetrical resonanttank parameters is obtained by analyzing statistical DoE results. Optimization of wide voltagerange operation of these resonant tank parameters is verified by experiments in Section 2.3. Finally,the summary is drawn in Section 2.4.2.1 Mathematical Model of Asymmetric Designed CLLCConverters2.1.1 Equivalent Circuit ModelAs shown in Fig. 2.1, CLLC resonant converters can transfer power bidirectionally. Power istransferred from the DC side to the batteries side in charging mode and it flows back to the DC bus31VSS5 S7S8S6S1 S3Lr1Lm1 Lm2ILr1VP VABCr1 Cr2n:1S4S2 Lr2VCD ILr2ChargeDischargeFigure 2.1: Circuit topology of CLLC converterfrom the batteries in discharging mode. There are two full bridges in the CLLC converter. The oneon the primary side acts as a high-frequency inverter while the secondary side performs rectificationin charging mode, and the roles of these two full bridges are reversed in discharging mode. TheCLLC resonant tank and high-frequency transformer are in the middle of the two full bridges, andthere are 6 parameters to be designed, which are resonant inductors Lr1 and Lr2, resonant capacitorsCr1 and Cr2, magnetizing inductance Lm, and transformer ratio n. Due to the proposed asymmetricdesign method, resonant parameters are no longer symmetric, which means:Lr1 6= n2Lr2,Cr1 6=Cr2/n2 (2.1)where Lr1, Lr2, Cr1, Cr2, and n are greater than 0.Compared with symmetric design, APM in this work has more design freedom for resonanttank components. This offers better flexibility for designing, but also brings some trade-off chal-lenges. Different from LLC converters, the CLLC resonant tank is composed of two LC tanks onthe primary and the secondary side respectively. Therefore, two quality factors and two resonantinductance ratios need to be defined to facilitate the design as:Q1 =√Lr1Cr1n2ReqS,Q2 =n2√Lr2Cr2ReqP(2.2)k1 =Lm1Lr1,k2 =Lm2Lr2(2.3)where ReqS and ReqP in (2.2) are an equivalent load of secondary and primary sides respectively.They can be obtained using the First Harmonic Approximation (FHA) modeling method, which is32widely used and assumes that only the first harmonic signals contribute to power transfer. AlthoughFHA models are easy to obtain, they tend to be inaccurate when the converter operates at frequen-cies far from its resonant frequency. In Section 2.2, a novel modeling method with higher accuracywill be presented to address the precision issue of FHA. As a commonly used design approach,FHA models are introduced in this section just for comparison with the later proposed accuratemodeling method. The equivalent loads of the secondary and primary, namely ReqS and ReqP, canbe calculated using the voltage and power on both sides with FHA as,ReqS =8pi2V 2SPS,ReqP =8pi2V 2PPP(2.4)Lm1 and Lm2 in (2.3) are transformer magnetizing inductance looking from the primary and sec-ondary side as shown in Fig. 2.2. Their ratio is Lm1/Lm2 = n2. The reflection rules to primary sidein Fig. 2.2(a) are L′r2=n2Lr2 and C′r2=Cr2/n2. The reflection rules to secondary side in Fig. 2.2(b)are L′r1=Lr1/n2 and C′r1=n2Cr1. VP is fixed in the application of the CLLC converter as the primaryside is usually connected to the DC bus, while the voltage of the batteries side VS varies within acertain range. Since CLLC converters should guarantee inductive operation and output maximumpower for the entire load range, the heaviest load is chosen as the design point, thus ensuring theconverter works properly under lighter loads. Considering the same power for both charging anddischarging mode, i.e., PP = PS, the load ratio based on (2.4) is written asReqPReqSmin=V 2PV 2Smin= (nMCmin)2 = (nMDmax)2 (2.5)where MCmin and MDmax represent the minimum gain in charging mode and maximum gain indischarging mode as shown in Fig. 1.16.2.1.2 Gain Formulas DerivationApart from the asymmetric loads mentioned above, gain requirements are also different for charg-ing and discharging. According to Fig.2.2(a), the current amplitude relationship between ILr1 and33Lr1Lm1Cr1 Cr2Lr2n2ReqSVABILr1 ILr2‘‘‘(a)Lr1Lm2Cr1 Cr2Lr2VCDILr1 ILr2‘‘‘ReqPn2(b)Figure 2.2: Equivalent circuit of CLLC resonant tank in (a) charging mode, obtained byreflecting the secondary equivalent load ReqS, Lr2 and Cr2 to the primary side as n2ReqS,L′r2 and C′r2, (b) discharging mode, obtained by reflecting the primary equivalent loadReqP, Lr1 and Cr1 to the secondary side as ReqP/n2, L′r1 and C′r1.I′Lr2 in charging mode can be shown as follows, where ωs is angular frequency,I′Lr2=∣∣∣∣∣ jωsLm1jωsLm1+ jωsn2Lr2+ n2jωsCr2 +n2ReqSmin∣∣∣∣∣ ILr1 (2.6)The voltage gain when charging MC isMC=nVSVP=I′Lr2ILr1n2ReqSminZinC(2.7)where ZinC is input impedance in charging mode,ZinC= jωsLr1+1jωsCr1+ ( jωsLm1)‖( jωsn2Lr2+ n2jωsCr2+n2ReqSmin) (2.8)34Combining (2.2), (2.3), and (2.5) to (2.8), gain formula of charging modeMC=∣∣∣∣∣ jωsLm1jωsLm1+ jωsn2Lr2+ n2jωsCr2 +n2ReqSmin∣∣∣∣∣·∣∣∣∣∣ n2ReqSminjωsLr1+ 1jωsCr1 + ( jωsLm1)‖( jωsn2Lr2+ n2jωsCr2 +n2ReqSmin)∣∣∣∣∣(2.9)Define resonant ωr asωr = 1/√Lr1Cr1 = 1/√Lr2Cr2 (2.10)Based on (2.2), (2.3) and (2.10), the CLLC resonant tank parameters Lr1, Lr2, Lm1(Lm2), Cr1and Cr2 areLr1 =Q1ReqSminn2ωr(2.11)Lr2 =Q2ReqPn2ωr(2.12)Lm1 =k1Q1ReqSminn2ωr(2.13)Lm2 =k2Q2ReqPn2ωr(2.14)Cr1 =1ωrQ1ReqSminn2(2.15)Cr2 =n2ωrQ2ReqP(2.16)35Combining equations (2.11), (2.12), (2.13), (2.14), (2.15) and (2.16) into equations (2.9)MC=∣∣∣∣∣∣∣∣jωsk1Q1ReqSminn2ωrjωsk1Q1ReqSminn2ωr + jωsn2 Q2ReqPn2ωr+ n2jωs n2ωrQ2ReqP+n2ReqSmin∣∣∣∣∣∣∣∣·∣∣∣∣∣∣∣∣n2ReqSminjωsQ1ReqSminn2ωr +1jωs 1ωrQ1ReqSminn2+ ( jωsk1Q1ReqSminn2ωr )∥∥∥( jωsn2 Q2ReqPn2ωr + n2jωs n2ωrQ2ReqP +n2ReqSmin)∣∣∣∣∣∣∣∣(2.17)Normalizing ωs with (2.10)ω∗ =ωsωr1=ωsωr2=ωs1/√Lr1Cr1=ωs1/√Lr2Cr2(2.18)ωr1 and ωr2 represent series resonant angular frequency for Lr1Cr1 and Lr2Cr2 respectively. Theseries resonant angular frequency ωr for CLLC resonant tank in both charging and dischargingmodes isωr =1√(Lr1+L′r2)(Cr1C′r2Cr1+C′r2)(2.19)Bringing equation (2.5) into (2.17), and simplifying the result by collecting k1MC(k1,Q1,Q2,ω∗) =k1√σ2k21 +σ1k1+σ0(2.20)whereσ0=((ω2∗ −1)2 Q22M4Cmin+ω2∗)(ω∗+1)2(ω∗−1)2ω6∗(2.21)σ1=2Q22M4Cmin(ω∗−1)3(ω∗+1)3+ 2Q1Q2M2Cmin (ω∗−1)3(ω∗+1)3−2ω2∗ω4∗+2 (2.22)σ2=(ω∗−1)2(ω∗+1)2(Q1+Q2M2Cmin)2ω2∗+1 (2.23)Likewise, the gain of discharging mode MD can be obtained as followsMD(k2,Q1,Q2,ω∗) =k2√ς2k22 + ς1k2+ ς0(2.24)36whereς0=((ω2∗ −1)2 Q21M4Dmax+ω2∗)(ω∗+1)2(ω∗−1)2ω6∗(2.25)ς1=2Q21M4Dmax(ω∗−1)3(ω∗+1)3+ 2Q1Q2M2Dmax (ω∗−1)3(ω∗+1)3−2ω2∗ω4∗+2 (2.26)ς2=(ω∗−1)2(ω∗+1)2(Q1M2Dmax+Q2)2ω2∗+1 (2.27)According to the derived equations (2.20) and (2.24), the gain requirements for the CLLCconverter with a wide voltage range are asymmetric in charging and discharging modes. Therefore,resonant tank parameters of the CLLC converter should be asymmetrically designed as well.2.1.3 Ranges of Quality FactorsThe equations for the ranges of quality factors can be obtained from bidirectional voltage gainrequirements. More specifically, the voltage gain in charging mode should be between its maximumand minimum values, which can be expressed as follows, MC ≤MC maxMC ≥MC min (2.28)Combining (2.20) with (2.28), voltage gain requirements in charging mode can be expressed asfollows, k1√σ2k21+σ1k1+σ0≤MC maxk1√σ2k21+σ1k1+σ0≥MC min(2.29)Square both sides of (2.29) and simplifyk21M2C max≤ σ2k21 +σ1k1+σ0k21M2C min≥ σ2k21 +σ1k1+σ0(2.30)37Collect k1 (σ2− 1M2C max )k21 +σ1k1+σ0 ≥ 0(σ2− 1M2C min )k21 +σ1k1+σ0 ≤ 0(2.31)Considering (2.31) has two quadratic functions of k1, define them as FC1(k1) and FC2(k1), whichcan be written in equations as:FC1(k1)∆= (σ2− 1M2C max )k21 +σ1k1+σ0 ≥ 0FC2(k1)∆= (σ2− 1M2C min )k21 +σ1k1+σ0 ≤ 0(2.32)To find the solution of charging mode gain requirements FC1(k1) and FC2(k1), discriminants oftwo quadratic inequations in (2.32) are defined as:∆FC1(k1)∆= σ21 −4σ0(σ2− 1M2C max )∆FC2(k1)∆= σ21 −4σ0(σ2− 1M2C min )(2.33)where, from (2.21) to (2.23), it can be observed thatσ0 ≥ 0σ1 ≥ 0 orσ1 ≤ 0σ2 ≥ 1(2.34)To obtain the solution of FC1 (k1) ≥ 0 and FC2 (k1) ≤ 0 in (2.32), case studies need to be per-formed based on (2.33) and (2.34). The results of the studies are shown in Table 2.1 and Table 2.2of this section. In these two tables, the sign of σ2− 1M2C max (or σ2−1M2C min) determines the open di-rection (up or down) of the parabola. σ1 and σ2− 1M2C max (or σ2−1M2C min) together determine the axisof symmetry for the parabola. ∆FC1 (k1) and ∆FC2 (k1) determine the number of intersection pointswith x-axis for parabolas FC1 (k1) and FC2 (k1) respectively. k1 is always greater than 0 accordingto its definition. The orange and turquoise indicate the σ1 ≥ 0 and σ1 < 0 respectively. And N/Ais used because ∆FC1 (k1) < 0 is not possible when σ2− 1M2C max < 0 according to (2.33). The samething happens for ∆FC2 (k1)< 0 when σ2− 1M2C min < 0.38Table 2.1: Case Studies for FC1 (k1) ≥ 0Conditions Casesσ2− 1M2C max < 0∆FC1 (k1)< 0 N/A∆FC1 (k1)≥ 0FC1k1FC1≥0, if①σ1≥0,k1>0②σ1<0,k1>0σ2− 1M2C max=0FC1≥0, ifk1FC1④σ1<0,k1>0③σ1≥0,k1>0σ2− 1M2C max > 0∆FC1 (k1)< 0k1FC1FC1>0, if⑤σ1<0,k1>0⑥σ1≥0,k1>0∆FC1 (k1)≥ 0k1k1a k1bFC1FC1≥0, if⑨σ1<0,0<k1<k1a⑧σ1<0,k1>k1b⑦σ1≥0,k1>039Table 2.2: Case Studies for FC2 (k1)≤ 0Conditions Casesσ2− 1M2C min < 0∆FC2 (k1)< 0 N/A∆FC2 (k1)≥ 0FC2k1 FC2≤0, if⑩σ1≥0,k1>0⑪σ1<0,k1>0σ2− 1M2C min=0(⑫No Solution for FC2≤0, if σ1≥0, k1>0)k1FC2⑬σ1<0,k1>0FC2≤0, ifσ2− 1M2C min > 0∆FC2 (k1)< 0k1FC2(⑮No Solution for FC2≤0, if σ1≥0, k1>0)(⑭No Solution for FC2≤0, if σ1<0, k1>0)∆FC2 (k1)≥ 0(⑯No Solution for FC2≤0, if σ1≥0, k1>0)k1FC2⑰σ1<0,k1>0FC2≤0, if40There are 17 cases ( 1© - 17©) in total in Table 2.1 and Table 2.2. From Table 2.1, FC1 (k1) ≥ 0can always find solutions when k1 > 0. However, in Table 2.2, solutions cannot be guaranteed forsome σ1 in cases 12©, 14©, 15©, and 16©. Only when σ2− 1M2C min < 0 can guarantee the solution for allσ1 when k1 > 0 in cases 10© and 11©.Therefore, the condition to meet (2.32) isσ2− 1M2C min< 0 (2.35)Combine σ2 in (2.34), and (2.35)  σ2 ≥ 1σ2− 1M2C min < 0 (2.36)By simplifying (2.36), the constraint on quality factors in charging mode can be obtained as1≤ σ2 ≤ 1M2C min(2.37)Combine (2.37) and (2.18), the following equation can be obtained:1≤(ω∗−1)2(ω∗+1)2(Q1+Q2M2C min)2ω2∗+1≤ 1M2C min(2.38)Solve (2.38), the quality factors range for charging mode is0≤(Q1+Q2M2C min)≤ω∗√1−M2C minMC min |ω2∗ −1|(2.39)There are two factors in (2.39), which are ω∗ and MC min, that restrict the upper limit of qualityfactors in charging mode. The closer ω∗ is to 1, the higher the upper limit is. However, MC min hasthe opposite effect.41Similarly, by (2.24) to (2.27), the range of quality factors in discharging mode is,1≤ ς2 ≤ 1M2Dmin(2.40)which can be simplified by plugging in (2.27) as0≤ Q1M2D max+Q2 ≤ω∗√1−M2DminMDmin |ω2∗ −1|(2.41)It can be observed that both Q1 and Q2 affect the gain range in charging mode and dischargingmode. When estimating ranges of quality factors for the CLLC converter, range restrictions onquality factors (2.39) and (2.41) should be considered at the same time for any mode.2.1.4 Ranges of Resonant Inductance RatiosIn charging mode, the maximum and minimum gain satisfy the following formulas:1M2C max< 1,1M2C min> 1 (2.42)Therefore, (2.37) can be summarized into 7 cases shown in Table 2.1. Considering all the casesin this table, to meet FC1(k1)≥ 0 and FC2(k1)≤ 0 simultaneously, k1 should bek1 > max(k1b,k1d) (2.43)where k1b and k1d can be calculated by letting FC1(k1) = 0 and FC2(k1) = 0 in (2.32), which arek1b =−σ1+√σ21−4σ0(σ2− 1M2C max)2(σ2− 1M2C max)k1d =−σ1+√σ21−4σ0(σ2− 1M2C min)2(σ2− 1M2C min)(2.44)Similarly, k2 should followk2 > max(k2b,k2d) (2.45)42where k2b =−ς1+√ς21−4ς0(ς2− 1M2Dmax)2(ς2− 1M2Dmax)k2d =−ς1+√ς21−4ς0(ς2− 1M2Dmin)2(ς2− 1M2Dmin)(2.46)According to (2.3) and (2.4), the ratio of k1 and k2 isk1k2=Q2Q1M2Cmin=Q2Q1M2Dmax (2.47)Combining (2.43), (2.45) and (2.47), the final upper limit for k1 in charging mode and discharg-ing mode isk1 > max[max(k1b,k1d) ,Q2Q1M2Cminmax(k2b,k2d)](2.48)The above two formulas show that k2 can meet the design requirements as long as k1, Q1, andQ2 are designed within a reasonable range. However, (2.48) does not mean that k1 can be infinite.Increasing k1 could lead to excessive magnetizing inductance Lm. This could flatten gain curvesand result in a large switching frequency range. Moreover, Lm also limits k1 from ZVS performanceperspective,Lm1 <TCs · tdead8C j,Lm2 <TDs · tdead8C j(2.49)where TCs and TDs are switching period in charging mode and discharging mode, tdead is the deadtime, and C j is the equivalent output capacitor of MOSFET.The range formulas of k1 and k2 are obtained from bidirectional gain requirements and ZVSperspectives in this section. Range equations (2.48) and (2.49) can be considered as a reference forestimating the range for k1 and k2.2.2 Statistical Design of Experiments for APMAccording to the mathematical model part above, there are four normalized parameters in the gainequations. These parameters affect the switching frequency range of the CLLC converter differ-ently. Meanwhile, the variation of parameters has an impact on each other as well. The optimizationof wide battery voltage operation for the CLLC bidirectional charger imposes a multivariate and43Table 2.3: Normalized Parameter RangeParameters Symbols Ranges SelectedQuality factor 1 Q1 [0.01 - 0.48] 0.239Quality factor 2 Q2 [0.01 - 0.23] 0.124Resonant inductance ratio 1 k1 [4 - 10] 5.5Resonant inductance ratio 2 k2 [4 - 10] 5.0multiple trade-off challenge. Motivated by these tradeoffs and challenges, the Design of Exper-iments (DoE) is adopted in the proposed APM to simplify the design. It is a general approachthat is widely adopted to obtain accurate models for multivariable systems [131]. DoE models cancompletely characterize maximum and minimum switching frequencies over the ranges of chosenfactors with a few measurements, and model accuracy is higher than FHA, especially when con-verters operate in a wide voltage range. Intermediate parameters of quality factor ratios (Q1, Q2)and resonant inductance ratios (k1, k2) are introduced as well to simplify the analysis of the impactsof multiple CLLC resonance variables. In this section, the design process of the statistical DoE willbe explained step by step. The entire design process is shown in Fig. 2.5.2.2.1 Initial Factor Ranges and ResponsesThe first step of statistical DoE is to determine factors and input their estimated initial range. ForCLLC converters, Q1, Q2, and k1 are selected as three factors for the charging mode, while Q1,Q2, and k2 are selected as three factors for the discharging mode. The formulas in Section 2.1of the mathematical model can be used as a reference to estimate initial factor ranges, or sometentative simulations can also help to define the boundary of factor ranges. In general, statisticalDoE can be performed with any initial factor ranges if these factor ranges cover the optimum factorvalues, although wider factor ranges may require more simulations to achieve satisfactory modelaccuracy. The factors ranges used for the proposed APM are summarized in Table 2.3. Consideringthe goal of the proposed APM is about the bidirectional switching frequency ranges, the responsesare selected as maximum and minimum switching frequencies fCmin, fCmax, fDmax and fDmin.442.2.2 Design Simulations and Obtain ResponsesIn general, the proposed APM (Asymmetric Parameters Methodology) requires two types of soft-ware. The first one is used to simulate the bidirectional CLLC resonant converters for checking thesoft switching and obtaining switching frequency responses for DoE. The following software canall be used to achieve this goal, including but not limited to• MATLAB with Simulink: it allows engineers to model complex battery charger systems withmultiple switching devices using standard circuit components. It helps them understand theinteraction of power converters and digital control during early development before hardwaretesting starts. With fast closed-loop simulation, power electronics engineers can evaluate andverify the resonant tank design and switching frequency responses before implementing aprototype.• PLECS: it helps to design and simulate the behavior of a battery charger under various op-erating conditions, including load and input voltage variations. It can visualize the circuit’soperation, including the waveforms of key signals and the flow of current and voltage throughthe circuit. This can be useful for understanding the frequency responses and the operationof the bidirectional resonant CLLC converters.• PSIM: it also helps engineers design and simulate the battery charger circuit, including thepower conversion stage and control logic, and analyze the frequency responses of the chargerunder different operating conditions. The frequency response data can be useful for laterstatistical DoE analysis and for understanding how the CLLC resonant DC/DC converterswill perform in real-world applications.Another kind of required software is the statistical DoE tool, which will be used to performthe statistical significance test and quadratic regression analysis in DoE. Various software packagescan do this, including but not limited to• The Real Statistics Resource Pack for Microsoft Excel [132, 133]: It is an add-on for Mi-crosoft Excel that offers additional statistical functions and tools for data analysis and designof experiments (DoE). These include functions for creating and analyzing full and fractional45factorial designs, functions for generating and analyzing response surface designs, tools forgenerating and analyzing custom designs, and tools for analyzing the results of DoE exper-iments through methods such as analysis of variance (ANOVA) and regression analysis. Byusing the Real Statistics Resource Pack, power electronics engineers can easily perform DOEin Excel, without the need for specialized software. This add-on is a valuable resource forthose looking to expand their statistical capabilities within Excel.• pyDOE [134]: Free and open-source package to perform DoE with Python. It provides toolsfor generating experimental designs using various sampling methods, such as full factorial,fractional factorial, and response surface designs. Using pyDOE, power electronics engineerscan design experiments to study the effects of different variables on a system or process,and identify optimal combinations of variables that yield the desired results. pyDOE alsoprovides tools for analyzing the results of experiments, including tools for fitting responsesurfaces and performing statistical analysis. This can help power electronics engineers toidentify trends in the data and understand how different variables are related to each otherand to the response of the system or process.• MATLAB [135]: One of the widely used software among engineers. It provides a range oftools and functions for DoE data analysis and visualization, including regression analysis,ANOVA, and t-tests. MATLAB also has powerful tools for visualizing data, including 2Dand 3D plots, histograms, and scatter plots. This can help engineers to identify patterns andtrends in the data, and to understand the relationships between different variables.• Design Expert [136]: It is a statistical software package, which is specifically dedicated toperforming DoE. It allows engineers to systematically vary the input factors that influencethe performance of the converter, such as switching frequency, inductance values, and capac-itor values, and to analyze the resulting output responses, such as efficiency and power factor.Using Design Expert, engineers can choose from a variety of experimental designs, includingfull factorial designs, fractional factorial designs, and response surface designs, dependingon the goals of the experiment and the resources available. They can also use the software46to analyze the results of the experiment using a variety of statistical techniques, includingANOVA, regression analysis, and surface response plots, to identify the key factors that in-fluence the frequency response of the converter and to optimize the design for the desiredperformance.To realize the proposed APM, researchers/engineers can choose a combination of the above twotypes of software. The combination used in the work is the PSIM and Design Expert. A range ofsimulation points based on the variations of factors will be designed in this step with two software.The Response Surface Methodology (RSM) can be applied in selecting these points for the CLLCswitching frequency modeling [137]. To minimize simulation runs while creating a robust quadraticparametric model, three measurement regions are considered in RSM design: factorial points, ax-ial points, and midpoint points[138]. These points are selected within factor range space. Withthree factors in charging or discharging mode, the design requires 20 simulations to completelycharacterize every maximum or minimum switching frequency for both charging and dischargingmode over the range of the chosen factors. After factor levels of factors are obtained, these RSMsimulation points could be generated by the statistical software mentioned above (Microsoft Excel,pyDOE, MATLAB, Design Expert, etc.). Then, simulations of these points can be performed by aPSIM script to sweep them in batches to obtain maximum and minimum frequency responses forcharging and discharging modes. The factors and extracted frequency responses for fcmin, fcmax,fdmin, and fdmax are summarized in Table 2.4, Table 2.5, Table 2.6, and Table 2.7 respectively. Allfactors used in the simulations and the response have three significant digits.2.2.3 Obtain Models and Analyze ResponsesThe statistical DoE uses regression analysis to produce accurate parametric models for multivariateand complex systems. It can be expressed mathematically as [131]F(Y ) = a0+n∑i=1aixi+n∑i=1n∑j=1bi jxiy j (2.50)In (2.50), Y is the response to be measured. F is a function of Y , which represents the parametricmodel. a0 is the overall mean value of the measurement, ai is the linear regression coefficients, bi j47Table 2.4: Simulation run points composed of different combinations of factors (Q1, Q2, andk1) are selected between the high and low factor levels. The minimum frequency responsein charging mode ( fcmin) for every run is recorded.Run Factor Q1 Factor Q2 Factor k1 Response fcmin1 0.0993 0.0100 6.25 0.7042 0.299 0.0389 6.34 0.7003 0.0100 0.232 7.06 0.6764 0.308 0.0917 9.85 0.6015 0.0118 0.232 4.42 0.7606 0.104 0.0822 10.0 0.6147 0.219 0.0100 4.00 0.7788 0.0118 0.232 10.0 0.6039 0.139 0.172 5.81 0.71310 0.0100 0.151 8.60 0.64411 0.0100 0.137 4.00 0.77712 0.0100 0.0400 4.00 0.78213 0.261 0.114 4.00 0.77614 0.480 0.0100 7.41 0.66315 0.431 0.0115 10.0 0.59816 0.480 0.0104 4.00 0.77717 0.0100 0.0100 8.68 0.66118 0.0100 0.0988 6.40 0.70519 0.221 0.0100 8.80 0.64020 0.191 0.107 7.69 0.661denotes the quadratic and interaction regression coefficients. n indicates the number of factors, andxi and x j are the variable factors.With the factor ranges and responses listed in Table 2.4, Table 2.5, Table 2.6, and Table 2.7,bidirectional maximum and minimum switching frequency models ( fCmin, fCmax, fDmax and fDmin)can be obtained through statistical significance test and quadratic regression analysis using equation(2.50). The resulting model equations are presented in equations (2.51), (2.52), (2.53), and (2.54)48Table 2.5: Simulation run points composed of different combinations of factors (Q1, Q2, andk1) are selected between the high and low factor levels. The maximum frequency re-sponse in charging mode ( fcmax) for every run is recorded.Run Factor Q1 Factor Q2 Factor k1 Response fcmax1 0.0993 0.0100 6.25 4.142 0.299 0.0389 6.34 2.023 0.0100 0.232 7.06 1.764 0.308 0.0917 9.85 1.865 0.0118 0.232 4.42 1.656 0.104 0.0824 10.0 2.557 0.219 0.0100 4.00 2.278 0.0118 0.232 10.0 1.839 0.139 0.172 5.81 1.7310 0.0100 0.151 8.61 2.2211 0.0100 0.137 4.00 1.9412 0.0100 0.0400 4.00 3.6913 0.261 0.114 4.00 1.6514 0.480 0.0100 7.41 1.8315 0.431 0.0115 10.0 1.9716 0.480 0.0104 4.00 1.6817 0.0100 0.0988 6.40 2.6418 0.167 0.158 10.0 1.7919 0.191 0.107 7.69 1.9620 0.222 0.0100 8.80 2.82asfCmin(k1,Q1,Q2) = 0.929+0.0456 ·Q1+0.0614 ·Q2−0.0425 · k1−0.0129 ·Q1 · k1−0.0198 ·Q2 · k1+0.00132 · k21(2.51)49Table 2.6: Simulation run points composed of different combinations of factors (Q1, Q2, andk2) are selected between the high and low factor levels. The minimum frequency responsein discharging mode ( fdmin) for every run is recorded.Run Factor Q1 Factor Q2 Factor k2 Response fdmin1 0.0993 0.0100 6.25 0.6082 0.299 0.0389 6.34 0.5973 0.0100 0.232 7.06 0.5524 0.308 0.0917 9.85 0.4865 0.0118 0.232 4.42 0.6616 0.104 0.0822 10.0 0.5007 0.219 0.0100 4.00 0.6898 0.0118 0.232 10.0 0.4699 0.139 0.172 5.81 0.60310 0.0100 0.151 8.60 0.52211 0.0100 0.137 4.00 0.69112 0.0100 0.0400 4.00 0.69313 0.261 0.114 4.00 0.68514 0.480 0.0100 7.41 0.55815 0.431 0.0115 10.0 0.49216 0.480 0.0104 4.00 0.68617 0.0100 0.0100 8.68 0.54818 0.0100 0.0988 6.40 0.60219 0.222 0.0100 8.80 0.53920 0.191 0.107 7.69 0.546fCmax(k1,Q1,Q2) = 4.47−14.9 ·Q1−33.9 ·Q2+0.190 · k1+81.5 ·Q1 ·Q2−0.300 ·Q1 · k1−0.676 ·Q2 · k1+17.9 ·Q12+90.7 ·Q22(2.52)50Table 2.7: Simulation run points composed of different combinations of factors (Q1, Q2, andk2) are selected between the high and low factor levels. The maximum frequency re-sponse in discharging mode ( fdmax) for every run is recorded.Run Factor Q1 Factor Q2 Factor k2 Response fdmax1 0.0993 0.0100 6.25 2.992 0.299 0.0389 6.34 1.823 0.0100 0.232 7.06 1.744 0.308 0.0917 9.85 1.835 0.0118 0.232 4.42 1.556 0.104 0.0822 10.0 2.457 0.219 0.0100 4.00 1.718 0.0118 0.232 10.0 1.869 0.139 0.172 5.81 1.6510 0.0100 0.151 8.60 2.1811 0.0100 0.137 4.00 1.6612 0.0100 0.0400 4.00 2.0613 0.261 0.114 4.00 1.4914 0.480 0.0100 7.41 1.7315 0.431 0.0115 10.0 1.9016 0.480 0.0104 4.00 1.4917 0.0100 0.0988 6.40 2.3318 0.156 0.164 9.97 1.8219 0.191 0.107 7.69 1.8820 0.222 0.0100 8.80 2.48fDmin(k2,Q1,Q2) = 0.889+0.0163 ·Q1+0.0743 ·Q2−0.0564 · k2−0.00902 ·Q1 · k2−0.0334 ·Q2 · k2+0.00204 · k22(2.53)51fDmax(k2,Q1,Q2) = 1.61−3.92 ·Q1−9.24 ·Q2+0.296 · k2+30.26 ·Q1 ·Q2−0.497 ·Q1 · k2−1.04 ·Q2 · k2+6.70 ·Q12+34.9 ·Q22(2.54)Equations (2.51) ∼ (2.54) as are valid over the entire factor ranges with accuracy proportionalto the adjusted R2 value of the model [131]. Taking (2.51) as an example, the fit statistics areshown in Table. 2.8. The Predicted R2 of 0.9976 is in reasonable agreement with the Adjusted R2of 0.9986; i.e. the difference is less than 0.2. Adeq Precision measures the signal-to-noise ratio. Aratio greater than 4 is desirable. A ratio of 114.926 indicates an adequate signal. Therefore, thismodel can be used to navigate the design space.Table 2.8: Fit statistics of DoE model for minimum switching frequency fCmin in the chargingmode.Std. Dev. 0.0025Mean 0.6917C.V. % 0.3597R2 0.9991Adjusted R2 0.9986Predicted R2 0.9976Adeq Precision 114.9256To show the model error intuitively, four test points with different space types are selectedrandomly, and they are different from the data used in modeling in Table 2.4. The model analysisresults are shown in Table 2.9.The errors in Table 2.9 is calculated byferr =∣∣ fcmin p− fcmin s∣∣fcmin p(2.55)where fcmin p is the minimum switching frequency predicted by DoE model in (2.51); fcmin s is theminimum switching frequency by simulation. It can be seen from Table 2.9 that the model (2.51)52Table 2.9: Model errors analysis for minimum switching frequency fCmin in the chargingmode.RunSpacetypeQ1 Q2 k1Fre. bymodel(2.51):fcmin pFre. bysim.:fcmin sErrorsferr1 Plane 0.146 0.154 4.00 0.776 0.775 0.129%2 Interior 0.368 0.062 4.27 0.767 0.766 0.130%3 Edge 0.262 0.113 5.801 0.713 0.713 0%4 Vertex 0.218 0.134 10.0 0.599 0.601 0.334%accurately predicts fcmin, and the maximum error is 0.334%.To facilitate trade-off analysis, switching frequency models (2.51) ∼ (2.54) are visualized inFig. 2.3 and Fig. 2.4. For each switching frequency response figure, two different variables areselected carefully according to their significance.The optimization goals are to increase the bidirectional overlapping frequency range and reducethe switching frequency range. Therefore, optimal parameters should meet the following threerequirements. 1) maximum and minimum switching frequencies of charging mode and dischargingmode ( fCmin, fCmax, fDmax and fDmin) of the converter should move closer to the resonant frequencyfr = 1 compared with symmetrical design; 2) the maximum ( fCmax, fDmax) and minimum frequency( fCmin and fDmin) of charging mode and discharging mode should be similar to increase overlappingswitching frequency range; 3) optimized parameters should also ensure that the gain characteristicscan completely cover the required range without multi-peaks.In Fig. 2.3, as Q2 increases, the available range of Q1 is narrowing. Similar things happen inFig. 2.4. Moreover, kr and Qr(= Q1/Q2) are coupled, which can be obtained through definitionequations (2.2), (2.3) and (2.5) as:kr=k1k2=1QrM2C min=M2DmaxQr(2.56)This shows that k1 6= k2 for APM and kr can be adjusted by tuning Qr. In contrast, kr is fixed53(a)(b)Figure 2.3: Response surfaces of statistical DoE in charge mode: (a) surfaces of the minimumcharge frequency fcmin versus k1, Q1 and Q2. (b) surfaces of the maximum chargefrequency fcmax versus k1, Q1 and Q2. Optimal parameter candidate areas (dark gray)are highlighted by turquoise rectangles.(k1 = k2) for conventional symmetric design. Therefore, the proposed APM brings higher designflexibility to the CLLC converter. Considering the regulation flexibility and efficiency of CLLCconverters, the ranges of k1 and k2 in figures are limited between 4 and 10 due to limitationsin (2.56). Therefore, as k1 increases, the available space of Qr becomes smaller. Trade-offs ofparameter selection can be analyzed from the switching frequency range perspective in Fig. 2.3and Fig. 2.4. In Fig. 2.3(b), the value of Q1 and Q2 have a dominant role on fCmax, and thebidirectional frequency range of the CLLC converter can be reduced if both Q1 and Q2 are designedto be sufficiently large. However, they cannot be simultaneously large due to (2.56), so the selectionof Qr needs to take kr into consideration. According to (2.56), if Qr <M2Dmax, then kr > 1 (k1 > k2);54(a)(b)Figure 2.4: Response surfaces of statistical DoE in discharge mode: (a) surfaces of the min-imum discharge frequency fdmin versus k2, Q2 and Q1. (b) surfaces of the maximumdischarge frequency fdmax versus k2, Q2 and Q1. Optimal parameter candidate areas(dark gray) are highlighted by green rectangles.meanwhile, Fig. 2.4(a) shows that the smaller k2 can bring fDmin closer to fr = 1. Hence, fDminrange could be optimized by APM (k1 > k2), while conventional symmetric design (k1 = k2) cannot.As for fDmax demonstrated in Fig. 2.4(b), increasing Q2 (i.e. decreasing Qr, so k1 > k2) in the APMwill decrease fDmax, and decreasing k2 also leads fDmax closer to fr = 1. Then, the frequency rangeof the high voltage discharge fDmax is still optimized by kr increasing and Qr decreasing. ForfCmin in Fig. 2.3(a), increasing k1 will decrease fCmin, which causes fCmin away from resonantfrequency. Therefore, k1 cannot be increased excessively, as fCmin and fDmin should be close to55Define initial factor ranges and responsesObtain switching frequency models ((2.51) - (2.54)) bystatistical significance test and quadratic regression analysisCalculate resonant tank parameters by definition equations (2.2) (2.3) (2.18)Expand initial factor ranges Design simulations by Response Surface MethodologyPlot response surfaces with models, and do trade-off analysis to refine initial factor ranges (Dark gray area in Fig. 2.3, Fig. 2.4)Select factor values within refined factor ranges.Obtain max. and min. switching freqency responses by simulationsEndNYFulfill bidirectional gain and ZVS requirements?(Check by simulations)StartFigure 2.5: Design flowchart for the proposed APM to find optimum asymmetric parametersby DoE.improve the overlapping frequency range of charging mode and discharging mode. It can only beproperly greater than k2 so that kr can be greater than 1. Based on the above trade-offs analysis anddefinition equation (2.56), criteria for selection of kr and Qr are kr > 1Qr < 1/M2C min = M2Dmax (2.57)According to Fig. 2.4(a), fDmin that is closest to fr = 1 is around 0.6 to 0.7. Therefore, fCminin Fig. 2.3(a) can also be selected around 0.7, considering the bidirectional overlapping and fCmaxselection. In Fig. 2.3(a) and Fig. 2.4(a), two ranges are indicated by gray areas for Qi and ki (i=1,2).The points in the dark gray area (common area) are candidates for optimal Qi and ki. Parameter5610.6911.23 Proposed APMConventional DesignMC(MCmin)(MCmax)f*1.7 1.970.70.62Range of APM DesignRange of Conventional Design(a)1 1.610.640.53 1.90.8111.45Proposed APMConventional Design(MDmax)Range of APM DesignRange of Conventional Design(MDmin)MDf*(b)Figure 2.6: Simulation gain curves to compare proposed APM and conventional design: (a)charge mode, and (b) discharge mode. Two subfigures show that the proposed APMdesign has the advantage of a narrower switching frequency variation range for bothmodes.candidates for fCmax and fDmax can also be found in a similar way as dark gray areas in Fig. 2.3(b)and Fig. 2.4(b). Finally, the optimum resonant tank parameter can be selected within those pointsthat satisfy (2.57), and that in the intersection of four common areas in Fig. 2.3 and Fig. 2.4.2.2.4 Selection and Verification of Factor ValuesSeveral simulations can help with the final parameter decision within those limited points in con-sidering overlapping and switching frequency variation ranges of charging mode and dischargingmode. By doing this, kr is selected as 1.1 in this work with respect to (2.57) and simulations ofparameter points in four common areas. It represents the asymmetric degree of the resonant tank,and kr = 1.1 means that the resonant tank is 10% asymmetry. Therefore, the final k parametersare k1 = 5.5, and k2 = 5. The final selected Qi parameters are Q1 = 0.239, Q2 = 0.124 whenQr = 1.93. Selected values are summarized in Table 2.3. The designing process of the proposedAPM is presented in the flowchart Fig. 2.5.57To verify the selected asymmetric parameters, a series of simulations have been done to plotgain curves as shown in Fig. 2.6. The conventional symmetric design results are also shown in thesame figure as a comparison. From simulation results in Fig. 2.6, the operating frequency range ofAPM meets the design requirements. The bidirectional minimum frequency is around the expectedvalue 0.7 ( fCmin=0.7, and fDmin=0.64), while the maximum frequency is, as expected, in the rangeof [1.6 - 1.7] ( fCmax=1.7, and fDmax=1.61). Meanwhile, for charging mode and discharging mode,APM has a high bidirectional frequency overlapping range as well, namely [0.7 - 1.61] (from fCminto fDmax). In contrast, the traditional design results are farther away from the resonance point fr =1 than the APM, which results in the problem of a wider switching frequency variation.The improvement in switching frequency range brought by the APM proposed in this workhelps the design of transformers and EMI filters. With the proposed APM, the CLLC bidirectionalresonant converters operate with a smaller transformer size since the minimum normalized switch-ing frequency in discharging mode is 0.64 for the proposed APM ( fsmin APM) as compared to 0.53( fsmin conv) for conventional design as shown in Fig. 2.6(b). The transformer core is selected toavoid saturation for the lowest switching frequency [130]. Then, the change of flux-density ∆B canbe expressed as∆B=VP2 fsmin ·N ·A (2.58)Where Vp is the voltage of the DC bus on the primary side, fs min is the minimum switching fre-quency, N is the number of turns, and A is the core cross-section area. Assuming the same ∆B, N,and Vp are adopted for both transformers of the proposed APM and the conventional design, thecore cross-section area ratio obtained from (2.58) isAconvAAPM=fsmin APMfsmin conv=0.640.53= 1.21 (2.59)Since the core for fsmin APM is smaller than the core for fsmin conv, the size of the core cross-section of the conventional symmetric design Aconv is 21% larger than the size of the core cross-section of the proposed APM AAPM.The purpose of the EMI filter is to contain the converter noise within the converter and not58let it go to the grid. The converter noise comes from both AC/DC and DC/DC. And EMI filter isdesigned to target all noise sources. In EV battery charger circuits, noise can come from varioussources (AC/DC and DC/DC stages) and can affect the performance of the chargers. Noise can beclassified into two categories: differential mode noise and common mode noise. Differential modenoise is a type of noise that appears as a voltage difference between two conductors of a circuitand is rejected by differential amplifiers. Common mode noise is a type of noise that appears asa voltage common to both conductors of a circuit and is not rejected by differential amplifiers.Differential mode noise and common mode noise can have different pathways through a circuit asshown in Fig. 2.7 below. Very high di/dt and du/dt are generated during the high-frequency on-offprocess of MOSFET, and strong inrush current and peak voltage are formed. This is one of the mostbasic reasons for the electromagnetic interference of switching power converters. If the switchingrange is smaller, the design of the EMI filter will be more optimal, as we can tune it for narrowerfrequencies. When the frequency variation is large, the EMI filter should be able to provide enoughattenuation for a broad range of operating points. Therefore, we might overdesign the filter to beable to comply with the standard for all operating points.Filter AC/DCBidirectionalDC/DCBidirectional EVBatteryEMITheGridMain noise sources from equipmentDifferential Mode noiseCommon Mode noiseFigure 2.7: AC/DC and DC/DC converters are the main EMI noise sources. Differentialmode noise and common mode noise can have different pathways.2.3 Experimental Verification of the Proposed APMTo verify the proposed AMP for wide battery voltage range operation, a 1 kW bidirectional CLLCconverter prototype was built as shown in Fig. 2.8. Based on the selected normalized parametersin Table 2.3, and (2.2), (2.3), and (2.18), APM designed resonant tank parameters Lr1, Lr2, Lm, Cr1,and Cr2 can be obtained. These prototype parameters are summarized in Table 2.10. For power59Control boardCLLC resonant tankBridges of primary andsecondary sides TransformerFigure 2.8: The bidirectional resonant CLLC converter prototype was designed by the pro-posed APM.switches, S1 - S4 act as a high frequency inverter while S5 - S8 perform high frequency rectifica-tion with their body diodes in charging mode. Their roles are exchanged in discharging mode.Therefore, SiC MOSFETS are adopted to ensure fast reverse recovery of power switches. Consid-ering voltage and power levels, SCT3060AL MOSFET from ROHM Semiconductor is selected.An electronic load is used in both charging mode and discharging mode. Its voltage in chargingmode, which is Vs, is programmed to vary between 250V and 450V at 1kW to emulate the batterycharging process, and the DC power supply connected to Vp is fixed as 400V. Meanwhile, this DCpower supply is connected to Vs in discharging mode, and it varies from 250V to 450V to emulatebatteries in discharging mode where these batteries are considered as input DC source. The e-loadin discharging mode, connected to Vp, is set as 400V 1kW.2.3.1 Experiments of Proposed APM DesignFig. 2.9 shows measured voltage and current waveforms of APM designed CLLC charger operatingat different switching frequencies in charging mode. To verify wide voltage range performance incharging mode, the voltage of battery side VS is set as 450V and 250V with fixed VP=400V, andexperiment results are shown in Fig. 2.9(a) and Fig. 2.9(b) respectively. In Fig. 2.9(a), CLLCbidirectional charger works at boost mode. Some high frequency oscillations appear on the outputrectifier diode. Charger operates at buck mode in Fig. 2.9(b), where the gain is less than 1 to meetthe gain requirements of low battery voltage. Switching frequencies fmin and fmax in Fig. 2.9(a)and Fig. 2.9(b) are 69 kHz and 185 kHz. In Fig. 2.9(c), the prototype works in an open loop at60Ir1VABVPIr2VCDVSZVSZCSIr2max=4.6A69 kHz(a)Ir1VABVPIr2VCDVSZVS185 kHz(b)Ir1VABVPIr2VCDVSZVS100 kHzIn phaseZCS(c)Figure 2.9: Experiments in the charging mode of the proposed APM designed CLLC, whichare showing that the converter regulates wide output voltage with a switching frequencyrange from 69kHz to 185kHz. (a) below resonance, (b) above resonance and (c) atresonance.61Table 2.10: Parameters of CLLC Converter PrototypeParameters Symbols ValuesSpecificationsVoltage of DC Bus VP 400 VdcBatteries Voltage Range [VSmin-VSmax] [250 - 450] VdcCharging Gain Range [MC min - MC max] [0.688 - 1.234]Discharging Gain Range [MDmin - MDmax] [0.809 - 1.455]Nominal Power Pn 1 kWResonant Frequency fr 100 kHzDesigned ParametersTransformer Ratio n 1.1Resonant Inductor 1 Lr1 23 uHResonant Inductor 2 Lr2 21 uHMagnetizing Inductance Lm 128 uHResonant Capacitor 1 Cr1 110 nFResonant Capacitor 2 Cr2 120 nFthe resonant frequency of 100 kHz. Bridge voltage VAB and VCD are in phase, and both Ir1 and Ir2are sinusoidal with a frequency around 100kHz. Moreover, ZVS for the primary side MOSFETsand ZCS for the secondary side diodes are achieved. The efficiency at the resonant frequency is97.31%.Fig. 2.10(a) and Fig. 2.10(b) show the wide voltage range operation results of the CLLC con-verter in discharging mode. Similar to charging mode, the e-load side VP is fixed at 400V whilethe DC source side VS are 250V and 450V for operation below and above resonance respectively.frmin and frmax can be measured in Fig. 2.10(a) and Fig. 2.10(b) as 60kHz and 194kHz. Com-bined with the charging frequency range shown in Fig. 2.9, the overlapping frequency range in thecharging mode and discharging mode of APM is from 69kHz to 185kHz. This wide overlappingfrequency range can reduce the bidirectional frequency range of APM designed chargers for a widevoltage range operation. CLLC bidirectional converter is working at resonant frequency 100 kHzin discharging mode in Fig. 2.10(c). As power direction changes in discharging mode, the ZVScharacteristic can be found in waveforms of secondary bridge voltage VCD and secondary resonant62Ir1VABVPIr2VCDVSZVSZCSIr1max=5.8A60 kHz(a)Ir1VABVPIr2VCDVSZVS194 kHz(b)Ir1VABVPIr2VCDVSZVSZCS100 kHzIn phase(c)Figure 2.10: Experiments in the discharging mode of the proposed APM designed CLLC,which are showing that the converter regulates wide output voltage with a switchingfrequency range from 60kHz to 194kHz. (a) below resonance (b) above resonance,and (c) at resonance.630.6911.23MC(MCmin)(MCmax)0.7 1 1.3 1.6 1.9 2.2SimExpDoEFHAf*(a)0.7 1 1.3 1.6 1.9 2.2SimExpDoEFHAf*0.8111.45(MDmax)(MDmin)MD(b)Figure 2.11: Predicted frequency ranges comparison of statistical DoE and FHA model. Sta-tistical DoE shows higher accuracy in predicting max. and min. frequencies than FHAto simulations and experiments in (a) charging mode (b) discharging mode.current Ir2. And primary side body diodes can also switch with ZCS characteristics. The efficiencyof the converter working at resonance in discharging mode is 98.1%.In order to show the frequency range prediction results of the traditional FHA and statisticalDoE, gain and switching frequency data obtained through FHA, DoE, simulations, and experi-ments are shown in Fig. 2.11. It can be found that statistical DoE can predict switching frequen-cies for maximum and minimum charging/discharging gain with reasonable errors in simulationsand experiments. This is because models of statistical DoE are extracted from the simulations.Nonetheless, for FHA, there are large errors in most cases, especially for minimum charging anddischarging gain (MCmin and MDmin). As for the discrepancies between simulation and experimen-tal results, it primarily arises due to real-world complexities like component tolerances, parasitics,and non-ideal operating conditions, which are not fully accounted for in simulations. Therefore, itcan be concluded that the DoE model predicts the bidirectional operating frequency range of CLLCconverters more accurately than FHA.642.3.2 Design Trade-offs for Turn-off CurrentsThe turn-off current is the tradeoff result of the phase angle of input impedance φ , ZVS margin,and bidirectional switching frequency range. The ZVS angle φ in charging mode, which refers tothe angle of the zero-crossing of Vab and Ir1, is shown in Fig. 2.12 below. When ZVS angle φ isbetween 0◦ and 90◦, the larger φ , the larger the turn-off current. The detail will be discussed below.(a)(b)Ir1VABVPIr2VCDVSZVS100 kHzZCSZVS Angle φIr1VABVPIr2VCDVSZVS185 kHzZVS Angle φFigure 2.12: Experiments in charging mode of proposed APM designed CLLC (a) At res-onance (b) Above resonance, showing that φ decreases as the switching frequencyincreases.To find the phase angle of input impedance φ , the equation of input impedance in charging65mode ZinC can be obtained from Fig. 2.2(a) in the paper asZinC( jωs) = |ZinC|e jϕ= jωsLr1+ 1jωsCr1 + ( jωsLm1)‖( jωsn2Lr2+n2jωsCr2+n2ReqS) (2.60)Where the symbol ‖ indicates that two impedance is in parallel.If fs = fILr1, which means ωs = ωr, Lr1, and Cr1 will be in series resonance, and Lr2 and Cr2will be in series resonance as well. The (2.60) is simplified asZinC( jωr) = |ZinC|e jϕ= ( jωsLm1)‖(n2ReqS)=jωrLm1n2ReqSjωrLm1+n2ReqS=ωrLm1n2ReqS√n4R2eqS+ω2r L2m1e j arctann2ReqSωrLm1(2.61)Where ZVS angle φ can be obtained asϕ = arctann2ReqSωrLm1(2.62)Therefore, when fs = fILr1 in charging mode, φ is mainly determined by Reqs, ωr, n, and Lm1.The heavier the load (the smaller the Reqs), the smaller the φ . At the same time, as the frequency(ωr) goes higher, and Lm1 becomes larger, the φ becomes smaller as well. It is obvious from Fig.2.12 that φ should be positive to provide soft-switching conditions (ZVS) for MOSFETs. Thelarger the phase angle φ , the larger the ZVS margin. However, too large a phase angle φ wouldcause a high turn-off current for power switches and passive elements.To achieve a smaller turn-off current, according to equation (2.62), a larger Lm1 could be se-lected. Nonetheless, excessive Lm1 may reduce φ and ZVS margin. Especially when the switchingfrequency increases, φ will decrease further, as shown in the experimental results in Fig. 2.12(b).At the same time, a larger Lm1 could cause a larger k1 (shown in equation (2.3)), which may lead toa larger switching frequency range. Therefore, the proposed APM comprehensively considers theparameters designed by the following 3 points: turn-off current, the φ margin to ensure ZVS at thelowest voltage, and the switching frequency range.66Table 2.11: CLLC Resonant Tank Parameters of Conventional Symmetrical DesignConventional Symmetrical Design Parameters Symbols ValuesResonant Inductor 1 (Conv) Lr1 Conv 20.50 uHResonant Inductor 2 (Conv) Lr2 Conv 17.07 uHMagnetizing Inductance (Conv) Lm Conv 164.06 uHResonant Capacitor 1 (Conv) Cr1 Conv 130 nFResonant Capacitor 2 (Conv) Cr2 Conv 150 nF2.3.3 Comparison of Proposed APM Design and Conventional SymmetricDesignTo compare the proposed APM and conventional symmetric design, a conventional symmetricallydesigned CLLC resonant converter was built in the lab. The proposed DoE was also used to selectthe resonant tank parameters for conventional symmetrical design in comparison experiments. Theparameters chosen were Q1 = 0.21, Q2 = 0.10, k1 = 8, and k2 = 8. Using these parameters, thevalues of tank inductance and capacitance can be calculated, which are listed in Table 2.11.Fig. 2.13 and Fig. 2.14 show the experimental results of conventional symmetric designedCLLC in charging mode and discharging mode respectively. When the symmetrical designedCLLC is operating in a wide voltage range as shown in the figures, fmin and frmin are at 58 kHzand 49 kHz to provide sufficient gain, which is lower than the APM design in Fig. 2.9(a) and Fig.2.10(a). These low frequencies of symmetric design lead to a larger peak current on the rectifierside, which brings higher current stress to the switching devices. In Fig. 2.13(a) and Fig. 2.14(a),the charging mode and discharging mode currents are 5.1A and 6.8A respectively, while the APMdesign currents can be read from Fig. 2.9(a) and Fig. 2.10(a) as 4.6A and 5.8A.Similarly, the symmetrical design of fmax and frmax are larger than the APM design, as shownin Fig. 2.13(b) and Fig. 2.14(b), which are 210kHz and 330kHz. The overlapping frequency rangeof conventional design in charging mode and discharging mode is from 58kHz to 210kHz, but thegap between fmax and frmax reaches 120kHz, which causes a large gap between the bidirectionalworking frequency range of charging mode and discharging mode, bringing difficulties in designingEMI filters for bidirectional converters. Besides, fmax and frmax far from resonant frequency also67Ir1VABVPIr2VCDVSZVSZCSIr2max=5.1A58 kHz(a)Ir1VABVPIr2VCDVSZVS210 kHz(b)Figure 2.13: Experiment results of conventional symmetric designed CLLC in chargingmode with different switching frequencies. (a) below resonance, and (b) above res-onance. Compared with the proposed APM, the conventional symmetric design op-erating in a wide voltage range has the disadvantages of a larger frequency range andhigher peak current.bring additional switching losses and reduce the efficiency of the converter. Further efficiencycomparisons are introduced below.As shown in Fig. 2.15, an efficiency comparison was conducted between the proposed APM de-sign method and the conventional symmetric design method. The efficiency was measured for thebattery voltage Vs range of 250V-450V. The bidirectional resonant CLLC convert is in CC mode forthe battery voltage range of 250V-410V when using the CC/CV charging profile. Once the batteryvoltage reaches 410V, the charger switches to CV mode. Efficiency curves of APM design are in-dicated by solid lines, and traditional symmetrical design efficiency curves are indicated by dashedlines. The blue and orange lines demonstrate the efficiency in charging mode and discharging mode68Ir1VABVPIr2VCDVSZVSZCSIr1max=6.8A49 kHz(a)Ir1VABVPIr2VCDVSZVS330 kHz(b)Figure 2.14: Experiment results of conventional symmetric designed CLLC in dischargingmode with different switching frequencies. (a) below resonance, and (b) above reso-nance. Compared with the proposed APM, the conventional symmetric design oper-ating in a wide voltage range has the disadvantages of a larger frequency range andhigher peak current.respectively. It was found that the proposed APM designed CLLC converter is more efficient thanthe traditional symmetric design whether in charging mode or discharging mode. The maximumefficiency of the two design methods is similar. The highest efficiency of APM in charging modeand discharging mode are 97.9% and 98.06%, while the traditional symmetrical design of chargingmode and discharging mode are 97.36% and 97.6%. However, there is a certain gap in minimumefficiency. The minimum APM bidirectional efficiency is 94.69% and 94.74%, but the traditionalsymmetrical design is 92.9% and 93.8%, which are lower than the proposed designed APM.According to the trend of the efficiency curves in Fig. 2.15, CLLC converter has higher bidi-rectional efficiency within 300V-400V due to working near the resonance frequency. However,69250 275 300 325 350 375 400 425 450Battery Voltage CV Mode Vs [V]9293949596979899Efficiency [%]Proposed APM ChargingProposed APM DischargingConventional Symmetric ChargingConventional Symmetric DischargingCC Mode Figure 2.15: Measured Efficiency Comparison of Proposed APM and Traditional SymmetricDesign. Proposed APM shows higher efficiency in both charging mode and discharg-ing mode than conventional symmetric design.charging mode and discharging mode perform differently in the low Vs range (250V-300V) andhigh Vs range (400V-450V). Higher efficiency of charging mode is obtained in the low Vs rangethan high Vs range, where switching frequency fs is higher than the resonance frequency fr in250V-300V Vs range. On the other hand, in discharging mode, the converter has higher efficiencyin the high Vs range (400V-450V) than low Vs range. It is worth noting that Vs is regarded as theinput power side in discharging mode because of the power flow direction. Therefore, fs is stillhigher than fr in high Vs range in discharging mode. In summary, the bidirectional CLLC resonantcharger has the highest efficiency near the resonance frequency, and the bidirectional efficiency isgreater than 97%. Moreover, bidirectional efficiency below fr drops faster than above fr.2.4 SummaryIn this chapter, an APM to design a resonant tank was proposed for bidirectional CLLC resonantchargers to optimize wide battery voltage range operation. To meet the multivariate optimizationchallenge of CLLC, the statistical Design of Experiments (DoE) has been adopted. It can obtainaccurate models for multivariable systems with a few measurements. With the proposed APM, extraparameters freedom could be used to design gain curves for charging and discharging separately.70Hence, the switching frequency ranges of CLLC converters in charging mode and dischargingmode are narrower and more unified compared with conventional symmetric design. The efficiencyof wide battery voltage range operation is improved, and the transformers’ design of the CLLCconverter can also benefit from it. Finally, these advantages of the proposed APM design areproved by comparison experiments on a CLLC bidirectional charger prototype.71Chapter 3Unified Bidirectional Resonant FrequencyTracking for CLLC Converters1In the previous chapter, an asymmetric design method was proposed to improve the wide voltageregulation performance of CLLC resonant DC/DC converters. CLLC converters also show signif-icant potential in unregulated operations in two-stage battery chargers due to their high efficiencyand bidirectional capability. The term ”unregulated” means that the output is not controlled to aspecific value, but the converter could still be controlled in a way that meets the needs of the ap-plication. In these applications, unregulated CLLC converters are usually designed to have theirswitching frequency fixed at resonance for maximum efficiency. However, the resonant frequencydrifts from the designed value due to resonant tank parameter deviations, which leads to a decreasein efficiency for unregulated CLLC converters. Although the parameter deviation problem hasbeen studied for unidirectional converters, published solutions cannot be applied directly to bidi-rectional tracking. CLLC converters have multiple different resonant frequencies in both forwardand backward modes. Therefore, the generalized resonant frequency equations characteristics andbidirectional resonant frequency tracking method are still worth studying.To address these issues, this chapter proposes a unified bidirectional resonant frequency track-ing algorithm as shown conceptually in Fig. 1.17. With the proposed tracking algorithm, theforward mode and backward mode resonant frequencies tracking is unified and simplified, and1Portions of this chapter have been published in [3, 4]72therefore the cost and complexity are reduced compared with using unidirectional tracking meth-ods in forward and backward modes separately. These advantages are achieved with the help oftwo interesting features of the Bidirectional Resonant Frequency (BRF or fBRF). To begin with, bythe analysis of generalized resonant frequency equations, one of the features is discovered: forwardmode and backward mode achieve maximum efficiency at an identical (but not constant) resonantfrequency under parameter deviations. Therefore, this unique resonant frequency is defined as theBRF in this work. With this feature, the resonant frequencies tracking is unified into tracking onespecific frequency, namely BRF. The second feature is derived from the analysis of the phase shiftof voltages at both sides of the CLLC resonant tank (i.e., Vab and Vcd , which are shown in Fig. 1.17):Vab and Vcd are always in phase at fBRF for bidirectional operations regardless of parameter devia-tions. With this feature, the bidirectional tracking is further unified into tuning switching frequencyonline to keep Vab and Vcd in phase. Once Vab and Vcd are in phase as shown in Fig. 1.17, the max-imum efficiency is achieved in both modes, regardless of the deviation of resonant tank parameterscompared with conventional fixed switching frequency for unregulated CLLC converters.The rest of this chapter is organized as follows: the fBRF formula is derived in Section 3.1;the proposed unified bidirectional tracking algorithm is analyzed and demonstrated in Section 3.2and Section 3.3, respectively; efficiency improvement by the proposed algorithm is verified byexperiments in Section 3.4; The proposed tracking algorithm is compared with published trackingmethods in detail in Section 3.5; and, finally, Section 3.6 summarizes this chapter.3.1 The Bidirectional Resonant Frequency (BRF)The CLLC resonant tank, as shown in Fig. 1.17, can be considered as two LC resonant tanks onthe primary and secondary sides of the transformer, respectively. Conventionally, the deriving ofresonant frequency equations of CLLC converters is usually based on two assumptions: Lm is infi-nite (Lm→+∞), so it can be omitted in the resonant frequency equations; secondary LC resonanttank components are dependent on the primary LC components (Lr1 = n2Lr2,Cr1 =Cr2/n2, wheren is the transformer ratio). However, actual resonant tank components deviate from nominal values.These parameter deviations break the design dependency and cause bidirectional resonant frequen-73fsfr, f1 fr, f2 fr, f3Forward Mode GainGv, fGv, b(a)fr, b1 fr, b2 fr, b3Backward Mode Gain(b)fs➊➋➌➊➋➌The load increasesThe load increasesFigure 3.1: Gain curves for CLLC resonant converters with different load conditions in (a)forward mode; (b) backward mode. CLLC converters have up to 3 resonant frequencies(Ê -Ì) in each mode: fr, f 1, fr, f 2, fr, f 3 in forward mode, and fr,b1, fr,b2, fr,b3 in backwardmode.cies to drift from the designed values. Tracking the resonant frequency calculated by equationswith assumptions may lead to inaccurate tracking of resonance for unregulated CLLC converters.To study generalized resonant frequency equations without these assumptions, all the CLLCresonant tank parameters (Lr1, Lr2, Cr1, Cr2, and Lm) are regarded as independent (Lr1 6=n2Lr2,Cr1 6= Cr2/n2) in this chapter. Therefore, all the resonant frequency equations in this workwill be generalized for any combination of CLLC resonant tank elements, whether with or with-out parameter deviations. Accordingly, gain curves with independent parameters in forward andbackward modes are shown in Fig. 3.1. As this gain curve figure shows, varying with the loadconditions, CLLC converters have up to 3 resonant frequencies in forward or backward mode, andtheir generalized formulas will be obtained first. Then, the BRF of CLLC converters will be derivedwith these equations in this section, after which the BRF will be tracked by the proposed unifiedbidirectional tracking algorithm in later sections.743.1.1 Bidirectional Short-circuit Resonant FrequenciesForward ModeIn Fig. 3.1(a), among three resonant frequencies in forward mode ( fr, f 1, fr, f 2 and fr, f 3), two of them( fr, f 1 and fr, f 3) do not vary with load conditions. Therefore, to facilitate the calculation of fr, f 1 andfr, f 3, the load is set as Rload = 0. Consequently, the equivalent circuit of the CLLC resonant tankis changed as shown in Fig. 3.2(a), where the forward mode short circuit impedance formula isobtained asZ f ,sc= jωsLr1+1jωsCr1+ ( jωsLm)‖( jωsL′r2+1jωsC′r2) (3.1)In (3.1), L′r2 and C′r2 are Lr2 and Cr2 reflected to the primary side through L′r2 = n2Lr2 andC′r2 =Cr2/n2; Lr1, L′r2, Lm, Cr1 and C′r2 are independent parameters; angular switching frequencyωs = 2pi fs.By letting the short circuit impedance (3.1) be 0 and solving for fs, the forward mode shortcircuit resonant frequencies fr, f 1 and fr, f 3 are derived as (3.2) and (3.3), respectively:fr, f 1(Lr1,L′r2,Cr1,C′r2,Lm) =12pi√−λ1+λ2λ3(3.2)fr, f 3(Lr1,L′r2,Cr1,C′r2,Lm) =12pi√λ1+λ2λ3(3.3)whereλ1=√(Cr1 (Lm+Lr1)−C′r2(Lm+L′r2))2+4Cr1C′r2L2m (3.4)λ2=Cr1 (Lm+Lr1)+C′r2(Lm+L′r2)(3.5)λ3=2Cr1C′r2((Lr1+L′r2)Lm+Lr1L′r2)(3.6)Backward ModeCLLC resonant converters in backward mode also have two short-circuit resonant frequencies ( fr,b1and fr,b3) as shown in Fig. 3.1(b). Based on the equivalent circuit in Fig. 3.2(b), the backward mode75short-circuit impedance formula is presented asZb,sc= jωsL′r2+1jωsC′r2+ ( jωsLm)‖( jωsLr1+ 1jωsCr1 ) (3.7)Similar to forward mode, the backward mode short-circuit resonant frequencies fr,b1 and fr,b3 arederived from (3.7) asfr,b1(Lr1,L′r2,Cr1,C′r2,Lm) =12pi√−γ1+ γ2γ3(3.8)fr,b3(Lr1,L′r2,Cr1,C′r2,Lm) =12pi√γ1+ γ2γ3(3.9)whereγ1=√(Cr1 (Lm+Lr1)−C′r2(Lm+L′r2))2+4Cr1C′r2L2m (3.10)γ2=Cr1 (Lm+Lr1)+C′r2(Lm+L′r2)(3.11)γ3=2Cr1C′r2((Lr1+L′r2)Lm+Lr1L′r2)(3.12)It can be found from (3.2), (3.3), (3.8) and (3.9) that the formulas of fr, f 1, fr, f 3, fr,b1 and fr,b3include all 5 independent components of the CLLC resonant tank. In fact, (3.2), (3.3), (3.8) and(3.9) are more precise and generalized equations for the short-circuit resonance frequencies ofCLLC converters in forward and backward mode than conventional equations. When necessary,fr, f 3 and fr,b3 can be simplified to the conventional resonant frequency fr,conv from (3.3) and (3.9)by assuming that Lm is very large (Lm→+∞) and those secondary LC components are dependenton primary components as:fr,conv =12pi√Lr1Cr1=12pi√L′r2C′r2(3.13)Analysis of Short-circuit Resonant FrequenciesAlthough bidirectional short-circuit impedance Z f ,sc and Zb,sc (shown in (3.1) and (3.7)) differ, theirshort-circuit resonant frequencies are the same. More specifically, by comparing (3.2) - (3.6) with76(a)Lr1Zf,scLmCr1 Cr2Lr2‘‘(b)Lr1LmCr1 Cr2Lr2‘‘Zb,scFigure 3.2: Equivalent circuits of short-circuit condition for CLLC resonant tank in (a) for-ward mode (b) backward mode(3.8) - (3.12), it is found thatfr, f 1 = fr,b1 (3.14)fr, f 3 = fr,b3 (3.15)The above two equations indicate that two resonant frequencies of the forward mode ( fr, f 1 andfr, f 3) are identical to the corresponding two resonant frequencies of the backward mode ( fr,b1 andfr,b3) for any load and even for any CLLC resonant tank with parameter deviations, as (3.14) and(3.15) are derived from the generalized formulas of short-circuit resonant frequencies ((3.2), (3.3),(3.8), and (3.9)).Therefore (3.14) and (3.15) enable the tracking of the forward and backward resonant frequen-cies to be unified into the tracking of one unique frequency, and this unique frequency can beselected as fr, f 1(= fr,b1) or fr, f 3(= fr,b3). However, since output voltage regulation is not required forunregulated CLLC converter applications such as DC transformers, Lm is usually designed to belarge for higher efficiency under the premise of ensuring soft switching. This causes fr, f 1 to be atvery low frequency or even close to 0, which can be explained mathematically from (3.2) aslimLm→+∞fr, f 1(Lr1,L′r2,Cr1,C′r2,Lm) = 0 (3.16)77The lower switching frequency can adversely affect the energy density of converters, so fr, f 1 is notsuitable for unregulated CLLC converters to work.In contrast, fr, f 3 is a more favorable switching frequency for unregulated CLLC converters towork at. To begin with, fr, f 3 is not close to 0 for larger Lm design:limLm→+∞fr, f 3(Lr1,L′r2,Cr1,C′r2,Lm) =12pi1√(Lr1+L′r2)(Cr1C′r2Cr1+C′r2)(3.17)Moreover, CLLC converters achieve better efficiency performance at fr, f 3. When CLLC converterswork in the region of fs > fr, f 3, the rectifier side will enter the hard switching from ZCS (ZeroCurrent Switching), which will increase the switching loss and impair efficiency; at the same time,the switching loss of the inverter side will be increasing as well due to high switching frequencyin the region of fs > fr, f 3. If the switching frequency fs is in the region of fr, f 2 < fs < fr, f 3, theMOSFETs on the inverter side experience ZVS, and the MOSFETs on the rectifier side have ZCSwhen the slope of the voltage gain curves in CLLC converters is negative. However, there is a timewhen the inverter side is decoupled from the rectifier side in the region of fr, f 2 < fs < fr, f 3. Thefarther fs is from fr, f 3, the longer the decoupling time. During the decoupling time, no energy istransferred from the inverter side to the rectifier side. As a result, the current circulates inside theinverter side, which causes extra conduction loss. However, all the loss problems mentioned aboveare gone if fs = fr, f 3: the resonant current will be sinusoidal; both ZVS on the inverter side andZCS on the rectifier side can be obtained; and there is no decoupling time. Operation waveformsproving these advantages at fs = fr, f 3 can be found in Section 3.4.Considering the above analysis and (3.15), an interesting feature is discovered that fr, f 3 ( fr,b3)is the efficient resonant frequency for CLLC converters in both forward and backward modes.Therefore, the BRF of CLLC converters fBRF is defined asfBRF = fr, f 3= fr,b3 (3.18)To summarize this subsection, by the analysis of generalized short-circuit resonant frequencyequations, one of the interesting features is discovered: forward mode and backward mode achieve78(a)Lr1Zf,ocLmCr1 Cr2Lr2‘‘(b)Lr1LmCr1 Cr2Lr2‘‘Zb,ocFigure 3.3: Equivalent circuits of open-circuit condition for CLLC resonant tank in (a) for-ward mode (b) backward modemaximum efficiency at an identical resonant frequency under parameter deviations. Therefore, thisunique resonant frequency is defined as the BRF in this work. However, these analysis results do notmean fBRF, fr, f 3 and fr,b3 are constant. In practical applications, these resonant frequencies can driftwith resonant tank parameter deviations. This resonant frequency varying leads to efficiency degra-dation for unregulated CLLC resonant converters that conventionally have the switching frequencyto be fixed at the calculated resonant frequency. To keep unregulated CLLC converters working atthis bidirectional efficient BRF, a bidirectional unified tracking algorithm will be proposed in Sec-tion 3.3. With the feature discovered from (3.18), the bidirectional resonant frequencies trackingcan be unified and simplified into tracking one specific frequency, namely fBRF.3.1.2 Bidirectional Open-circuit Resonant FrequenciesThe generalized open-circuit resonant frequencies will be discussed in this subsection. They canbe used to determine the switching frequency boundary of the capacitive or inductive region inSections 3.2 and 3.3.Forward ModeIn Fig. 3.1(a), the switching frequency for CLLC converters to get the highest gain in forwardmode varies with different load conditions. The lighter the load, the greater the maximum gain of79the CLLC converter. Therefore, the boundary case is when the converter is at no load (Rload = ∞),and this boundary case can be illustrated as Fig. 3.3(a). The impedance of the forward modeopen-circuit is derived asZ f ,oc = jωs(Lr1+Lm)+1jωsCr1(3.19)By letting Z f ,oc = 0 and solving for fs, the open-circuit resonant frequency in forward modefr, f 2 can be obtained:fr, f 2 =12pi1√(Lr1+Lm)Cr1(3.20)Backward ModeThe equivalent circuit in the backward mode of the CLLC converter at no-load conditions is shownin Fig. 3.3(b). Hence, the impedance of this circuit is given asZb,oc = jωs(L′r2+Lm)+1jωsC′r2(3.21)The open circuit resonant frequency in forward mode fr.b2 obtained from (3.21) isfr,b2 =12pi1√(L′r2+Lm)C′r2(3.22)Analysis of Open-circuit Resonant FrequenciesIt can be seen from (3.20) and (3.22) that unless Lr1 = L′r2 and Cr1 =C′r2 perfectly, fr, f 2 in forwardmode will not be equal to fr,b2 in backward mode. Consequently, parameter deviation of the CLLCresonant tank leads to different switching frequencies for maximum gain in forward mode andbackward mode even under the same load conditions. The open-circuit resonant frequencies arenot suitable for the operation frequency of unregulated CLLC converters due to efficiency loss.When working at fr, f 2 or fr,b2, the rectifier side of converters is decoupled from the inverter sidefor a long time, thereby causing high conduction loss and high current stress.However, the open-circuit resonant frequencies (3.20) and (3.22) can be used as the minimum80switching frequency boundary with different load conditions when the proposed unified trackingalgorithm tunes switching frequency online to track fBRF for unregulated CLLC converters in Sec-tion 3.3.3.2 Phase Shift Analysis of Resonant Tank Voltage Vab and VcdIn the previous section, it is found that both forward mode and backward mode achieve maximumefficiency at BRF even under parameter deviations. However, due to the resonant tank parametertolerances, temperature, and aging, the parameters of resonant tank components are hard to obtainaccurately, thereby causing difficulties for unregulated CLLC converters to work at fBRF preciselyonly with equations (3.18) and (3.3) (or (3.9)) in engineering applications. Therefore, a unifiedbidirectional resonance tracking algorithm for fBRF is proposed in this section. As the proposedunified tracking algorithm uses the phase difference of falling edges from Vab and Vcd (definedin Fig. 1.17), the phase shift of these two voltages will be analyzed in this section to show theprinciple of the proposed tracking algorithm, after which detailed operation modes of the unifiedtracking algorithm will be presented in Section 3.3.3.2.1 Phase Shift Analysis of VoltagesBecause the phase shift of falling edges from Vab and Vcd during forward mode is similar to thatduring the backward mode, the analysis below will focus on forward mode.The voltages phase shift in forward mode ϕ f and corresponding current waveforms when fs >fBRF, fs < fBRF and fs = fBRF are shown in Fig. 3.4 (a), (b) and (c), respectively. Differentfrom unidirectional LLC converters, the CLLC resonant tank is composed of two LC tanks on theprimary and the secondary side, respectively. Therefore, to facilitate modeling phase shift ϕ f , twoquality factors Q and two resonant inductance ratios k need to be defined asQ1 =√Lr1Cr1n2ReqS,Q2 =n2√Lr2Cr2ReqP(3.23)k1 =Lm1Lr1,k2 =Lm2Lr2(3.24)81(a)(c)VabVcdILr1ILmtttφf <0t0 t1 t2 t31/(2fs) 1/(2fs) fs > fBRF fs < fBRF fs = fBRF 1/(2fs) 1/(2fs) 1/(2fs) (b)VabVcdILr1ILmtttt0 t1 t2φf >0VabVcdILmtttφf =0t2t0 t1ILr1Figure 3.4: In the forward mode, the phase shift ϕ f varies with the switching frequencyfs(= 1/Ts). (a) ϕ f is less than 0 when fs > fBRF; (b) ϕ f is greater than 0 when fs < fBRF;(c) ϕ f is equal to 0 when fs = fBRF(= 1/TBRF).82(a)Lr1LmCr1 Cr2Lr2‘‘‘(b)Lr1LmCr1n2ReqSVab nVcdnVcdVabILr1ILr1ILr2Cr2Lr2‘‘‘ILr2ReqPFigure 3.5: Equivalent circuit of CLLC resonant tank in (a) forward mode, (b) backwardmode.where ReqS and ReqP in (3.23) are an equivalent load of secondary and primary sides, respectively.According to Fig. 3.5(a), the current amplitude relationship between Ir1 and I′r2 in chargingmode can be shown as follows, where ωs(= 2pi fs) is the angular switching frequency:I′Lr2=jωsLm1jωsLm1+ jωsL′r2+1jωsC′r2+n2ReqSILr1 (3.25)Moreover, the voltage ratio of Vab and Vcd in forward mode can also be derived from Fig. 3.5(a)asnVcdVab=I′Lr2ILr1n2ReqSZ f ,in(3.26)where Z f ,in is input impedance in forward mode asZ f ,in= jωsLr1+1jωsCr1+ ( jωsLm1)‖( jωsL′r2+1jωsC′r2+n2ReqS) (3.27)The phase shift ϕ f is the argument of the voltage ratio of Vab and Vcd , so it is obtained by takingthe argument of (3.26) and then combining equations (3.23)-(3.27) as:ϕ f (Q1,Q2,k1,ω1∗,ω2∗) = arg(nVcdVab) = arctan(σ1+σ2+σ3σ4)(3.28)83whereσ1 =−ω31∗k1ω2∗Q1σ2 =−Q2(ω22∗−1)(k1+1)ω21∗σ3 = ω1∗k1ω2∗Q1+Q2ω22∗−Q2σ4 = ω2∗(−1+(k1+1)ω21∗)(3.29)ω1∗ =ωs1/√Lr1Cr1,ω2∗ =ωs1/√Lr2Cr2(3.30)The phase shift equation of Vab and Vcd in forward mode ϕ f is obtained in this part. Furtheranalysis will be done in the next part to show how parameter deviations affect the ϕ f .3.2.2 Parameter Deviation Analysis for Phase Shift of VoltagesTo facilitate the analysis of deviations of resonant tank parameters, the deviation ranges of theactual resonant tank parameter values are defined based on the nominal value as follows:Lr1 ∈ [(1−α)Lr1n , (1+α)Lr1n]Lr2 ∈ [(1−β )Lr2n , (1+β )Lr2n]Cr1 ∈ [(1− ς)Cr1n , (1+ ς)Cr1n]Cr2 ∈ [(1−ξ )Cr2n , (1+ξ )Cr2n](3.31)where Lr1, Lr2, Cr1, and Cr2 are the actual value of the resonant tank components. Lr1n, Lr2n, Cr1n,and Cr2n are their nominal values. α , β , ς and ξ are the possible variation ranges for Lr1, Lr2, Cr1,and Cr2, respectively.To show how the deviations of CLLC resonant tank components affect the phase shift of Vaband Vcd , the ω∗e and the Qe are defined asω∗e =ω1∗ω2∗∈ [ω∗emin,ω∗emax] (3.32)Qe =Q1Q2∈ [Qemin,Qemax] (3.33)84ω1*(=ω s/ω1)ωs=ωBRF*φf φf =0Q1➊➋➌Figure 3.6: Phase shift between Vab and Vcd in forward mode ϕ f is always 0 when ωs =ωBRF∗, although ωBRF∗ changes with different resonant tanks parameter variation cases:ω∗e = ω∗emax , Qe = Qemax (¶), ω∗e = 1, Qe = 1 (·), and ω∗e = ω∗emin, Qe = Qemin(¸). Moreover, ϕ f > 0 when ωs < ωBRF∗; ϕ f < 0 when ωs > ωBRF∗ regardless ofparameter variation cases. These two characteristics enable the tracking of ωBRF∗.With equation (3.31), the maximum and the minimum for ω∗e and Qe are derived asω∗emin =√(1−α)(1− ς)(1+β )(1+ξ ), ω∗emax =√(1+α)(1+ ς)(1−β )(1−ξ ) (3.34)Qemin =√(1−α)(1−ξ )(1+β )(1+ ς), Qemax =√(1+α)(1+ξ )(1−β )(1− ς) (3.35)By combining (3.28) to (3.35), the phase shift in forward mode ϕ f for Vab and Vcd with respectto parameters ω1∗ and Q1 can be presented in Fig. 3.6, where the ωBRF∗ is defined asωBRF∗ =ωsωBRF=ωs2pi fBRF(3.36)There are three surfaces in Fig. 3.6: the surface for the ideal symmetrical design CLLC resonanttank (ω∗e = 1 and Qe = 1) is plotted according to (3.28); two surfaces considering resonant tankparameters’ deviations are also plotted to show the impacts of the deviations on phase shift ϕ f . Themaximum and the minimum of ω∗e and Qe are calculated by (3.34) and (3.35). To show surfacesclearly, the parameters α,β ,ς , and ξ are considered as 10% in Fig. 3.6. It is worth noting that85ω1*(=ωs/ω1)φb Q 1➊➋➌ωs=ωBRF*φb =0Figure 3.7: Phase shift between Vab and Vcd in backward mode ϕb is always 0 when ωs =ωBRF∗, although ωBRF∗ changes with different resonant tanks parameter variation cases:ω∗e = ω∗emax , Qe = Qemax (¶), ω∗e = 1, Qe = 1 (·), and ω∗e = ω∗emin, Qe = Qemin(¸). Moreover, ϕb < 0 when ωs < ωBRF∗; ϕb > 0 when ωs > ωBRF∗ regardless ofparameter variation cases. These two characteristics enable the tracking of ωBRF∗.the parameter deviations in engineering applications are usually within 10%, so the voltages phaseshift surface with the corresponding parameter deviations should be between two ±10% deviationsurfaces.It can be found from Fig. 3.6 that the parameter deviations cause the voltages phase shift ϕ fto change between the surfaces with maximum and minimum of ω∗e and Qe. However, thesethree surfaces have similar trends: for any Q1, the phase shift of Vab and Vcd in forward modeϕ f decreases monotonically with the increase of ωs. When ωs < ωBRF, the farther ωs is awayfrom ωBRF, the greater the voltages phase shift ϕ f . Moreover, the increase in Q1 will also leadto a faster increase in the voltage phase shift ϕ f , which reaches pi/2 at the open-circuit resonantfrequency. Therefore, the voltages phase shifting range of ϕ f for ωs < ωBRF is (0, pi/2). Whenωs > ωBRF, voltages phase shift ϕ f decreases nonlinearly. As Q1 increases, voltages phase shiftϕ f drops rapidly. Moreover, with the increase of ωs, voltages phase shift ϕ f approaches −pi/2 butwill not exceed −pi/2. Therefore, the minimum variation of ϕ f is −pi/2. When ωs = ωBRF, ϕ f isalways equal to 0.Therefore, the variation range of phase shifting in forward mode ϕ f regardless of parameter86deviations is summarized asϕ f ∈(−pi/2 , 0) , fs > fBRF0 , fs = fBRF(0 , pi/2) , fr,f2 < fs < fBRF(3.37)where fr, f 2 is the open-circuit resonant frequency in forward mode.In the backward mode, the phase shifts ϕb can also be calculated similarly, and this is presentedin Fig. 3.7. The variation range of ϕb, therefore, is summarized asϕb ∈(0 , pi/2) , fs > fBRF0 , fs = fBRF(−pi/2 , 0) , fr,b2 < fs < fBRF(3.38)where fr,b2 is the open-circuit resonant frequency in backward mode.3.2.3 Gain Curves Slope Analysis for Phase Shift of VoltagesThe slope of the gain curves is important for the ZVS and ZCS soft switching of bidirectionalresonant CLLC converters. The proposed BRF tracking algorithm can tune the switching frequencyto track the fBRF for both positive and negative voltage gain slopes as shown in Fig. 3.8.To be specific, when fs < fBRF and the slope of the voltage gain curves are negative, the MOS-FETS of the inverter side have ZVS while the rectifier side can achieve ZCS. However, the ZVScharacteristic may be lost when the slope of the voltage gain curves gets positive due to heavy load.When fs > fBRF , the inverter side MOSFETS can still switch with ZVS, although the rectifier sideMOSFETS loses ZCS and enter hard switching mode. When fs = fBRF , the ZVS on the inverterside and ZCS on the rectifier side can be obtained for bidirectional operations. Meanwhile, thebidirectional maximum efficiency is achieved. Therefore, fBRF is the frequency being tracked.Although different loads have different voltage gain slopes, this manuscript uses the phasedifference of the voltage Vab and Vcd (ϕ f in forward mode and ϕb in backward mode), instead ofvoltage gain. It can be seen from equations (3.37) and (3.38) that the signs of ϕ f and ϕb depend87If fs>fBRFIf fs<fBRFIf fs<fBRFIf fs>fBRF( fBRF)( fBRF)Figure 3.8: The proposed BRF tracking algorithm can tune the switching frequency to trackthe fBRF for both positive and negative voltage gain slopes.on the switching frequency. In other words, as shown in Fig. 3.8, whether the voltage gain slopeis positive or negative, fBRF will be tracked if the proposed tracking algorithm tunes fs to make ϕ fand ϕb equal to 0. In this way, the CLLC resonant converter can focus on galvanic isolation andefficient operation. The PFC stage will be responsible for tuning the DC bus voltage V1 (shown inFig. 1.9) to control the power and its direction.This does not mean that the slope of voltage gain can be ignored when designing an unregulatedCLLC resonant converter. It can be seen from Fig. 3.6 and Fig. 3.7 that sharp ϕ f and ϕb changeswill be caused by small ωs ( fs) changes when the load is heavy and when the voltage gain slope issteep. Therefore, it is necessary to design the voltage gain slope of the unregulated CLLC converternear fBRF to be negative and change smoothly to avoid hard switching and sharp phase changes.In summary, the phase shifts of Vab and Vcd have been discussed in this section. By analyzingthe influence of parameter deviations on the phase shift, another interesting feature of BRF is found88that ϕ f and ϕb are always equal to 0 when fs = fBRF even with parameter deviations. With thisfeature, the bidirectional tracking is further unified into tuning switching frequency online to keepVab and Vcd in phase, which will be discussed in detail in the next section.3.3 The Unified Bidirectional Resonant Frequency TrackingAlgorithmIn Sections 3.1 and 3.2, two interesting features are discovered for fBRF: 1) forward mode andbackward mode achieve maximum efficiency at fBRF even under parameter deviations; 2) Vab andVcd are always in phase at fBRF even under parameter deviations. With these two features, thebidirectional efficient resonance tracking is unified into tuning switching frequency online to keepVab and Vcd in phase. In engineering applications, the phase shift of Vab and Vcd can be obtainedby measuring the time difference of their falling edges. The time difference combined with theequations (3.37) and (3.38) can determine the relationship between fs and fBRF. In other words,by aligning the falling edges of Vab and Vcd , resonance tracking for fBRF can be achieved. Detailedoperation analysis in forward mode and backward is presented as follows.Vab tt0 t1 t2 ttt0 t1 ttt0 t1 t3t2 tΔtfe>0Increase fs Decrease fstt tt0 t1 t ttt0 t1 t2 t0 t1 t3t2Increase fs Decrease fsForward modeBackward modeVcdVabVcdΔtfe<0Δtfe>0Δtfe>0Δtfe<0Δtfe<0VabVcdVabVcdΔtfe=0Δtfe=0VabVcdVabVcdΔtfe<0Δtfe>0➊➊(a1) fs < fBRF (a2) fs = fBRF (a3) fs > fBRF(b1) fs < fBRF (b2) fs = fBRF (b3) fs > fBRF➋➋➋➋➌➌Figure 3.9: The switching frequency tuning strategy of the proposed unified bidirectionalresonant frequency tracking algorithm, where the switching frequency is tuned basedon converter operation modesÊ and time difference ∆t f e of voltage falling edgesË. Byaligning the falling edge of Vab with the falling edge of Vcd , the bidirectional efficientfBRF is tracked Ì.Voltage waveforms of Vab and Vcd in forward and backward mode with different switchingfrequencies are shown in Fig.3.9 (a1) to (a3) and (b1) to (b3). In Fig.3.9 (a1) where fs < fBRF in89forward mode, rising edges of two voltages are concurrent at t0, but the falling edge of Vab at t2 isbehind Vcd at t1. Therefore, the time difference of falling edges ∆t f e for Vab and Vcd is larger than0 (i.e., ∆t f e =t2− t1 > 0). If fs = fBRF as shown in Fig.3.9 (a2), both rising and falling edges oftwo voltages happen at the same time, and thereby ∆t f e = 0. However, ∆t f e < 0 when fs > fBRF inforward mode as Fig.3.9 (a3) shows. The sign of the ∆t f e in backward operation mode is oppositeto that in the forward operation mode of CLLC converters. The falling edges of Vab at t1 lead theedge of Vcd at t2, which means that ∆t f e < 0 when fs < fBRF. Meanwhile, both the rising and fallingedges Vab lag behind the edges of Vcd in Fig.3.9 (b2), so ∆t f e > 0 if fs > fBRF in backward mode.Same as in forward mode, CLLC converters work at resonance with the common bidirectionalresonant frequency fBRF at backward mode.Considering all 6 cases in Fig.3.9 (a1)-(a3) and (b1)-(b3), it is found that, in both forwardand backward operation, the rising edges occur simultaneously when the switching frequency fsis lower than or equal to the resonance frequency fBRF. Therefore, rising edges may not be ableto determine whether the switching frequency is drifting. However, the time at which the fallingedges of two voltages Vab and Vcd occur is always different unless the switching frequency is equalto the resonance frequency. Therefore, this work chooses the falling edges as the basis to adjust theswitching frequency.Moreover, Fig.3.9 (a2) in forward mode and (b2) in backward share the common fBRF as ana-lyzed in (3.18). Therefore, by aligning falling edges of Vab and Vcd , bidirectional resonant frequencytracking can be achieved with the proposed unified bidirectional frequency tracking algorithm. Itis based on the sign of ∆t f e and the operation mode (forward or backward mode) of CLLC convert-ers. If the CLLC converter works below resonance with fs < fBRF and ∆t f e > 0 in forward mode asshown in Fig.3.9 (a1), the unified tracking algorithm would increase switching frequency fs by ∆ fs(i.e., fs +∆ fs). In the next switching period, the ∆t f e and the operation mode are checked again.If the CLLC converter still works with ∆t f e > 0 in forward mode, the unified tracking algorithmwould increase switching frequency fs by ∆ fs again. After several periods, the switching frequencyfs will be increased step by step to align the falling edges of Vab with Vcd , thereby eventually re-alizing resonant frequency tracking. The proposed tracking algorithm also increases switching90Initialize fs as fBRF with (3.17) for both forward and backward modes StartHave falling edges for Vab and Vcd arrived?Calculate Δtfe, is Δtfe=0?In forward mode?fs = fs +Δfs fs = fs -Δfs Δtfe>0?NNNNYYYYfs = fs +Δfs fs = fs -Δfs Δtfe>0?NYFigure 3.10: The flowchart for the proposed unified bidirectional resonance tracking algo-rithm, shows how the proposed algorithm tunes fs online according to ∆t f e and opera-tion modes.frequency in a similar way when ∆t f e < 0 in backward mode as shown in Fig.3.9 (b1). Likewise,the switching frequency would be gradually decreased by the proposed tracking algorithm when∆t f e < 0 in forward mode or ∆t f e > 0 in backward mode, as shown in Fig.3.9 (a3) and (b3), respec-tively. Finally, falling edges of Vab will align with Vcd , and therefore fs = fBRF in both forward andbackward operation of bidirectional CLLC converters. All the mentioned steps for the proposedbidirectional resonance tracking algorithm can be summarized in a flowchart in Fig. 3.10.Although falling edges of Vab and Vcd are synchronized for ensuring BRF tracking, the bidirec-tional power direction is still controllable by regulating the DC bus voltage V1 via the PFC stage asshown in Fig. 1.9. The DC/DC stage in Fig. 3.11(a) can be equivalent to Fig. 3.11(b) because theCLLC resonant converter is working the inductive region for ZVS (Zero Voltage Switching).When the converter reaches a steady-state condition, the value of ILr1 in Fig. 3.11(b) can be91Cr1LmLr1(a)(b)(c)LreqLr2Cr2V1+V1-V1V2+V2-V2ILr2VabVabVAB...VcdVcdVCDILr1ILr1tt1t0 tFigure 3.11: Although Vab and Vcd are synchronized for ensuring BRF tracking, the directionof power flow across the CLLC resonant tank is still controllable by regulating theamplitude of port voltage V1.determined by analyzing the fundamental component of the voltage and current asI˙Lr1 =V˙AB−V˙CDjωLreq=VAB∠ϕAB−VCD∠ϕCDjωLreq(3.39)Since Vab and Vcd are synchronized,ϕAB = ϕCD (3.40)Define ϕAB = ϕCD = 0, and combine equations (3.39) and (3.40),I˙Lr1 =VAB∠ϕAB−VCD∠ϕCDjωLreq=VAB−VCDjωLreq(3.41)92Thus, if amplitude VAB−VCD > 0 , the power flow is positive (from Vab to Vcd). If VAB−VCD < 0,the power flow is negative (from Vcd to Vab). From Fig. 3.11(c), it is known that the amplitude ofVab is V1, and the amplitude of Vcd is V2. Therefore, by regulating the DC bus voltage V1, the powerflow direction can be controlled via the PFC stage.In summary, the unified bidirectional tracking algorithm uses a falling edges-based techniqueto detect the phase difference of Vab and Vcd , so CLLC converters can always work at efficient fBRFin both forward and backward modes even under resonant tank parameter deviations.3.4 Experiment ResultsIn this section, the challenges and their solutions in implementing the unified bidirectional reso-nance tracking algorithm for engineering applications will be discussed and then verified by exper-iments.High-speedOptocouplerIsolation StageSources Synchronized eCaps(DSP )High-speedOptocouplerVab tab(tab - tcd)VcdeCAP1eCAP2 tcdΔtfe❶❷Figure 3.12: Two symmetric sampling channels (¶ and ·) are implemented to obtain thetime difference ∆t f e of voltage falling edges. Propagation delay skew of tab and tcd isminimized due to this symmetric structure and synchronized eCaps.3.4.1 Implementation StrategyTo realize the unified bidirectional tracking algorithm successfully, the first challenge is to accu-rately capture the falling edges mentioned in Fig. 3.10 for Vab and Vcd . This is because Vab and Vcdare high-voltage and high-frequency signals. In particular, when the switching frequency fs < fBRF,one of the Vab or Vcd on the rectifier side will oscillate, which causes multiple falling edges in oneswitching period. This has negative impacts on the accurate capture of the falling edges.To solve this problem, this work adopts a low-cost and precise solution. The implementation93block diagram of the solution is shown in Fig. 3.12. The high-speed optocoupler converts the high-voltage and high-frequency Vab and Vcd into two DSP-compatible low-voltage and high-frequencysignals. In this way, voltage transformation and isolation are achieved using two high-speed opto-couplers. Then, two enhanced Capture (eCap) modules in the DSP are adopted to capture the pre-cise timing of falling edges. To improve the robustness against the oscillating noise when fs < fBRF,two eCaps are set to one-shot mode, and they are re-armed at every rising edge of Vab. This meansthat the correct falling edge time of each cycle will be latched until a new cycle arrives: eCaps’counters start counting from 0 and wait for the falling edge capture interruptions; when the firstfalling edges arrive, the corresponding counter stops counting and latch the timing of the fallingedge till the eCap is rearmed next period. At the same time, the Capture Event Interrupt flag willbe set as high. When Capture Event Interrupt flags for both eCap1 and eCap2 (CEVT1 and CEVT2registers) are set as high, the latched falling edge time for VAB and VCD is adopted to calculate thetime difference of falling edges ∆t f e. Then the switching frequency can be tuned online based onthe sign of ∆t f e and the operation mode (forward or backward) of the CLLC converters as shownin the flowchart in Fig. 3.10. Finally, PWM driving signals based on the tuned switching frequencywill be generated by ePWM modules and sent to MOSFETs. Therefore, the proposed bidirectionalresonance tracking algorithm is realized. It is worth noting in Fig. 3.10 that the question “Havefalling edges for Vab and Vcd arrived?” is answered by checking both the eCap1 and eCap2 in-terruption flags (CEVT1 and CEVT2) using an if statement in the main function of the code. Theproposed tracking algorithm requires falling edge timing from both eCap1 and eCap2 start, so thetracking algorithm is not written into the Interrupt Service Routine (ISR) of one specific eCap. Thischecking will not reduce the accuracy of frequency tracking, because the time of falling edges hasbeen latched in eCap registers when interruption flags are set.Another challenge is propagation delay skew. As the proposed bidirectional unified trackingalgorithm tracks the BRF based on the time difference of Vab and Vcd falling edges. Therefore, thepropagation delay of Vab and Vcd does not directly cause accuracy degradation of BRF tracking.It is the propagation delay skew of the Vab and Vcd that causes tracking error. To minimize thepropagation delay skew, two symmetric sampling channels are implemented to obtain the time94Control boardCLLC resonant tankBridges of primary andsecondary sides TransformerFigure 3.13: The bidirectional resonant CLLC converter prototype for verifying the perfor-mance of the unified bidirectional resonant frequency tracking algorithmTable 3.1: Parameters of CLLC Converter PrototypeParameters Symbols ValuesNominal Power Pn 1.2 kWInput DC Bus Voltage V1 (or V2) 200 VdcTransformer Ratio n 1.1Resonant Inductor 1 Lr1 21 µHResonant Inductor 2 Lr2 17 µHMagnetizing Inductance Lm 128 µHResonant Capacitor 1 Cr1 120 nFResonant Capacitor 2 Cr2 150 nFBidirectional Resonant Frequency fBRF 100 kHzFrequency Tuning Step ∆ fs 0.1 kHzMain Chips and Their ModelsDSP TI TMS320F28335High-speed Optocoupler Broadcom ACPL-071Ldifference ∆t f e of voltage falling edges. Propagation delay skew of tab and tcd is minimized due tothis symmetric structure and internally synchronized eCaps as shown in Fig. 3.12.3.4.2 Experimental VerificationAs shown in Fig. 3.13, a prototype has been built in the lab to verify the performance of theunified bidirectional resonant frequency tracking algorithm. The parameters of this prototype aresummarized in Table 3.1.95(a)(b)(c)V2V1Ir1Zoom in to subfig. (b) VABIr2VCDZoom in to subfig. (c) Δtfe<0V2 V1Ir1VABIr2VCDΔtfe=0V2 V1Ir1VABIr2VCDFigure 3.14: Frequency tracking process in the forward mode of the proposed bidirectionalresonant frequency tracking algorithm starting with fs > fBRF. ∆t f e increases from lessthan 0 to equal to 0, which indicates that the CLLC converter is working at fBRF afterfrequency tracking. (a) Overall tracking transit waveforms (b) Zoomed-in view show-ing before frequency tracking. (c) Zoomed-in view showing after frequency tracking.Due to deviations of parameters, unregulated bidirectional CLLC with fixed switching fre-quency fs may be higher or lower than the bidirectional resonant frequency fBRF. Combined withforward and backward operation modes, four cases in total will be verified as Fig. 3.14 to Fig. 3.17.To capture the voltage V1 and V2 dynamic waveforms during BRF tracking, all these bidirectionaldynamic response experimental results are obtained in standalone operation with loads instead ofa grid-tied operation, and without the input voltage closed-loop control. Fig. 3.14 and Fig. 3.15demonstrate the experiment results for the CLLC converter in forward mode starting with fs > fBRFand fs < fBRF, respectively. Fig. 3.14(a) shows the dynamic process of switching frequency tuning96(a)(b)(c)V2V1Ir1Zoom in to subfig. (b) VABIr2VCDZoom in to subfig. (c) Δtfe>0V2V1Ir1VABIr2VCDΔtfe=0V2V1Ir1VABIr2VCDFigure 3.15: Frequency tracking process in the forward mode of the proposed bidirectionalresonant frequency tracking algorithm starting with fs < fBRF. ∆t f e increases fromgreater than 0 to equal to 0, which indicates that the CLLC converter is working atfBRF after frequency tracking. (a) Overall tracking transit waveforms (b) Zoomed-inview showing before frequency tracking. (c) Zoomed-in view showing after frequencytracking.by the proposed bidirectional unified BRF tracking algorithm. Due to starting with fs > fBRF, theproposed algorithm will decrease the switching frequency fs, resulting in a gain increase. Conse-quently, the output voltage (that is V2 in forward mode) will increase, and the current Ir1 and Ir2gradually rise with the increase of voltage. The waveforms before and after frequency tuning canbe zoomed in to Fig. 3.14(b) and (c), respectively. In 3.14(b), due to fs > fBRF, the Ir1 is distortedfrom the sine wave. And Vab is leading Vcd , so the ∆t f e < 0. The experimental waveforms afterfrequency tracking by the proposed algorithm are shown in 3.14(c). It can be found that Ir1 has97(a)(b)(c)V2V1Ir1Zoom in to subfig. (b) VABIr2VCDZoom in to subfig. (c) Δtfe>0V2 V1Ir1VABIr2VCDΔtfe=0V2V1Ir1VABIr2VCDFigure 3.16: Frequency tracking process in the backward mode of the proposed bidirectionalresonant frequency tracking algorithm starting with fs > fBRF. ∆t f e drops from greaterthan 0 to equal to 0, which indicates that the CLLC converter is working at fBRF afterfrequency tracking. (a) Overall tracking transit waveforms (b) Zoomed-in view show-ing before frequency tracking. (c) Zoomed-in view showing after frequency tracking.become a sine wave, and ∆t f e increases from less than 0 to equal to 0, which indicates that theCLLC converter is working at fBRF after frequency tracking.Experimental results for CLLC converters in forward mode with starting switching frequencyfs < fBRF are shown in Fig. 3.15(a)-(c). Since fs starts below fBRF, the output voltage V2 and thecurrent Ir1 and Ir2 decrease with the increase of fs as shown in Fig. 3.15(a). It is worth notingthat in Fig. 3.15(b), although the rectifier side Vcd has ringing noise, the proposed bidirectionaltracking algorithm can still accurately capture and latch the correct falling edges. The waveformafter successful frequency tracking is shown in Fig. 3.15(c), and the time difference ∆t f e is reduced98(a)(b)(c)V2V1Ir1Zoom in to subfig. (b) VABIr2VCDZoom in to subfig. (c) Δtfe<0V2 V1Ir1VABIr2VCDΔtfe=0V2 V1Ir1VABIr2VCDFigure 3.17: Frequency tracking process in the backward mode of the proposed bidirectionalresonant frequency tracking algorithm starting with fs < fBRF. ∆t f e increases from lessthan 0 to equal to 0, which indicates that the CLLC converter is working at fBRF afterfrequency tracking. (a) Overall tracking transit waveforms (b) Zoomed-in view show-ing before frequency tracking. (c) Zoomed-in view showing after frequency tracking.to 0.Fig. 3.16 and Fig. 3.17 show the experimental results of the CLLC converter in backward mode.The frequency tuning strategy in backward mode is different from forward mode. In backwardmode, Vab is on the rectifier side and Vcd is on the inverter side. As shown in Fig. 3.16(b) and (c),when fs > fBRF, ∆t f e is greater than 0. In this case, the proposed bidirectional tracking algorithmwill lower fs until ∆t f e = 0. When fs < fBRF, as shown in Fig. 3.17(b) and (c), ∆t f e is less than 0,so the proposed algorithm will increase fs until delta ∆t f e = 0.Unregulated CLLC converters conventionally use a fixed switching frequency. To reflect the99Efficiency with the proposed tracking algorithmSwitching frequency of the proposed algorithm Fixed Switching frequencyEfficiency with fixed switching frequency92.6%93.0%93.4%Forward Efficiency93.8%415W 475W 550W 660W 830W 1100W98.2kHz 97.5kHz96.8kHz 96.3kHz 95.9kHz 95.8kHz98kHz 98kHz 98kHz 98kHz 98kHz 98kHzFigure 3.18: In forward mode, the proposed tracking algorithm tracks fBRF of different powerlevels, so better efficiency has been achieved compared with the conventional methodof fixed switching frequency (98kHz). Measured with input voltage V1 varies whileoutput voltage V2 is fixed at 182V.Efficiency with the proposed tracking algorithmSwitching frequency of the proposed algorithm Fixed Switching frequencyEfficiency with fixed switching frequencyBackward Efficiency98kHz 98kHz 98kHz 98kHz 98kHz 98kHz92.6%92.8%93.0%93.2%93.4%415W 475W 550W 660W 830W 1100W97.6kHz 96.9kHz 96.4kHz 95.9kHz 95.7kHz 95.3kHzFigure 3.19: In backward mode, the proposed tracking algorithm tracks fBRF of differentpower levels, so better efficiency has been achieved compared with the conventionalmethod of fixed switching frequency (98kHz). Measured with input voltage V2 varieswhile output voltage V1 is fixed at 182V.Efficiency with the proposed tracking algorithmSwitching frequency of the proposed algorithm Fixed Switching frequencyEfficiency with fixed switching frequency92.0%92.5%93.0%Forward Efficiency93.5%415W 475W 550W 660W 830W 1100W92.7kHz 92.0kHz 91.3kHz 90.8kHz 90.4kHz 90.1kHz98kHz 98kHz 98kHz 98kHz 98kHz 98kHzFigure 3.20: In forward mode with 10% resonant tank parameter deviations, the proposedtracking algorithm shows up to 0.27% efficiency improvement compared with the con-ventional fixed switching frequency (98kHz) in different power levels. Measured withinput voltage V1 varies while output voltage V2 is fixed at 182V.100Efficiency with the proposed tracking algorithmSwitching frequency of the proposed algorithm Fixed Switching frequencyEfficiency with fixed switching frequencyBackward Efficiency98kHz 98kHz 98kHz 98kHz 98kHz 98kHz92.0%92.3%92.6%92.9%93.2%415W 475W 550W 660W 830W 1100W92.0kHz 91.3kHz 90.9kHz 90.5kHz 90.1kHz 89.9kHzFigure 3.21: In backward mode with 10% resonant tank parameter deviations, the proposedtracking algorithm shows up to 0.3% efficiency improvement compared with the con-ventional fixed switching frequency (98kHz) in different power levels. Measured withinput voltage V2 varies while output voltage V1 is fixed at 182V.efficiency improvement for the unregulated CLLC converter by the proposed bidirectional resonantfrequency tracking algorithm, an efficiency comparison is performed. As listed in Table 3.1, thefBRF is designed at 100kHz. Considering the dead time, the actual switching frequency would be alittle smaller than the fBRF. Therefore, the conventional fixed switching frequency is set as 98kHzfor comparison. As shown in Fig. 3.18, the efficiency of the forward mode presents a trend ofincreasing first and then decreasing, and the switching frequency tracked by the proposed algorithm( fBRF) decreases monotonically with the increase of power level. At 415W, the fixed switchingfrequency is close to fBRF, so the efficiency is the same. As the power increases to 1100W, fBRFdecreases to 95.8kHz, and the gap between fBRF and the fixed switching frequency (98kHz) reachesa maximum of 2.2kHz, and the efficiency difference is 0.05%. The backward mode presents similarexperimental results. As shown in Fig. 3.19, the maximum difference between the fBRF (95.3kHz)and the fixed switching frequency is 2.7kHz, and the efficiency difference is 0.07%. It is concludedthat the optimal switching frequency varies with load conditions, and therefore the proposed BRFtracking algorithm can improve the efficiency in different load conditions for bidirectional CLLCconverters.By comparing Fig.3.18 and Fig. 3.19, it can be found that the efficiency is slightly differentin the forward and backward modes under the same power level. This is because the CLLC con-verter prototype is not perfectly symmetric. Although the bidirectional output voltage is constantin these experiments, the input voltage and the current on the rectifier side in forward mode could101be different from that of backward mode due to the transformer ratio. Therefore, the bidirectionalloss differs slightly. Similarly, the tracked switching frequency under the same load is also slightlydifferent bidirectionally. According to (3.37) and (3.38), as long as the falling edges of Vab andVcd are in phase, the switching frequency fs is tracked as fBRF, and therefore the efficiency forunregulated CLLC converters is optimal bidirectionally.To verify tracking performance under parameter deviations due to tolerances, aging, and tem-perature, the CLLC resonant rank parameters (Lr1, Lr2, Cr1, and Cr2) are all increased by 10%approximately from the values listed in Table 3.1. This is to emulate the situation that the switch-ing frequency was set without the knowledge of component variations. Then all efficiency andswitching frequency comparison experiments have been redone as shown in Fig.3.20 and Fig. 3.21.Although the trends are similar to experiments without parameter deviations, a larger difference inefficiency and switching frequency can be observed. Due to the deviations of the resonant tankparameters, the fBRF of the CLLC resonant tank has changed. Even at 415W, fBRF is reduced fromthe designed 98kHz to 92.7kHz. At the same time, the efficiency difference with the fixed 98kHz is0.07%. When the power level increases to 1100W, the switching frequency difference is expandedto 7.9kHz, and the efficiency of the proposed tracking method is 0.27% higher than that of the fixedswitching frequency. Similarly, the backward mode experiment results are shown in Fig. 3.21.The tracked fBRF is reduced from 92kHz at 415W to 89.9kHz at 1100W. Compared with the fixedswitching frequency, the maximum efficiency with the proposed tracking method is 0.3% higher at1100W.In summary, the proposed unified tracking algorithm dynamically adjusts the switching fre-quency according to different loads and parameter deviations to track fBRF fast and accurately,so that unregulated CLLC converters always work at the bidirectional resonant frequency. Theefficiency improvement rises as the power increases.3.5 Comparison with Conventional Tracking MethodsBidirectional resonant frequency tracking for CLLC converters is an interesting new topic, whichrequires some different considerations. The published conventional unidirectional frequency track-102ing techniques so far can be categorized as current-sensing based [82–84] and voltage-sensingbased [85, 86]. They need some analytical and experimental modifications before applying them toCLLC converters for bidirectional resonance tracking. Therefore, the simplicity and flexibility ofboth forward and backward tracking are important ones to compare. Sensitivity against oscillationsnoise and propagation delay also needs to be considered. The comparisons with those unidirec-tional tracking methods when they apply to bidirectional tracking can be summarized in Table 3.2.Table 3.2: Comparisons of bidirectional operations with unidirectional tracking methodsTrackingmethodsResonanttankSensing ComplexityAdaptive SRDependencyCurrentSensorsNoiseSensitivityCost Delay skewPowerDensity[85, 86] LLC Voltage High Yes None Medium Medium High Medium[82–84] LLC Current High No 2 Low High High LowThis work CLLC Voltage Low No None Low Low Low High3.5.1 Compare with Voltage-sensing based Unidirectional TrackingMethodsSimplicity and Flexibility of Bidirectional Operation ComparisonThe theoretical analysis of Pulsewidth Locked Loop (PWLL) in [85, 86] is for unidirectional LLCconverters, which does not apply to bidirectional resonance tracking of CLLC converters. It isworth noting that one of the contributions of this chapter is the derivation of Bidirectional ResonantFrequency (BRF) for CLLC converters. The resonance tracking in forward and backward modeshas been unified and simplified because of BRF. Another contribution of this chapter is ParameterDeviation Analysis for Phase Shift of Voltages Vab and Vcd . Through this analysis, Vab and Vcdat BRF will always be in phase regardless of the parameter deviations. This analysis allows thebidirectional tracking to be further unified to synchronize the two voltages. Therefore, the proposedBRF tracking algorithm is a conclusion drawn from the bidirectional operation analysis perspective.With the help of this chapter’s proposed BRF and parameter deviation analysis in Section 3.2 ofthis chapter, PWLL could be applied to CLLC converters. and the implementation block diagram103is shown in Fig. 3.22. Voltages of VdsSR1 and VdsSR2 on both sides of the transformer are requiredto be sampled when PWLL is applied to bidirectional tracking. However, to ensure the isolationbetween the primary side and the secondary side of the converter, the PWLL requires additionalisolation stages before the controller when PWLL is implemented to the bidirectional tracking,such as optocouplers. Since PWLL relies on adaptive SR, the adaptive SR controller also needs tobe added to both sides of the converter. Due to the small turn-on resistance of the SR MOSFETs,the sensed voltage VdsSR1 and VdsSR2 are minimal. As a result, two high accuracy, small offset, andfast response comparators are also needed. All the extra stages added for unidirectional PWLL tobe a bidirectional tracking are highlighted in red in Fig. 3.22. This is more complicated than theproposed BRF tracking method in bidirectional operations.ControllerCr1 Cr2LmLr1Ir1VdsSR1 VdsSR2V1Lr2V2Ir2Comparator 2Isolation stage2(e.g. Optocouplers)Adaptive SR 2Comparator1Isolation stage1(e.g. Optocouplers)Adaptive SR 1PWLL To secondary side MOSFETSFor forwardmodeFor backwardmodeTo primary side MOSFETSS1, S2S3, S4S5, S6S7, S8Figure 3.22: With the help of this chapter’s proposed BRF and voltage shift analysis, theconventional voltage-sensing based PWLL technique could be applied to bidirectionaltracking. However, extra stages, highlighted in red, are required to add for PWLL,which is more complicated than the proposed BRF tracking method in bidirectionaloperations.Moreover, SR is not a necessary feature for the bidirectional resonant CLLC converters in someapplications. However, the PWLL proposed by references [85, 86] relies on the adaptive SR drivingscheme, which limits the PWLL application scope and reduces tracking accuracy. For those CLLC104converters that do not require SR, if unidirectional PWLL was used for bidirectional tracking,complex and unnecessary adaptive SR and extra isolation stages must be installed on both theprimary and the secondary sides. For example, for 400V 3kW full-bridge bidirectional chargers, thecurrent is not excessively high, but the implementation of SR increases the unnecessary complexity,more extra driving loss, and switching loss.In contrast, the bidirectional tracking is simplified and unified by the proposed BidirectionalResonant Frequency (BRF) tracking algorithm. It is flexible that can work with/without SR. Onlyone optocoupler isolation stage is added before the proposed BRF tracking controller. Therefore,the flexibility and the simplicity of the proposed unified BRF tracking are better than adoptingexisting unidirectional tracking methods [85, 86] for forward and backward modes separately. Theimplementation diagram is shown in Fig. 3.23.eCAP1 eCAP2Cr1 Cr2LmLr1Ir1VabV1Lr2Vcd V2Ir2S1, S2S3, S4S5, S6S7, S8High-speedOptocouplersDSP TMS320The proposed BRFtracking algorithm Figure 3.23: The implementation diagram for the proposed BRF tracking algorithm. It canwork with/without SR. Therefore, it is more flexible and simpler than adopting con-ventional unidirectional tracking methods for forward and backward modes separately.Oscillating voltage measuring comparisonIt is natural for both LLC and CLLC resonant converters that the rectifier side voltage oscillateswhen switching frequency below the resonant frequency. This voltage oscillation is a factor thatneeds to be considered by voltage-sensing-based tracking methods. It has been tackled differentlyin this work and references [85, 86]. These two solutions have different effects on the accuracy of105resonant frequency tracking.Capacitivecurrentspikegate drivePrematureturn-onCorrectturn-onshortTD_OnproperTD_Ongate driveISR ISR ISRFigure 3.24: This figure shows the effect of parasitic on adaptive SR, which is used in con-ventional PWLL tracking methods: in the case of the reduced load a capacitive currentspike should trigger the turn-on, there would be a current inversion (flowing from theoutput capacitor toward the SR MOSFET). This current inversion would cause a dis-charge of the output capacitor and consequently an increase of the rectified currentRMS value, in order to balance that discharge; this in turn would affect the converterefficiency. Therefore, the adaptive turn-on delay will cause the propagation delay skewto conventional PWLL tracking methods.PWLL in references [85, 86] relies heavily on the performance of the adaptive SR scheme.The voltage used for adaptive SR and resonance tracking is VdsSR. It oscillates at both rising andfalling edges as shown in Fig. 16 in Ref. [85]. To solve this oscillation problem, the thresholdvoltage Vth is set as a negative value (-300mV). Then the sensed VdsSR is compared with Vth atevery turn-off moment. Based on comparison results, SR pulse width will be tuned for the nextperiod. Since it is not possible to detect when the SR pulse width is larger than needed, whenthe compare output is low, the SR duty is decreased by ∆D. Therefore, the sensed voltage VgsSRfor resonance tracking may always have the error of ∆D from the correct duty as shown in Fig.6 in Ref. [85]. This error caused by adaptive SR will adversely affect the accuracy of frequencytracking. Apart from this, to avoid false triggering on of the gate driver, an adaptive maskingturn-on delay TD On must be introduced for adaptive SR. Turn-on TD On aims to avoid a prematureturn-on at lower load conditions, triggered by capacitive currents (due to secondary side parasiticcapacitance), which is shown in Fig. 3.24 from the datasheet of SRK2001 [139]. Fig. 3.25 fromthe SRK2001 datasheet shows the turn-on at the full load with minimum delay (TD On min) and the106reduced load with increased delay. The turn-on masking delay can be equal to up to 40% of theclock cycle. This delay, introduced by adaptive SR, may also cause a large error for obtaining theaccurate duty of VgsSR, therefore reducing the resonant frequency tracking accuracy of PWLL in[85, 86].VDS ISR Blanked turn-off crossing VTH_ON Turn-on masking delay Turn-off blanking time Gate drive VDS 50% ISR Blanked turn-off crossing VTH_ON Turn-on masking delay Turn-off blanking time Gate drive 50% Figure 3.25: The turn-on at the full load with minimum delay (TD On min) and at the reducedload with increased delay (up to TD On max equal to 40% of the clock cycle). .In contrast, this chapter does not have the error of ∆D and turn-on masking delay TD On, becausethe correct duty for both VAB and VCD is directly measured and latched by two synchronized eCapmodules, instead of using adaptive SR. As shown in Fig. 3.26, the eCap1 and eCap2 are synchro-nized and rearmed at every rising edge, where eCaps’ counters start counting from 0 and wait forthe falling edge interruptions. When the first falling edges arrive, the corresponding counter stopscounting and latches the timing of the falling edge till the eCap is rearmed. Because eCaps stopcounting when the first falling edge is latched, the duty measurement of both VAB and VCD will notbe affected by voltage oscillations regardless of forward mode or backward mode shown in Fig.3.26(a) and (b) respectively.Although AC voltages VAB and VCD are sampled, it is not likely to cause problems for the pro-posed BRF tracking method. As the proposed BRF tracking only needs the falling edge of VAB andVCD, the AC voltages of VAB and VCD are converted to DC signals by optocouplers before sending107(a)(b)Ir1VABVCDIr2VABVCDLatching first falling edge by eCap2(stop eCap2 counter)Rearm two eCaps at rising edge (start counters as 0 andwait for falling edge) Latching first falling edge by eCap1(stop eCap1 counter)Duty of VcdDuty of VabLatching first falling edge by eCap2(stop eCap2 counter)Rearm two eCaps at rising edge (start counters as 0 andwait for falling edge) Latching first falling edge by eCap1(stop eCap1 counter)Duty of VcdDuty of VabFigure 3.26: The measuring and latching of the duty of VAB and VCD in (a) Forward mode (b)Backward mode. It is showing that the correct duty of VAB and VCD is latched, and itis not affected by voltage oscillations.to eCaps in the DSP controller. To test the high-frequency AC signals performance of BroadcomACPL-071L optocoupler, a wave generator is adopted to provide ±2V input voltage with the fre-quency of 500kHz and 1MHz for the two optocouplers used in this work. As shown in Fig. 3.27, theoptocoupler input Vin opto =±2VAC are converted to output of optocoupler Vin opto1 and Vin opto2 as0 ∼ +3V DC. The output amplitude of the optocoupler is determined by its supply voltage (3V inthis work). Therefore, the optocouplers achieve isolation and conditioning at the same time. Theiroutputs can connect to the eCap in the DSP controller without adding extra conditioning circuits,thus simplifying the sampling circuits, and reducing propagation delay. Besides, these high-speedoptocouplers are showing stable propagation delay and propagation delay skew for both 500kHzand 1MHz input. Therefore, the high-speed optocoupler will not be the bottleneck for high fre-quency applications.In short, voltage oscillation has been tackled differently in this chapter and references. Unlike108Figure 3.27: High frequency tests for optocouplers at (a) 500kHz (b) 1MHz. High-speedoptocouplers are showing stable propagation delay and propagation delay skew forboth 500kHz and 1MHz input. Therefore, optocouplers will not be the bottleneck forhigh frequency applications. The AC voltages of VAB and VCD are converted to DCsignals by optocouplers before sending to eCaps in the DSP controller.using adaptive SR in references [85, 86], this chapter uses a direct measurement method to obtainthe duty of VAB and VCD. It avoids delay problems caused by adoptive SR, and therefore the higheraccuracy and simplicity of voltage duty measuring are achieved.Propagation Delay ComparisonThe proposed BRF tracking method tracks the resonance based on the time difference of VAB andVCD falling edges. Therefore, the propagation delay of V AB and VCD may not directly reduce theaccuracy of resonant frequency tracking. It is the skew of the propagation delay of the VAB and VCDthat causes tracking error. As shown in Fig. 3.28, VAB and VCD are the voltages to be measured;109V ′AB and V′CD are the measured voltages with the same delay. Although V′AB and V′CD have certainpropagation delays, their propagation delay skew of falling edges is still 0, and φ f = 0, so theproposed BRF tracking method considers the converter works at resonance and will not tune theswitching frequency. However, the propagation delay skew can reduce the tracking accuracy asshown as V ′′AB and V′′CD. References [85, 86] and this work proposed BRF tracking method havedistinct performance in propagation delay skew, which will be compared below. φf =0φf ≠0Still in phasedue to notransmission delay skewReferencevoltagesHave delaybut no delay skew Have delayand delay skew Out of phasedue to transmission delay skewDelay of VAB Delay skewDelay of VCD VabVcdV’abV’cdV’’abV’’cdttφf =0t2t0 t1ttttFigure 3.28: The proposed BRF tracking method tracks the resonance based on falling edgestime difference of VAB and VCD. Therefore, the propagation delay may not directlyreduce the accuracy of resonant frequency tracking, but the skew of the propagationdelay of the two signals is the source of tracking error.To minimize the propagation delay skew of VAB and VCD, the proposed BRF tracking methoduses two completely symmetrical channels to determine the falling edge timing; similar lengthwires for two same model optocouplers are applied for their input and output; two eCaps aresynchronized internally. The block diagram of symmetric measuring falling edges timing of theproposed method is shown in Fig. 3.29(a). However, PWLL in references [85, 86] may have a110high delay skew for TgsS1 and TdsSR as shown in Fig. 3.29(b). This is because TgsS1 is directly fromthe pulse width calculator, but the TdsSR is obtained with stages of the comparator, adaptive SR,and pulse width calculator. Among these stages, the adaptive SR controller may introduce highpropagation delay skew due to the adaptive SR duty step ∆D and adaptive masking turn-on delayTD On [139–141]. Therefore, the tracking accuracy of references [85, 86] is affected adversely.ComparatorDelay skewVdsSR TdsSRHigh-speedOptocouplerIsolation Stage 2 symmetric measuring channels Sources(a)(b)Synchronized eCapsHigh-speedOptocouplerVAB tABtAB -VCDeCAP1eCAP2 tCDtCDLow delay skewof tAB and tCDΔtfe=Asymmetric channelsto obain TdsSR and TgsS1 High delay skewof TdsSR and TgsS1*Voltage-sensing based refs - PWLL method*This paper proposed methodΔT= AdaptiveSR controllerTgsS1TdsSR - TgsS1Pulse WidthCalculatorPulse WidthCalculatorFigure 3.29: The propagation delay skew comparison of (a) the proposed BRF tacking; (b)the PWLL method in references. As the proposed BRF tacking method has symmetricmeasuring channels for VAB and VCD, the propagation delay skew of the two channelsis lower than the references.Experiments have been done to measure propagation delay and propagation delay skew ofBroadcom ACPL-071L used in this work. Same input voltage Vin opto =±200V , 100kHz is appliedto two Broadcom ACPL-071L. The time delay of falling edges of Vin opto and Vout opto1, Vout opto2are measured as shown in Fig. 3.30(a). The figure is showing the measured propagation delay is26.8ns, which is fewer than the number (40ns) in the datasheet. As discussed, this propagationdelay may not directly reduce the accuracy of resonant frequency tracking of the proposed BRFtracking method. It is the skew of the propagation delay of two optocouplers that causes trackingerrors. Therefore, another measurement is done to get the delay skew, which is 2.75ns as shown in111Fig. 3.30(b). Considering the resonant frequency of the prototype is 100kHz, 2.75ns of delay skewonly can cause the tracked resonant frequency to vary from 100kHz within [99.97kHz,100.03kHz].Plus, the step of BRF tracking step is 0.1kHz. In the worst case, the final resonant frequency rangetracked by the proposed BRF tracking method is [99.87kHz,100.13kHz], considering the delayskew and tracking step resolution. This accuracy is good for bidirectional battery chargers applica-tions.Vin_optoVin_optoVout_opto1Vout_opto1Zoom in(a)(b)Falling edge delay of optocouplersfrom input voltageVout_opto2Vout_opto226.8 nsVin_optoVin_optoVout_opto1Vout_opto1Zoom inFalling edge delay skew of optocouplersVout_opto2Vout_opto22.75 nsFigure 3.30: Same input voltage Vin opto = ±200V , 100kHz is applied to two BroadcomACPL-071L used in this work’s prototype. (a) this figure is showing the measuredpropagation delay is 26.8ns, but this propagation delay will not directly cause accuracydegradation for this work. (b) this figure is showing the delay skew of two optocou-plers is only 2.75ns, which only can cause the tracked resonant frequency to vary from100kHz within [99.97kHz,100.03kHz].1123.5.2 Compare with Current-sensing based Unidirectional TrackingMethodsCr1 Cr2LmLr1Ir1Idiode1 Idiode2V1Lr2V2Ir2Comparator 2Low pass filter 2Isolatedcurrent sensor 2Current BasedTracking ControllerTo secondary side MOSFETSFor forwardmodeFor backwardmodeTo primary side MOSFETSS1, S2S3, S4S5, S6S7, S8Comparator 1Low pass filter 1Isolatedcurrent sensor 1Figure 3.31: Extra stages (highlighted in red) are required to add for current-sensing-basedunidirectional tracking methods for bidirectional operations. Two current sensors arerequired, which are unfavorable due to the high cost, and low power density. Theproposed BRF tracking method is lower cost, simpler, and has higher power density inbidirectional operations.The current-sensing-based tracking methods in [82–84] cannot be applied directly to bidirec-tional tracking for CLLC converters because more stages are required to be added for backwardoperations as highlighted in red in Fig. 3.31. To measure the current Idiode1 in the backward mode,one more isolated current sensor (Hall current sensor) is required to add. After this, the sensedIdiode is converted to a pulse signal Vsig by using the crossing-zero comparator. Then, the averagevalue of Vsig is obtained by using the RC low-pass filter. It is worth noting that the current-sensing-based tracking methods are not measuring tzero directly for Idiode. The average value of Idiode isobtained by comparators and RC low-pass filters. The robustness again current noise is thereforeimproved, but RC low-pass filters may cause high delay issues [142] and resonant frequency track-ing accuracy degradation. Moreover, two Hall current sensors are needed for references [82–84] totrack resonant frequency bisectionally, which are unfavorable due to the high cost, and low powerdensity.113In contrast, the proposed BRF tracking algorithm only requires two optocouplers in the con-ditioning circuit for bidirectional tracking, and no current sensors or low-pass filters are required.Therefore, the proposed method offers lower cost, simpler, and high power density for bidirectionalresonant frequency tracking compared with current-sensing-based methods.To sum up, extra stages are required to add existing unidirectional tracking methods for bidi-rectional tracking operations. These are unfavorable due to the complexity, delay, cost, and powerdensity issues. Therefore, the proposed BRF and unified bidirectional tracking method offer lowercost, and simpler solutions than using conventional unidirectional tracking methods for forwardand backward separately.3.6 SummaryIn this chapter, a unified bidirectional resonant frequency tracking algorithm has been proposed forunregulated bidirectional CLLC resonant converters to improve efficiency when the switching fre-quency drifts due to parameter deviations. Based on the generalized resonant frequency equations,the bidirectional resonant frequency (BRF) has been derived. As both the forward mode and thebackward mode achieve maximum efficiency at BRF, the bidirectional resonant frequencies track-ing is unified to track the BRF. With the analysis of the voltages phase shift of the CLLC resonanttank, it is discovered that Vab and Vcd are in phase at fBRF for bidirectional operations regardlessof parameter deviations. Therefore, the bidirectional tracking is further unified into tuning switch-ing frequency online to keep Vab and Vcd in phase. The introduction of the BRF combined withthe unified bidirectional tracking algorithm provides a simple, accurate, and low-cost solution forbidirectional resonance tracking of unregulated CLLC converters. Finally, the challenges and theirsolutions in implementing the proposed bidirectional resonance tracking algorithm for engineeringapplications are discussed. And the bidirectional efficiency improvement for unregulated CLLCresonant converters by the proposed tracking algorithm has been verified by experiments.114Chapter 4Cascaded Half-bridge Based BidirectionalMulti-level Bridgeless PFC with MultiOutput Ports1In the previous two chapters, two novel techniques for improving the performance of the bidirec-tional resonant CLLC DC/DC stage are proposed in Chapter 2 and Chapter 3. These two techniquesare highly versatile and can be applied to both high and low voltage EV for e-mobility purposes.However, the use of CLLC DC/DC converters in low voltage EV applications, such as scootersand golf carts, presents certain design challenges. This is primarily due to the low battery volt-age, which typically falls between 48V and 60V. In such instances, if the DC bus voltage fromthe AC/DC stage remains fixed at a high voltage, such as 400V, the transformer ratio for the CLLCDC/DC converter stage will be high, leading to design challenges for the secondary side inductanceof CLLC resonant tank. Therefore, in addition to the two proposed techniques for the DC/DC stage,solutions must be sought from the AC/DC stage to address the high transformer ratio problem inlow voltage EV applications.Motivated by these problems, a cascaded half-bridge based multi-level multi-port bridgelessPFC AC/DC rectifier is proposed in this chapter as shown in Fig. 1.18. It is a bridgeless PFC topol-1Portions of this chapter have been published in [5], and submitted a peer-reviewed journal in the field of powerelectronics.115ogy since the rectification is achieved without using a full bridge diode rectifier. Traditional PFCcircuits with a full bridge diode rectifier can lead to significant power loss. By contrast, bridgelessPFC designs reduce this loss by eliminating the full bridge rectifier, thus cutting down on compo-nents and related power losses. This offers efficient rectification without a diode bridge. In essence,the absence of a full bridge diode rectifier is what makes these configurations bridgeless. The pro-posed topology also offers multiple low-voltage DC output ports that can be used to power multipleCLLC DC/DC converter loads. Compared with cascaded full-bridge multi-level PFC, the numberof switches per cell for the proposed topology is significantly reduced by half while maintainingthe same output ports. The added two switches K1 and K2 are just working at grid frequency, andthey can be simply replaced by two diodes if this proposed topology only works unidirectionally.Thanks to the volt-second reduction on the boost inductor brought by multi-level voltage, the inputcurrent ripple drops remarkably with the same boost inductance compared with conventional totempole PFC rectifiers. The switching loss can also benefit from the proposed cascaded half-bridgetopology. Compared with cascaded full-bridge PFC with n full-bridge cells, the proposed PFC canhave 2n half-bridge cells. Therefore, the switching voltage for each cell is lower than the cascadedfull-bridge PFC, thereby causing lower switching loss. Moreover, the conduction losses can alsobenefit from the proposed rectifier as the lower voltage switches with smaller Rds on are adopted inhalf-bridge cells compared with conventional totem pole PFC rectifiers.The rest of this chapter is organized as follows. In section 4.1, detailed operation principlesof the proposed cascaded half-bridge multi-level PFC are analyzed, and the steady state model isproposed. In Section 4.2, the proposed PFC is compared with conventional PFC topologies. Then,the parameter mismatch is analyzed and the control strategy is presented for the proposed PFC inSection 4.3. The effectiveness and performance are verified by experiments in Section 4.4. Finally,the conclusions are drawn in Section 4.5.4.1 Operation Principles and Steady State Model of ProposedCascaded Half-bridge PFCIn this section, operation principles of the proposed cascaded half-bridge based multi-level multi-port PFC will be introduced. Then, the steady-state model will be presented, which can help with116developing the control strategy in Section 4.3.4.1.1 Operation Mode AnalysisS1aS1bC1C2C3C4S2aS2bS3aS3bS4aS4bK1K2uswuPuNR1R2R3R4us Ls(a) Mode 1S1aS1bC1C2C3C4S2aS2bS3aS3bS4aS4bK1K2uswuNR1R2R3R4us Ls(c) Mode 3 (d) Mode 4(b) Mode 2S1aS1bC1C2C3C4S2aS2bS3aS3bS4aS4bK1K2uswuNR1R2R3R4us LsS1aS1bC1C2C3C4S2aS2bS3aS3bS4aS4bK1K2uswuNR1R2R3R4us LsuP uPuPFigure 4.1: Operation modes of the proposed PFC. Sub figs (a)-(d) show the 4 different op-eration modes during the positive half cycles of the grid voltage us> 0.The proposed cascaded half-bridge PFC consists of an upper arm and a lower arm. The upperarm works during the negative grid voltage cycle (us6 0). The AC side voltage of upper arm cellsis defined as uN . Similarly, the lower arm works during the positive grid cycle (us> 0) and its AC117side voltage is uP. Each arm has n identical half-bridge cells in series. For simplicity, the proposedPFC with 4 cells, 2 cells in each arm, is adopted here as an example to demonstrate operationmodes. There are eight operation modes as shown in Fig. 4.1. K1 and K2 are complementaryswitches working at the grid voltage us frequency. During the positive grid cycle, K1 is always onand K2 is always off; for the negative cycle, K1 is always off and K2 is always on. Meanwhile, theswitches of half-bridge cells in the upper and lower arms (Sxa, and Sxb, x = 1...4) also operate in acomplementary fashion, but with switching frequency fs. As there are no current charging C1 andC2 loads during the positive grid cycles, the load voltage is held up by C1 and C2. It is the samefor the capacitors C3 and C4 to hold the loads in the negative grid cycle. This requirement does notnecessarily bring additional cost to the capacitors of the proposed PFC converter, since the DC sidecapacitance of the PFC is generally designed to hold up half the grid cycle.There are eight operation modes for the proposed cascaded half-bridge multi-port PFC. Whenus> 0, the proposed cascaded half-bridge multi-level PFC works in Mode 1 to Mode 4 in Fig. 4.1,and it works in Mode 5 to Mode 8 when us6 0, as shown in Fig. 4.2.Mode 1 (Fig. 4.1(a)): switches S3a and S4a are turned off, so capacitors C3 and C4 are bypassedfrom the grid current is loop. The inductor current Ls rises, and the energy from the grid voltage usis stored in the Ls. The voltage at switching node usw equals the lower arm voltage, which is 0V(usw =uP=0V). During this mode, the energy and voltage of the load are provided by capacitors C1to C4.Mode 2 (Fig. 4.1(b)): Switch S3a is turned on while S4a is turned off. In this mode, the capacitorC3 is connected to the grid current loop although C4 is still bypassed. The magnetic field in Ls willbe reduced in energy to maintain the current towards C3 and load R3. Therefore, the polarity of Ls isreversed to negative on the left side. Consequently, two sources, i.e., us and Ls, are in series creatinga higher voltage to charge C3 and load R3. The voltage at switching node usw =uP=UC3=Udc/4.Mode 3 (Fig. 4.1(c)): This mode is similar to Mode2, but C3 is bypassed while C2 is connectedto the power loop to be charged by us and Ls. The voltage at switching node usw =uP=Uc4=Udc/4.Mode 4 (Fig. 4.1(d)): Both switches S3a and S4a are turned on in this mode, so capacitors C3and C4 are connected to the power loop. us and Ls are in series creating a higher voltage to charge118S1aS1bC1C2C3C4S2aS2bS3aS3bS4aS4bK1K2uswuPuNR1R2R3R4us Ls(a) Mode 5S1aS1bC1C2C3C4S2aS2bS3aS3bS4aS4bK1K2uswuPuNR1R2R3R4us LsS1aS1bC1C2C3C4S2aS2bS3aS3bS4aS4bK1K2uswuPuNR1R2R3R4us LsS1aS1bC1C2C3C4S2aS2bS3aS3bS4aS4bK1K2uswuNR1R2R3R4us Ls(c) Mode 7 (d) Mode 8(b) Mode 6uPFigure 4.2: Operation modes of the proposed PFC. Sub figs (a)-(d) show the 4 different op-eration modes during the negative half cycles of the grid voltage us6 0.C3 and C4 clockwise. The voltage at switching node usw is equal to the lower arm voltage uP, whichis the voltages of C3 and C4 in series, usw =uP= UC3+Uc4=Udc/2.Mode 5 to Mode 8 (shown in Fig. 4.2(a) to Fig. 4.2(d)) are the proposed PFC working duringthe negative half cycle. These modes resemble the corresponding Mode 1 to Mode 4 of the positivehalf cycle, so they are not repeated here. These 8 operation modes are summarized in Table 4.1.Fig. 4.3 shows how the multi-level switching node voltage usw changes with the grid voltage119Table 4.1: Operation Modes of the Proposed PFCModes Grid Volt. SW. Volt. usw Charging CapsMode 1 us> 0 0 N/AMode 2 & 3 us> 0 Udc/4 C3 or C4Mode 4 us> 0 Udc/2 C3 and C4Mode 5 us6 0 0 N/AMode 6 & 7 us6 0 Udc/4 C1 or C2Mode 8 us6 0 Udc/2 C1 and C22 cells each arm, 4 cells in totallK1 ONOFFOFFON0Udc2-Udc2K2S3aS4aS1aS2auPusw(=uP-uN)-uN tttttttt0 t3t1 t2 t4 t5 t6usFigure 4.3: Operation waveforms diagram of the proposed PFC. It is showing that multi-levelswitching node voltage usw changes sinusoidally with the grid voltage us. Switches K1and K2 operate alternately with grid frequency. S3a and S4a switch during positive girdcycle, while S1a and S2a work during negative gird cycle. The width of the gate drivingsignals of S1a to S4a varies sinusoidally during their working time.120us. Each half bridge cell has two switches, Sxa and Sxb, working in complementary. When Sxaturns on and Sxb turns off, the cell is defined as the on state, where the capacitor Cx and load Rx areconnected to the power loop to be charged by energy from both the inductor and grid. Similarly,the cell is defined as the off state, where the capacitor Cx and Rx are bypassed. Therefore, the loadenergy and voltage are provided by the capacitor Cx. To simplify the demonstration, only drivingsignals of Sxa are shown in Fig. 4.3. During the positive half cycle, K1 is always one while K2 isoff. The PWM width of S3a and S4a varies sinusoidally. S1a and S2a are always off. From t0 to t1,the switching node voltage usw varies between 0 and Udc/4 in the positive cycle of grid voltage.According to Table 4.1, the proposed cascaded half-bridge multi-level multi-port PFC is workingin Mode 1, Mode 2 and Mode 3. For period t1 to t2, the usw switches between Udc/4 and Udc/2,thereby resulting in the proposed rectifier working in Mode 2, Mode 3 and Mode 4. The operationduring t2 to t3 resembles the period t0 to t1. As for the negative grid cycle, the periods t3 ∼ t4, t4 ∼ t5and t5 ∼ t6 are operating in Mode5∼Mode7, Mode6∼Mode8 and Mode5∼Mode7, respectively.4.1.2 Steady State ModelIn this subsection, the steady state model will be presented for the proposed cascaded half-bridgemulti-level multi-port PFC. To ensure generality, there are n half-bridge cells in both the lower andupper arm, so 2n cells are adopted in total. The steady-state model derived in this subsection willbe used for the parameter mismatch analysis and control strategy derivation in Section 4.3.The generalized topology with 2n cells is shown on the left side of Fig. 1.18. Its electricalequivalent circuits for positive and negative grid cycles can be obtained as shown in Fig. 4.4. Theupper and lower arm voltages uN and uP areuN =n∑i=1Si · UiuP =2n∑j=n+1S j · U j(4.1)121uPuK1uK2uK1uK2uswNegativeHalf CyclesiNLsiPPositiveHalf CyclesuN(a) Positive Half CyclesuPuswLsuN(b) Negative Half Cyclesus usFigure 4.4: Equivalent circuits for the proposed PFC in (a) Positive us Cycles (b) Negative usCyclesThe upper and lower arm currents iN and iP are iN =−SkisiP = Skis (4.2)Wherei = 1. . .n (4.3)j = (n+1). . .2n (4.4)Si = 1 when Sia = 1, Sib = 00 when Sia = 0, Sib = 1 (4.5)S j = 1 when S ja = 1, S jb = 00 when S ja = 0, S jb = 1 (4.6)SK = 1 when K1 = 1, K2 = 00 when K1 = 0, K2 = 1 (4.7)122SK = 1−SK (4.8)With the KVL and the KCL, voltage and current equations of the equivalent circuit when us> 0in Fig. 4.4(a) can be written as  us = Lsdisdt +uP+uK1C jdU jdt = S jiP−U jR j(4.9)where uK1 = 0 during the positive grid cycle when SK = 1.Combining equations (4.1), (4.2), and (4.9):Ls disdt = us−2n∑j=n+1S j ·U j−uK1C jdU jdt = S jSkis−U jR j(4.10)Based on equation (4.10), the state space equation in the matrix form isdisdtdUn+1dt...dU2ndt=0 −Sn+1Ls ... −S2nLsSn+1SkCn+1−1Cn+1Rn+1... 0... ... ... ...S2nSkC2n0 ... −1C2nR2n·isUn+1...U2n+1Ls0...0us+uK1Ls0...0(4.11)Similarly, during the negative grid cycle, Fig. 4.4(b) can be modeled as:Ls disdt = us+n∑i=1Si ·Ui+uK2Ci dUidt =−SiSkis− UiRi(4.12)where uK2 = 0 during the negative grid cycle when SK = 1. And the equation (4.12) can be written123in matrix form as disdtdU1dt...dUndt=0 S1Ls ...SnLs−S1SkC1−1C1R1... 0... ... ... ...−SnSkCn0 ... −1CnRnisU1...Un+1Ls0...0us+uK2Ls0...0(4.13)According to equations (4.11) and (4.13), the steady state model can be shown as Fig. 4.5.Ls isiUusuNuPiLS1U1 -SkS1isSnUnSn+1Un+1S2nU2nU1 R1-SkSnis Un RnSkSn+1is Un+1 Rn+1SkS2nis U2n R2nuK2NegativeHalf CyclesiNuK1iPPositiveHalf CyclesFigure 4.5: The steady-state model for the proposed cascaded half-bridge based multi-levelmulti-port PFC. It can be regarded as two sub-systems for the positive and negative gridcycles.In this section, the operation modes and steady state model are presented to show how theproposed half-bridge based PFC works. It can be regarded as two sub-systems working for thepositive and negative grid cycles, respectively. The switch functions Si and S j can be seen as theduty ratio factors. By adjusting the time applying Si and S j, the current charging the DC capacitorscan be controlled, and then the DC voltage of each cell can be regulated. The analysis presented in124this section provides a theoretical basis for the parameter mismatch analysis and control strategy,which will be discussed in Section 4.3.4.2 Comparison with Conventional PFC TopologiesTo demonstrate the advantages of the proposed cascaded half-bridge based multi-level multi-portPFC, this section will compare it with cascaded full-bridge PFC and conventional 3-level bridgelesstotem-pole PFC. In the following comparisons, the same input voltage, boost inductor, and outputpower will be assumed. For a cascaded full-bridge PFC with n cells, 4n MOSFETs are required.For a fair comparison, it is assumed that the proposed PFC topology also uses the same numberof 4n MOSFETs. Since it is a half-bridge structure, the proposed PFC can have 2n half-bridgecells. The three topologies will be compared below in terms of switching loss, conduction loss, andcurrent ripple. Since the equivalent frequency of the conventional totem pole PFC is lower than theproposed PFC and cascaded full-bridge PFC, the switching loss, conduction loss and current rippleare compared with the assumption that the conventional totem pole PFC increases the switchingfrequency n times to achieve the same equivalent frequency with two cascaded topologies. Thecomparison results are summarized in Table 4.2.Table 4.2: Comparison of conventional 3-level totem-pole PFC, cascaded full-bridges PFC,and the Proposed PFCTopologies Output Ports No. MOSFETs No. Volt. Levels Eff. Sw. Freq. Sw. Loss Current RippleConventionaltotem-polePFC1 4 3 fs Psw,on,tot,conv ∆imax,convCascadedfull-bridgesPFCn 4n 2n+1 n · fs < 2Psw,on,tot,convn∆imax,convnThe ProposedPFC2n 4n+2 2n+1 n · fs < Psw,on,tot,conv2n∆imax,conv2n1254.2.1 Switching LossFor these three PFC topologies, the switching on and off for MOSFET loss can be calculated basedon the current and voltage overlapping area during the transition. The total turning on and off theloss of all MOSFETs can be written in equations asPsw,on,tot = 1/2 · vds · ids · ton · fs ·NMOS (4.14)Psw,o f f ,tot = 1/2 · vds · ids · to f f · fs ·NMOS (4.15)where vds and ids are the voltage and current of drain to source pins of the MOSFETs, fs is switchingfrequency, and Nmos means the total MOSFETs of a topology. The time of ton and to f f are theoverlapping time of current and voltage, which are related to the gate-drain charge (Qgd) during theMiller plateau, gate resistors of turning on and off (Ron and Ro f f ), the gate driving voltage (Vgs,onand Vgs,o f f ), and Miller plateau voltage (Vplat) aston =QgdIg,on=Ron ·QgdVgs,on−Vplat (4.16)to f f =QgdIg,o f f=Ro f f ·QgdVplat−Vgs,o f f (4.17)Taking turn-on loss as an example, it can be seen from equations (4.14) and (4.16) that vds isthe DC link voltage Udc for the conventional totem pole PFC. Because the same output power isassumed, the ids are the same input current is for the three topologies. A conventional totem polePFC has a total of four MOSFETs, two of which work at the grid frequency with low switchingloss. Therefore, only the switching loss caused by the two MOSFETs operating at high frequencyis considered here. To achieve the same switching frequency as cascaded topologies, conventionaltotem pole PFC must work at n · fs. Total switching loss can be written asPsw,on,tot,conv = 1/2 ·Udc · is · ton,conv · (n · fs) ·2 (4.18)126For a cascaded full-bridge PFC with n cells, the DC link voltage of each cell is Udc/n. Thecurrent of each cell is equal to the grid current is. Assuming bipolar modulation is adopted, thetotal switching loss of 4n MOSFETs can be expressed as (4.19). Compared with the conventionaltotem pole PFC, the cascaded full bridge can use low voltage MOSFETs with lower gate-draincharge Qgd , so overlapping time ton,casc f ull < ton,conv. Since Qgd varies with MOSFETs, quantitativecomparison can be calculated by referring to MOSFET datasheets with (4.16) and (4.17). Thequalitative comparison with conventional totem pole PFC is provided as:Psw,on,tot,casc f ull = 12 · Udcn · is · ton,casc f ull · fs ·4n <2Psw,on,tot,convn(4.19)For the proposed PFC, there are n cascaded half-bridge cells on the upper arm, and another ncells in the lower arms. They work in the negative and positive half cycles of the grid, respectively.Therefore, there are n half-bridges causing switching losses at any time, which are a total of 2nMOSFETs. Since there are 2n cells in total, the switching voltage of each cell is Udc/2n, totalswitching loss is presented asPsw,on,tot,prop = 12 · Udc2n · is · ton,prop · fs ·2n <Psw,on,tot,conv2n(4.20)From (4.18), (4.19) and (4.20), it can be seen that the proposed cascaded half-bridge PFC haslower switching losses than the topologies of cascaded full-bridge PFC and conventional totempole PFC.4.2.2 Conduction LossThe conduction loss can be derived from the RMS current and conduction resistance of MOSFETsasPcondc = I2RMSRds,onNon,MOS (4.21)For the proposed PFC with 2n cells, the number of conducted MOSFETs in the switching powerloop Non,mos are (n+ 1), while the cascaded H bridges topology with n cells has 2n MOSFETs inthe conduction power loop. Therefore, the conduction loss of the cascaded full bridge will ramp127up rapidly with the increase of the number of modules n. When the number of modules n is largeenough, cascaded full bridges have nearly 2 times higher conduction losses than the proposed PFCtopology. Although the conduction loss of these cascaded full or half bridge topologies rises withmodule number n, this does not necessarily mean that the cascaded topologies are always worsethan the conventional totem pole PFC in conduction loss. This is because cascaded topologiescan use lower voltage MOSFETs with lower Rds,on. In summary, comprehensive evaluation of theconduction loss requires consideration of all the parameters shown in (4.21).4.2.3 Current Ripple and Required InductanceOne of the challenges to further improving the power density of PFC is still the large volumeof inductors. In this subsection, the current ripple and requirements of inductance will be com-pared among the three topologies. Assuming the three topologies being compared use the sameinductance, the relation between maximum peak-to-peak boost inductor current ripple ∆imax andinductance L can be given with equations for conventional totem pole PFC, cascaded full bridgePFC and the proposed cascaded half-bridge PFC topologies as:∆imax,conv =UDC4 · (n · fs)L (4.22)∆imax,casc f ull =UDC4n2 fsL=∆imax,convn(4.23)∆imax,prop =UDC8n2 fsL=∆imax,conv2n(4.24)It can be found from (4.22), (4.23) and (4.24) that the inductor current ripple is caused by thevolt-seconds applied to it. For consistency of comparison, the switching frequency of conventionaltotem pole PFC is still assumed to be equal to n · fs to match cascaded topologies, although this willdramatically increase the switching loss of conventional totem pole PFC as discussed previously.However, the current ripple is still 2n times higher than the proposed cascaded half-bridge PFC.As for the cascaded full bridge PFC, the current ripple is 2 times higher than the proposed PFC.128This is because the Udc is divided by 2n cells for the proposed PFC, rather than n. The benefit ofthe proposed PFC is brought not only by the higher equivalent switching frequency but also by thereduction of volt-seconds on the inductor.To sum up, compared with conventional totem-pole PFC and cascaded full-bridge PFC, theproposed cascaded half-bridge PFC has advantages in switching losses, conduction losses and cur-rent ripple while providing more output ports. In the next section, the parameter mismatch will beanalyzed, and the control strategy will be presented for the proposed cascaded half-bridge PFC.4.3 Control strategy for the proposed Cascaded Half-bridgePFCAs a PFC with multi-DC out ports, the control target of the stable operation is to distribute DC linkvoltage among cells. Moreover, circulating current caused by cell parameter mismatch from ratedvalues may also be a challenge for multi-out port converters. Therefore, in this section, the impactof parameter mismatch on the circulating current for the proposed PFC will be analyzed first, andthen a control and modulation strategy will be presented.4.3.1 Analysis of Parameter MismatchDue to manufacturing tolerances and the aging process, the capacitance of DC link electrolyticcapacitors varies from the designed values. This parameter mismatch may lead to extra conductionloss due to circulating current among cells.The proposed cascaded half-bridge multi-port PFC working with ISOP (Input Series OutputParallel) DC/DC converter is adopted as an example here. As shown in Fig. 4.6(a), the multi-ports of the proposed PFC are fed to multiple isolated DC/DC converters. Three factors may causecirculating current: the DC link capacitors of the proposed PFC, the transformer ratio in the DC/DCstage, and the output filter (Lx and Co) in the DC/DC stage. The analysis below will focus on theparameter mismatch of the DC link capacitors of the proposed PFC (C1 ∼C2n), while assuming thatthe transformer ratio and output LC filter of the DC/DC stage are the same (ZL = ZL1 = · · ·ZL2n).Therefore, the AC equivalent circuit of the proposed PFC in the ISOP application can be obtainedin Fig. 4.6(b). Since the output voltage of the DC/DC stage will be regulated as constant, the output129irec,ac,NCell(1) Circuit Lower ArmCellsUpper ArmCellsThe proposed Cascaded Half-bridge PFC stage The DC/DC stage Norton’s Theorem equivalent circuit for Cell(2) ~ Cell(2n) Cell(1) Circuit Norton’s Theorem equivalent circuit for Cell(2) ~ Cell(2n) DC/DCDC/DCic1,PiL1,ac,PiNorton,PUoirec,ac,N ic1 iL1ZC1ZLZLZLZLUoirec,ac,NZCnirec,ac,PZC(n+1)irec,ac,PZC2nicn iLnic(n+1) iL(n+1)ic2n iL2nZC1ZLZLNortonZCNortonic1,NiL1,ac,NiNorton,NUoZC1ZLZLNortonZCNortonirec,1(b)(a)(c)(d)iPDC/DCCell(n+1)Cell(n)Cell(2n)usS1aS1bC1 Co UoK1K2 iNLsL1LnLn+1L2nisDC/DCCell(1)Figure 4.6: Circulating current analysis of the proposed cascaded half-bridge based multi-level multi-port PFC: (a) the proposed PFC with 2n cells in ISOP application (b) ACequivalent circuit of the proposed PFC in ISOP application, where the cascaded halfbridges in proposed PFC can be modeled as controlled current sources. (c) Assumingonly DC link capacitor of the first cell (ZC1) has parameter mismatch from other (2n−1)cells (ZC). By using Norton Theorem, the simplified equivalent circuit for the negativegrid cycle can be obtained. (d) Norton equivalent circuit for the positive grid cycle.130capacitor Co can be ignored in Fig. 4.6(b) during the circulating current analysis. As discussed inSection 4.1, the proposed cascaded half-bridge PFC can be modeled as current sources as shown inFig. 4.5. The AC component of interest for the analysis below has double grid frequency, with theassumption of ignoring negligible DC link voltage ripples. In the analysis below, we could assumethat the AC components of the rectification current after the half-bridge for the positive cycle cellsare equal, which could be defined as irec,ac,P. Similarly, irec,ac,N indicates AC components of therectification current for the negative cycles cells as shown in Fig. 4.6(b).To simplify the analysis of circulating current, only the first cell’s DC link capacitance (ZC1)is assumed to be different from other (2n− 1) cells (ZC1 6= ZC = ZC2 = · · · = ZC2n). By using theNorton Theorem for Cell(2) ∼ Cell(2n) in Fig. 4.6(b), the simplified AC equivalent circuit forthe negative grid cycle can be obtained as shown in Fig. 4.6(c): the DC link capacitors in half-bridge Cell(2) ∼Cell(2n) can be simplified as ZCNorton; the output inductor filters are combined asZLNorton. Equations for ZCNorton and ZLNorton are ZC Norton =ZC2n−1ZLNorton = ZL2n−1(4.25)where ZC = 1/( j2ωgC), ZL = j2ωgL, and ωg is the angular frequency of the grid.During the negative grid cycle, the Norton equivalent circuit obtained from Fig. 4.6(b) can beshown in Fig. 4.6(c). As for iNorton,N in Fig. 4.6(c), it could be determined with negative gridcycles, when the irec,ac,P is regarded as 0. Therefore, the iNorton,N can be obtained by taking currentsources for Cell(2) ∼Cell(n) into consideration:iNorton,N =ZC · (n−1)ZL+ZC· irec,ac,N (4.26)Similarly, the Norton Theorem’s equivalent current during the positive grid cycle iNorton,P canbe derived by taking current sources for Cell(n+1) ∼Cell(2n) into consideration asiNorton,P =ZC ·nZL+ZC· irec,ac,P (4.27)131In equations (4.26) and (4.27), the irec,ac,N and irec,ac,P can be calculated based on the totalpower Ptot and the total DC link voltage Udc of all the 2n cells asirec,ac,N = irec,ac,P =PtotUdc(4.28)Therefore, with equations (4.26) and (4.27), Norton Theorem’s equivalent current can be writtenasiNorton = iNorton,N , us < 0iNorton,P, us ≥ 0 (4.29)By using the superposition law for two current sources (irec,ac,N and iNorton,N) as shown in Fig.4.6(c), the capacitor current during the negative grid cycle iC1,N is obtained as:iC1,N = iNorton,NZC,Norton+ZL,NortonZtot+ irec,ac,NZL+ZC,Norton+ZL,NortonZtot(4.30)where Ztot = ZL+ZC,Norton+ZL,Norton+ZC1.For the positive grid cycle, the current irec,ac,N for Cell(1) ∼ Cell(n) is 0, so the Norton equiv-alent circuit considering irec,ac,P is obtained as shown in Fig. 4.6(d). The capacitor current duringthe positive grid cycle iC1,P is:iC1,P = iNorton,PZC,Norton+ZL,NortonZtot(4.31)By combining equations (4.28), (4.29), (4.30) and (4.31), the circulating current amplitudegoing through the module 1 output filter inductors of the DCDC stage (connected after the proposedPFC) during the negative grid cycle iL1,ac,N and positive grid cycle iL1,ac,P are:iˆL1,ac,N =∣∣irec,ac,N− iC1,N∣∣= PtotUdc ∣∣∣ ZC1(2n−1)−ZC(n−1)ZC1(2n−1)+2n·ZL+ZC ∣∣∣ (4.32)iˆL1,ac,P =∣∣−iC1,P∣∣= PtotUdc∣∣∣∣ ZC ·nZC1(2n−1)+2n ·ZL+ZC∣∣∣∣ (4.33)As for the Cell(2) ∼ Cell(2n) that are without parameter mismatch, their circulating current132during negative and positive grid cycles can be given asiˆL2,ac,N= · · · =iˆL2n,ac,N = iˆL1,ac,N2n−1 (4.34)iˆL2,ac,P= · · · =iˆL2n,ac,P = iˆL1,ac,P2n−1 (4.35)It can be found from equations (4.32) and (4.33) that if the DC side capacitance for Cell(1)ZC1 is equal to the rest (2n− 1) cells capacitance ZC, the circulating current amplitude duringthe negative cycle in (4.32) will be equal to the positive grid cycle circulating current in (4.33).The circulating current difference becomes larger as the difference between Zc and ZC1 increases.Although the circulating current will not cause the runaway situation for the proposed cascadedhalf-bridge PFC, its increase could lead to a higher RMS current for the MOSFETs and magneticcomponents, and might thereby cause extra losses.4.3.2 Control and Modulation Strategy for the Proposed CascadedHalf-bridge PFCThe control and modulation strategy of the proposed cascaded half-bridge based PFC will be pre-sented in this subsection. Since the upper and lower arm cells are connected in series, the currentsgoing through them are the same. Therefore, only the DC link voltages of cells need to be con-trolled. The output current sharing is usually realized by DC/DC converters connecting to theproposed PFC converter. To balance the DC link voltage of all the cells naturally, the common dutyratio control strategy is adopted in this work. There are also phase shift degrees applied to bothupper and lower cells in the modulation strategy.The control diagram for the proposed PFC is shown in Fig. 4.7. The DC link voltage for theupper arm cells (U1, · · · , Un) and lower arm cells (Un+1, · · · , U2n) are controlled separately. Thereare voltage and current control loops and feed-forward in the controller. Taking the control duringthe negative grid cycle as an example, for the output voltage loop, the voltages of the upper armcells (U1, · · · , Un) are sampled by ADC and added up in DSP. The result of their summation isthen subtracted from half of the DC link voltage reference to obtain the voltage errors. To ensurethat the PI controller of the upper arm cells only accumulates voltage errors in the negative grid133Output Voltage Loop Current Loop Feed ForwardΣ PI PIModulation Cell 1Cell 2Cell nU1U2UnUDCref /2us DN,f (Eq. 37)DNDN,iDPDP,iisis,ref,Nis,ref,Pus0Un+1Un+2U2nΣ PI PIModulation Cell n+1Cell n+2Cell 2nUDCref /2us DP,f (Eq. 39)isus0Figure 4.7: The control diagram of the proposed cascaded half-bridge based multi-levelmulti-port PFC, which consists of four parts: output voltage loop, current loop, feed-forward and modulation. The DC link voltages for upper and lower cells are controlledseparately.cycle, voltage errors are multiplied by the comparison of 0V and the grid voltage. Afterward, thePI controller output is multiplied by the normalized grid voltage us to get the current loop referenceis,re f ,N in the negative half cycle. Then the duty ratio signal from current loop DN,i can be obtainedby sending the difference between reference is,re f ,N and the grid current is into the current innerloop P controller. In this way, the current follows a sinusoidal waveform with the grid voltage,thereby increasing the power factor.To cope with the challenge of peak current at AC zero-crossing and improve the transient re-sponse capability, duty cycle feedforward DN, f is added to the current (inner) control loop. Basedon the volt-second balance principle and equation (4.12), volt-seconds applied to inductor Ls arethe same when the Cells are charged (Si = 1) and bypassed (Si = 0). During the positive grid cycle,the voltage on switch K1 (uK1) is 0, so the feed-forward formula for common duty ratio DN, f withthe help of equation (4.12) for cells on the upper arm can be written asus ·DN, f = (n∑i=1Ui−us) · (1−DN, f ) (4.36)By solving (4.36), the feed-forward formula during the negative cycle for common duty ratio134DN, f isDN, f = 1− usn∑i=1Ui= 1− 2 ·usUdc(4.37)The common duty ratio DN for all the upper cells can be obtained by adding up the duty ratiofrom current loop output DN,i and feedforward DN, f asDN = DN,i+DN, f (4.38)As for the positive grid cycle, the control strategy is similar except for the comparison of thegrid voltage and 0V. Moreover, with equation (4.10), the feed-forward duty ratio equation for thepositive grid cycles DP, f can be obtained for Cells on the lower arm asDP, f = 1− us2n∑j=n+1U j= 1− 2 ·usUdc(4.39)The common duty ratio for lower arm cells:DP = DP,i+DP, f (4.40)DN and DP represent the required duty cycle for the upper and lower arms of the proposed PFC,which are sent to the modulation module. For the proposed PFC with 2n cells (n for the upperarm, and n for the lower arm), the phase shift among cells on the upper arm is n/360 degrees. Thesame phase shift degrees are applied to lower arm n cells. In the positive half cycle, Cell(n+1) toCell(2n) are driven by PWMs modulated from common duty ratio DP, while the upper arm Cell(1)to Cell(n) are in the bypass state (all Cells are set as Si = 0) to reduce the voltage of switches K2.Similarly, in the negative half cycle of the grid, the lower Cell(n+1) to Cell(2n) are in the bypassedmode (S j = 0), and the upper arm Cell(1) to Cell(n) are driven by PWMs modulated by duty ratioDN to generate multi-level voltage.In this section, the circulating current caused by the DC link capacitor mismatch is analyzed indetail. Then the control and modulation strategies are discussed for the proposed PFC converter. In135the next section, the design method for the proposed PFC will be presented and the prototype withthe designed parameters will be verified by experiments.4.4 Design and Experimental verificationsIn this section, the proposed cascaded half-bridge based multi-level multi-port PFC will be de-signed, and a prototype will be built based on this design. Then, the proposed PFC will be verifiedby experiments with the prototype.4.4.1 Design of Proposed PFCDC link capacitorsThere are n half-bridge cells in series in the upper arm for the proposed PFC. The same number ofn cells are in the lower arm as well. Although the grid current cannot charge the upper and lowerhalf-bridge arm cells at the same time, this does not mean that the proposed PFC requires largerDC-link capacitance compared with conventional PFC. This is because the DC link capacitors ofthe PFC are usually designed according to the hold-up time. This requires the PFC to be able tosupply the same amount of power to load for the half grid period after the grid outage. Designingthe DC link capacitor according to the hold-up time rule can just hold the cell voltage up for theproposed PFC when there is no corresponding charging current.The hold-up time is typically chosen to be half a cycle of the incoming AC voltage frequency(60Hz). In this work, the hold-up time thold for this application has been set at 8.3ms, and themaximum allowable drop of the DC link voltage rate δ as 20%; for a 2n cells prototype with a totaloutput power Po of 500W , the required DC link capacitance of each cell can be calculated as [143]:Ccell.dc ≥ 2 ·Po/(2n) · thold(Udc/(2n))2− (Udc · (1−δ )/(2n))2(4.41)After calculation, 3465uF capacitance is required. Therefore, two 2200uF electrolytic capacitorsare chosen in parallel for each half-bridge cell of the proposed PFC.136Boost inductor LsThe boost inductor is one of the most important components in a PFC, as it can determine theoperating mode of the PFC. The smaller current ripple allows the PFC to operate in continuousconduction mode, but this means that the boost inductor must have a high inductance value. How-ever, the higher the inductance value, the larger the size of the inductor. To optimize the overallperformance of the proposed PFC, so that it can achieve an efficient balance between low poweroperation and maximum power operation, the inductance value can be calculated as [129]:Ls =UDC8n2 fs∆imax,prop(4.42)With (4.42), the required boost inductance can be calculated as 13µH. In the experimentalprototype, four 3.3µH(19.6A) inductors are in series for a total of 13.2µH inductance.MOSFETs and DiodesThere is a total of six half-bridge cells in the prototype. Therefore, the voltage stress on each GaNMOSFET is only Udc/6. Hence, the EPC2152 is chosen as the MOSFETs for all the half-bridgecells in the proposed PFC. It integrates the input logic interface, level shifting, bootstrap charging,and gate drive buffer circuits along with GaN output FETs configured as a half-bridge. There areseveral advantages of integrated GaN MOSFET IC. The integration of GaN MOSFETs with on-chip gate drivers could minimize the common source inductance and gate drive loop inductance.The power loop inductance is also reduced by the LGA pinouts, thereby facilitating the optimallayout. As for the power switches of K1 and K2, two diodes are adopted for them to switch at gridfrequency. The model is FES10G.All the system parameters and component models used in the prototype are summarized inTable 4.3. The picture of the assembled prototype is shown in Fig. 4.8.4.4.2 Experimental ResultsThe measured experimental results are presented in this subsection. As shown in Fig. 4.9 (a), boostinductor current iLs and switching node multi-level voltage usw are following the sinusoidal grid137Table 4.3: Parameters of the proposed PFC prototypeSystem parametersParameters Symbols ValuesNominal Output Power Po 500WDC Link Voltage Udc 200VNumber of Cells 2n 6Cell Switching Frequency fs 100kHzHold-up Time thold 8.3ms,20% volt. dropComponent ModelsMOSFETs 6×EPC2152, 80V , 8.5mΩDiodes 2×OnSemi, FES10G, 600V , VF = 1.2VBoost Inductors 4×ETQ-P8M3R3JFA, 3.3µH, 19.6ACaps of Each Cell 2×LKG2A222MESCCK, 2200µF , 100VCurrent Sensor LEM, HLSR 32-P/SP33, 32Avoltage us properly. The zoomed-in waveforms are demonstrated in Fig. 4.9 (b). The maximumcurrent ripple observed on the boost inductor was measured to be 2.1A at 0.5 duty ratio. Thisrepresents a relatively low level of current ripple, particularly given the fact that only a 13.2µHinductance was utilized in this prototype. This is realized thanks to the reduced volt-second appliedto the boost inductor from multi-level voltage usw. Firstly, the voltage change step of usw dropsto Udc/2n (33V). This means a decrease of 2n times compared with conventional totem pole PFC.Moreover, the equivalent frequency of iLs is n times higher than the switching frequency. Takingupper arm cells in the negative grid cycle as an example, the gate driving signals for low sideMOSFETs (S1b, S2b and S3b, shown in Fig. 4.9 (b)) are 100kHz, and are 120◦ phase shifted witheach other, while the equivalent frequency on usw and iLs is 300kHz. Therefore, the current rippleof the proposed multi-level PFC is low.Fig. 4.10 and Fig. 4.9 present experimental comparison results of the current ripple in a con-ventional totem pole PFC and the proposed PFC. For a fair comparison, the experimental resultsof the totem pole PFC are presented with the same inductance as the proposed PFC. To match the138Figure 4.8: Prototype of the proposed cascaded half-bridge based multi-level multi-port PFCwith 6 cells according to Table 4.3. (a) the experimental setup consists of the proposedPFC board, control board, loads, and AC power source. (b) Close-up view of the pro-posed PFC board. The size of the boost inductor has been significantly reduced by theapplication of multi-level voltage.equivalent switching frequency of the proposed PFC, the switching frequency for the totem polePFC is increased to 300kHz instead of the cell switching frequency (100kHz). Fig. 4.10 (a) showsthe measured results of the totem pole PFC input voltage us, switching node voltage usw, and boostinductor current iLs. Fig. 4.10 (b) provides a zoomed-in view of the totem pole converter currentripple. It can be observed that the current has maximum ripple (12.7A) when the input voltage (us)reaches its peak. Despite the switching frequency being increased to match that of the proposedPFC, the current ripple is still approximately six times higher than the ripple of the proposed PFC(2.1A shown in Fig. 4.9 (b)). This is because of the six times higher ∆usw for the totem pole PFC.Fig. 4.10 and Fig. 4.9 demonstrate the benefits of the proposed PFC in reducing current ripple andenhancing overall performance.139usiLsuswZoom in(a)(b)60HziLsS1bS2bS3bφ=120°φφφfs=100kHzfiLs=300kHzΔusw=33VΔiLs=2.1A➊➋➋Figure 4.9: The experimental captures of the proposed PFC. (a) Boost inductor current iLsand switching node multi-level voltage usw are following the sinusoidal grid voltage us.(b) Zoomed in view of iLs showing low current ripple (300kHz, 2.1A) at 0.5 duty ratio.This is because the reduced volt-second is applied to the boost inductor from usw. Dueto the multi cell feature of the proposed PFC topology: ¶ usw voltage step is reduced toUdc/2n (33V); · iLs ripple frequency (300kHz) is n times faster than cell gate drivingsignals (S1b, S2b and S3b, 100kHz, 120◦ phase shifted).Considering cells in either the upper arm or the lower arm have similar voltage ripples, Cell(1)(from upper arm) and Cell(6) (from lower arm) are used as an example here to show the cell outputDC voltage ripple in the positive (us > 0) and negative grid (us ≤ 0) cycles. The experimentalcapture is shown in Fig. 4.11. Upper arm cells and lower arm cells are charged by iLs alternatelyat 60Hz. When us ≤ 0, cells in the upper arm are charged, while lower arm cells are held bythe DC link capacitors. The voltage ripple in the full grid cycle is 7V . Driving signal S1a changesbetween high and low to control the duty ratio of Cell(1), while S6a is always high to avoid potentialovershoot during the us zero crossing. Therefore, the iLs follows the sinusoidal us. Similarly, whenus > 0, Cell(6) in the lower arm is charged, and Cell(1) is held up by capacitors. S6a outputs PWMwaveforms, while S1a is always high.140(a)(b)usiLsiLsuswZoom in60HzfiLs=300kHzΔusw=200VTotem-pole PFC as comparisonTotem-pole PFC as comparisonΔiLs=12.7A➊➋Figure 4.10: Experimental results of the conventional totem pole PFC with the same induc-tance as the proposed PFC. (a) The measured results of the converter input voltage us,switching node voltage usw, and the boost inductor current iLs. (b) Zoomed-in viewof the totem pole converter current ripple. The current has maximum ripple when usreaches its peak. Although the switching frequency is increased to the same as the pro-posed PFC equivalent switching frequency (300kHz)·, the maximum current ripple isstill as high as 12.7A, which is around 6 times higher than the ripple of the proposedPFC shown in Fig. 4.9 (b). This is a consequence of the 6 times higher ∆usw for thetotem pole PFC ¶.S1aS6aU6us>0us≤0U1 ΔU1=7VΔU6=7V60HzFigure 4.11: The experimental capture showing the output DC voltage ripple of Cell(1) andCell(6) in the positive (us > 0) and negative grid (us ≤ 0) cycles. Gate driving sig-nals are showing upper arm cells (Cell(1) to Cell(3)) and lower arm cells (Cell(4)to Cell(6)) are charged by iLs alternately. The cell voltage ripple during the full gridcycle is 7V.141To demonstrate the ability of the DC output ports to equally distribute power despite mis-matched system parameters, an experiment was conducted as shown in Fig. 4.12. During theexperiment, the output current and voltage of Cells (1), Cells (2), Cells (5), and Cells (6) weremeasured. Cells (1) had a +20% mismatch in output capacitance and Cells (2) had the designedcapacitance to serve as a comparison with Cells (1) in the upper arm. Similarly, Cells (5) had a-20% mismatch in output capacitance while Cells (6) had the designed capacitance to work as areference to Cells (5) in the lower arm. As shown in Fig. 4.12, although there were some differ-ences in the voltages and currents ripples of the cells, the proposed multi-level multi-ports PFCremained stable. The average current and voltage values were used to calculate the power for eachcell, which resulted in 81.5W , 80.5W , 81W , and 81.3W respectively. These results indicate that thepower was evenly distributed among the cells despite the mismatched system parameters.U1Cell(1) caps with +20% mismatchCell(5) caps with -20% mismatchI1U2I2U5I5U6I6Figure 4.12: Experimental results demonstrate the ability of multiple DC output ports to dis-tribute output power evenly, despite ±20% mismatches in output capacitance parame-ters of Cells(1) and Cells(5). The results show stable and evenly distributed poweramong Cells(1), Cells(2), Cells(5), and Cells(6) with calculated values of 81.5W,80.5W, 81W, and 81.3W respectively, despite differences in voltage and current rippleamplitudes.To demonstrate the dynamic performance of the proposed PFC, the input voltage step-down andstep-up experiments are conducted to emulate the grid voltage variations, and the correspondingresults are presented in Fig. 4.13 and Fig. 4.14, respectively. In the step-down experiment ofFig. 4.13, the input voltage (us) was reduced by 20%, and the cell voltages (U1 to U6) returnedto the set reference value of 33V after a brief reduction. It is worth noting that the references ofthe six cells were intentionally staggered in the Fig. 4.13(b) and Fig. 4.13(c) to clearly show theirrespective voltages. The voltages of U1 to U6 were stabilized at the set values before and after the142(a)(b)(c)usZoom in to subfig. (b) us step-down 20%U1,U2, U3U4,U5, U6iLsusU1,U2, U3U4,U5, U6iLsPower Factor=0.993Power Factor=0.996usU1,U2, U3U4,U5, U6iLsZoom in to subfig. (c) Figure 4.13: Experimental results of proposed PFC converter for 20% input voltage (us) step-down. (a) overall waveforms demonstrating steady operation before and after the step-down transition. (b) zoomed-in view before the input voltage step-down, with a powerfactor of 0.993. (c) zoomed-in view after the input voltage step-down, with a powerfactor of 0.996.step-down experiment, and the control of the proposed PFC ensured voltage equalization for eachcell. Moreover, the power factors are as high as 0.993 and 0.996 in Fig. 4.13(b) and Fig. 4.13(c),respectively, demonstrating that the proposed PFC effectively ensures power quality.Fig. 4.14 presents the step-up experimental results of the proposed PFC topology, indicatingthat the voltages of Cell(1) to Cell(6) returned to the set target value after a brief increase, and thevoltages were uniformly distributed across the cells. The power factors were as high as 0.996 and0.993 in Fig. 4.14(b) and Fig. 4.14(c), respectively. Overall, the results showed stable voltages andhigh power factor, demonstrating the proposed PFC’s ability to ensure power quality and uniformvoltage distribution in dynamic performance.143(a)(b)(c)usZoom in to subfig. (b) us step-up 20%U1,U2, U3U4,U5, U6iLsusU1,U2, U3U4,U5, U6iLsPower Factor=0.996Power Factor=0.993usU1,U2, U3U4,U5, U6iLsZoom in to subfig. (c) Figure 4.14: Experimental results of proposed PFC converter for 20% input voltage (us) step-up. (a) overall waveforms demonstrating steady operation before and after the step-uptransition. (b) zoomed-in view before the input voltage step-up, with a power factorof 0.996. (c) zoomed-in view after the input voltage step-up, with a power factor of0.993.The measured and estimated conversion efficiency for the proposed half-bridge based multi-level multi-port PFC is shown in Fig. 4.15. Interpolation in this figure refers to the process ofcreating a smooth and continuous representation of discrete efficiency data points, enabling accu-rate estimation or prediction of values between the known efficiency data points. The loss esti-mation relies on equations presented in Section 4.2 and simulations. The measured efficiency ofthe converter is around 96.5% at 250W . It increases with the rising of output power level. It goesup to 97.5% @350W. Finally, it reaches the highest measured efficiency of 98.3% at 500W . Thebreakdown of power loss analysis for the proposed PFC topology at 500W based on experimen-tal results is presented in Fig. 4.16. Four main factors contribute to the total loss in the system.144The MOSFETs switching and conduction losses account for the largest portion of the total lossat 47.67%. The DC-link capacitors contribute to 29.94% of the total loss. The boost inductanceand other factors account for 8.28% and 19.11% of the total loss, respectively. The figure providesimportant information on the sources of power loss in the proposed PFC topology and can be usefulin optimizing the design for higher efficiency.Power (W)250 300 350 400 450 500MeasurementEstimationInterpolationEfficiency (%)96.096.597.097.598.598.099.0Figure 4.15: Measured and estimated efficiency of the proposed half-bridge based multi-levelmulti-port PFC. The estimation of losses is based on equations presented in this paperand simulations.MOSFETs Loss(42.67%)BoostInductance Loss (8.28%)DC-link Capacitors Loss (29.94%)Other(19.11%)Figure 4.16: The figure shows the power loss breakdown of the proposed PFC topology basedon experimental results at 500W. MOSFETs switching and conduction losses accountfor 47.67% of the total loss, while the DC-link capacitors contribute to 29.94% of thetotal loss. The boost inductance and other factors account for 8.28% and 19.11% ofthe total loss, respectively.To sum up, the experimental results prove the stable operation of the proposed PFC under145various conditions, while achieving high-efficiency power conversion, multi-DC output ports, andlow current ripples.4.5 SummaryIn this chapter, a cascaded half-bridge based bidirectional multi-level multi-port bridgeless PFC hasbeen proposed. Compared with cascaded full-bridge PFC, the number of power switches per cellis reduced by half while providing the same DC output ports, since the power cells are composedof half bridges. Due to the multi-level voltage, the volt-second on the boost inductor drops, therebyreducing the current ripple compared to the conventional totem pole PFC with the same inductance.Moreover, as the DC link voltage Udc is handled by 2n cells, the switching loss and conduction losscan also benefit from the use of lower voltage rating power switches. Finally, a prototype wasbuilt in the lab, and all the advantages of the proposed PFC topology were verified by experimentalresults.146Chapter 5Conclusion5.1 Conclusions and ContributionsThis thesis researched bidirectional battery chargers for e-mobility in terms of topologies, model-ing, and design. By choosing appropriate combinations of the proposed method/topology, bidirec-tional chargers could bidirectionally accommodate both high and low-battery voltage EVs to therenewable power grid.The work includes an asymmetric design method for CLLC resonant tanks in the DC/DC stageof battery chargers (Chapter 2); a unified bidirectional resonant frequency tracking method for theunregulated CLLC DC/DC converter stage of battery chargers (Chapter 3); a cascaded half-bridgebased multi-level multi-port bridgeless PFC rectifier on the AC/DC stage of chargers (Chapter 4).5.1.1 Bidirectional Resonant CLLC Converter for Wide Battery VoltageRange: Asymmetric Parameters MethodologyThe Asymmetric Parameters Methodology (APM) was proposed in Chapter 2, which enables thebidirectional resonant CLLC Converter to operate over a wide range of battery voltage variations.This design method can be used in both high battery voltage EVs and low battery voltage EVs.The APM uses statistical Design of Experiments (DoE) to develop accurate maximum andminimum bidirectional switching frequency models for the multivariable system of CLLC reso-nant tank with minimal measurement data. The proposed APM allows for additional freedom in147designing the CLLC tank parameters, which can be used to create separate gain curves for chargingand discharging. This results in narrower switching frequency ranges for both charging/discharg-ing modes and more uniform between bidirectional operations, improving the chargers over a widerange of battery voltages and benefiting the design of transformers in the CLLC converter. Theeffectiveness of the proposed APM design was demonstrated through comparison experiments ona prototype CLLC bidirectional charger.5.1.2 Unified Bidirectional Resonant Frequency Tracking for CLLCConvertersChapter 3 develops a unified bidirectional resonant frequencies tracking algorithm for unregu-lated bidirectional CLLC resonant DC/DC converters to improve efficiency when the switchingfrequency drifts due to parameter deviations. It unifies bidirectional resonance tracking to track theBidirectional Resonant Frequency (BRF) in both high and low battery voltage applications.The BRF is developed based on the generalized resonant frequency equations, which are validfor any combination of CLLC resonant tank elements, whether with or without parameter devia-tions. It was found that both the forward and backward modes of the converter achieve maximumefficiency at the BRF. By analyzing the phase shift of two port voltages of the CLLC resonant tank,it was discovered that Vab and Vcd are in phase at the BRF for bidirectional operations regardless ofparameter deviations. As a result, the bidirectional tracking was further unified into continuouslytuning the switching frequency to maintain Vab and Vcd in phase. This unified BRF tracking algo-rithm provides a simple, accurate, and low-cost solution for maintaining resonance in unregulatedCLLC converters. The challenges and solutions involved in implementing the proposed algorithmin engineering applications were also discussed. Finally, the effectiveness of the proposed algo-rithm was verified through experiments, which demonstrated improved efficiency for unregulatedCLLC converters.1485.1.3 Cascaded Half-bridge Based Bidirectional Multi-level Bridgeless PFCwith Multi Output PortsA cascaded half-bridge based bidirectional multi-level multi-port bridgeless PFC rectifier is pro-posed in Chapter 4 to address the high transformer ratio problems encountered in the CLLC DC/DCstage. As a result, this rectifier is particularly suitable for low voltage battery applications.This PFC topology has several benefits compared to cascaded full-bridge PFC, including a re-duction in the number of power switches per cell by half while maintaining the same number ofDC output ports, and a reduction in volt-seconds on the boost inductor leading to lower currentripple compared to conventional totem pole PFC with the same inductance. The proposed PFCtopology also reduces both switching loss and conduction loss, as the DC link voltage is dividedamong 2n cells and lower voltage rating power switches are used. The operation principles and asteady state model of the proposed PFC were analyzed in detail, and the proposed PFC was com-pared with conventional PFC topologies in terms of output ports, MOSFETs numbers, multi-levelvoltage levels, effective switching frequencies, switching loss, and current ripples. The impact ofparameter mismatch was also analyzed, and a control strategy for the proposed PFC was presented.A prototype was built in the lab and the advantages of this PFC topology were verified throughexperimental results.5.2 Specific Academic ContributionsThe following publications proposed the Asymmetric Parameters Methodology (APM) for theDC/DC stage of chargers for both high and low-battery voltage EVs to bidirectionally connectto the renewable power grid. These works introduce the concept of APM for bidirectional CLLCresonant tank design, enabling the charging and discharging gain curves design separately for widebattery voltage range operations.• J. Min and M. Ordonez, ”Bidirectional Resonant CLLC Charger for Wide Battery VoltageRange: Asymmetric Parameters Methodology,” in IEEE Transactions on Power Electronics,vol. 36, no. 6, pp. 6662-6673, June 2021.• J. Min and M. Ordonez, ”Asymmetric Parameters Design for Bidirectional Resonant CLLC149Battery Charger,” 2020 IEEE Energy Conversion Congress and Exposition (ECCE), 2020,pp. 5375-5379.The following publications proposed the bidirectional resonant frequencies tracking algorithmfor unregulated bidirectional CLLC resonant DC/DC converters in order to improve efficiencywhen the switching frequency drifts due to variations in resonant tank parameters.• J. Min and M. Ordonez, “Unified bidirectional resonant frequency tracking for CLLC con-verters,” IEEE Transactions on Power Electronics, vol. 37, no. 5, pp. 5637-5649, 2022.• J. Min and M. Ordonez, ”Bidirectional resonant frequency tracking for CLLC convertersbased on voltage falling edges,” in 2021 IEEE Energy Conversion Congress and Exposition(ECCE), 2021, pp. 1793-1797.Cascaded half-bridge based bidirectional multi-level bridgeless PFC was introduced in the fol-lowing publications. These publications solved the problem of high transformer ratio in the DC/DCstage of battery chargers by proposing a novel cascaded PFC topology on the AC/DC stage.• J. Min and M. Ordonez, ”Cascaded Half-bridge Multi-Level Multi-Outputs Bridgeless PFC,”2023 IEEE Applied Power Electronics Conference and Exposition (APEC), Orlando, FL,USA, 2023, pp. 2027-2031.• J. Min and M. Ordonez, ”Cascaded Half-bridge Based Bidirectional Multi-level BridgelessPFC with Multi Output Ports,” submitted to IEEE Transactions on Power Electronics.5.3 Future WorkThis work opens up many full areas of research that can build upon its findings. Some of the mainareas in which multiple Master’s and Ph.D. students could be supervised include:• Optimal Overall Efficiency of Bidirectional Chargers: one potential area for future researchcould be to more thoroughly examine the optimal overall efficiency of a bidirectional chargerwhen both DC/DC and DC/AC stages are used for voltage regulation. This could involveconducting a detailed analysis of the losses and efficiency of the two-stage converters under150diverse battery voltages and power levels, and using the results to determine the optimaldistribution of voltage regulation between the two stages for a specific battery voltage. Thiswork could involve both theoretical modeling and experimental testing to validate the resultsand ensure their accuracy. By studying the impact of different input voltage and power levelson the efficiency of the charger, it may be possible to identify opportunities for improvingthe overall performance of EV chargers. This could include the development of new controlstrategies that can more effectively accommodate diverse battery voltages. The findings ofthis research could be used to inform the design of more efficient bidirectional chargers inthe future and could be valuable for optimizing the performance of these chargers in a varietyof EV applications.• Bidirectional Chargers for Wide AC Voltage range: one more possible direction for futurework on the bidirectional charger could involve improving the compatibility of these chargerswith a wider range of AC voltage levels. As this thesis has researched bidirectional chargersthat can accommodate diverse battery voltages, the AC voltage levels used in renewableenergy power lines can also vary significantly depending on geographic locations, which canpose challenges for the design of bidirectional chargers. By developing a charger that iscapable of working with a wider range of AC voltages, it would be possible to expand theuse of bidirectional charger technology to more regions around the world, which could helpto reduce the cost of design and manufacturing.• Multiphase Operation of Bidirectional CLLC Resonant Converters: For high-power bidi-rectional DC/DC converter applications, such as fast charging and energy storage systems,module paralleling is a useful expansion solution. However, the current sharing and stabil-ity analysis of parallel converters are challenging problems in these systems, especially formultiphase bidirectional CLLC resonant converters with complex models. While there arepublished papers on current sharing in the literature, few of them address multiphase bidi-rectional CLLC resonant converters. While these topologies can be extended to multiphasesystems, they require additional sensors and switches, which increase the cost and complex-ity of the charger. Therefore, researching simpler current sharing methods for multiphase151bidirectional CLLC resonant converters is an important area of research. Additionally, whilemany papers have studied the parallel operation of phase-shifted type bidirectional convert-ers, the current sharing stability analysis of multiphase resonant bidirectional converters israrely discussed in the existing literature, which is also an area worthy of further study.152Bibliography[1] J. Min and M. Ordonez, “Bidirectional resonant cllc charger for wide battery voltage range:Asymmetric parameters methodology,” IEEE Transactions on Power Electronics, vol. 36,no. 6, pp. 6662–6673, 2021. → pages vi, 15, 22, 30[2] J. Min and M. Ordonez, “Asymmetric parameters design for bidirectional resonant cllcbattery charger,” in 2020 IEEE Energy Conversion Congress and Exposition (ECCE), 2020,pp. 5375–5379. → pages vi, 15, 22, 30[3] J. Min and M. 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Thesis/Dissertation
eng
Electrical and Computer Engineering
Vancouver : University of British Columbia Library
Attribution-NonCommercial-NoDerivatives 4.0 International
Graduate
Ordonez, Martin
Bidirectional resonant chargers for e-mobility
Text