Applied Science, Faculty of
Engineering, School of (Okanagan)
DSpace
UBCO
Bieber, Levi Michael
Doctor of Philosophy - PhD
University of British Columbia
Today’s state-of-the-art voltage-source-converter high-voltage direct-current (VSC-HVDC) technology uses modular-multilevel converters (MMCs) for their highly efficient AC/DC conversion and filterless operation. However, half-bridge submodule-based (HBSM) MMCs lack inherent DC-fault protection and require significantly more capacitive energy storage than the previous generation of converters, leading to converter stations of immense size and cost. This dissertation proposes six novel VSC-HVDC-based technologies that amend the MMC’s disadvantages. Firstly, this dissertation presents three converter technologies: the Hybrid Three-Level Converter (H3LC), the Thyristor-based Hybrid Three-Level Converter (TH3LC), and the Hybrid Five-Level Converter (H5LC), which use AC-side cascaded submodules (SMs) and share a similar operating principle. Secondly, three converters that use DC-side cascaded SMs are proposed, including the Dual-Arm Converter (DAC), the Quad-Arm Converter (QAC), and the Multiplexed-Stack Converter (MSC), which require fewer SMs than the MMC by using proposed multiplexed converter arms (M-Arms). All the proposed converters have DC-fault protection enabled inherently --- for the TH3LC, DAC, QAC, and MSC --- or by novel DC-fault-blocking mechanisms in the cases of the H3LC and H5LC. Results from HVDC-scale simulation studies are presented for all converters to demonstrate their proposed operating principles as well as to determine their expected semiconductor losses; meanwhile, lab-scale hardware verifications are presented for three converters. Analytical methods are proposed to programmatically calculate the converters' theoretical energy storage requirements and semiconductor losses. The proposed converters all have reduced energy storage requirements compared to the MMC, with the H3LC requiring approximately one-tenth of the MMC's energy storage. The TH3LC displays the highest efficiency of the proposed converters and has inherent DC-fault tolerance. The H5LC is demonstrated to have higher efficiency than the HBSM-MMC and the least number of SMs. The DAC uses only two M-Arms for AC/DC conversion and is inherently DC-fault tolerant. The QAC uses four SM-based stacks without DC-side capacitors. The MSC uses four SM-based stacks without DC-side capacitors and has DC-fault ride-through capability. The high efficiency and compactness of these converters are expected to facilitate their widespread acceptance throughout the industrial and academic communities.
DC-Fault Tolerant Multilevel Voltage Source Converterswith Hybrid and Multiplexed-Arm Structures for HighVoltage Direct Current ApplicationsbyLevi Michael BieberB.A.Sc. HONS., The University of British Columbia, 2018A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THEREQUIREMENTS FOR THE DEGREE OFDOCTOR OF PHILOSOPHYinTHE COLLEGE OF GRADUATE STUDIES(Electrical Engineering)The University of British Columbia(Okanagan)February 2023© Levi Michael Bieber, 2023The following individuals certify that they have read, and recommend to the College ofGraduateStudies for acceptance, a dissertation entitled:DC-Fault Tolerant Multilevel Voltage Source Converters with Hybrid andMultiplexed-Arm Structures forHighVoltage Direct CurrentApplicationssubmitted by Levi Michael Bieber in partial fulfillment of the requirements for the degree ofDoctor of Philosophy in Electrical Engineering.Examining Committee:Dr. Liwei Wang, School of EngineeringSupervisorDr. Juri Jatskevich, The University of British Columbia—VancouverCo-supervisorDr. Wilson Eberle, School of EngineeringSupervisory Committee MemberDr. Christine Chen, The University of British Columbia—VancouverSupervisory Committee MemberDr. Peter Lehn, The University of TorontoAdditional ExaminerAdditional Supervisory Committee Members:Dr. Mohammad Arjmand, School of EngineeringUniversity ExamineriiAbstractToday’s state-of-the-art voltage-source-converter high-voltage direct-current (VSC-HVDC)technology uses modular-multilevel converters (MMCs) for their highly efficient AC/DCconversion and filterless operation. However, half-bridge submodule-based (HBSM) MMCslack inherent DC-fault protection and require significantly more capacitive energy storage thanthe previous generation of converters, leading to converter stations of immense size and cost.This dissertation proposes six novel VSC-HVDC-based technologies that amend theMMC’sdisadvantages. Firstly, this dissertation presents three converter technologies: the HybridThree-Level Converter (H3LC), theThyristor-based HybridThree-Level Converter (TH3LC),and the Hybrid Five-Level Converter (H5LC), which use AC-side cascaded submodules (SMs)and share a similar operating principle. Secondly, three converters that use DC-side cascadedSMs are proposed, including the Dual-Arm Converter (DAC), the Quad-Arm Converter(QAC), and the Multiplexed-Stack Converter (MSC), which require fewer SMs than the MMCby using proposed multiplexed converter arms (M-Arms). All the proposed converters haveDC-fault protection enabled inherently — for the TH3LC, DAC, QAC, andMSC— or by novelDC-fault-blocking mechanisms in the cases of the H3LC and H5LC.Results fromHVDC-scale simulation studies are presented for all converters to demonstratetheir proposed operating principles as well as to determine their expected semiconductor losses;meanwhile, lab-scale hardware verifications are presented for three converters. Analyticalmethods are proposed to programmatically calculate the converters’ theoretical energy storagerequirements and semiconductor losses.The proposed converters all have reduced energy storage requirements compared to theMMC, with the H3LC requiring approximately one-tenth of the MMC’s energy storage. TheTH3LC displays the highest efficiency of the proposed converters and has inherent DC-faulttolerance. The H5LC is demonstrated to have higher efficiency than the HBSM-MMC and theleast number of SMs. The DAC uses only twoM-Arms for AC/DC conversion and is inherentlyiiiDC-fault tolerant. The QAC uses four SM-based stacks without DC-side capacitors. TheMSC uses four SM-based stacks without DC-side capacitors and has DC-fault ride-throughcapability. The high efficiency and compactness of these converters are expected to facilitatetheir widespread acceptance throughout the industrial and academic communities.ivLay SummaryWith the increasing number of renewable energy projects (REPs), e.g., offshore windfarms, there is a growing need for high-voltage AC/DC converter stations of smaller sizes andhigher efficiencies. The modular-multilevel converter (MMC) is the ubiquitous technologyfor such stations due to its high efficiency and filterless AC voltage generation. However, thehundreds-to-thousands of semiconductor-based submodules composing the MMC requiresignificantly more capacitive energy storage than the previous generation of converters, whichcontributes to an immense size.This dissertation proposes six AC/DC converters that are demonstrated to have improvedor comparable efficiency to the MMC, AC-/DC-network fault protection, and small expectedsizes due to their significantly reduced capacitive energy storage requirements. These benefitsare expected to reduce the overall costs of prospective REPs, thereby improving their economicfeasibility. HVDC-scale simulations, theoretical analyses, and lab-scale hardware verificationsare presented to provide confidence in the converters’ modes of operation and claimed benefits.vPrefaceThe research presented throughout this dissertation has either been published, is submittedto various IEEE Transactions journals but not yet accepted, or is in the final stages of the draftingprocess. For these research papers, I derived the mathematical expressions and operatingprinciples of the proposed converters, designed and implemented the detailed and real-timesimulations, and produced drafts of each of the papers upon which this dissertation is based.These research outputs have been under the close supervision of Dr. Liwei Wang and, morerecently, the co-supervision of Dr. Juri Jatskevich. Both Drs. Wang and Jatskevich providedinvaluable feedback on the papers they helped to co-author. Other co-authors include:→ Wei Li, fromOPAL-RTTechnologies®, who provided valuable simulation andmodelingadvice;→ My colleague and friend Jintao Han, who provided valuable insight regarding theaccelerated simulation of the proposed converters;→ Joel Pfannschmidt, my previous colleague and friend, who helped immensely with thehardware implementations of the converters;→ Alireza Nami, from Hitachi-ABB Power Grids, who has extensive knowledge in thefield of VSC-HVDC.viThis doctoral dissertation is a direct result of the following accepted, submitted, or to-be-submitted journal and conference papers:On the basis of Chapter 2:⇒ L. Bieber, J. Pfannschmidt, L. Wang, A. Nami and W. Li, “A Hybrid Three-Level andModular Multilevel Converter With DC Fault Blocking Capability and Reduced Semi-conductor Losses,” in IEEE Transactions on Power Delivery, vol. 35, no. 4, pp. 1895-1908,2020.On the basis of Chapter 3:⇒ L.Bieber, L.Wang andW. Li, “ALow-LossThyristor-BasedHybridThree-Level andMod-ular Multilevel Converter With DC Fault Blocking Capability for HVDC Transmission,”in IEEE Open Access Journal of Power and Energy, vol. 7, pp. 111-121, 2020.⇒ L. Bieber and L.Wang, “AnActive-Forced-CommutatedThyristor-BasedMultilevel Con-verter for HVDC Transmission,” 2019 IEEE 10th Annual Information Technology, Elec-tronics and Mobile Communication Conference (IEMCON), Vancouver, B.C., Canada,2019, pp. 0447-0453. (Best Paper Award)On the basis of Chapter 4:⇒ L. M. Bieber, J. A. Pfannschmidt, L. Wang, J. Jatskevich and W. Li, “A Hybrid Five-Level Modular Multilevel Converter With High Efficiency and Small Energy StorageRequirements for HVDC Transmission,” in IEEE Transactions on Industrial Electronics,vol. 70, no. 2, pp. 1597-1608, Feb. 2023.On the basis of Chapter 5:⇒ L. Bieber, L. Wang, and J. Jatskevich, “A Dual-Arm Modular Multilevel Converter witha Compact Footprint for VSC-HVDC Applications,” submitted to IEEE Transactionson Power Delivery on Oct. 16, 2022 and under second round of revision. Paper ID:TPWRD-01539-2022.On the basis of Chapter 6:⇒ L. Bieber, L. Wang, J. Jatskevich andW. Li, “A DC-Fault Tolerant Quad-Arm Converterwith High Efficiency, Compactness, and Reliability for VSC-HVDC Applications,” to besubmitted to IEEE Transactions on Power Delivery.On the basis of Chapter 7:vii⇒ L. Bieber, L. Wang, and J. Jatskevich, “A DC-Fault Tolerant Multiplexed-Arm Converterwithout DC-side Pole Capacitors,” to be submitted to IEEE Transactions on IndustrialElectronics.On the basis of Chapter A:⇒ L. Bieber, L. Wang, J. Jatskevich and W. Li, “AQuantitative Analysis of Energy StorageRequirements for the Hybrid Cascaded Multilevel Converters,” 2020 IEEE 21st Controland Modeling for Power Electronics Conference (COMPEL), Aalborg, Denmark, 2020.On the basis of Chapter B:⇒ L. Bieber, L. Wang, J. Jatskevich andW. Li, “Analytical Semiconductor Conduction andSwitching Loss Calculation Method for Hybrid Cascaded Multilevel Converters,” to besubmitted to IEEE Transactions on Power Delivery after final revision.⇒ L. Bieber, L.Wang, J. Jatskevich,W. Li, “Analytical Conduction Loss Calculation Methodfor Hybrid Three-Level Converters,” 2021 IEEE Electrical Power and Energy Conference(EPEC), Toronto, ON, Canada, 2021, pp. 44-49.viiiTable of ContentsAbstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiiLay Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vPreface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viTable of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ixList of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviList of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviiiList of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxiiiAcknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvDedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvi1 Introduction and Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 History of High Voltage Direct Current Power Transmission . . . . . . . . 41.1.1 Early History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.1.2 Line-Commutated Converter HVDC Technology . . . . . . . . . . . 51.1.3 Voltage-Source-Converter HVDC Technology . . . . . . . . . . . . 81.1.4 The Modular Multilevel Converter . . . . . . . . . . . . . . . . . . . 101.2 Status of Multilevel Voltage Source Converter Research . . . . . . . . . . . 151.2.1 Alternate Arm Converter . . . . . . . . . . . . . . . . . . . . . . . . 171.2.2 Hybrid Two-Level Converter . . . . . . . . . . . . . . . . . . . . . . 191.3 Motivation, Research Objectives, and Overview of Work Accomplished . . 212 Hybrid Three-Level and Modular Multilevel Converter . . . . . . . . . . . 252.1 Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.2 Operating Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282.2.1 DS Square Wave Modulation and Third-Order Harmonic Injectionto AC-side Cascaded FBSMs. . . . . . . . . . . . . . . . . . . . . . . 30ix2.2.2 Limits of Third-Order Harmonic Voltage Injection . . . . . . . . . . 312.2.3 DC-Side Pole Capacitor Voltage Balancing . . . . . . . . . . . . . . 332.2.4 AC-Side Cascaded FBSM Energy Balancing and FBSM CapacitorVoltage Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342.2.5 DC Fault Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 352.3 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382.3.1 Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382.3.2 DC-Side Fault Operation . . . . . . . . . . . . . . . . . . . . . . . . 402.3.3 Hardware Verification . . . . . . . . . . . . . . . . . . . . . . . . . . 432.4 Component, Loss, and Energy Analysis . . . . . . . . . . . . . . . . . . . . 472.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 Thyristor-Based Hybrid Three-Level and Modular Multilevel Converter . 503.1 Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513.2 Operating Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533.2.1 Thyristor Turn-OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . 533.2.1.1 Natural Commutation Event . . . . . . . . . . . . . . . . . 563.2.2 Sinusoidal Voltage Generation . . . . . . . . . . . . . . . . . . . . . 563.2.3 Optimal Third-Order Harmonic Injection . . . . . . . . . . . . . . . 583.2.4 AC-side Cascaded FBSMs Modulation and Energy Balancing . . . . 603.2.5 Commutation Cascaded FBSMs Energy Balancing and DC-sidePole Capacitor Energy Balancing . . . . . . . . . . . . . . . . . . . 613.2.6 DC-side Pole-to-Pole Fault Blocking Capability . . . . . . . . . . . . 633.3 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643.3.1 Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653.3.2 DC-side Fault and STATCOM Mode . . . . . . . . . . . . . . . . . . 683.4 Component, Loss, and Energy Analysis . . . . . . . . . . . . . . . . . . . . 703.4.1 Semiconductor Losses . . . . . . . . . . . . . . . . . . . . . . . . . . 703.4.2 Energy Storage Comparison . . . . . . . . . . . . . . . . . . . . . . 714 Hybrid Five-Level Modular Multilevel Converter . . . . . . . . . . . . . . 744.1 Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754.2 Operating Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77x4.2.1 DS Control and FBSM Modulation . . . . . . . . . . . . . . . . . . . 794.2.2 Flying Capacitor Voltage Balancing . . . . . . . . . . . . . . . . . . 814.2.3 DC-side Pole Capacitor Balancing . . . . . . . . . . . . . . . . . . . 824.2.4 Cascaded FBSM Total Energy Balancing and FBSM Capacitor Volt-age Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834.2.5 FBSM IGBT Switching Frequency . . . . . . . . . . . . . . . . . . . 844.2.6 DC-Fault Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 884.2.7 Post-Fault Capacitor Charge Restoration . . . . . . . . . . . . . . . 894.3 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904.3.1 Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904.3.2 DC-Side Fault Operation . . . . . . . . . . . . . . . . . . . . . . . . 914.3.3 AC-side Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944.3.4 Hardware Verification . . . . . . . . . . . . . . . . . . . . . . . . . . 954.4 Converter Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014.4.1 Converter Rating Analysis . . . . . . . . . . . . . . . . . . . . . . . 1014.4.2 Energy Storage Comparison . . . . . . . . . . . . . . . . . . . . . . 1044.4.3 Semiconductor Losses . . . . . . . . . . . . . . . . . . . . . . . . . . 1084.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105 Dual-Arm Modular Multilevel Converter . . . . . . . . . . . . . . . . . . . 1115.1 Multiplexed Converter Arm . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115.2 Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165.3 Operating Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175.3.1 AC Output Voltage and Current Definition . . . . . . . . . . . . . . 1225.3.2 Naturally Balanced Operating Point . . . . . . . . . . . . . . . . . . 1255.3.3 Hybrid Director Switches . . . . . . . . . . . . . . . . . . . . . . . . 1265.3.4 Stack and Pole Capacitor Energy Balancing Strategy . . . . . . . . . 1285.3.4.1 Reactive Power Control to Maintain Optimal OperatingVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1285.3.4.2 Overlap Period . . . . . . . . . . . . . . . . . . . . . . . . 1295.4 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1325.4.1 Normal Operation — No Overlap . . . . . . . . . . . . . . . . . . . . 1335.4.2 Normal Operation — With Overlap . . . . . . . . . . . . . . . . . . 137xi5.4.3 DC-Fault Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 1385.4.4 Hardware Verification . . . . . . . . . . . . . . . . . . . . . . . . . . 1415.5 Converter Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456 Quad-Arm Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1466.1 Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1466.2 Operating Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1486.2.1 Generation of Output Voltage and Operation of Director Switches . 1486.2.2 Director Switch Switching Operation and Sizing . . . . . . . . . . . 1556.2.3 Arm Currents and Optimal Operating Point . . . . . . . . . . . . . 1586.2.4 Triplen Harmonic Voltage Injection . . . . . . . . . . . . . . . . . . 1606.2.5 DC-side Fault Ride-Through Capability . . . . . . . . . . . . . . . . 1626.3 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1646.3.1 Steady-State Normal Operation . . . . . . . . . . . . . . . . . . . . 1656.3.2 Converter Power Transfer . . . . . . . . . . . . . . . . . . . . . . . 1676.3.3 DC-Side Pole-to-Pole Fault . . . . . . . . . . . . . . . . . . . . . . . 1686.4 Converter Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1706.4.1 Converter General Capabilities and Semiconductor Requirements . 1716.4.2 Converter Semiconductor Losses . . . . . . . . . . . . . . . . . . . . 1716.4.3 Energy Storage Analysis . . . . . . . . . . . . . . . . . . . . . . . . 1736.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1747 Multiplexed-Stack Converter . . . . . . . . . . . . . . . . . . . . . . . . . . 1757.1 Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1757.2 Operating Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1767.2.1 Sinusoidal AC Line-to-Line Voltage Generation . . . . . . . . . . . 1777.2.2 Inner Stack Voltage Definitions . . . . . . . . . . . . . . . . . . . . 1807.2.3 Energy Balance and Outer Stack Voltage Definitions . . . . . . . . 1827.2.3.1 Midpoint Clamped with Optional FMS . . . . . . . . . . . 1827.2.3.1.1 Stack Energy Balancing — Option #1 . . . . . . 1847.2.3.1.2 Stack Energy Balancing — Option #2 . . . . . . 1877.2.3.2 Midpoint Floating . . . . . . . . . . . . . . . . . . . . . . 189xii7.2.4 Control and Balancing Current Synthesis . . . . . . . . . . . . . . . 1917.2.5 DC-Side Fault-Blocking and Ride-Through . . . . . . . . . . . . . . 1947.3 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1947.3.1 Normal Operation with Midpoint Clamped through FMS . . . . . . 1957.3.1.1 Operating Mode — Option #1 . . . . . . . . . . . . . . . . 1957.3.1.2 Operating Mode — Option #2 . . . . . . . . . . . . . . . . 1997.3.2 Normal Operation with Floating Midpoint . . . . . . . . . . . . . . 2047.3.3 DC-Fault Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 2047.3.4 Hardware Verification . . . . . . . . . . . . . . . . . . . . . . . . . . 2087.4 Converter Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2097.4.1 Converter General Comparison . . . . . . . . . . . . . . . . . . . . 2107.4.2 Semiconductor Losses . . . . . . . . . . . . . . . . . . . . . . . . . . 2127.4.3 Energy Storage Analysis . . . . . . . . . . . . . . . . . . . . . . . . 2137.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2168 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2188.1 High-Level Converter Comparison . . . . . . . . . . . . . . . . . . . . . . . 2188.1.1 Onshore HVDC Converter Stations . . . . . . . . . . . . . . . . . . 2188.1.2 Offshore HVDC Converter Stations . . . . . . . . . . . . . . . . . . 2208.1.3 Front-to-Front DC/DC Converter Applications . . . . . . . . . . . . 2228.1.4 STATCOM Applications . . . . . . . . . . . . . . . . . . . . . . . . 2228.2 Overview of Main Contributions . . . . . . . . . . . . . . . . . . . . . . . . 2228.2.1 Conclusions on the Hybrid Three-Level Converter . . . . . . . . . . 2238.2.2 Conclusions on the Thyristor-based Hybrid Three-Level Converter 2248.2.3 Conclusions on the Hybrid Five-Level Converter . . . . . . . . . . . 2268.2.4 Conclusions on the Dual-Arm Converter . . . . . . . . . . . . . . . 2278.2.5 Conclusions on theQuad-Arm Converter . . . . . . . . . . . . . . . 2288.2.6 Conclusions on the Multiplexed-Stack Converter . . . . . . . . . . . 2298.3 Potential Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2308.3.1 Further VSC-HVDC Converter Research . . . . . . . . . . . . . . . 2308.3.2 Accelerated CPU and CPU/FPGA Simulation Frameworks . . . . . . 2318.3.3 STATCOM Schemes and Renewable Energy Integration . . . . . . . 2318.3.4 VSC-HVDC Scale DC/DC Converters . . . . . . . . . . . . . . . . . 233xiiiBibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234Appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242Appendix A Energy Storage Requirements forHybrid CascadedMultilevelConverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243A.1 Nominal Energy Storage Calculation . . . . . . . . . . . . . . . . . . . . . . 243A.2 Capacitor Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245A.3 Energy Storage Sizing of the H3LC . . . . . . . . . . . . . . . . . . . . . . . 247A.3.1 DC-Side Pole Capacitor Energy Storage Sizing . . . . . . . . . . . . 247A.3.1.1 Calculation for 5% Pole-to-Pole Voltage Ripple . . . . . . 249A.3.1.2 Calculation for 5% Individual Pole Capacitor Voltage Ripple 250A.3.2 Cascaded FBSM Energy Storage Sizing . . . . . . . . . . . . . . . . 251A.3.3 Total Energy Storage Sizing . . . . . . . . . . . . . . . . . . . . . . . 253A.4 Energy Storage Sizing of the H2LC . . . . . . . . . . . . . . . . . . . . . . . 256A.4.1 DC-Side Pole Capacitor Energy Storage Sizing . . . . . . . . . . . . 257A.4.2 Cascaded FBSM Energy Storage Sizing . . . . . . . . . . . . . . . . 258A.4.3 Total Energy Storage Sizing . . . . . . . . . . . . . . . . . . . . . . . 258A.5 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259A.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262Appendix B Analytical Semiconductor Conduction and Switching Loss Cal-culation for H3LC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263B.1 Semiconductor Conduction Loss Calculation . . . . . . . . . . . . . . . . . 263B.1.1 Upper and Lower DS Semiconductor Conduction Losses . . . . . . 266B.1.2 Midpoint DS Semiconductor Conduction Losses . . . . . . . . . . . 272B.1.3 Cascaded FBSM Semiconductor Conduction Losses . . . . . . . . . 274B.2 Semiconductor Switching Loss Calculation . . . . . . . . . . . . . . . . . . 276B.2.1 Cascaded FBSM Semiconductor Switching Losses . . . . . . . . . . 277B.2.1.1 Discrete Switching Events . . . . . . . . . . . . . . . . . . 283B.2.2 DS Semiconductor Switching Losses . . . . . . . . . . . . . . . . . . 285B.3 Comparison to Detailed-Equivalent Model . . . . . . . . . . . . . . . . . . 286B.4 Application to the EO-AAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 288B.4.1 Cascaded FBSM Semiconductor Conduction Losses . . . . . . . . . 290xivB.4.2 DS Semiconductor Conduction Losses . . . . . . . . . . . . . . . . . 290B.4.3 Cascaded FBSM Semiconductor Switching Losses . . . . . . . . . . 291B.4.4 Comparison to Detailed-Equivalent Model . . . . . . . . . . . . . . 292B.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293xvList of TablesTable 2.1 Ratings of the DSs and the FBSM Switches . . . . . . . . . . . . . . . . . 27Table 2.2 Simulation Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Table 2.3 Comparison of Selected Converters . . . . . . . . . . . . . . . . . . . . . 48Table 3.1 Cascaded AC-side FBSMs’ Peak Voltages for Varying  . . . . . . . . . . 59Table 3.2 TH3LC Simulation Parameters . . . . . . . . . . . . . . . . . . . . . . . . 65Table 3.3 High-Level Comparison of Converters . . . . . . . . . . . . . . . . . . . 71Table 3.4 Semiconductor Losses of Selected Converters . . . . . . . . . . . . . . . 72Table 3.5 Normal Operation Energy Storage and Capacitor Sizing Results . . . . . 72Table 4.1 DS Switching States, DS Voltage Ratings, and Currents of the ProposedH5LC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Table 4.2 Switching States for FC Balance . . . . . . . . . . . . . . . . . . . . . . . 82Table 4.3 Simulation Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Table 4.4 Comparison of Selected Converters . . . . . . . . . . . . . . . . . . . . . 103Table 4.5 Normal Operation Energy Storage and Capacitor Sizing Results of Pro-posed Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104Table 4.6 FC and Pole Capacitor Energies versus DS Switching Frequency . . . . . 107Table 4.7 Submodule Energy Storage of H5LC Compared to Other Technologies . 108Table 5.1 DS Switching States and Topology Intervals for Varying ωt. . . . . . . . 119Table 5.2 Simulation Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133Table 5.3 Comparison of Selected Converters . . . . . . . . . . . . . . . . . . . . . 144Table 6.1 Director Switching States, Topology Intervals, and M-Arm Currents vs.the Converter Angle, ωt . . . . . . . . . . . . . . . . . . . . . . . . . . . 150Table 6.2 Simulation Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165Table 6.3 Comparison of Selected Converters . . . . . . . . . . . . . . . . . . . . . 172Table 7.1 DS Switching States and Topology Intervals for Varying ωt. . . . . . . . 177Table 7.2 Currents of the MSC for Varying ωt. . . . . . . . . . . . . . . . . . . . . 180Table 7.3 Stack Voltages of the MSC for Varying ωt. . . . . . . . . . . . . . . . . . 180Table 7.4 Simulation Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196xviTable 7.5 Comparison of Selected Converters . . . . . . . . . . . . . . . . . . . . . 211Table 7.6 Energy Storage for Varying Operating Voltages andDifferent OperatingModes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215Table A.1 H3LC’s Total Normalized Energy for 5% DC-Side Voltage Ripple . . . . . 255Table A.2 H3LC’s Total Normalized Energy for 5%DC-Side Pole Capacitor VoltageRipple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255Table A.3 H2LC’s Total Normalized Energy . . . . . . . . . . . . . . . . . . . . . . 262Table B.1 Director Switch Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . 265Table B.2 Summary of Equations to Find DSs’ Average and RMS Currents and toFind DSs’ and FBs’ Power Losses . . . . . . . . . . . . . . . . . . . . . . 283Table B.3 Semiconductor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 287xviiList of FiguresFigure 1.1 Planned and operating HVDC links in Europe. . . . . . . . . . . . . . . 2Figure 1.2 Yearly cumulative installed capacity of VSC HVDC. . . . . . . . . . . . 2Figure 1.3 Illustration of the upfront and lifetime costs of HVDC vs. HVAC powertransmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Figure 1.4 Example of a twelve-pulse LCC HVDC system and its constituent six-pulse LCC systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 1.5 A single-phase diagram of: (a) A two-level converter. (b) A three-levelconverter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Figure 1.6 The MMC topology with example waveforms. . . . . . . . . . . . . . . 11Figure 1.7 Examples of submodules. . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 1.8 HVDC converter station examples. . . . . . . . . . . . . . . . . . . . . . 15Figure 1.9 The alternate arm converter with full-bridge submodules. . . . . . . . . 18Figure 1.10 The hybrid two-Level converter. . . . . . . . . . . . . . . . . . . . . . . 20Figure 1.11 Key waveforms of the voltages generated and outputted by the H2LC’sDSs and submodules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Figure 2.1 The H3LC topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 2.2 Control flow diagram of the H3LC. . . . . . . . . . . . . . . . . . . . . . 29Figure 2.3 Example voltage waveforms of the H3LC . . . . . . . . . . . . . . . . . 30Figure 2.4 The H3LC’s protection branch topology. . . . . . . . . . . . . . . . . . . 36Figure 2.5 External AC/DC rectifier charging the FBSMs in the main breaker. . . . 38Figure 2.6 H3LC’s performance in normal operation. . . . . . . . . . . . . . . . . . 41Figure 2.6 H3LC’s performance to the DC-side pole-to-pole fault event. . . . . . . 44Figure 2.7 Experimental setup of the proposed H3LC. . . . . . . . . . . . . . . . . 45Figure 2.8 H3LC’s experimental results. . . . . . . . . . . . . . . . . . . . . . . . . 46Figure 3.1 The TH3LC topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Figure 3.2 Detailed and idealized voltage and current waveforms through theTH3LC DSs and CFB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Figure 3.3 Example voltage waveforms of the TH3LC at the operating voltageV1h = 0.62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57xviiiFigure 3.4 Optimal third-order harmonic results. . . . . . . . . . . . . . . . . . . . 59Figure 3.5 Analytical third-order harmonic calculation compared against optimalsweep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Figure 3.6 Simplified control scheme for the TH3LC. . . . . . . . . . . . . . . . . . 61Figure 3.7 TH3LC’s key waveforms during normal operation. . . . . . . . . . . . . 67Figure 3.8 TH3LC’s key waveforms during DC-side fault operations operations. . 69Figure 3.9 Nominal energy storage requirements of the TH3LC for varying . . . . 73Figure 4.1 Detailed circuit diagram of the proposed H5LC. . . . . . . . . . . . . . 76Figure 4.2 H5LC control flow diagram. . . . . . . . . . . . . . . . . . . . . . . . . 79Figure 4.3 FC voltage balancing diagram. . . . . . . . . . . . . . . . . . . . . . . . 83Figure 4.4 Average FBSM IGBT switching frequency for the operating voltagesV1h ∈ [0.475VDC, 0.62VDC]. . . . . . . . . . . . . . . . . . . . . . . . . . 88Figure 4.5 H5LC’s performance in normal operation. . . . . . . . . . . . . . . . . . 93Figure 4.5 H5LC’s performance during DC-side pole-to-pole faults. . . . . . . . . 95Figure 4.5 H5LC’s performance during an AC-side single-phase-to-ground fault. . 97Figure 4.6 Lab-scale experimental setup of the proposed H5LC. . . . . . . . . . . . 97Figure 4.7 Experimental results of H5LC. . . . . . . . . . . . . . . . . . . . . . . . 98Figure 4.8 Transient response of the H5LC’s experimental hardware setup. . . . . 100Figure 5.1 The proposedM-Arm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Figure 5.2 The DAC’s topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116Figure 5.3 Ideal voltage waveforms explaining the operation of the DAC. . . . . . 120Figure 5.4 Six topological states of the DAC corresponding to the six intervals ofoperation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Figure 5.5 Operating principle of the DAC depicting rotation of the line-to-linevoltage phasors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122Figure 5.6 The DAC’s key waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 124Figure 5.7 The DAC’s DS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127Figure 5.8 The DAC’s key waveforms with and without an exaggerated overlapperiod of 20◦. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131Figure 5.9 The DAC’s normal operation when no overlap period is considered —zoomed-in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134xixFigure 5.10 The DAC’s normal operation when no overlap period is considered —zoomed-out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135Figure 5.11 The DAC’s normal operation with a 10° overlap period considered —zoomed-in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136Figure 5.12 The DAC’s normal operation with a 10° overlap period considered —zoomed-out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137Figure 5.13 The DAC’s response to the DC-side fault — zoomed-in. . . . . . . . . . 139Figure 5.14 The DAC’s response to the DC-side fault — zoomed-out. . . . . . . . . . 140Figure 5.15 Results from the hardware verification of the DAC from the Tektronixoscilloscope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141Figure 5.16 Results from the hardware verification of the DAC as measured by theOP4510 simulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142Figure 6.1 TheQuad-Arm Converter topology. . . . . . . . . . . . . . . . . . . . . 147Figure 6.2 Idealized voltages explaining the operation of the QAC over two elec-trical cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148Figure 6.3 Twelve topological states of the QAC corresponding to the twelve in-tervals of operation forming a complete electrical cycle. . . . . . . . . . 149Figure 6.4 Twelve topological states and operating principle of the QAC depictingrotation of the line-to-line voltage phasors. . . . . . . . . . . . . . . . . 154Figure 6.5 Ideal DS voltage of Sa of Upper M-Arm 1. . . . . . . . . . . . . . . . . . 156Figure 6.6 Current of Upper M-Arm 1 for different operating voltages and powerfactor angles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161Figure 6.7 Ideal M-Arm voltage of Upper M-Arm 1 both with (vtriu1) and without(vu1) the injection of the triplen harmonic voltage, vtri. . . . . . . . . . . 162Figure 6.8 Ideal M-Arm voltage of Upper M-Arm 1 during a DC-side fault, i.e.,when vDC ≡ 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163Figure 6.9 Key waveforms of Upper M-Arm 1 during normal operation. . . . . . . 166Figure 6.10 Key waveforms of the QAC during a power change. . . . . . . . . . . . 167Figure 6.11 The performance of the QAC during the DC-side fault. . . . . . . . . . 169Figure 6.12 The performance ofUpperM-Arm 1 during DC-side fault operation. (a)M-Arm stack voltage; (b)M-Arm current. . . . . . . . . . . . . . . . . . 170Figure 7.1 The topology of the MSC. . . . . . . . . . . . . . . . . . . . . . . . . . . 176xxFigure 7.2 Idealized voltages explaining the operation of the MSC. . . . . . . . . . 178Figure 7.3 Six topological states of the MSC corresponding to the six intervals ofoperation forming a complete electrical cycle. . . . . . . . . . . . . . . 179Figure 7.4 Outer stack voltages of the MSC with and without the FMS. . . . . . . 190Figure 7.5 Control flow diagram for the MSC using Option #1 control with themidpoint connected through the FMS. . . . . . . . . . . . . . . . . . . . 192Figure 7.6 MSC normal operation with optional FMS — in Option #1 mode. . . . . 198Figure 7.7 MSC normal operation with optional FMS — Option #2. . . . . . . . . . 201Figure 7.8 MSC normal operation without optional FMS . . . . . . . . . . . . . . . 203Figure 7.9 MSC DC fault operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 207Figure 7.10 Hardware verification results. Tektronix-measured. . . . . . . . . . . . 208Figure 7.11 Hardware verification results. OP4510-measured. . . . . . . . . . . . . 209Figure A.1 The hybrid three-level converter. . . . . . . . . . . . . . . . . . . . . . . 247Figure A.2 Example voltage waveforms of the H3LC. . . . . . . . . . . . . . . . . . 248Figure A.3 H3LC’s normalized energy within DC-side pole capacitors with 5%pole-to-pole voltage deviation. . . . . . . . . . . . . . . . . . . . . . . . 251Figure A.4 Normalized energy contained within H3LC’s pole capacitors for 5%pole capacitor voltage ripple. . . . . . . . . . . . . . . . . . . . . . . . . 252Figure A.5 Normalized energy of the H3LC’s cascaded FBSMs. . . . . . . . . . . . 253Figure A.6 H3LC’s total normalized energy with a 5% pole-to-pole voltage ripple. . 254Figure A.7 H3LC’s total normalized energy with a 5% pole capacitor voltage ripple. 254Figure A.8 The hybrid two-level converter alongside the topology of a FBSM. . . . 256Figure A.9 H2LC operational figures. . . . . . . . . . . . . . . . . . . . . . . . . . . 256Figure A.10 Normalized energy of the H2LC’s DC pole capacitor. . . . . . . . . . . 258Figure A.11 Normalized energy of the H2LC’s cascaded FBSMs. . . . . . . . . . . . 259Figure A.12 Total normalized energy that the H2LC requires for varying V1h and ϕ. 260Figure A.13 The total normalized energy required by the MMC. . . . . . . . . . . . 261Figure A.14 The total normalized energy required by the EO-AAC. . . . . . . . . . . 261Figure B.1 A per-phase illustration of the hybrid three-level converter (H3LC). . . 264Figure B.2 Example current waveforms for phase-a with varying ϕ angles forCase (1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268xxiFigure B.3 Example current waveforms for phase-a with varying ϕ angles forCase (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270Figure B.4 Example current waveforms for phase-a with varying ϕ angles forCase (3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271Figure B.5 Example current waveforms for phase-a with varying ϕ angles forCase (4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272Figure B.6 Comparison between the proposed analytical loss method and the DEM. 287Figure B.7 Analytical loss method compared to DEM at V1h = 0.575VDC. . . . . . . 288Figure B.8 The total semiconductor losses of the H3LC. . . . . . . . . . . . . . . . 289Figure B.9 Analytical loss comparison against the DEM for the EO-AAC. . . . . . . 293Figure B.10 The total semiconductor losses of the EO-AAC. . . . . . . . . . . . . . . 294xxiiList of AbbreviationsAbbreviation MeaningAAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alternate-Arm ConverterAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alternating-CurrentACB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC-Side Circuit BreakerADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analogue-Digital ConverterAFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active-Forced-CommutatedBOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Breakover DiodeBTV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bypass Thyristor ValveCCSC . . . . . . . . . . . . . . . . . . . . . . . Circulating Current Suppression ControllerCFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Commutation Cascaded FBSMC-FBCL . . . . . . . . . . . . . . . . . . . . . . . . Commutation Full-Bridge Chain-LinkCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Central-Processing UnitCSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current-Source ConverterCTFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controlled Transition Full-BridgeDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct-CurrentDEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed-Equivalent ModelDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Director SwitchEO-AAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended-Overlap AACDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual-Arm ConverterFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC-Side Cascaded FBSMFBSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Full-Bridge SubmoduleFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flying CapacitorFMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast-Mechanical SwitchFPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Field-Programmable Gate ArrayGTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gate Turn-offThyristorH2LC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hybrid Two-Level ConverterH3LC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hybrid Three-Level ConverterH5LC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hybrid Five-Level ConverterHBSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Half-Bridge SubmoduleHCMC . . . . . . . . . . . . . . . . . . . . . . . . Hybrid Cascaded Multilevel ConverterHVAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Voltage ACHVDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Voltage DCIGBT . . . . . . . . . . . . . . . . . . . . . . . . . . . . Insulated Gate Bipolar TransistorxxiiiIGCT . . . . . . . . . . . . . . . . . . . . . . . . . Integrated Gate-CommutatedThyristorLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line-Commutated ConverterLCC-HVDC . . . . . . . . . . . . . . . . . . . . . . . . . . LCC-based HVDC TechnologyLFAC . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Frequency Alternating-CurrentLS-PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level-Shifted PWMLUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Look-Up TableM-Arm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Converter ArmMBSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mixed FBSMs and HBSMsMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main ConverterMEMC . . . . . . . . . . . . . . . . . . . . . . . Modular Embedded Multilevel ConverterMMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modular Multilevel ConverterMOSFET . . . . . . . . . . . . . . . . Metal-Oxide-Semiconductor Field-Effect TransistorMSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed-Stack ConverterMVDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Medium-Voltage DCNLM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nearest-Level ModulationNPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Neutral-Point-ClampedPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC-Side Pole CapacitorPCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Point-of-Common-CouplingPCIe . . . . . . . . . . . . . . . . . . . . . . . Peripheral Component Interconnect ExpressPWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse-Width-ModulationQAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad-Arm ConverterRMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Root-Mean-SquareSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SubmoduleSO-AAC . . . . . . . . . . . . . . . . . . . . . . . Short-Overlap Alternate-Arm ConverterSTATCOM . . . . . . . . . . . . . . . . . . . . . . . . . Static Synchronous CompensatorTAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transition Arm ConverterTH3LC . . . . . . . . . . . . . . . . . . . . Thyristor-Based HybridThree-Level ConverterTHD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Total Harmonic DistortionUHVDC . . . . . . . . . . . . . . . . . . . . . . . . . Ultra-High-Voltage Direct-CurrentVnh . . . . . . . . . . . . . . . . . . . . . . . . . nth-Order Harmonic Voltage ComponentVBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage-Balancing AlgorithmVSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage-Source-ConverterVSC-HVDC . . . . . . . . . . . . . . . . . . . . . . . . . . VSC-based HVDC TechnologyZVS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Zero-Voltage-SwitchingxxivAcknowledgmentsFirst, to Dr. Liwei Wang, my supervisor: I would like to express my deepest and mostsincere gratitude for your constant encouragement on our various research projects, and forproviding me with invaluable advice, insight, feedback, and support. This dissertation wouldcertainly not have taken form without your exceptional help and guidance.To Dr. Juri Jatskevich, who became my co-supervisor after our move to Vancouver, BC: Ithas been a pleasure to get to know you— and, of course, Jasmine— over the last couple of years.Even from the beginning, you constantly pushed me to improve and to practice the principlesof consistency, logic, and rigor. Working on our projects has certainly been a highlight of myPhD degree.I would also like to thank my parents, who gave to me much more than I ever gave in return.I appreciate their interest in my research, whether it was feigned or genuine! Despite theiruncertainty about my pursuance of a bachelor’s degree, and then a master’s degree,... and thena PhD degree, I thank them for their constant support, always being available, and I believe Imay have even changed their minds.Lastly, I would like to thank the Natural Sciences and Engineering Research Council ofCanada for its financial support, which helped to fund our research projects. NSERCgrantedmeseveral awards over the course of my studies, including the Alexander Graham Bell scholarshipand the CGS – Master’s scholarship, which helped to all but remove the financial hardshipsthat are often associated with graduate school.xxvThis dissertation is dedicated to my beautifulwife, Miya Bieber — Mer — who is steadfastin her support and love for me. And our dog, Gork.1. Introduction and OverviewVoltage-source-converter high-voltage direct-current (VSC-HVDC) technology is a rapidlyevolving, growing, and increasingly important field of research that enables the expandingnumber of renewable energy sources to be more effectively integrated into existing AC-grids.OnNov. 19, 2020, the EuropeanCommission presented the EU Strategy onOffshore RenewableEnergy, which proposes an increase in Europe’s offshore wind capacity from its present level of12GW to at least 60GW in 2030 and to 300GW by 2050 [1] — a twenty-fivefold increase incapacity. As offshore wind power schemes are typically commissioned tens to hundreds ofkilometers from land, HVDC or low-frequency alternating-current (LFAC) power transmissionsystems are often implemented because of their lower transmission line losses and theirincreased viable transmission distances [2]–[8].Figs. 1.1 and 1.2 and [9] show that there is a large and growing number of operating,planned, or presently-under-construction VSC-HVDC projects. Fig. 1.1 presents a map of theHVDC-links that are operating, planned, or under construction in Europe. From the blue linesof Fig. 1.1, many of the HVDC DC-link systems under construction are between mainlandEurope and offshore wind farms. Fig. 1.2 presents an approximately exponential increase inVSC-HVDC capacity.With such an increase, an overarching focus in the VSC-HVDC field of research is theproduction of cost-effective converter stations that, crucially, feature small physical footprints.Compared to HVAC, which only requires widely-available and inexpensive power transform-ers to meet the grid voltage amplitudes, VSC-HVDC converter stations present significanttechnological challenges, including:• They need thousands of semiconductor devices, and the control, cooling, and electricalinsulation thereof;• Typically, AC- and/or DC-side inductors are used to slow system transients (especiallyduring faults) and improve waveform quality;1Operating (as of 2019)Under construction (as of 2019)Planned/under considerationFig. 1.1. HVDC links that are operating, planned, and under construction in Europe. Copyright: Hitachi.[9]50101520253035VSC-HVDC cumulative capacity (GW)Year20102011201220132014201520162017201820192020Fig. 1.2. Yearly cumulative installed capacity of VSC HVDC. Copyright: Hitachi. [9]2• They need a means to protect the converters in the event of AC- or DC-side short-circuitfault scenarios;• Due to their capacitive energy storage requirements, interfacing transformers, componentspacing (for insulation purposes), the semiconductor devices, and, depending on theconverter topology, the AC- and DC-side filtering, VSC-HVDC converter stations canhave a physically large footprint.However, these challenges are mitigated by VSC-HVDC’s benefits, which include:• Low-loss power transmission without an upper limit on transmission distance [10];• The ability to regulate the amount of real and reactive power independently;• The ability to electrify or integrate into weak or passive grids or networks;• The ability to interconnect regions of asynchronous voltages;• The stabilization of grid voltages, even without real power flow (e.g., static compensator(STATCOM) mode [11]);• The stabilization of wind farm voltages even when energy generation rapidly fluctuates;• Providing voltage support to the AC grid during AC-side or DC-side faults, dependingon the converter topology.Another practical implementation of VSC-HVDC is for point-to-point power transmissionschemes, which historically use HVAC. Since the capacitance of transmission lines increaseswith distance, extra conduction losses are incurred in an HVAC system to simply chargeand discharge the transmission line once per fundamental frequency cycle [11]. Moreover,transmission lines’ inductance also increases with distance; hence, for a desired voltage andpower level at the receiving end of the HVAC-link, the supplying side needs to increase itsoutput voltage to compensate for the voltage drop across the transmission line — which3HVDC converterstationLifetime costsTransmission distanceHVACHVDCHVAC transformerEconomic feasibility crossover pointFig. 1.3. Illustration of the upfront and lifetime costs of HVDC vs. HVAC power transmission.increases with higher current/power flow. Therefore, there exists an upper limit on the distancethat HVAC power may be transmitted. The constant DC current enabled by HVDC systemsremoves this limit, as the transmission lines remain charged in normal operation. Therefore,there exists a situation-dependent crossover point where the economic feasibility of the HVDCconverter stations surpasses that of the HVAC transformers. A general illustration of lifetimecosts vs. transmission distance is shown in Fig. 1.3.The economic feasibility crossover point in Fig. 1.3 is highly variable, with a dependenceon, e.g., the conductor selection, the HVDC converter station footprint, the transmission lines’right of way (HVAC requires three conductors while HVDC requires two), and transmissionvoltage. [10] shows that the economic feasibility crossover point is in the neighbourhoodof 450 km for overhead lines; for submarine cables, which exhibit significantly increaseddistributed capacitance, the crossover point may be reduced to under 150 km [11], [12].1.1 History of HighVoltage Direct Current Power Transmission1.1.1 Early HistoryThe development of HVDC schemes began with the invention of the mercury-arc valve inthe 1930s. The first commercial HVDC contract was placed in 1941, in Germany, to supply theCity of Berlin with 60MW of power via a 115 km underground cable. However, at the end4of 1945, coinciding with the end of World War II, the system was dismantled and was neverput into service. The first operational HVDC scheme, the Gotland 1, was commissioned in1954, which transmitted 20MW at 100 kV over 98 km from the island of Gotland to Västervik,Sweden, using line-commutated converter-HVDC (LCC-HVDC) with mercury-arc valves.After the Gotland 1 HVDC scheme was established, many more mercury-arc valve-basedHVDC schemes followed in quick succession. In 1961, the Cross-Channel link between Franceand the UK featured an eight-fold increase in power transmission compared to Gotland 1, at160MW [13]. Shortly thereafter, in 1965, the Konti-Skan 1 scheme was commissioned betweenDenmark and Sweden, which had a power transmission capability of 250MW over a distanceof 176 km. Also in 1965, the notable Volgograd–Donbass HVDC-link was commissioned andwas, at the time, the largest mercury-arc valve HVDC scheme, with a rated power of 750MWat ±400 kV across a distance of 475 km. Over the years, the HVDC power transmissioncapacity continued to rise until the Bipole I HVDC system on Nelson River, Manitoba, wascommissioned in 1972, which used mercury-arc valves to transmit 1.62GW of power at±450 kV, setting many records at the time [14]–[16].In 1972, the first back-to-back asynchronous interconnection was commissioned betweenQuebec and New Brunswick at Eel River, which also marked the first converter station touse thyristors in favour of mercury-arc valves [17]. Since the construction of the Eel Riverconverter station, the use of thyristor valves in HVDC systems has proliferated throughoutthe industry, such that the last of the mercury-arc valve-based HVDC systems, the HVDCKingsnorth and the Nelson Bipole I, were commissioned in 1975 and 1977, respectively [13].1.1.2 Line-Commutated Converter HVDCTechnologyEven until today (2022), most of the world’s newly commissioned point-to-point HVDCprojects use the thyristor-based line-commutated converter (LCC) HVDC technology toachieve high efficiency HVAC/HVDC conversion [13], [18], [19]. LCC-HVDC, often referredto as “HVDC classic,” [20] is defined by its use of switching devices that have a controllableturn-on event at the so-called firing angle, but their turn-off requires the natural zero crossings5of the AC grid voltage to reverse-bias the switches. LCCs are also referred to as current-sourceconverters (CSCs) due to the approximately constant DC current enabled by large DC-sideinductors.All of the LCC-HVDC converter schemes commissioned today use thyristors as the solid-state switching devices. Compared to other semiconductor technologies, thyristors havethe lowest on-state voltage drops and on-state resistances, which, for the slow-switchingimplementations for which they are used, make thyristor-based LCC-HVDC technology themost efficient means of converting between HVDC and HVAC. Moreover, being a maturetechnology, thyristors are reaching ever-higher blocking voltages and current ratings. Due totheir unmatched blocking voltages, and the improving technology that enables their series-connection for even greater blocking voltages, thyristors have enabled construction of ultra-highvoltage DC (UHVDC) transmission schemes of the likes of the Zhundong-Wannan DC-link,which uses a±1,100 kV bipole setup for the transmission of up to 12GW across a distance of3,324 km, making it the largest HVDC project at the time of writing — in terms of voltagerating, power rating, and distance of transmission [21].A simplified circuit schematic of a thyristor-based LCCs is shown in Fig. 1.4, where thetwelve-pulse LCC is shown. The twelve-pulse LCC uses two six-pulse LCCs connected in series,with each six-pulse LCC interfacing with a separate transformer — one with ∆-connectedwindings and the other with Y-connected windings. The benefit of the twelve-pulse LCC isthat the thyristors in each switch position block only half the DC-side voltage, VDC, comparedto the six-pulse LCC. Moreover, the twelve-pulse LCC displays better harmonic performanceby having twice as many switching events — at half the voltage — as the six-pulse LCC, byoperating the upper and lower six-pulse LCCs 30◦ out of phase. This has the added benefit ofreducing the need of harmonic filtering, which reduces the converter station size.Although LCC-HVDC systems are among the most dependable, efficient, and well-testedmeans of HVAC/HVDC conversion, there are several key disadvantages that make their use6VDCIDCvavbvcSix-pulse LCCTwelve-pulse LCCFig. 1.4. Example of a twelve-pulse LCC HVDC system and its constituent six-pulse LCC systems.impractical, impossible, or prohibitively expensive for some applications [22]. Some of theseinclude their:• Requirement of AC-side voltage zero crossings to reliably turn-off their switches.• Inability to interface with weak or passive grids, precluding them from most renewableenergy source applications [23].• Large converter footprint due to the significant AC-side and DC-side filtering requiredto meet total harmonic distortion (THD) requirements.7(a)Two-Level Converter Three-Level Converter(b)VDC voutVDCvoutFig. 1.5. A single-phase diagram of: (a) A two-level converter. (b) A three-level converter.• Inability to provide black-start capability to a grid, i.e., only healthy grids may be inter-connected.• Power reversal requires varying the DC voltage, thereby making the prospect of anHVDC grid difficult.1.1.3 Voltage-Source-Converter HVDCTechnologyDifferentiated from current-source/line-commutated converters, voltage-source-converters(VSCs) are defined by their use of fully controllable semiconductor switches, i.e., those thatmay be both turned on and turned off. Most frequently, insulated gate bipolar transistors(IGBTs) enable this functionality for HVDC applications for their robustness and high efficiency.Gate turn-off thyristors (GTOs), integrated gate-commutated thyristors (IGCTs), and metal-oxide-semiconductor field-effect transistors (MOSFETs) are increasingly finding use as theirtechnologies mature, but they are less suitable for series-connection compared to IGBTs;therefore, their use is limited mostly to motor drive applications and small scale renewableenergies projects.Having semiconductor switches with a controllable turn-on and turn-off allows VSCs to8generate symmetrical AC voltages, thereby enabling complete control over the real and reactivepower levels exchanged with the AC grid. Consequently, VSCs do not require connection to astrong AC grid; they can be used for motor drives, remote power applications, power factorcorrection, and electrification of entirely passive networks.Compared to thyristor valves, which consist of tens-to-hundreds of thyristors placed inseries and operated in unison once per fundamental-frequency AC cycle, the series-connectionof IGBTs is more challenging. In the erroneous and limiting scenario that all but one of thethyristors composing a thyristor valve are triggered to turn on, catastrophic failure would ensue.Thyristor valves use safeguards to prevent this in the form of breakover diodes (BODs) thatautomatically trigger a turn-on event in case of overvoltage [24]. IGBTs, on the other hand, aremore sensitive to overvoltage, such that commanding hundreds of series-connected IGBTsto operate in unison leaves little room for error; if one or more IGBTs erroneously remain inthe off state after they are commanded to turn on, the voltage experienced across them willsignificantly exceed their rated limits, causing catastrophic failure.However, IGBT technology has been revolutionized in recent years by the introduction of,e.g., ABB’s StakPak IGBTmodule [25], which is designed for high-power, high-voltage VSCs forHVDC and flexible AC transmission system (FACTS) applications, where hundreds of StakPakIGBTs can be connected in series to scales of up to hundreds of kilovolts. ABB’s StakPak IGBTis a well-proven technology that has been used in two-level or three-level VSC-HVDC schemes(the circuit topologies of which are presented in Figs. 1.5 (a) and (b), respectively) for ratings ofup to 320 kV since 1997 [26]–[31]. When connected in series, StakPak IGBTs are designed forsafe and reliable operation over the 30-year service life of the VSC.This is due to the packagingfeature, i.e., the short-circuit failure mode (SCFM), which triggers the stable short-circuit modeof the StakPak IGBT module in case of failure using a metallic alloy [25], [32].An example of a two-level converter scheme is the Estlink Transmission System [33], [34]between Estonia and Finland that was commissioned in 2006. It uses ABB’s HVDC Light®technology for a pole-to-pole DC-link voltage of ±150 kV and maximum power levels of9365MW. Each phase of the two-level converter operates under a voltage stress of 300 kV 23times per 50Hz cycle.Despite the many benefits enabled by VSC technology, the semiconductor valves of thetwo-level and three-level converters of Figs. 1.5 (a) and (b) suffer from substantial switchinglosses due to the high operating frequencies that are required to generate sinusoidal AC voltageswith sufficiently low THD. Nonetheless, from 1999 until 2010, the two-level and three-levelconverters were the main technologies used for VSC-HVDC transmission.1.1.4 The Modular Multilevel ConverterAfter 2010, however, the Trans Bay Cable project was completed, which was the first VSC-HVDC project to use a new type of VSC: the modular multilevel converter (MMC) [35]–[52].Composed of hundreds to thousands building-blocks, popularly referred to as “submodules,”that may be incrementally inserted to or bypassed from the current path, theMMC can producehigh quality output voltages — within the resolution of the number of submodules per arm—at a low switching frequency and without extraneous AC-side or DC-side filtering [44]–[46].These attributes have enabled the MMC to quickly become the ubiquitous technology withinVSC-HVDC, such that many new renewable energies projects use MMC technology for itsefficient HVDC/HVAC conversion, especially for offshore wind farms.Fig. 1.2 shows that since the MMC’s first implementation in 2010, the cumulative amountof installed HVDC capacity has been, and continues to be, increasing exponentially. For windpower integration into the grid, the MMC is the preferred VSC-HVDC technology due to itshigh reliability as well as its ability to interface with the highly variable AC voltages — bothin magnitude and frequency — that are inherent to wind power generation. Its effect on theprocess of integrating wind power into the main grid has been disruptive in that virtually allnew VSC-HVDC projects use MMC technology.The topology of the conventional modular multilevel converter (MMC) is shown in Fig. 1.6(a). TheMMCuses six arms of submodules— three upper and three lower arms. For phase-a, ex-ample voltagewaveforms are presented for the upper and lower arms in Fig. 1.6 (b), wherein each10vavu,avbvcSMSMSMSMSMSMvl,a(a) (b)SMSMSMSMSMSMVDC0VDCPhase-a upper arm voltage, vu,aPhase-a lower arm voltage, vl,aPhase-a output voltage, vaVDC1200VDCVDC12VDC12VDC12−piωt (rad)2pi0 pi23pi2Fig. 1.6. (a) TheMMC topology. (b) Example voltage waveforms for the phase-a upper and lower arms,as well as the phase-a output voltage.arm contains 10 submodules such that the arm voltages and the phase-j voltages (j ∈ {a, b, c})are quantized with a resolution of 10 steps. It is noted that for VSC-HVDC implementations,the number of submodules for the MMC is in the hundreds, and occasionally thousands.The submodules that comprise theMMC—and othermultilevel converters, to be discussed— are typically composed of IGBTs. They may output unipolar or bipolar voltages, such thatthey may insert positive or negative voltages into the stack of submodules, or be bypassed [37],[44]–[49], [53]–[56].In Figs. 1.7 (a) and (c), example circuit diagrams of bipolar and unipolar submodules arerespectively shown, wherein the bipolar submodule is the full-bridge type (FBSM) and theunipolar submodule is the half-bridge type (HBSM).The most popular bipolar submoduleis the FBSM, which can generate the voltages vFBSM ∈ {−vc, 0, vc}, depending on its switchpositions; the most common unipolar submodule — and the most efficient submodule withthe fewest switches — is the HBSM, which can generate voltages vHBSM ∈ {0, vc}. Examplevoltage outputs of the FBSM and HBSM are given in Figs. 1.7 (b) and (d), respectively, whichalso present which of the submodules’ switches are in the on state to generate their respectivevoltages. Lastly, in Fig. 1.7 (e), an example HBSM fromMitsubishi [57] is presented.11vc vcvFBSMvHBSMFBSM++ --S2S1S4S3(a)+-HBSM(c)+-S2S1(d)(e)(b)S1 & S4S1 & S3 or S2 & S4S2 & S30vc−vcFBSM output voltages, vFBSMS1S20vcHBSM output voltages, vHBSMFig. 1.7. (a) Full-bridge submodule (FBSM). (b) Half-bridge submodule (HBSM). (c) Example outputvoltages of the FBSM. (d) Example output voltages of the HBSM. (e) Example of HBSM—Copyright:Mitsubishi. [57]With an increasing number of submodules, the number of voltage levels [as in Fig. 1.6 (b)]increases proportionally, such that the amount of THD within the MMC’s output voltages is adesign parameter; with enough submodules, no inductive or capacitive AC-side filtering isrequired, while maintaining a low switching frequency. This is a fundamental departure fromthe operating principles of the two-level and three-level converters, which require increasinglyhigh switching frequencies to minimize the AC-side voltage’s THD, which increases theswitching losses approximately proportionally.The MMC holds many benefits over the previous two-level and three-level converters,including:• Being entirely modular in structure, the MMC is easily scalable. Compared to thetwo-level and three-level converters, which require many hundreds of IGBTs in series,the submodules of the MMC are individual entities that are independently serviceable.12Moreover, the IGBTs of each of the submodules only experience a maximum voltageequivalent to the SM capacitor, minimizing the risk of overvoltage [43].• A large number of submodules leads to a very small, or nullified, filtering requirement.• The addition of bipolar submodules into the MMC’s arms enables its AC- and DC-sidesto be decoupled. That is, it can control the AC- and DC-side currents independentlywhen bipolar submodules are used [45], [48].• Continuous current on the DC link cable removes the need of a DC-side pole capacitor,simplifying design.• When bipolar submodules are used, the MMC can continue operation even with acollapsed DC-side voltage during, e.g., pole-to-pole fault scenarios [such that VDC ≡ 0in Fig. 1.6]. That is, with bipolar submodules, the MMC has DC-fault ride-throughcapability, which is impossible for converters such as the two-level and three-levelconverters.Although featuring significant advantages over the two-level and three-level converters,the MMC also has disadvantages, such as:• If the highly efficient and less expensive HBSM is used — as is most common in newprojects — the MMC shares the two-level and three-level converters’ inability to providereverse-blocking voltages against the AC-side grid voltage during DC-side fault scenarios.Hence, if the arms are made entirely of HBSMs, the MMC possesses no DC-side faultblocking capability nor DC-fault ride-through capability. Therefore, the MMC requireseither the addition of bipolar submodules to supply reverse blocking voltages against theAC-side grid voltage, or AC-side circuit breakers (ACBs) [43].• The MMC requires six bulky arm reactors (one per arm) to limit the flow of lossy circu-lating currents between the arms. Although circulating current suppression controllers13(CCSCs) have been proposed [58], [59], such control methods add complexity to theconverter’s control design and can contribute negatively to the MMC’s switching losses.• Compared to the two-level converter, the HBSM-based MMC (HBSM-MMC) requirestwice as many semiconductor devices; the FBSM-based MMC (FBSM-MMC) requiresfour times as many. Hence, the MMC has high upfront costs, while its lifetime costs arereduced due to its favourable semiconductor loss profile.• Each of its armsmust be sized to generate or block the entire DC-side voltage, VDC, whichrequires a substantial number of submodules per arm.• Despite having no DC-side pole capacitors, as in the cases of the two-level and three-levelconverters of Fig. 1.5, the MMC has a significant capacitive energy storage requirement— far more than the two-level and three-level converters’ — which contributes to a largeconverter footprint. However, the reduction in size enabled by its absence of AC- andDC-side filtering offsets its large energy storage requirements.Therefore, despite MMC technology’s high reliability and low semiconductor switchinglosses, its converter station comes with a large physical size such that offshore wind farmprojects may be prohibitively expensive, especially due to wind farms’ increasing distances fromthe mainland. For example, Fig. 1.8 (a) shows the DolWin2 [60] offshore wind transmissionplatform being ferried to a location 45 km from Dörpen West in Emsland, Germany. Fig. 1.8(b) shows the HelWin2 project being ferried to its location 85 km offshore. Both DolWin2and HelWin2 use MMC technology with the DC-side voltage of ±320 kV and maximumpower flows of 916MW and 690MW, respectively. As seen in Fig. 1.8, such MMC-based VSC-HVDC transmission schemes are immense in size: the HelWin2 platform, for example, has thedimensions 98m x 42m x 28m and weighs 10,200 tonnes. A typical valve-hall implementation,showing the MMC’s constituent submodules suspended from the ceiling, is shown in Fig. 1.8(c).14(a)(c)(b)Fig. 1.8. (a) ABB delivers the offshore DolWin2 wind transmission link. Copyright: ABB. [60] (b)HelWin2 wind transmission link. Copyright: TenneT. [61] (c) Typical valve hall contained withinoffshore platforms. Copyright: ABB. [62]1.2 Status of Multilevel Voltage Source Converter ResearchHence, much of today’s VSC-HVDC research is focused on developing new topologiesthat feature high efficiency, small converter footprints, and DC-side fault tolerance. So-calledhybrid multilevel converters have been proposed that combine the merits of the MMC, i.e.,its modularity and high-fidelity output voltages, with the simplicity-of-design enabled bythe simpler two-level and three-level converters [63]–[80] . The hybrid two-level converter(H2LC, [69]–[75]) is one such type of converter that combines the modularity of the MMCwith the simplicity of the two-level converter. The H2LC features DC-side fault blocking whilerequiring only a quarter of the submodules as the MMC. However, despite its small expectedfootprint, the H2LC experiences high semiconductor switching and conduction losses due tohaving twice as many semiconductors in the conduction path. Moreover, the director switches15(DSs) that form the two-level converter portion of the H2LC experience hard switching, whichcontributes negatively to the semiconductor’s switching losses and longevity.The alternate arm converter (AAC) [63], [65]–[67] is another type of hybrid converterthat uses submodules similarly to the MMC to generate high-fidelity voltage outputs whilerequiring only half as many submodules. The AAC improves upon the MMC’s compactnesswhile inherently being able to suppress fault currents in the event of DC-side faults. Moreover,the AAC features zero-voltage-switching (ZVS) of its director switches, which improves itssemiconductor losses.Further hybrid converter topologies include: the controlled transition full-bridge (CTFB)converter [76]; the transition arm converter (TAC) [77], [78], which generates trapezoidaloutput voltages; and themodular embeddedmultilevel converter (MEMC), which uses thyristortechnology to reduce the footprint of the MMC [79]. The CTFB hybrid multilevel converter isproposed in [76], which uses a set of cascaded FBSMs between the two phase legs in each phaseto a generate multilevel sinusoidal AC output voltage. TheMEMC of [79] uses series-connectedthyristor-based director switches and IGBTHBSMs or FBSMs. These converters have improvedconverter efficiency and compactness compared to the conventional HBSM-MMC. However,they do not provide DC pole-to-pole fault blocking capability.Therefore, at present, the direction of research in the VSC-HVDC field is to invent novelconverter topologies that address theMMC’s chief downsides, i.e., its large footprint and its lackof inherent DC-side fault blocking/ride-through capability, where DC-side fault ride-throughcapability is defined as the ability for the converter to continue operation despite a collapsedDC-side voltage by supplying reactive power support.In this section, two state-of-the-art converter topologies are briefly analyzed: the alternatearm converter (AAC) and the hybrid two-level converter (H2LC). These converters belong to aclass of VSC-HVDC converters that are commonly referred to as hybrid cascaded multilevelconverters (HCMCs) which, as the name implies, are a hybrid of the simpler two-level orthree-level converters with the modularity and multilevel functionality of the MMC.161.2.1 Alternate Arm ConverterAmong the best known of the HCMCs is the alternate arm converter (AAC), as shownin Fig. 1.9 (a), which is a combination of the two-level converter and the FBSM-MMC [63],[65]–[67]. The series-connected IGBTs are commonly referred to as the AAC’s director switches(DSs). With the bipolar voltage generation capability enabled by its FBSMs, the voltages at vj(j ∈ {a, b, c}) can reach higher voltages than the MMC.The AAC can be separated into twooperating modes: the short-overlap (SO-AAC) and extended-overlap (EO-AAC) modes. TheSO-AAC is more-or-less fixed to its “sweet-spot” operation voltage of V1h = 2piVDC, where V1his the peak value of the fundamental component (harmonic) of the AC-side phase-to-neutralvoltages. The EO-AAC, on the other hand, can generate even higher voltages, e.g., V1h = 23VDC,and can operate at any voltage, V1h.Both formulations of the AAC use the FBSMs to enable zero-voltage switching (ZVS) for itsDSs for minimal switching losses. During the DSs’ off state, the voltages across the stacks ofsubmodules output their maximum values to minimize the voltage across the DSs. For phase-a,the upper and lower stack voltages are denoted by vu,a and vl,a, respectively, and are presented inFig. 1.9 (b). Thewaveforms of Fig. 1.9 (b) correspond to the voltages generated by the SO-AAC’sarms, where it is noted that they each operate for half of the fundamental-frequency cycle andtemporarily generate negative voltages, corresponding to the peak values of the phase-a outputvoltage. Meanwhile, for both the SO-AAC and EO-AAC, as they were presented in [63], [67],the DSs are sized for the peak AC-side voltage magnitude, V1h, while their cascaded FBSMstacks are rated for 12VDC and 23VDC, respectively, which represent a 50% and 33.3% reductionin the total number of submodules compared to the MMC, respectively.Moreover, compared to the MMC, the EO-AAC requires approximately 47% of the totalenergy storage, while the SO-AAC requires only 39% of the MMC’s energy [81]. Hence,compared to the MMC, the AACs are expected to have a significantly reduced converterfootprint due to their reduced numbers of submodules as well as the significantly reducedcapacitive energy storage requirements.17(b)vaVDCvu,avbvcFBSMFBSMFBSMFBSMFBSMFBSMFBSMFBSMFBSMFBSMFBSMFBSMDirectorSwitchesvl,a(a)0VDCPhase-a upper arm voltage, vu,aPhase-a lower arm voltage, vl,aPhase-a output voltage, vaVDC1200VDCVDC12VDC12VDC12−piωt (rad)2pi0 pi23pi2Fig. 1.9. The alternate arm converter with full-bridge submodules.The AAC’s main benefits include:• A reduced footprint due to a lower total energy storage requirement and number ofsubmodules compared to the MMC.• Inherent DC fault blocking and DC fault ride-through capabilities.• ZVS for its DSs, which are operated complementarily at the fundamental frequency.Considering its attributes, the AAC also has shortcomings, including:• The discontinuous DC current requires a large DC-side pole capacitor for the case of theSO-AAC [63], [81].• The SO-AAC’s AC-side is not decoupled from the DC-side, unlike theMMCwith bipolarsubmodules, such that its cascaded FBSMs are used primarily to remove harmonicsfrom the two-level voltage waveform otherwise generated from the DSs’ complementaryoperation.18• The EO-AAC’s AC-side is decoupled from the DC-side due to its extended overlap ofits upper and lower DSs (for a third of each fundamental-frequency cycle), but its DScurrents are only continuous when it is operated at the voltage V1h = 23VDC.• The EO-AAC requires approximately 166% more equally-rated semiconductors as theHBSM-MMC.• Compared to the HBSM-MMC, the SO-AAC and EO-AAC respectively present 26%and 23% higher semiconductor losses when the converters are operated as inverters [67].While the AAC holds many benefits over the MMC, the SO-AAC’s inflexibility in termsof voltage output and its meager reduction in footprint from its energy storage precludes itfrom many applications, especially those with fluctuating voltages, such as offshore wind farms.Moreover, the SO-AAC and EO-AAC both have a large requirement of semiconductors, whichincreases their upfront costs.1.2.2 Hybrid Two-Level ConverterTheH2LC [69]–[75] is a lesser known HCMC that is similar to the AAC in that it operateswith DSs and submodules, but rather than having the submodules placed in series with the DSson the DC-side, the submodules are cascaded at the AC-side to remove harmonics from theoutput voltage of the DSs, i.e., at v2LC,j (j ∈ {a, b, c}), such that the phase-to-neutral voltagesat vjt (j ∈ {a, b, c}) have only the fundamental-frequency harmonic, V1h, with an additionaland optional third-order harmonic, V3h. A circuit diagram of the H2LC is shown in Fig. 1.10.The H2LC’s Two-Level Converter employs minimal frequency switching of its DSs, i.e., ata frequency that is three times the fundamental frequency, to generate the square waves inFig. 1.11 (a), which are measured at v2LC,j (j ∈ {a, b, c}) in Fig. 1.10. By varying the switchingangles, the amplitude of the fundamental frequency voltage component may be controlled. Bythe subtraction of the fundamental-frequency sinusoidal voltage, as well as a sinusoidal voltageof three times the fundamental frequency — i.e., a third-order harmonic — the cascadedFBSMs of Fig. 1.10 remove all non-fundamental and non-triplen harmonics at vj (j ∈ {a, b, c}).19FBSMTwo-Level Converter+-v2LC,av2LC,bv2LC,cvatvbtvctS2S1S4S3FBSMCascaded FBSMsFBSMFBSMFBSMFBSMFBSMT1T2T3T4 T6T5Fig. 1.10. The hybrid two-Level converter.With 3rd Order HarmonicWithout 3rd Order Harmonicv2LC,a(t)−V1hsin(ωt)v2LC,a(t)−V1hsin(ωt)−V3hsin(3ωt)v2LC,a(t)V1hsin(ωt)V3hsin(3ωt)(a)(b)πωt (rad)2π0 π23π200VDC12VDC12−VDC12VDC12−Fig. 1.11. Key waveforms of the voltages generated and outputted by the H2LC’s DSs and submodules.The third-order harmonic, as shown in Fig. 1.11 (b) enables the peak voltage of the cascadedFBSMs to be limited to±12VDC, which reduces the required number of semiconductors andFBSMs.The H2LC’s main benefit is its reduced footprint, which is enabled by its having onlyone-quarter of the submodules as the MMC, as well as requiring only 32% of the capacitiveenergy storage of theMMC [82]. Moreover, the H2LC features inherent DC-side fault-blockingand ride-through capabilities such that it can supply reactive power support during DC-sidefaults. However, a significant drawback of the H2LC is that, compared to the HBSM-MMC,20there are twice as many IGBTs in the conduction path, which lowers its efficiency. As willbe shown in subsequent chapters, the H2LC’s semiconductor losses are approximately 67%higher than the HBSM-MMC’s. Despite its poor efficiency, the H2LC’s small expected size andinherent DC-fault blocking/ride-through capability make the H2LC a strong candidate forfurther research.1.3 Motivation, Research Objectives, and Overview ofWorkAccomplishedIn order to decrease humanity’s dependence on fossil fuels, it is necessary to put forthtechnologies that enhance the economic viability of harvesting renewable energy sourcesand incorporating them into the current power grid. Given that the most abundant sourcesof renewable energy are frequently located in remote and challenging geographical areas, aconsiderable portion of their extraction costs are associated with transmission.VSC-HVDC is one technology that has gained popularity in facilitating the transmissionof renewable energy sources. However, the current leading VSC-HVDC technology, MMC,poses significant challenges, particularly in terms of its large converter footprint. As a result,HCMCs have garnered significant attention as a potential alternative to the MMC, as outlinedin Section 1. Nevertheless, the HCMCs proposed have their own limitations, such as the lowefficiency of the H2LC and the only modest decrease in energy storage offered by the AAC.Therefore, the primary objectives of this thesis include proposing VSC-HVDC convertersthat aim to achieve:(1) Competitive power efficiency of land-based or offshore HVDC transmission systems,(2) Minimized physical footprints of the converter stations,(3) DC-side short-circuit fault-blocking capabilities and, preferably, ride-through capabili-ties.Motivated by the advantages of the aforementionedH2LC andAAC—namely, their reducedfootprints and DC fault-blocking and ride-through capabilities—the main scope of my PhD21research, and the overall topic of this PhD dissertation, is on the design and development ofVSC-HVDC topologies with the highest of efficiencies and the smallest of footprints that stillprovide reliable DC-side fault operation.For the first part of my PhD program, I designed three VSC-HVDC converters that weredeveloped into IEEE journal papers. These converters, which have similar operating principleswith varying levels of compactness and efficiency, constitute the first part of this thesis andcollectively belong to the class of VSC-HVDC converters with hybrid structures.The second part of my PhD program resulted in three more converter topologies that usean entirely different operating principle. These converters collectively belong to the novel classof converters named the Multiplexed-Arm Converters (MACs), which form the second partof this thesis. At the time of writing, these converter topologies have been fully developed,with manuscripts at varying stages of development. However, since I and Drs. Wang andJatskevich are working with the UBC UILO to secure a patent for the Multiplexed ConverterArm technology on which the converters are based, the concept was not publicly disclosed atthe time of writing, and hence no publications have yet resulted.In short, the converters belonging to the class of VSC-HVDC converters with hybridstructures include:HybridThree-Level Converter: The hybrid three-level converter (H3LC, [83]), published inthe IEEE Transactions on Power Delivery, was the first of my proposed and publishedconverters. The H3LC uses a three-phase T-type neutral-point-clamped converter as itsbase unit and employs cascaded full-bridge submodules on its AC-side output. TheH3LCis an improvement upon the H2LC of [69] that enables reduced losses and capacitiveenergy requirements while retaining DC-side fault-blocking capability.Thyristor-based HybridThree-Level Converter: The TH3LC is a highly efficient variant ofthe H3LC that features inherent DC-side fault protection and ride-through capabilitydue to its use of robust thyristor technology. The TH3LC employs cascaded full-bridgesubmodules that enable it to operate as a STATCOM during DC-side fault scenarios22while its thyristor-based director switches grant it best-in-class efficiency during normaloperation. A journal article on the TH3LC was published to the IEEE Open AccessJournal of Power and Energy [84], while a conference article was accepted to the 2019IEEE 10th Annual Information Technology, Electronics and Mobile CommunicationConference (IEMCON) [85], where it received the Best Paper Award.Hybrid Five-Level Converter: The hybrid five-level converter (H5LC) is a highly efficientVSC-HVDC converter that employs a novel DC-fault blocking structure that does notsignificantly increase its footprint. Its five-level converter voltage output, enabled by itsuse of flying capacitors, allows its number of full-bridge submodules to be quarteredcompared to the H2LC, thereby reducing its overall losses and expected converterfootprint. The H5LC was published in the IEEE Transactions on Industrial Electronics,which is an especially influential journal in the area.The next three converters belong to the class of converts with Multiplexed-Arm structures:Dual-Arm Converter: TheDAC uses only two submodule-based stacks to generate sinusoidalline-to-line voltages. Its main contributions include its reduced footprint, enabled byits significantly reduced number of submodules, as well as its zero-voltage-switchingof its DSs, which leads to their simpler design. A manuscript written on the DAC wassubmitted to the IEEE Transactions on Power Electronics on July 26, 2022 [86].Quad-Arm Converter: TheQAC is a new type of VSC-HVDC converter with four stacks ofsubmodules that does not need DC-side pole capacitors, as with the H3LC, TH3LC,H5LC, and DAC. The QAC features high efficiency and a small converter footprint,enabled by its reduced number of SMs. Of the proposed converters, the QAC can operateat the highest AC voltage amplitude, resulting in better utilization of the DC-side voltage.Multiplexed-Stack Converter: The MSC represents a significant modification to the DACby employing two additional HBSM-based stacks, such that it uses four stacks in totalthat span the DC-side. The MSC employs DC-side pole capacitors that enable it to23generate any AC voltage amplitude within the limitations imposed by its semiconductors.Moreover, the MSC is proposed with a reduced-stack operation, wherein the numberof submodules in its FBSM-based stacks can be significantly reduced, giving the MSCextraordinarily high efficiency.In addition to the three accepted papers on the H3LC, TH3LC, and H5LC, I have also pre-pared conference papers to expand upon the ideas presented in the journal papers. Accepted tothe 2020 IEEE 21st Workshop on Control and Modeling for Power Electronics (COMPEL) con-ference, [82] proposes a methodology to accurately calculate the energy storage requirements ofthe aforementioned converters; the methods are derived and provided in this dissertation. Also,accepted to the 2021 IEEE Electrical Power and Energy Conference (EPEC), [87] proposeda method to analytically calculate the losses of the H3LC (instead of using the conventionalswitching-based simulation). I am preparing journal paper that expands upon [87] to includethe analytical expression for the switching losses of the H3LC. Much of the expanded journalpaper is presented in Chapter B of the dissertation and will soon be submitted to the IEEETransactions on Power Delivery.242.Hybrid Three-Level and Modular Multilevel Con-verterMotivated by the DC-fault blocking capability and high compactness of the H2LC (asbriefly mentioned in Section 1.2.2 [69]–[75]), this chapter presents a new type of converter,belonging to the class of HCMCs, which features reduced semiconductor losses. The H3LCbuilds upon the attributes of the H2LC, while rectifying its disadvantages — namely, its poorefficiency, high semiconductor count, and high DS switching frequency. The H3LC usesa neutral-point-clamped (NPC) three-level converter to enable a three-level voltage withstates 12VDC, 0, and − 12VDC compared to the H2LC’s two-level converter that generatesonly 12VDC and − 12VDC. This has the key advantage of reducing the cascaded FBSMs’ totalblocking voltages and hence their size. The topology of the H3LC is presented and explainedin Section 2.1.2.1 TopologyThe proposed topology of the H3LC of Fig. 2.1 uses stacks of series-connected IGBTsemiconductor switches, referred to herein as director switches (DSs), to generate three-levelsquare-wave voltages at v3LC,j , where j ∈ {a, b, c}. The main converter, which performsAC/DC conversion and sets the fundamental-frequency voltage amplitude, is formed by aT-type three-level NPC converter, but other three-level topologies, such as the diode-clampedthree-level converter [88], can be used for their reduced switch count. The DSs T1, T2, T3, andT4 of Fig. 2.1 correspond to the four DSs of phase-c. As shown in Table 2.1, the upper andlower-position DSs (T1 and T4) are rated for the entire DC-link voltage, i.e., VDC, while themidpoint DSs (T2 and T3) are each rated for half the DC-link voltage, i.e., 12VDC. It is noted thatthe lowercase VDC of Fig. 2.1 refers to the time-varying value of the DC-side voltage (equal toThis chapter is based on the IEEE article “A Hybrid Three-Level and Modular Multilevel Converter withDC Fault Blocking Capability and Reduced Semiconductor Losses,” accepted to IEEE Transactions on PowerDelivery [83].25+++−−−+vDCvuvliaibicv3LC,av3LC,bv3LC,cvSMvcvbtvatvctS1S2S4S3T2T3 T4ProtectionBranchProtectionBranchProtectionBranchT1−iNormal OperationBranchesFBSM FBSMFBSMFBSMvFB,aFBSMFBSMiDCFig. 2.1. The H3LC topology.vu + vl), while the uppercase VDC refers to the nominal value. The H3LC’s DSs operate at thefundamental-frequency, i.e., at fsw = fp, which enables lower switching losses of its DSs thanother hybrid converters’ DSs, such as the H2LC’s, which operates at fsw = 3fp. Therefore, theswitching losses of the three-level converter of the H3LC are lower than that of the two-levelconverter of the H2LC.The H3LC’s AC-side cascaded FBSMs of the normal operation branches in Fig. 2.1 areoperated to remove all of the harmonics contained within v3LC,j (within the resolution of thestepped-voltage that they produce) except for the fundamental-frequency and third-orderharmonics. Therefore, The H3LC’s line-to-line voltages at the converter terminals, vjt, wherej ∈ {a, b, c} are virtually free of any harmonic content.The switching states and voltage ratings of the DSs and the cascaded FBSMs of the proposedH3LC are given in Table 2.1 in which the DSs belonging to the jth phase, i.e., T1,j , T2,j , T3,j ,and T4,j , can output three voltage levels, i.e., 12VDC, 0, and −12VDC, at the phase-to-groundvoltage v3LC,j (j ∈ {a, b, c}) as defined in Fig. 2.1. Therefore, fundamental-frequency three-level square-wave AC voltages with the peak values of±12VDC can be generated at v3LC,j . Thefundamental-frequency voltage is regulated by the pulse width of the fundamental-frequency26TABLE 2.1Ratings of the DSs and the FBSM SwitchesDirector Switches Full-Bridge Submodulesvj T1,j T2,j T3,j T4,j vSM S1 S2 S3 S412VDC 1 1 0 0 14NVDC 1 0 0 10 0 1 1 0 010011001−12VDC 0 0 1 1 − 14N VDC 0 1 1 0Rating(×VDC) 112121Rating(×VDC)14N14N14N14Nsquare waves. The blocking voltage ratings of the DSs are listed in Table 2.1, which can be usedto dimension the number of the series-connected IGBT modules.The AC-side cascaded FBSMs in the normal operation branches output harmonic voltagesthat complement the square-wave voltages of the three-level converter to produce smoothsinusoidal voltages vjt (j ∈ {a, b, c}) at the converter’s AC terminals in Fig. 2.1. Section 2.2will show that the peak output voltage of the cascaded FBSMs of each phase’s normal operationbranch can be limited to±14VDC. Therefore, the DC voltage of each FBSM is 14NVDC, assumingN is the number of FBSMs in each phase’s normal operation branch. The switching states of aFBSM corresponding to the positive, zero, and negative SM output voltages are also listed inTable 2.1.It is noted in Table 2.1 that turning onT2 when T1 is already on (i.e., during the 12VDC voltagelevel) results in lossless turn-on for T2: since the diode of T2 is already forward-biased duringthe 12VDC voltage level, T2 and T1 are both turned on to define the 12VDC voltage level. WhenT1 is operated to turn off during the 12VDC → 0 transition, T3 is turned on at the same timethat T1 is turned off. If at turn-off the current is positive (i.e., flowing downward through T1),T1 will experience IGBT turn-off losses, Eoff, and T3’s diode will experience lossless turn-on.Conversely, if the current is negative at turn-off (i.e., it is flowing upward through T1), T1will experience diode reverse-recovery losses, Erec, while T3 will experience IGBT turn-onswitching loss, Eon.27The IGBTs within the cascaded FBSMs in the normal operation branches can be operatedto block the DC pole-to-pole fault by turning them off. However, the output voltage of thecascaded FBSMs in each phase, i.e., 14VDC, is insufficient to block the DC fault because theAC grid phase voltage can have a peak value of 12VDC, or higher. Therefore, additional DCpole-to-pole fault protection branches are proposed for the H3LC.The protection branchesconsist of a low conduction loss load-current carrying branch and a main breaker branch. Thedetailed configuration and operation of the protection circuit will be discussed in Section 2.2.5.2.2 Operating PrincipleThe control and modulation of the H3LC’s DSs and the AC-side cascaded FBSMs areproposed and investigated in this section. The overall control diagram of the proposed H3LCis demonstrated in Fig. 2.2. The outer-loop PQ controller and the inner-loop dq currentcontrol are not discussed in the paper since they are similar to the conventional VSC HVDCcontrollers [31], [44], [88]. The following lower-level converter control layers will be presented:(1) DS modulation.(2) AC-side FBSMs modulation, energy balancing, and voltage balancing.(3) DC-side pole capacitor balancing.(4) DC-side fault blocking capability.One of the main control schemes of the H3LC is the third-order harmonic voltage injectionto the AC-side cascaded which is used to limit the number of the FBSMs, leading to lowconduction loss. The other important feature of the proposed H3LC is the protection brancheswhich enable DC-side pole-to-pole fault blocking. The operation of the H3LC during theDC-fault is analyzed in detail in this section.For reference, the H3LC’s complete control flow diagram is presented in Fig. 2.2.28DC-pole capacitor balancing loopReference signal generationH3LCDC cablesP * Q * VDC vDCiabcsvc,abcv*abcv*abc v*abcv*3abcv*3abcV1hδδδωtωtωtSDSSDSEqn. (2.6)V1h Eqn. (2.2)V1hV3hsin+++−±+LS-PWM andSM voltagebalancing controlvDC/4∆Vabc1/V1h∆αα α1 , α2α2α1α1+SM switching generation & capacitor voltage balancingThird-order harmonic injection DS switching generationCascaded FBSMenergy balancing loop++PCCPQ current control loopvuvlvu−vl0PIPI∆vabc∆vabc3SSMSSMpi−α12pi−α2pi+α2+−+− +−vabcsiabcsvabcsvabctΣvc,abci vc,abciΣv3LC,abcv3LC,abcFig. 2.2. Control flow diagram of the H3LC.2900piωt (rad)2piv3LC,a(t)−V1hsin(ωt)v3LC,a(t)−V1hsin(ωt)−V3hsin(3ωt)(a)(b)α1Without 3rd Order HarmonicWith 3rd Order Harmonic02pi−α2pi−α1 pi+α2v3LC,a(t)V1hsin(ωt)V3hsin(3ωt)VDC12VDC12−VDC14pi23pi2VDC14−Fig. 2.3. Example voltage waveforms of the H3LC at the modulation index of V1h = 0.45VDC.2.2.1 DS SquareWave Modulation andThird-Order Harmonic Injectionto AC-side Cascaded FBSMs.The three-level T-type converter of the H3LC outputs symmetrical square-wave phasevoltages with three voltage levels: 12VDC, 0, −12VDC as shown in Fig. 2.3 (a). The switchingangle α is used to control the magnitude of the fundamental-frequency voltage component.Therefore, the DSs in the H3LC operate at a 50Hz switching frequency, leading to reducedswitching losses compared to the 150Hz SHE switching scheme used for the H2LC [69]–[72],[74]. The fundamental voltage component generated by the T-type converter, V1h, is calculatedthrough Fourier analysis asV1h =2picos (α) · VDC. (2.1)For an approximately constant DC voltage, VDC, the output voltage V1h of (2.1)may be regulatedby controlling the angle α asα = cos−1(pi2V1hVDC). (2.2)It is noted that when α = 0, the three-level voltage produced by the three-level convertercollapses into a two-level voltage. Hence, the H3LC has a theoretical peak operating voltage ofV1h =2piVDC.30From V1h in (2.1), the voltage across the phase-a cascaded FBSMs, i.e., vFB,a of Fig. 2.1, isrepresented asvFB,a(t) = v3LC,a(t)− V1h sin(ωt), (2.3)where ωt is the converter’s angular position and v3LC,a is the three-level voltage output presentedby theDSs. vFB,a, as defined in (2.3), corresponds to the solid green line of Fig. 2.3 (b). It is notedthat vFB,a exceeds the voltage envelope of±14VDC. To bound vFB,a to within±14VDC, third-orderharmonic voltage injection can be used to set a strict bound on the absolute maximum cascadedFBSM voltage, i.e.,vFB,a(t) = v3LC,a(t)− V1h sin(ωt)− V3h sin(3ωt). (2.4)If only the range ωt ∈ [0, α] is considered, vFB,a from (2.4) becomesvFB,a(t) = −V1h sin(ωt)− V3h sin(3ωt). (2.5)From inspection of Fig. 2.3 (b), the maximum value of the cascaded FBSM voltage onωt ∈ [0, α] occurs at ωt = α; therefore, if |vFB,a(α)| = 14VDC, vFB,a may be bounded by±14VDC.Hence, substituting ωt = α into (2.5) such that vFB,a(α) = −14VDC, the magnitude of thethird-order harmonic voltage may be found asV3h =14VDC − V1h sin(α)sin(3α). (2.6)2.2.2 Limits of Third-Order Harmonic Voltage InjectionFrom (2.6), it is noted that V3h is undefined for α ∈{pi3, 0}, corresponding to the operatingvoltages V1h ∈{1piVDC,2piVDC}. This can be understood since vFB,a of (2.4) experiences a31jump-discontinuity,∆vFB,a, at ωt = α of|∆vFB,a| = 12VDC − V1h sin(α)− V3h sin(3α); (2.7)when α ∈{pi3, 0}, V3h sin(3α) ≡ 0 such that third-order harmonic voltage injection isunavailable for such α. Moreover, in the neighborhoods of α ∈{pi3, 0}, V3h of (2.6) tendstoward infinity.As V3h increases, vFB,a of (2.4) increases or decreases most significantly at ωt = pi2. Hence,the value of V3h that results in vFB,a(pi2ω)≡ 14VDC is found according to, from (2.4):vFB,a( pi2ω)=14VDC⇒ 12VDC − V1h sin(pi2)−( 14VDC − V1h sin(α)sin(3α))sin(3pi2)=14VDC. (2.8)With the relationship between V1h and α from (2.2), (2.8) can be solved numerically for V1hasV1h ≈ {0.287VDC, 0.63VDC}. (2.9)The value V1h ≈ 0.287VDC defines the bound that is less than V1h = 1piVDC; to find thebound that is greater than V1h = 1piVDC, the additional maxima/minima of vFB,a are found, i.e.,those that are not the trivial solutions θs = kpi2: k ∈ Z. The values of θs corresponding to thenon-trivial local maxima/minima areθs = kpi± cos−1(√(VDC − 4V1h sin(α))(9VDC − 36V1h sin(α)− 4V1h sin(3α))2√3(4V1h sin(α)− VDC)), (2.10)where k ∈ Z. Numerically solving vFB,a(θsω)= 14VDC for V1h, where vFB,a is given from (2.4),results inV1h ≈ 0.334VDC. (2.11)Hence, the operating voltage range wherein third-order harmonic voltage injection ensures32that |vFB,a| ≤ 14VDC is defined asV1h ∈ [0, 0.287VDC] ∪ [0.334VDC, 0.63VDC]. (2.12)Therefore, to limit the cascaded FBSM sizing to ±14VDC, the H3LC’s output AC voltageamplitude is restricted to belowV1h = 0.63VDC. Moreover, from (2.12), it is noted that operationis unavailable on the intervalsV1h /∈ (0.287VDC, 0.334VDC) ∪(0.63VDC, 2piVDC](2.13)if |vFB,a| ≤ 14VDC is desired.2.2.3 DC-Side Pole Capacitor Voltage BalancingThe three-level converter uses two DC-pole capacitors — an upper and a lower, withvoltages denoted as vu and vl, respectively — connected to the midpoint of the DC side, asin Fig. 2.2. Under ideal circumstances wherein the upper and lower DC-side pole capacitorscharge or discharge equally, no extra control is required to ensure their voltage difference iszero. However, since there are practical asymmetries due to the tolerances of the H3LC’s upper,lower, and midpoint DSs, as well as to the tolerances of the pole capacitors themselves, thevoltages of the two DC-pole capacitors need extra control to be balanced to their rated valuesof 12VDC.The DC-pole capacitor voltages can be regulated using asymmetrical modulation of theupper- and lower-position DSs. That is, rather than the single switching angle α in Fig. 2.2,two switching angles, α1 and α2, are used for the upper and lower-position DSs, respectively.Therefore, v3LC,a(t) = vu for ωt ∈ [α1, pi − α1] and v3LC,a(t) = −vl for ωt ∈ [pi + α2, 2pi − α2].This asymmetry causes a DC voltage to be present at v3LC,j , thus driving a charging current tomaintain the DC pole capacitor voltages.A PI controller is used to control the different of vu and vl to zero by generating an33incremental switching angle∆α which is appended to the switching angle α such that α1 =α +∆α and α2 = α−∆α.2.2.4 AC-Side Cascaded FBSM Energy Balancing and FBSM CapacitorVoltage BalancingAs shown in Section 2.2.1, the AC-side cascaded FBSMs do not absorb nor generate realpower; rather, they function only to remove the non-fundamental harmonic voltage from thethree-level voltage output at v3LC,j . Therefore, no net energy deviation is expected at each cycle.However, due to the semiconductor on-state losses, snubber resistances, as well as the leakageeffects of the SM capacitors, the mean voltage of the summation of the jth phase of FBSMs’capacitors, i.e.,v sumc,j =12pi∫ 2pi0N∑i=1vic,j(ωt) dωt, (2.14)deviates cycle-to-cycle. Therefore, an injection of a small fundamental-frequency voltage intoeach set of cascaded FBSMs ensures the total energy of the FBSMs remains constant in steadystate. A PI controller may be used to generate the three fundamental voltage injections,∆va,b,c,to maintain the FBSM capacitor voltages to the set-point of 14VDC, as shown in Fig. 2.2.Still, the individual capacitor voltages must also be maintained around their set-points of14NVDC. This is accomplished like it is with the MMC: depending on the current direction andthe number of FBSMs to be inserted,Nins, either the FBSMwith the maximum or the minimumvoltage is either inserted or bypassed, such that the average voltage of the FBSM capacitorsremains tightly balanced around their set-point. The signalNins is generated by either nearestlevel modulation (NLM), or level-shifted pulse-width modulation (LS-PWM); the selection ofthe modulation method is determined by the number of FBSMs. A large number of FBSMssimplifies the controller since NLMmay be used, which only requires rounding the referencesignals, vFB,j .342.2.5 DC Fault ProtectionAs stated, the voltage supplied by the normal operation FBSMs of Fig. 2.1 are insufficient toblock the AC-side voltage in the event of a DC-side fault. During bolted DC-side short-circuitpole-to-pole faults, the DC-side voltage reduces to zero. In such scenarios, the AC-side line-to-line voltages drive rectified fault currents through the upper and lower DSs and into the faultlocation. Therefore, the line-to-line voltages each drive fault currents through two phases, suchthat two phases appear in series with respect to the line-to-line voltages. With a peak ratedphase-to-neutral voltage of V1h = 0.63VDC, it is required that two phases work in tandem tosupply the peak line-to-line voltage, i.e.,Vblock =√3 · 0.63VDC⇒ Vblock ≈ 1.09VDC. (2.15)However, two phases of the normal operation FBSMs may provide an equivalent blockingvoltage of 12VDC since they are individually rated for 14VDC. Hence, the protection branchesneed to supply the remaining voltage, i.e.,Vprot. =12(1.09VDC − 12VDC)≈ 0.3VDC. (2.16)The protection branch topology is shown in Fig. 2.4 (a), while two topologies for itsmain breaker are shown in Figs. 2.4 (b) and (c). The protection branch may use either series-connected FBSMs or a single asymmetric FBSM. In the former case, there is a requirement of0.3VDC14VDC= 120% more equally-rated FBSMs to supply the required blocking voltage; in thelatter case, one asymmetric FBSMmay be used to supply the required blocking voltage. Theadvantage of using one asymmetrical FBSM is the reduced numbers of IGBTs and FBSMsleading to lower semiconductor cost and higher converter compactness. In Figs. 2.4 (b) and35FBSM FBSM FBSMNormal Operation BranchMain BreakerProtection BranchMainBreakerFMSFBSM FBSM FBSM(a)(b) (c)+VprotvprotvprotFig. 2.4. The protection branch topology to provide the necessary reverse blocking voltage against theAC-side for DC-side fault protection. (a) Protection Branch scheme. (b) Protection branch employingseries-connected FBSMs. (c) Protection branch employing one large asymmetric FBSM.(c), vprot. is the output voltage of either topology of main breaker, which is determined by thedirection of the current flowing through them and has a peak value of Vprot..It is noted that if the protection branch topology of Fig. 2.4 (b) is used, the protection-branchcascaded FBSMs can be used during normal operation to enable the operating voltages of (2.13),thereby extending the AC voltage range of the H3LC. While the third-order harmonic voltageinjection scheme is unavailable for the AC voltages in the neighbourhoods of V1h = 2piVDCand V1h = 1piVDC (corresponding to the switching angles α = 0 and α = pi3, respectively), theprotection branches can be used in these neighbourhoods to enable high-fidelity AC voltagegeneration without the injection of V3h. Moreover, the protection branches with the cascadedFBSMs have the important benefit of increasing the H3LC’s reactive power compensationcapability, since the additional protection-branch cascaded FBSMs can be operated in serieswith the normal-operation cascaded FBSMs.The control sequence for the proposed DC fault blocking method is summarized as follows:(1) A DC pole-to-pole fault is detected by measuring the DC-side voltage drop or DC-sidesurge/discharging current. Upon the DC fault detection, all the DSs and FBSMs inthe normal operation branches are blocked immediately. The anti-series IGBTs in the36protection branch are also blocked to commutate the AC currents to the main breakers,which are bypassed in normal operation.(2) Once the AC currents through the anti-series IGBTs promptly decrease to zero, the FMSsare opened to isolate the anti-series IGBTs in the protection branches.(3) After the FMSs open, the IGBTs in the FBSMs or asymmetrical FBSMof themain breakersare turned off to provide the reverse blocking voltages that halt the short-circuit currents.During normal operation, the FBSM capacitors of the main breaker in Figs. 2.4 (b) or (c)are bypassed. The capacitor energy stored in the SM capacitors slowly dissipates due to theleakage current of the IGBT modules, which causes the SMs’ capacitors to slowly discharge. Inorder to regulate the SM capacitor voltages of the main breaker, twomethods can be considereddepending on implementation complexity and cost:(1) An external low power AC/DC rectifier can be used to charge the SM capacitors, asshown in Fig. 2.5. In Fig. 2.5 (a), the AC/DC rectifier outputs a low DC voltage, equal tothe nominal voltage of the rated SM capacitor voltage, e.g., 15 kV. Each of the cascadedSMs’ capacitors of the main breaker can be charged sequentially to vSM as shown inFig. 2.5(a). If the asymmetrical FBSM of Fig. 2.4 (c) is used in the main breaker, theexternal AC/DC rectifier needs to be rated for 0.3VDC to charge the asymmetrical FBSMcapacitor as shown in Fig. 2.5(b).(2) The second method of regulating the SM capacitor voltages of the main breaker [i.e.,Fig. 2.4 (b)] is to insert the cascaded FBSMs of the main breaker into the AC-side of theH3LC periodically whenever a SM capacitor voltage in the main breaker is lower thana voltage tolerance level (e.g., 80% of the rated SM voltage). The converter controllerused for the AC-side cascaded FBSM energy balancing and the SM capacitor voltagebalancing in Section 2.2.4 can be used to regulate the SM capacitor voltages of the mainbreaker. This method requires no additional hardware compared to the first method andthus may be preferred.37+(a) (b)Rcharge +0.3VDC+vSM+vSM+vSM+vSM+vSMRchargeFig. 2.5. External AC/DC rectifier charging the FBSMs in the main breaker. (a) Cascaded FBSMscase (the red part shows the charging current flows through one arbitrary SM capacitor). (b) Oneasymmetrical FBSM case.2.3 Performance EvaluationThe dynamic performance of the proposed H3LC is evaluated under two different scenarios:normal operation and DC-side pole-to-pole fault. The H3LC has a power rating of 1096MVAat the rated DC-side voltage of 600 kV. The H3LC is modeled in MATLAB/Simulink’s Sim-PowerSystems toolbox using the time step of 20 µs. The detailed switching-based convertermodel is used where the IGBT modules are represented by a piece-wise linear semiconductormodel using the slope resistance (rT or rD) and the device saturation voltage (VT0 or VD0). Thesimulation parameters are presented in Table 2.2, while the IGBT parameters used for the lossanalysis are presented in Chapter B in Table B.3. A 100 km transmission line, based on thepi-section model, is used to connect the DC-side of the converter to an external DC voltagesource of 600 kV. The H3LC has 22 FBSMs in each AC phase; 10 FBSMs are used in normaloperation and the other 12 FBSMs are used for DC pole-to-pole fault blocking as discussed inSection 2.2.5.2.3.1 Normal OperationIn this case study, the H3LC is controlled to transmit real power between AC and DC sides.Fig. 2.6 illustrates the steady-state and transient responses of the converter as it changes itspower outputs. At t = 0 s, the converter follows a ramp command to increase its power output38TABLE 2.2Simulation ParametersSimulation parametersMaximum power rating 1096MVAMaximum P 1000MWMaximumQ 500MVARDC-side pole capacitorcapacitance500 µFFBSM capacitorvoltage15 kVFBSM capacitorcapacitance1.6mFAC-side inductance 25mHDC-side inductance 25mHTransformer leakageimpedance0.001+ j0.18 puTransformer windingratio350 kV/400 kVfrom zero to P = 900MW and Q = −200MVAR. At t = 0.4 s, the H3LC is commandedto operate in rectifier mode and to output the real power P = −900MW and the reactivepowerQ = 200MVAR. It is observed in Fig. 2.6 (a) that the H3LC can control the real andreactive power effectively. The DC-side voltage is shown in Fig. 2.6 (b) in which the small DCvoltage variation for different loading conditions is due to the DC line resistance and powerflow direction.In Fig. 2.6 (c), ten FBSM capacitor voltages from phase-a are shown to be within±10% ofthe average capacitor voltage. The converter line-to-line voltages measured at the converterside of the transformer and the converter currents at the PCC are illustrated in Figs. 2.6 (d)and (e) during steady-state inverter mode from 0.2 s to 0.26 s. As observed in Figs. 2.6 (d) and(e), the converter delivers smooth three-phase sinusoidal voltage and current to the AC grideven with only 10 FBSMs per phase. The phase-a cascaded voltage generated by the 10 FBSMsis shown in Fig. 2.6 (f) in which the third-order harmonic voltage injection is used to controlthe cascaded output voltage to be within±14VDC. The average value of the ten FBSM capacitor39voltages from phase-aare shown in Fig. 2.6 (g). Figs. 2.6 (c) and (g) verify the effectiveness ofthe cascaded voltage and FBSM balancing controls as proposed in Fig. 2.2.2.3.2 DC-Side Fault OperationThe performance of the H3LC in the event of DC pole-to-pole fault is presented in thissubsection. It is assumed that the H3LC initially operates in steady state with P = 900MWand Q = −200MVAR. The DC pole-to-pole fault occurs in the middle of the 100 km DCtransmission line at 0.2 s for a duration of 150ms. At 0.35 s, the DC-link voltage is graduallyincreased to 600 kV. Thereafter, the real and reactive powers are restored to the prefaultsteady-state values.The DC fault transients of the H3LC are shown in Fig. 2.6. It is observed in Figs. 2.6 (a)0.80.40-0.4-0.8P (GW) and Q (GVAR) PQ(a)640620600580560 (b)13151617140.2 0.22 0.24 0.26 1.00 1.02 1.04 1.06(c) 1315161714FBSM CapacitorVoltages (kV)DC-side Voltage (kV)71311915170.0 0.2 0.8 1.0 1.20.4 0.6Time (s)40Chainlink Voltage (kV)0-150-10050-50100150()FBSM Capacitor VoltageSummation (kV)14.415.014.814.615.215.4Converter Line-to-lineVoltages (kV)0-600-400200-200400600(d)Current at PCC (kA)-2.00-1.01.02.00.20 0.21 0.24 0.25 0.260.22 0.23Time (s)0.30 0.31 0.330.32Time (s)(e)(g)Fig. 2.6. Converter performance in normal operation. (a). Real and reactive powers. (b). DC-sidevoltage. (c). Cascaded FBSM capacitor voltages. (d). Three-phase output line-line voltages. (e). OutputAC currents at PCC. (f). Phase-a cascaded voltage. (g) Phase-a average value of the ten FBSM capacitorvoltages.41and (b) that the real and reactive powers, and the DC-side voltage are reduced to zero duringthe fault. Due to the discharging transient of the two DC-pole capacitors of the three-levelconverter, the DC fault current experiences a negative surge current with the peak value of−64 kA at 0.202 s. It is assumed that the DC pole-to-pole fault is detected using the DC surgecurrent at 0.202 s, i.e., 2ms after the DC fault occurrence. Therefore, the DSs of the three-levelconverter, the two anti-series IGBTs in each of the protection branches, and the 10 FBSMsin each of the normal operation branches are blocked at 0.202 s. The AC currents are thencommutated from the two antiseries IGBTs to the 12 FBSMs in each of the protection branches.After an additional 2ms, the FMSs open to isolate the anti-series IGBTs so that the FBSMs inthe main breakers can then be blocked.Due to the use of the cascaded AC-side FBSMs, the H3LC can block DC pole-to-pole faultsimilar to the H2LC [69]. The capacitor voltages of the FBSMs are illustrated in Fig. 2.6 (e)which shows that the capacitor voltages experience slight increase due to the charging of theAC currents. The transient currents in the main breaker, as shown in Fig. 2.6 (f), are due tothe following converter operations: At 0.202 s, the DC fault is detected, which triggers theprotection logic to turn off the anti-series IGBTs. The main breaker will then take over theAC short-circuit current from the anti-series IGBT branch. Since the FBSMs in the normaloperation cascaded are blocked at 0.202 s, the AC short-circuit current gradually decreasesto zero due to the initially small AC voltage applied by the AC grid. When the AC voltageincreases, the reverse voltage provided by the FBSMs in the normal operation cascaded isinsufficient to block the AC voltage as they provide the blocking voltage of 14VDC. Therefore,the AC current increases again from zero. Since the FMS opens at 0.204 s, the IGBTs in themain breaker are turned off, which, together with the normal operation cascaded FBSMs,provides enough blocking voltage to suppress the AC short-circuit current.Fig. 2.6 shows that the H3LC is capable of handling DC-side faults. The DC-side faultwhich is incident at t = 0.2 s is quickly handled by the fault handling sequence of Section 2.2.5.It is seen in Fig. 2.6 (a) that the real and reactive powers quickly fall to zero, following the drop42of DC voltage in Fig. 2.6 (b). The DC-side current is shown to have a large spike in Fig. 2.6(c), as the DC pole capacitors rapidly discharge. The current to the PCC is seen to quicklybe blocked as the H3LC enters blocking mode in Fig. 2.6 (d). The FBSM voltage is seen toabsorb the remnants of the AC-side line current as the FBSMs slightly charge in Fig. 2.6 (e).In Fig. 2.6 (f), the current flowing through the protection branch is shown as the DC faultblocking sequence is initiated.2.3.3 HardwareVerificationAlthough the full-scale detailed switching-based converter model is generally accepted asan accurate representation of high-power converters for HVDC applications, the experimentalresults obtained from a scaled-down hardware converter are used to validate the concept of theproposed H3LC in this section. An MMC Testbench (OP1210) from OPAL-RT Technologies®-0.80.40-0.4P (GW) and Q (GVAR)60040020000-20-40-60DC-side Voltage (kV)DC-side Current (kA)0.1 0.2 0.5 0.60.40.3Time (s)-0.6-0.20.60.21.00.2 0.202 0.204 0.206(a)PQ.6 1.8vuvu+vl vl(b)-60-40-2000.2 0.22 0.24 0.26iDC=-64 kA(c)432.01.00-1.0-2.013151711970.1 0.2 0.5 0.60.40.3Time (s)Current at PCC (kA)FBSM CapacitorVoltages (kV)0.2 0.202 0.204 0.2062.0-2.00-1.01.0(d)15141617130.2 0.202 0.204 0.206(e)Main Breaker Current (kA)0-1.00.5-0.51.00.2 0.201 0.205 0.2060.202 0.2040.203Time (s)()FMS opened &protection FBSMs blockedFault detection & normal operation FBSMs blockedFig. 2.6. Converter performance to the DC-side pole-to-pole fault event. (a) Real and reactive powers.(b) DC-side voltage. (c) DC-side current. (d) AC currents at PCC. (e) cascaded FBSM capacitor voltages.(f) Three-phase cascaded currents flowing through the main breaker.RT Technologies [89] is modified to implement the H3LC, as shown in Fig. 2.7. Each OP1210module has ten cascaded FBSMs which are used as the AC-side cascaded FBSMs in each phase.The three-phase T-type converter is prototyped in house using discrete components includingMOSFETs, their gate drivers, DC-link capacitors, and fiber optic communication links. TheDC-side of the H3LC is connected to Chroma 62100H DC power supply with the DC voltageof 200 V.The AC terminals of the H3LC are connected to three-phase Wye-connected loadresistors of 12 Ω per phase.The digital control of the H3LC is based on Xilinx Kintex-7 FPGA integrated in OP4510, areal-time power electronic simulator and controller developed by OPAL-RT Technologies®-44Fig. 2.7. Experimental setup of the proposed H3LC.RT Technologies. The modulations of the three-level T-type converter and AC-side FBSMs(OP1210) are implemented using the RT-XSG Blockset in MATLAB/Simulink and RT-LAB11.3.6, which compiles and loads the Simulink controller model into the Kintex-7 FPGA.Switching signals from Kintex-7 are coded using series communication protocol and aretransmitted optically to the second FPGA, Artix 7, which performs switching signal decodingand implements dead-time to the MOSFETs. The sampling rate of the SM capacitor voltageand the AC-side current measurements is 20 µs. The 12-bit 500 ksps serial sampling ADCs areused for the SM voltage and converter AC current measurements.-8-40843.28 3.285 3.29 3.295 3.30 3.305 3.313.275Time (s)(a)Converter line-to-line voltage (80V/div)AC-side chainlink voltage (50V/div)45Time (s)AC Output Current (A)-8.0-4.00.08.04.03.28 3.285 3.29 3.295 3.30 3.305 3.313.275Time (s)3.28 3.285 3.29 3.295 3.30 3.305 3.313.275(b)Sum of SM Voltages (V)(d)(c)SM Voltages (V)4.44.64.44.85.05.25.85.65.43.276 3.278 3.280 3.282 3.284 3.286 3.2883.274Time (s)Fig. 2.8. Experimental results. (a) Converter AC line-to-line voltage and cascaded FBSM output voltage.(b) Converter three-phase AC output currents. (c) Phase-a ten FBSM capacitor voltages. (d) Phase-asum of the ten FBSM capacitor voltagesThe experimental results of the H3LC prototype are shown in Fig. 2.8. In Fig. 2.8 (a), theconverter AC line-to-line and cascaded FBSM voltages are captured by a Tektronix oscilloscope.It is observed in Fig. 2.8 (a) that the AC cascaded voltage has a waveform shape similar tothe simulated one in Fig. 2.6 (e). The three-phase converter AC output currents are wellbalanced and sinusoidal, as shown in Fig. 2.8 (b), which is consistent with the converter line-to-line voltage in Fig. 2.8 (a). The phase-a individual and the sum of the ten FBSM capacitorvoltages are shown in Figs. 2.8 (c) and (d), respectively, which validate the FBSM capacitor46voltage balancing control in Section 2.2.4 and the simulated FBSM capacitor voltage ripples inSection 2.3.1.2.4 Component, Loss, and Energy AnalysisHere, the nominal energy storage requirements and the semiconductor losses of the H3LCare briefly compared against the MMCs with HBSMs, MBSMs (i.e., the “mixed-bridge submod-ule”, which is an equal mixture of HBSMs and FBSMs), and FBSMs, as well as the H2LC [69]and EO-AAC [67]. In Chapters A and B, the methods to derive the nominal energy storagerequirements and the semiconductor losses will be described in detail. The results of theupper-level comparison, as well as the energy storage requirement and semiconductor lossanalyses, are shown in Table 2.3.For the comparison, the 4.5 kVWestcode T1800 GB45A IGBT module [90] is used, whereits on-state and switching parameters are presented and explained in Section B.3 and tabulatedin Table B.3. The IGBT is assumed to be de-rated by a factor of 2.5 kV:4.5 kV, as in [83], whichgives a practical safety factor.The loss and energy analyses of Table 2.3 assume that the converters are operated at theirnominal operating voltage, which is defined as the voltage that enables the AC voltage toincrease by 10% without exceeding the converters’ maximum AC voltage [91]. The MMCs’maximum AC voltage is given as V1h = 1√3VDC, which gives the nominal operating voltageof V1h = 0.523VDC; the H2LC’s maximum AC voltage is V1h = 2piVDC, giving it the nominalvoltage of V1h = 0.577VDC. The EO-AAC’s nominal operating voltage is set at its maximum,V1h =23VDC, due to its natural ability to operate above it. Lastly, the H3LC’s maximum ACoperating voltage is defined as V1h = 0.63VDC, such that its nominal operating voltage isV1h = 0.573VDC.The results show that the H3LC experiences 0.10% fewer losses than the MBSM-MMC,while having 0.09% more losses than the HBSM-MMC, where it is reiterated that the HBSM-MMC is considered the standard of high efficiency. Its efficiency closely rivals the EO-AAC’sand far surpasses the H2LC’s.47TABLE 2.3Comparison of Selected ConvertersConverter typeHBSMMMCMBSMMMCFBSMMMCH2LC EO-AAC H3LCGeneralconvertercomparisonMax AC voltage, V1h (×VDC) 1/√3 1/√3 1/√3 2/pi 2/3 0.63DC-side voltage 600 kV 600 kV 600 kV 600 kV 600 kV 600 kVNo. of IGBTs 2880 4320 5760 4392 4800 3744No. of 15 kV SMs 240 240 240 66 160 66DC-side pole capacitor No No No Yes No YesDC fault ride-through No Yes Yes Yes Yes YesLossanalysisAC voltage, V1h (×VDC) 0.523 0.577 2/3 0.573SM Pcond (MW) 3.68 5.62 7.56 3.62 3.77 1.75SM Psw (MW) 2.30 2.30 2.30 2.06 0.95 1.31DS Pcond (MW) - - - 3.53 1.80 3.42DS Psw (MW) - - - 0.77 - 0.44Total Loss (MW) 5.98 7.92 9.86 9.98 6.52 6.92Percentage Loss 0.60% 0.79% 0.99% 1.00% 0.65% 0.69%EnergyanalysisAC voltage, V1h (×VDC) 0.523 0.577 2/3 0.573Enom(J · radVA · s)9.565 3.03 4.50 1.106Normalized to MMC 1.00 0.317 0.471 0.116Moreover, and most importantly, the H3LC is shown to have, by far, the least energystorage requirements of any of the tested converters, requiring approximately one-third of theother converter of its class — the H2LC. Its small energy storage requirement implicates theH3LC’s use in applications that demand a volume-limited converter station. Requiring suchsmall energy (only approximately one-tenth of the MMC’s) while using fewer IGBTs than theMBSM-MMCmakes the H3LC an attractive choice for such applications.2.5 ConclusionThis chapter introduced the novel H3LC, which is a significant addition to the field of VSC-HVDC.The H3LC is a functionally complete VSC-HVDC converter with DC fault blockingand a small converter footprint. Compared to the H2LC, the H3LC has half as many normal-operation FBSMs, which enables it to have 31% less semiconductor losses (9.98MW comparedto the H3LC 6.92MW). Compared to theMBSM-MMC, the H3LC has 13% less semiconductor48losses when the converters are operated at their optimal operating voltages. Compared to anyof the tested converters, the H3LC has a very small energy storage requirement. Even comparedto the H2LC, which was proposed as a compact and DC-fault tolerant solution to the HBSM-MMC’s shortcomings, the H3LC features a 63.4% reduction in energy storage sizing, whichis enabled by its low pole-to-pole energy storage requirements (as provided in Section A.3).Moreover, from a component-count perspective, the H3LC requires approximately 15% fewerIGBT modules than the H2LC and 13% fewer than the MBSM-MMC.An HVDC-scale simulation of the H3LC with a 600 kV DC-side voltage and a power flowof 1096MVA was performed, which verified the H3LC’s operating principle as described inSection 2.2. The HVDC simulations were complemented by a lab-scale hardware verificationthat further proved the HVDC’s ability to invert DC voltage.In Section 2.2.5, a novel DC-fault blocking scheme was presented that uses additionalFBSMs and FMSs to quickly and effectively block AC-side fault currents during DC-side faultscenarios. The fault blocking mechanism was proven by simulation in Section 2.3.2. TheFBSMs contained within the H3LC’s novel “protection branches” may also be used to extendthe H3LC’s working operating voltage by functioning as a series-connected STATCOM.With its high efficiency, low energy storage requirements, and DC fault ride-throughcapability, the H3LC is expected to benefit the area of VSC-HVDC and should be researchedfurther.493.Thyristor-Based Hybrid Three-Level and ModularMultilevel ConverterRecently, research efforts have been focused on integrating high power thyristors withthe VSCs to increase overall converter efficiency and compactness [79], [80], [92]–[95]. Theactive-forced-commutated (AFC) thyristor-bridge VSCs were proposed in [92]–[94], which usea so-called commutation full-bridge chain-link (C-FBCL) to commutate current away from athyristor. Thyristor-based VSCs combine the benefits of VSC-HVDC with the higher efficiencyand reliability of LCC-HVDC. In addition, their fast control response, ability to support weakor passive networks, DC fault resilience, and high compactness make the thyristor-basedVSCs a viable alternative to the HBSM-MMC. Despite these benefits, the thyristor-basedVSCs [92]–[94] require significant AC-side filtering. Moreover, since the C-FBCL carriesload current in the zero-voltage state, large IGBT conduction losses occur for the converteroperations in low modulation indices.This chapter presents and expands upon the thyristor-based hybrid three-level converter(TH3LC) that was proposed in [84], [85].The TH3LC is inherently DC fault tolerant with reduced converter losses compared to theHBSM-MMC. Being composed of two stages, i.e., the TH3LC’s quasi-three-level converter actsas the main power stage, while the AC-Side FBSM Cascaded FBSMs as the active filter stage.The main power stage is composed of anti-parallel thyristor-based DSs and the CommutationBranch Cascaded FBSMs. The DSs are operated at a low frequency to generate a quasi-three-level trapezoidal voltage. The Commutation Branch’s cascaded FBSMs commutate currentaway from the thyristors for their turn-off and enables a stepped-trapezoidal voltage betweenthe thyristors’ conduction states for their zero-voltage-switching (ZVS), which makes theirturn-on and -off losses negligible. The AC-side cascaded FBSMs remove harmonics fromThe journal paper, “A Low-LossThyristor-Based HybridThree-Level andModular Multilevel Converter withDC Fault Blocking Capability for HVDC Transmission” [84] was accepted into the IEEE Open Access Journal ofPower and Energy, and [85] received the Best Paper Award at 2019 IEEE IEMCON conference.50the trapezoidal three-level output voltage, thus eliminating the need of bulky AC-side passivefilters.3.1 TopologyThe per-phase topology of the TH3LC is presented in Fig. 3.1, where the subscript j cantake values j ∈ {a, b, c}. The TH3LC is a significant modification of the H3LC that useshighly efficient thyristor-based DSs to conduct the majority of the current flowing throughthe converter. Using anti-parallel thyristors with fundamental-frequency switching insteadof series-connected IGBTs enables the TH3LC to efficiently perform bidirectional AC/DCpower conversion. Both anti-parallel thyristors of the upper- and lower-position DSs — i.e.,DSs{T pu,j, Tnu,j}and{T pl,j, Tnl,j}, respectively — are rated for the entire DC-side voltage, VDC,while the midpoint DSs,{T pm,j, Tnm,j}, are rated for 12VDC. Despite being the most efficientcommercially available semiconductor switching device, thyristors have only one degree ofcontrol freedom: they can only be turned on, while their turn-off is possible only once thecurrent flowing through them reduces to below the holding current, IH, for a time of at least Tq(both parameters are given in typical thyristor datasheets).The TH3LC uses a Commutation Branch, as in Fig. 3.1, to force, i.e., commutate, currentsaway from the presently conducting DS, thereby enabling reliable turn-off for the thyristors.For each of the three phases, the Commutation Branch consists of a set of cascaded FBSMs(CFBs), used to generate a commutation voltage, vcomm, and an inductor, Lcomm, that ensuresthat the thyristors’ critical rate-of-rise of the commutation voltage, dvdt crit, is not exceeded. Ifthe dvdtacross a thyristor exceeds dvdt crit, it will erroneously turn-on.It is noted that the superscript i ∈ {p, n} of the DSs denotes whether a positive (p) or nega-tive (n) commutation voltage, vcomm, at vCFB,j serves to reverse-bias the presently-conductingthyristor. For example, if current is flowing through any of the DSs with superscript p, thecommutation voltage should be positive at turn-off; if the current flows through any DS withsuperscript n, the commutation voltage should be negative for turn-off.On the AC-side, the TH3LC uses the AC-side Cascaded FBSMs (FBs) of Fig. 3.1 to remove51LDCDshRshLcommFBSM FBSMCommutation BranchCommutationCascaded FBSMsiCFB,jvT,jCDCVDCiu,jil,jvCFB,jim,jCDC+vSMvcS1S2S4S3−ivjvavbvcijFBSM FBSMAC-SideCascaded FBSMsvFB,jTu,jp Tu,jnTm,jnTm,jpTl,jpTl,jnQuasi-Three-Level ConverterFig. 3.1. The TH3LC topology.all harmonics except the fundamental and optionally third-order harmonics. The AC-sideCascaded FBSMs, with third-order harmonic voltage injection, generate the phase-j voltagevFB,j(t) = vT,j(t)− V1h sin(ωt+ φj)− V3h sin(3ωt), (3.1)where vT,j is the quasi-three-level voltage generated by the coordination of the CommutationCascaded FBSMs and the DSs and φj ∈{0,−2pi3, 2pi3}is the three-phase balanced phase-shifts.The TH3LC is inherently tolerant to DC-side pole-to-pole short-circuit faults without therequirement of additional hardware such as the H3LC’s “Protection Branches.” As thyristorscan block voltages bidirectionally, DC fault events require that the commutation branches turnoff the DSs, which functionally isolates the AC- and DC-sides. Once isolated, the FBs andCFBs may operate together to supply reactive power to the AC-side grid during DC faults.523.2 Operating Principle3.2.1 Thyristor Turn-OFFThe Commutation Cascaded FBSMs (CFBs) are controlled to not only enable the thyristors’reliable turn-off, but to also enable their turn-onwith zero-voltage-switching (ZVS). In general,the voltages to be generated by the CFBs, vCFB,j , equal vT,j except during the DS switchingintervals, during which vCFB,j generates an additional commutation voltage, ±vcomm, thatreverse-biases the presently conducting DS. In [84], [85], the value of vcomm was chosen as 5%of 12VDC, although smaller or larger values can be chosen depending on the voltage deviationof the CFBs as well as the value of Lcomm.To enable ZVS for the DSs, the CFBs step between the three DS voltage levels of vT,j thatcorrespond to the DSs’ on states, i.e.,−12VDC, 0, and 12VDC, such that the value of vT,j duringthe intervals between the DSs’ on states changes linearly between these voltage levels. Therefore,the voltage at vT,j is trapezoidal, where the interval and steepness of the transitions — i.e., and 12VDC, respectively — is a design parameter.To minimize the amount of current flowing through the CFBs, the rate-of-change of theCFBs’ output voltage, v′CFB,j , which has the peak absolute value of12VDC, should be maximizedwithin the bounds of dvdt crit. Doing so minimizes the on-time of the CFBs and hence the overalllosses of the converter.Generation of the three-level trapezoidal voltage at vT,j requires proper modulation of theCFBs. Fig. 3.2 outlines theoretical voltage and current waveforms for each of the DSs andthe CFBs for the illustrative case of unity power factor operation. The process to commutatecurrent from one thyristor to the next is outlined as follows. It is assumed that the phase currentis initially flowing through any of the upper, middle, or lower thyristors. A commutationcommand is issued at t1 of Fig. 3.2, which presents the case for phase-a. First, interval (i) ofFig. 3.2 is explained, which corresponds to the turn-off of the midpoint DS and the turn-on ofthe upper DS.53t1(i)t3 t4t2 t1 t3 t4t2 t1 t3 t4t2 t1 t3 t4t2v CFB,a (θc) v u,a (θc) i CFB,a (θc) i a (θc) v m,a (θc) i u,a (θc) i m,a (θc) v l,a (θc) i l,a (θc) ia^−ia^0ia^−ia^0ia^−ia^0ia^−ia^0ia^−ia^0v T,a (θc) pi 2pi021 pi23 pi021VDC21VDC−021VDC21VDC−021VDCVDC021VDCVDC021VDC21VDC−(ii) (iii) (iv)Fig. 3.2. Detailed and idealized voltage and current waveforms through the TH3LC DSs and CFB.54(i–1) [t1, t2]: With the unity power factor current, at t1, the current im,a is flowing throughT pm,a. Since current is flowing through the DS with the superscript p, vCFB,a increasesby vcomm at t = t1, which causes im,a to decrease at a rate ofdicommdt=vcommLcomm. At theinstance t2, the thyristor current im,a falls below its holding current, IH. Therefore, it isnoted that during the commutation time, Tcomm = t2 − t1, the added voltage of the CFBs,vcomm, does not appear in vT,j since the back EMF induced across Lcomm equals vcomm.(i–2) [t2, t3]: Once im,a falls below the holding current at t2, the commutation voltage, vcomm, issustained for an additionalTqwhich, as stated, is the thyristor turn-off time duringwhichthe thyristor current must be held below IH until turn-off is ensured. The turn-off timeis defined herein as Tq = t3 − t2. During this interval, vcomm appears in the three-leveltrapezoidal voltage at vT,j .(i–3) [t3, t4]: At t3, the midpoint DS is reliably turned off such that the CFBs are commandedto generate the stepped-trapezoidal voltage from vCFB,a = 0 to vCFB,a = 12VDC over aninterval equal to t4−t3 = ω , where ω is the fundamental frequency. At t4, vCFB,a =12VDCsuch that the upper DS is turned on under ZVS.The next interval explained is interval (iv).(iv–1) [t1, t2]: During interval (iv), ia is negative and therefore il,a = ia such that current flowsthrough the lower DS T nl,a. Since the current is flowing through a DS with superscript n,the CFBs decrease their output voltage by vcomm at t1. The lower DS current decreasesuntil it falls below its holding current at t2.(iv–2) [t2, t3]: Once il,a falls below the holding current at t2, the commutation voltage,−vcomm,is sustained for an additional Tq until turn-off is ensured.(iv–3) [t3, t4]: At t3, the lower DS is reliably turned off such that the CFBs are commanded togenerate the stepped-trapezoidal voltage from vCFB,a = −12VDC to vCFB,a = 0 over an55interval equal to t4 − t3 = ω , where ω is the fundamental frequency. At t4, vCFB,a = 0such that the midpoint DS is turned on under ZVS.3.2.1.1 Natural Commutation EventIf the DS current naturally changes polarity, both thyristors are in the on state until Tq afterthe polarity reversal elapses. Hence, applying vcomm to turn-off the DS at t1 would generate ashort-circuit current through the DS that experienced the natural commutation event, limitedonly by Lcomm and the CFBs’ and DSs’ on-state resistance. Therefore, if there is a natural DScurrent reversal within Tq prior to t1, the request to trigger on the DS is rejected; instead, theCFBs carry the phase current.To explain this concept, consider Interval (i) of Fig. 3.2. Consider that the phase currentchanges from being positive to negative at the instance t0, where t0 ∈ [t1 − Tq, t1]. In such acase, the midpoint DS T pm,a conducts current until t = t0, at which point Tnm,a is requestedto be triggered on. Since t0 is within Tq of t1, the request is rejected such that the CFBs arecommanded to carry the phase current on the interval t ∈ [t0, t1]. It is noted that operatingat power factor angles where this scenario occurs negatively affects the TH3LC’s efficiency —since the IGBTs will conduct for longer — and hence should be avoided.3.2.2 Sinusoidal Voltage GenerationIn comparison to the H3LC, which generates square waves at the output of the DSs, theTH3LC generates trapezoidal output voltages at the output of its quasi-three-level converter.The voltages produced by the quasi-three-level converter and by the AC-side Cascaded FBSMs(FBs) are seen in Fig. 3.3.As can be seen from Fig. 3.2, the function of the Commutation Branch is to provide afree-wheeling current path to reverse bias the previously-conducting DSs, and to provide acontrolled transition state between the voltage levels±12VDC ↔ 0, which enables the switchinglosses of the thyristor DSs to become negligible.For sinusoidal output voltage generation, we first begin with the Fourier expansion of v∗T,a,56 2pi−αpi−α pi+α αv*T,a (t) − V1hsin(ωt) − V3hsin(3ωt) v*T,a(t) − V1hsin(ωt) v*T,a(t) V1hsin(ωt) V3hsin(3ωt) 021VDC21VDC−041VDC41VDC−pi 2pi0 21pi 23piωt (rad)(a)(b)Fig. 3.3. Example voltage waveforms of the TH3LC at the operating voltage V1h = 0.62 with atrapezoidal slope duration of  = 0.1 rad.where the ·∗ superscript denotes the trapezoidal voltage at vT,j without the four instances of the±vcomm during the turn-off intervals of duration Tq as in Fig. 3.2. The shape of the voltage v∗T,a,as in Fig. 3.3 (a), is defined by the two variables, α and , such that kpi ± α : k ∈ Z defines thecenter of each trapezoidal voltage transition of duration . Hence, the Fourier expansion ofv∗T,a is given asv∗T,a(t) =2VDCpi∑n=1,3,5,...[1n2sin(n(2α + )2)− sin(n(2α− )2)]sin(nωt). (3.2)The amplitude of the fundamental-frequency voltage component, V1h, is then given asV1h =4VDCpicos(α) sin( 2). (3.3)From (3.3), it is noted that the minimum operating voltage, V min1h , for each value of  is given asV min1h =4VDCpicos(pi2− 2)sin( 2)=4VDCpisin2( 2). (3.4)57Under the assumption of a fixed transition duration, , the value of V1h of (3.3) can beregulated by adjusting the angle α byα = cos−1(pi4VDCV1h csc( 2)). (3.5)In [84], [85], a minimal  was chosen to minimize the transitions between the voltage states,which consequently maximizes the on-state duration of the thyristor DSs. Therefore, a minimal reduces the current flowing through the more lossy CFBs, which has the added benefit ofminimizing their energy deviation and subsequent capacitive energy storage requirements.Therefore, with a small , e.g.,  = 0.05, the same third-order harmonic that the H3LC uses forits cascaded FBSMs may also be used for the TH3LC’s FBs; that is,V3h =14VDC − V1h sin(α)sin(3α)(3.6)Therefore, similar to the H3LC, the TH3LC has a maximum AC voltage of V1h = 0.63VDC if itsAC-side cascaded FBSMs are desired to be bounded by±14VDC. However, unlike the H3LC, theTH3LC can vary its  angle to generate the voltages of (2.13), i.e., V1h ∈ (0.287VDC, 0.334VDC),while retaining the 14VDC rating for its AC-side cascaded FBSMs.3.2.3 Optimal Third-Order Harmonic InjectionAlthough (3.6) enables the FBs to be sized to a maximum of 14VDC, it is not the optimalsolution for the TH3LC’s trapezoidal voltages, especially if  is increased. The TH3LC’s optimalthird-order harmonic ensures the maximum and minimum peaks of the FBs’ voltages areminimized such that fewer FBSMs can be used within the FBs. However, no single equationdefines such a third-order harmonic for the TH3LC’s entire operating range. Therefore, alook-up table can be populated that ensures the optimal V3h for each V1h ∈ [0, 0.63VDC]. Fig. 3.4(a) presents the peak absolute voltage of the AC-side cascaded FBSMs for five evenly-spacedvalues of  ∈ [0, 0.5] for all values of V1h; meanwhile, Fig. 3.4 (b) presents the corresponding58Operating voltage, V1h (×VDC)Peak AC-Side CascadedFBSM Voltage, vFB,j (×VDC)Third-Order HarmonicVoltage, V3h (×VDC)0.2 0.3 0.4 0.5 0.61611631658141021−21316131−61−(a)(b) =0 =0.125 =0.25 =0.375 =0.5 =0 =0.125 =0.25 =0.375 =0.5Fig. 3.4. Results of sweeping to find the optimal V3h at each V1h for varying . (a) Minimum blockingvoltages of the AC-side cascaded FBSMs; (b) Corresponding optimal value of V3h.TABLE 3.1Cascaded AC-side FBSMs’ Peak Voltages for Varying  for V1h ∈ [0.5VDC, 0.6VDC] (rad) 0 0.1 0.2 0.3 0.4 0.5 0.6vˆFB,j (×VDC) 0.25 0.22 0.20 0.18 0.15 0.13 0.11values of V3h. It is noted that Fig. 3.4 considers the range V1h ∈ [0.16VDC, 0.63VDC], since, as(3.4) gives, V min1h ≈ 0.16VDC for  = 0.5. As expected, the  = 0 case corresponds to the constant14VDC blocking voltage of the H3LC, except for V1h within the neighborhood of V1h = 1piVDC.It is noted in Fig. 3.4 (a) that as the operating voltages approach V1h = 0.63VDC, the FBs’peak voltage increases sharply. For considering the operating voltage on the range, e.g., V1h ∈[0.5VDC, 0.6VDC], which corresponds to the nominal operating voltage V1h = 0.55VDC ± 10%,the FBs’ peak voltages for varying  are tabulated in Table 3.1.It is noted that within the nominal range of V1h ∈ [0.5VDC, 0.6VDC], at the values of  givenin Fig. 3.4, i.e.,  ∈ {0, 0.125, 0.25, 0.375, 0.5}, the optimal third-order harmonic serves toensure that the maximum andminimum peaks of the FBs’ voltage, vFB,j , have the same absolute59Operating voltage, V1h (×VDC)Peak AC-Side CascadedFBSM Voltage, vFB,j (×VDC)1611638141 =0 =0.125 =0.25 =0.375 =0.5 =0 =0.125 =0.25 =0.375 =0.50.5 0.52 0.53 0.54 0.55 0.56 0.57 0.58 0.59 0.600.51Fig. 3.5. Analytical third-order harmonic calculation compared against optimal sweep.value. Therefore, the optimal third-order harmonic on this range can be found by solvingvFB,a(αω− 2ω)= −vFB,a(αω+2ω), (3.7)which netsV3h =1VDC12VDC − 2V1h(sin(α) cos(2))sin(3α) cos(32) . (3.8)To provide confidence in the third-order harmonic of (3.8), Fig. 3.5 overlays the results ofthe third-order harmonic optimal sweep in Fig. 3.4 with the results produced by the analyticalmethod of (3.8), which shows identical results.3.2.4 AC-side Cascaded FBSMs Modulation and Energy BalancingDue to leakage effects as well as on-state conduction losses, the TH3LC requires theinjection of a small fundamental-frequency voltage component into its FBs to balance thesum of their capacitor voltages to the total voltage set-point of 14VDC — although, the set-pointcan change depending on the value of , according to Fig. 3.4. The summation of the phase-jcapacitor voltages of the FBs’ FBSMs,∑ivc,FB,j , is compared with the voltage set-point, e.g.,14VDC, and the result is sent to a PI controller to generate the incremental voltage,∆vj , which60TH3LC+-- +-VDCPCCωtωtωtαα, Trapezoidal waveformgeneration, CFBNLM, and DC-link capacitor balancingSDSSDSSCFB(2.6), (5.7),Fig. 5.4 (b)V1h V3hsinvT,abcvT,abcNLM&SM voltagebalancingcontrolVDC∆vabc1/V1h∆vabc+FBs switching generationThird-order harmonic voltage injectionFBs energy balancing++--DC cablePQ controller+vuvlvu-vlPI∆vabc3SFBCFBs/Pole Capacitor energy balancingPI iDC,bal∆iDC,baliDC,bal+--SFBSCFBvc,FB,abcvc,FB,abciΣvc,FB,abciΣvc,CFB,abcvc,CFB,abcP *Q*vabcsvabcsiabcsiabcsV1hv1h,abc*v1h,abc*v3h,abc*v1h,abc*v3h,abc*vDC14vu, vlPI+-vlvuFig. 3.6. Simplified control scheme for the TH3LC.is then multiplied by the fundamental-frequency sine wave to be injected into the FBs. Fig. 3.6shows the overall control flow for the TH3LC.3.2.5 Commutation Cascaded FBSMs Energy Balancing and DC-sidePole Capacitor Energy BalancingDuring the thyristor commutation events, the CFBs carries phase current for brief timeintervals, as shown in Fig. 3.2. That is, the CFBs supply or absorb energy from the AC-side,causing their total stored capacitive energy to deviate cycle-to-cycle. Such energy deviationscan be corrected by an exchange of energy between the DC-side pole capacitors and the CFBs.61When either the upper or lower DSs are in the on position, i.e., when vT,j ={12VDC,−12VDC},respectively, a balancing current may be modulated to flow between the upper and lowerDC-side pole capacitors to correct any energy deviation.With the interest of minimizing the TH3LC’s semiconductor conduction losses, the bal-ancing current during the upper or lower DS states should ideally be controlled to take theminimum necessary DC value. To achieve this, during the vT,j ={12VDC,−12VDC}voltagelevels, the CFBs are modulated to drive DC balancing currents over the rangesθuc ∈[α +2, pi −(α +2+ ω(Tq + Tcomm))], (3.9)θlc ∈[pi + α +2, 2pi −(α +2+ ω(Tq + Tcomm))], (3.10)where the superscripts u and l correspond to the ranges that the CFBs exchange currents withthe upper and lower DC-side pole capacitors, respectively. It is noted in (3.9) and (3.10) thatthe natural commutation event is ignored. For the worst-case, i.e., smallest, values of θuc andθlc, a natural commutation event occurs 2Tq before the desired DS turn-off event such thatTq + Tcomm of (3.9) and (3.10) is replaced by 2Tq.Although the value of such a balancing DC current can be determined using a PI controller,its analytical representation is given by determining the net energy deviation of the CFBsover half of a fundamental-frequency cycle, with the results being equal for either the positivehalf- or negative half-cycle. For the phase-a CFBs (and hence the other phases), the netenergy deviation,∆ECFB, over the positive half-cycle is given as (where vcomm is ignored in thecalculation since it is a design parameter that can be arbitrarily small)∆ECFB(ϕ) =∫ αω+ 2ωαω− 2ωvT,a(τ)ia(τ, ϕ) dτ +∫ piω−αω+ 2ωpiω−αω− 2ω−Tq−TcommvT,a(τ)ia(τ, ϕ) dτ (3.11)⇒ ∆ECFB(ϕ) = 1ω·[cos(ϕ)VDC iˆAC(( sin(α) + 2 cos(α))1sin( 2)− cos( 2)cos(α))−VDC iˆAC2(cos(α +2+ ω(Tq + Tcomm)+ ϕ)− cos(α +2+ ϕ))], (3.12)62With (3.12), the required minimal balancing DC current, iDC,bal, is determined asiDC,bal =2VDC∆ECFB(ϕ)pi − 2α− − ω(Tq + Tcomm) , (3.13)which is supplied equally from each of the upper and lower DC-side pole capacitors over theranges of (3.9) and (3.10), respectively.It is noted that a slight discrepancy in the balancing current,∆iDC,bal, can be used to balancetheDC-side pole capacitors. For example, if the upper pole capacitor’s voltage is greater than thelower’s, i.e., vu > vl in Fig. 3.6, then the PI controller increases∆iDC,bal such that the balancingcurrent from the upper and lower DC-side pole capacitors, iuDC,bal and ilDC,bal, respectively, areiuDC,bal = iDC,bal +∆iDC,bal, (3.14)ilDC,bal = iDC,bal −∆iDC,bal, (3.15)which are DC quantities in steady-state.It is further noted from the second line of (3.12) that, because of the term containing Tqand Tcomm, the CFBs’ energy deviates even if the TH3LC operates only in STATCOMmode, i.e.,with no real power flow; in STATCOMmode, ϕ ≡ 0, such that the first line of (3.12) vanishes.Therefore, (3.13) can be used for any operating conditions.Lastly, it is again noted that for the worst-case scenario when a natural commutation eventoccurs 2Tq before the desired DS turn-off event, Tq + Tcomm of (3.12) and (3.13) are replacedby 2Tq.3.2.6 DC-side Pole-to-Pole Fault Blocking CapabilityIn the event of a DC-side pole-to-pole fault, the thyristor currents are commutated to theCFBs as soon as the DC fault is detected. After the thyristors are turned off, the AC currentscan either be suppressed by blocking the FBSMs of the CFBs and FBs, or the CFBs and FBs canbe operated together to enable STATCOM operation.63As the TH3LC presented here is designed to operate at a maximum operating voltage ofV1h = 0.63VDC, it requires the same blocking voltage per phase as the H3LC, i.e., 0.55VDC. Asthe CFBs are sized to block approximately 12VDC, it is required for the FB to block a minimumof 0.05VDC. For nearly all values of  and V1h, the FB will be sized larger than 0.05VDC, thus it isnot a design concern. Nevertheless, if the TH3LC is desired to operate as a STATCOM duringDC faults, then it is necessary to size the FB such that significant capacitive reactive power maybe generated, which is dependent on the AC network inductance.3.3 Performance EvaluationIn this section, the proposed TH3LC is studied in two scenarios: normal operation andDC-side pole-to-pole fault using detailed switching-based electromagnetic transient (EMT)simulations. The TH3LC is modeled using standard library components from the MAT-LAB/Simulink 2017b Simscape/Specialized Power Systems Toolbox with a simulation timestep of 20 µs. The individual semiconductor switching signals for each FBSM of the CFBs andFBs are modulated based on the energy and capacitor voltage balancing controls proposed inFig. 3.6. The TH3LC is fed by a 600 kV DC source via 100 km DC cables for the rated apparentpower of 1096MVA.The converter∆− Y transformer is connected to a 440 kV AC grid. Theparameters of the converter and AC-DC systems are shown in Table 3.2. The FBSM capacitorvoltages in the CFBs and FBs are assumed to be 15 kV. Considering the voltage ratings of theCFBs and FBs are respectively 12VDC + vcomm and 14VDC, each phase of the TH3LC model has330 kV/15 kV = 21 and 150 kV/15 kV = 10 FBSMs for the CFBs and FBs, respectively.The 4.5-kVWestcode T1800GB45A IGBT of Chapter B is used such that the IGBTs’ on-stateparameters are given in Table B.3. The thyristor parameters assume the 8.5-kV ABB 5STP27N8500 [96]. Both the IGBT and thyristor are de-rated by a factor of 2.5 kV : 4.5 kV such thatthey are respectively individually rated for 2.5 kV and 4.7 kV.The thyristor has the on-state64TABLE 3.2TH3LC Simulation ParametersSimulation parametersDC-side voltage 600 kVAC-side RMS line-to-linevoltage440 kVCFBs and FBs FBSMcapacitor voltage15 kVCFBs and FBs FBSMcapacitance1.6mFTrapezoidal slopeduration, 0.1 radCommutationinductance, Lcomm6mHPole-to-pole DC-sidecapacitance, 12CDC250 µFTransformerleakage impedance0.001+j0.18 puAC inductance, LAC 23mHDC inductance, LDC 50mHparameters:RT = 0.394mΩ and VT0 = 1.13V (3.16)3.3.1 Normal OperationIn this case study, the TH3LC operates in inverter and rectifier modes, respectively, atdifferent power factors. At t = 0 s, the power control reference values are set to beP = 900MWandQ = −200MVAR via a ramp function. The TH3LC is then commanded at t = 0.4 s toreverse the real and reactive power flow to operate as a rectifier. The power generation andreversal are shown in Fig. 3.7 (a). The DC-side voltage is shown in Fig. 3.7 (b), where the slightvoltage drop from the rated voltage is due to the resistance in the DC cables. The voltage ripplesfor the individual FBSMs of the CFBs and FBs are shown in Figs. 3.7 (c) and (d), respectively,which verify the FBSM voltage balancing controls. The voltage ripples of the CFBs and FBs65are within±10% of the rated SM voltage, i.e., 15 kV. Figs. 3.7 (e) and (f) show the line-to-lineconverter voltage and line current which have the low THDs of 1.43% and 0.82%, respectively,despite only 10 FBSMs being used in the FBs. Figs. 3.7 (g) and (h) show the currents flowingthrough the phase-a DSs and CFBs over two fundamental cycles. It is observed in Figs. 3.7 (g)and (h) that the DSs carry the majority of the load current compared to the CFBs, justifyingthe use of thyristor DSs.Next, in Figs. 3.7 (g) and (h), the currents of the phase-aDSs and CFBs are shown. The DCP(GW) and Q(GVAR)0.40.0-0.40.8-0.8PQ(a)DC-side Voltage (kV)625650550575600(b)CFBs FBSM CapacitorVoltages (kV)15161314111210(c)15.415.1514.914.6514.4 14.414.815.215.6FBs FBSM CapacitorVoltages (kV)161514131211100.0 0.2 0.4Time (s)0.80.6 1.0(d)13.514.515.513.514.516.515.566Converter Voltage (kV)-600-400-2002004006000(e)Converter Current (kA) 2.0-2.01.0-1.00.00.79 0.80Time (s)0.81()DS Currents (kA)CFB Current (kA)2.401.20.6-0.61.80-1.20.6-0.61.20.2 0.21 0.22 0.23Time (s)0.24il,j iu,jim,jiCFB,aiDC,bal(g)(h)Fig. 3.7. Key converter waveforms during normal operation. (a). Converter real and reactive powers;(b). Converter DC-side voltage; (c). Phase-a FBSM voltages for the CFB; (d). Phase-a FBSM voltagesfor the FB; (e). Converter line-to-line voltage; (f). Converter line current. (g). DS currents; (h). CFBcurrent.67balancing current of (3.13) is seen in Fig. 3.7 (h), which is approximately 100A. It is noted thatthe polarity of the charging current is positive when Tl,a is on and negative when Tu,a is on.3.3.2 DC-side Fault and STATCOMModeIn this case study, the TH3LC’s ability to block DC-side pole-to-pole faults while providingreactive power support for the AC-grid during the DC fault is verified. Prior to the DC fault, theTH3LC is supplying the real and capacitive reactive power of P = 0.9GW andQ = 0.2GVAto the PCC. At t = 0.2 s, a 150ms pole-to-pole fault occurs at the DC terminals of the TH3LC.The TH3LC is blocked upon the detection of the DC fault. After the AC-side fault currentsP(GW) and Q(GVAR)1.00.2-0.20.6-0.6(a)PQDC-side Voltage (kV)400200300500-1006000100(b)DC-side Current (kA) 0-20-400-40-200.2 0.25 0.3 0.35(c)Converter Current (kA) 2.01.0-1.00.0-2.0 (d)68151412111613(e) 14.014.515.515.014.014.515.515.0CFBs FBSM CapacitorVoltages (kV)FBs FBSM CapacitorVoltages (kV) 1514121116130.1 0.2 0.3 0.4Time (s)0.5 0.70.6() 14.014.515.515.014.014.515.515.0Fig. 3.8. Key converter waveforms during DC-side fault operations operation. (a). Converter real andreactive powers; (b). Converter DC-side voltage; (c). Phase-a FBSM voltages for the CFB; (d). Phase-aFBSM voltages for the FB; (e). Converter line-to-line voltage; (f). Converter line current.are suppressed by the TH3LC, the FBSMs of the CFBs and FBs are de-blocked to generatecapacitive reactive power for AC-side voltage support during the DC fault. After the DC fault iscleared at t = 0.35 s, the DC-side voltage is gradually recovered to its nominal value of 600 kV.Thereafter, the real and reactive powers are restored to the pre-fault values.Key waveforms of the transient response of the TH3LC to the DC pole-to-pole fault areshown in Fig. 3.8. In Fig. 3.8 (a), the power transfer is shown to be discontinued shortly afterthe DC fault occurs during converter blocking. The reactive power transfer is resumed at thebeginning of the subsequent fundamental cycle, i.e., at t = 0.220 s using the CFBs and FBs.Figs. 3.8 (b) and (c) illustrates the DC-side voltage and current transients during and after theDC fault. Due to the use of shunt resistor and diode, the DC-side voltage does not experiencehigh frequency oscillation which, otherwise, could be produced by the LC resonance of theDC-pole capacitor and DC cable inductance. It is shown in Fig. 3.8 (c) that the DC-side surgecurrent is quickly extinguished. It is assumed that the DC fault is detected using DC-sidevoltage or DC surge current at t = 0.202 s, i.e., 2ms after the DC fault occurrence. The thyristor69DSs are turned off by commutating their currents to the CFBs. It is shown in Fig. 3.8 (d) that theAC-side currents are quickly suppressed to zero by the converter after the DC fault is detected.Thereafter, the IGBTs in the FBSMs of the CFBs and the FBs are operated in STATCOMmodefor reactive power transfer. Figs. 3.8 (e) and (f) illustrate the transient voltage responses of theFBSMs in the CFB and FBs. The SM voltages of the cascaded FBSMs absorb the stored energyin the AC-side inductance and maintain their voltages within±10% of the rated SM voltage.3.4 Component, Loss, and Energy AnalysisAs with the H3LC, the losses and the energy storage requirements of the TH3LC arecompared against the MMCs with HBSM, MBSM, and FBSM configurations, the EO-AAC[67], and the H2LC [69]. For these analyses, the nominal operating voltage of each of theconverters is assumed, i.e., the voltage V1h that is 10% below the converters’ maximumoperatingvoltages. The IGBT and thyristor used for the converter comparisons are the Westcode 4.5 kVT1800 GB45A [90] and the ABB 8.5 kV 5STP 27N8500 [96]. As a practical safety factor, thesemiconductors are de-rated by a ratio of 2.5 kV:4.5 kV as in [83]. To satisfy the DS or SMvoltage blocking ratings, the required number of semiconductors are connected in series. Forthe component count, loss, and energy storage analyses, each of the converters assumes theDC-side voltage of 600 kV and the power flow of 1GW without reactive power.The methods to calculate the semiconductor losses and the energy sizing were presentedin Chapters A and B, respectively. An upper-level comparison that shows the converters’component counts and general capabilities is shown inTable 3.3. As in [84], [85], the trapezoidaltransition interval is set to  = 0.035 for the following analyses, while Tcomm is assumed tobe negligible and the turn-off time, Tq, is assumed to be the typical value for high-voltagethyristors, i.e., 500 µs.3.4.1 Semiconductor LossesUsing the methods outlined in Sections B.1 and B.2, the conduction and switching lossesfor the various converters were determined at the operating voltage enabling 10% headroom.70TABLE 3.3High-Level Comparison of ConvertersConverterTypeHBSMMMCMBSMMMCFBSMMMCEO-AACH2LC TH3LCLimit of OperationV1h (×VDC) 1/√3 1/√3 1/√3 2/3 2/pi 0.63No. of IGBTs 2880 4320 5760 4800 3024 2160No. of thyristors - - - - - 1920No. of 15 kV SMs 240 240 240 160 66 90DS switching frequency (Hz) - - - 50 150 50DC-side Pole Capacitors No No No No Yes YesInherent DC Fault Ride-Through CapabilityNo Yes Yes Yes Yes YesTable 3.4 shows that at the same operating voltage (V1h = 0.523VDC), the TH3LC is onlymarginally less efficient than the HBSMMMC (which is considered to set the standard forbest efficiency). However, the HBSMMMCmay only reach a maximum operating voltage ofV1h = 0.575VDC, and it requires additional hardware to ensure DC-side fault tolerance. TheTH3LC can reach the higher operating voltage of V1h = 0.63VDC which enables it to generatehigher voltages than the HBSMMMC for the same power flow and DC-side voltage. Hence,with the increased AC voltage, i.e., V1h = 0.573VDC, the TH3LC outperforms all the presentedconverters in terms of efficiency, while possessing inherent DC fault blocking and ride-throughcapability.3.4.2 Energy Storage ComparisonTable 3.5 shows a comparison of the TH3LC’s energy storage requirements to the afore-mentioned converters’, where it is seen that the TH3LC requires approximately one-fifth of theenergy storage of the MMCs, and 45% of the EO-AAC’s. Moreover, it needs only 72% as muchenergy storage as the H2LC.To show the effect that varying values of  have on the TH3LC’s energy storage requirements,Fig. 3.9 presents the nominal energy storage requirements of theCommutation Branch cascaded71TABLE 3.4Semiconductor Losses of Selected ConvertersConverterTypeHBSMMMCMBSMMMCFBSMMMCEO-AACH2LC TH3LCAC Voltage, V1h (×VDC) 0.523 2/3 0.577 0.523 0.573SM Pcond (MW) 3.68 5.62 7.56 3.77 3.62 2.94 2.36SM Psw (MW) 2.30 2.30 2.30 0.95 2.06 2.34 1.69DS Pcond (MW) - - - 1.80 3.53 0.87 0.79DS Psw (MW) - - - - 0.77 0.16 0.16Total Loss (MW) 5.98 7.92 9.86 6.52 9.98 6.31 5.00Percentage Loss 0.60% 0.79% 0.99% 0.65% 1.0% 0.63% 0.50%TABLE 3.5Normal Operation Energy Storage and Capacitor Sizing ResultsConverter type MMC EO-AACH2LC TH3LCFBsPoleCapacitorFBs CFBsPoleCapacitorsAC Voltage, V1h (×VDC) 0.523 2/3 0.577 0.573∆E (MJ) per set of SMs/one Pole Capacitor2.02 0.95 0.819 0.702 0.245 0.326 0.219NSM per set 40 27 20 1 10 21 1VSM,nom (kV) 15 15 15 600 15 15 300CSM (mF) 1.13 0.78 0.91 0.020 0.544 0.345 0.024Enom (MJ) per set of SMs/one Pole Capacitor5.07 2.37 2.05 3.51 0.611 0.815 1.09Total Energy (MJ) 30.45 14.21 6.15 3.51 1.835 2.445 2.187Total energynormalized to MMC1.0 0.47 0.32 0.212FBSMs, theAC-Side cascaded FBSMs, and theDC-side pole capacitors at the nominal operatingvoltage, V1h = 0.573VDC. The results show that the Commutation Branch’s FBSMs’ energystorage increases nearly linearly with , while the AC-side cascaded FBSMs’ energy storagedecreases relatively linearly. The pole capacitors’ energy is not significantly influenced byvarying . The energy deviation of the CFBs is provided by (3.12) while the energy deviationsof the FBs and pole capacitors was presented in detail for the H3LC in Chapter A.72Nominal energystorage (MJ) Commutation FBSMs AC-side FBSMs Pole Capacitors00 0.2 0.4 0.6 0.82468 (rad)Fig. 3.9. Nominal energy storage requirements of the TH3LC for varying  when V1h = 0.573VDC.The TH3LC is expected, then, to be the most compact out of the three. Since it also featuresbest-in-class efficiency, the TH3LC outperforms these tested converters in terms of bothefficiency and converter footprint; therefore, it is worthy of further research.734.Hybrid Five-Level Modular Multilevel ConverterThis chapter proposes a new hybrid cascaded multilevel converter, herein referred to asthe hybrid five-level converter (H5LC) [97]. The construction of the five-level converter of theH5LC is similar to the three-level T-type converter with the addition of two low-cost flyingcapacitors (FCs) per phase that enable two additional voltage levels. With a five-level voltageoutput, the number of cascaded FBSMs required for normal operation is halved compared tothe H3LC and quartered compared to the H2LC.Therefore, the H5LC is expected to have aneven smaller footprint and improved semiconductor losses compared to the H3LC.The maincontributions of the proposed H5LC are as follows:(1) Fundamental frequency switching of the H5LC’s DSs significantly improves their switch-ing losses compared to the PWM two- or three-level converters and the H2LC.(2) Reduction in the required blocking voltage of the cascaded FBSMs results in a compactfootprint that significantly improves the economic viability of volume-limited converterstations. Moreover, compared to the H2LC and H3LC, there are 37.5% and 16.7% fewerIGBTs in the conduction path, respectively, which enables a respective reduction of thesemiconductor conduction losses.(3) Bypass thyristor valves (BTVs) are proposed in tandem with fast mechanical switches(FMSs) which, in the event of DC-side faults, disconnect the cascaded FBSMs from thecircuit and suppress the contribution of AC-side currents. The proposed BTVs havethe added benefit of using the already mature thyristor technology, enabling simpleconstruction and a minimal increase in the converter’s footprint.Moreover, a lab-scale hardware implementation of a three-phase H5LC that uses threebuilt-in-house five-level converters, each connected to 10 FBSMs, verifies the operation of theThis chapter is based upon the accepted IEEE Transactions on Industrial Electronicsmanuscript, “A HybridFive-Level Modular Multilevel Converter with Competitive Efficiency and Small Energy Storage Requirementsfor HVDC Transmission.”74H5LC. The hardware verification is realized using components from OPAL-RT Technologies’®MMC Testbench [89].4.1 TopologyThe detailed circuit diagram of the H5LC is presented in Fig. 4.1, displaying its DSs, FCs,cascaded FBSMs, BTVs, and FMSs. The two DSs of the upper and lower switching positions,i.e., {T1,j, T2,j} and {T3,j, T4,j} are together rated for the entire nominal pole-to-pole DC-sidevoltage, VDC , such that each is rated for 12VDC. Throughout this chapter, the subscript indexj ∈ {a, b, c} is reserved to denote the phases. The H5LC’s anti-series midpoint DSs, i.e.,{T5,j, T6,j, T7,j, T8,j}, are each rated for 14VDC and the FCs are charged to the nominal valueof 14VDC. It is noted that each of the DSs is composed of series-connected IGBT modules toreach the required voltage ratings, as shown in Table 4.1. It is further noted that the nominalDC-side voltage, VDC, is different from vDC = vPC,u+vPC,l, the instantaneous DC voltage acrossthe H5LC’s DC-pole capacitors. The five-level converter of the H5LC generates a five-levelvoltage at v5LC,j with step sizes of 14VDC. In Fig. 4.1, vabct and vabcs are the converter and AC-gridvoltages, respectively. All voltages are measured with reference to the ground point, located atthe junction of the DC-side pole capacitors, as shown in Fig. 4.1.Table 4.1 presents seven switching states of the H5LC to generate the five voltage levelswithin±12VDC. The states are denoted byH (high),MH1,2 (mid-high), Z (zero),ML1,2 (mid-low),and L (low) which correspond to the nominal voltage levels 12VDC, 14VDC, 0,−14VDC, and−12VDC.As noted from Table 4.1, the mid-high and mid-low states each have two unique switchingconfigurations which enable vFC,u,j and vFC,l,j to be balanced to their set-point voltages of 14VDC.The method of switching state selection of MH1,2 and ML1,2 is proposed in Section 4.2.2.To smooth the five-level output voltage, v5LC,j , shown in Fig. 4.1, the H5LC’s cascadedFBSMs are operated together to remove the non-fundamental voltage harmonics such that theline-to-line outputs at vabct are smooth sinusoidal voltages. As the cascaded FBSMs do notparticipate in real power exchange, their average energy remains constant cycle-to-cycle. Whencoupled to a delta-connected transformer at the output terminals of the H5LC, third-order75++ LcommvFB, jvat vabctorFMSiconv,uiconv,l+vciFBSMFBSMBTViFC,u, j++iDCLDCiPC,uiPC,lvPC,uvFC,l, jvFC,u, jiFC,l, jv5LC, jijiDC,l, jiDC,u, jT1, jT2, jT3, jT4, jT5, jT6, jT7, jT8, jvPC,lFig. 4.1. Detailed circuit diagram of the proposed H5LC.harmonic voltage injection may be used to limit the total blocking voltage of the cascadedFBSMs to an 8h of the DC-side voltage, i.e., 18VDC, as will be shown in Section 4.2.1. Therefore,theN FBSMs per phase each sustain the nominal voltage of 18NVDC. It is shown in Section 4.4that the H5LC’s reduced number of cascaded FBSMs and fundamental switching frequency ofits DSs lead to comparable conduction losses to the HBSM-MMC (and improved conductionlosses compared to the MBSM-MMC), and lower semiconductor switching losses.When the FCs and DC-side pole capacitors discharge during DC-side pole-to-pole faults,the per-phase voltage of 18VDC produced by the H5LC’s cascaded FBSMs is insufficient tocounteract the AC-side line-to-line voltages. As two phases of cascaded FBSMs are in serieswith respect to the line-to-line voltage, the FBSMs can counteract peak line-to-line voltagesof only 14VDC in DC-side fault scenarios. However, the H5LC’s peak line-to-line voltage maybe 1.07VDC, as will be shown in Section 4.2.1. For the safe operation of the H5LC, additionalhardware in the form of BTVs and FMSs is used to enable the FBSMs to be disconnected fromthe current path without the use of bulky AC-side circuit breakers. The H5LC’s BTVs and76TABLE 4.1DS Switching States, DS Voltage Ratings, and Currents of the Proposed H5LCDirector switches CurrentsState v5LC,j T1,j T2,j T3,j T4,j T5,j T6,j T7,j T8,j iFC,u,j iFC,l,j iDC,u,j iDC,l,jH vPC,u 1 1 0 0 1 0 1 0 0 0 ij 0MH1 vPC,u − vFC,u,j 1 0 0 0 1 1 1 0 ij 0 ij 0MH2 vFC,u,j 0 1 0 0 1 0 1 1 −ij 0 0 0Z 0 0 0 0 0 1 1 1 1 0 0 0 0ML1 −vFC,l,j 0 0 1 0 0 1 1 1 0 ij 0 0ML2 −vPC,l + vFC,l,j 0 0 0 1 1 1 0 1 0 −ij 0 −ijL −vPC,l 0 0 1 1 0 1 0 1 0 0 0 −ijRating(×VDC) 1212121214141414FMSs provide the necessary blocking voltages to counteract the line-to-line voltages duringDC-side pole-to-pole faults while retaining its small footprint. Upon DC fault detection, theFBSMs are blocked to commutate the AC currents to the BTVs which enables the FMSs toopen, thus isolating the FBSMs from the conduction path. Once the FMSs open, the BTVs’trigger signals are removed. Since the BTVs’ turn-off is uncontrollable, a single BTV sustainsthe entire line-to-line voltage until the next BTV turns off, implying that each of the BTVs israted for the entire peak line-to-line voltage, i.e., 1.07VDC. Therefore, only two phases requirethe fully rated BTVs and FMSs while the third phase’s BTV needs to block only 18VDC and noFMS is necessary.4.2 Operating PrincipleThe control and modulation of the H5LC requires accurate coordination between its DSsand the cascaded FBSMs. Similar to other VSCs, generic PQ control enables independentcontrol over the real and reactive powers. However, in the case of the H5LC, additional controllayers are required to (1) generate and coordinate the DS and cascaded FBSM IGBT switchingsignals; (2) inject a precise third-order harmonic to enable the cascaded FBSM blocking voltageof 18vDC; (3) ensure that the H5LC’s FCs remain balanced around their setpoints of 14vDC; (4)77ensure that the H5LC’s DC-pole capacitors each support an average voltage of 12vDC; (5) ensurethat the voltages of the individual FBSMs are tightly regulated around their setpoints of 18NvDCwhile also regulating their total voltage to 18vDC; and (6) quickly respond to AC- and DC-sidefaults for safe operation of the H5LC’s IGBTs.The control flow diagram for the nominal operation of the H5LC is shown in Fig. 4.2,wherein a generic PQ controller for the test system in Fig. 4.2 (a) is assumed in Fig. 4.2 (b), thusforegoing the need to explicitly show it. Given the desired reference power values, P ∗ andQ∗,the PQ controller provides the balanced three-phase reference voltages and their magnitudes,v∗1h,abc and V∗1h, and the converter angle, ωt.H5LCP *++-- +--VDCQ*vabcsiabctiabctiabcsvFCvFCvSM,abcvSM,abcvωtωtMH1,2ML1,2ΔVabc+FBSM energy balancingDC cablePQ controllerLook-up tablePower controllerLS-PWM or NLMand FBSM voltagebalancing algorithm+vDC,uvDCvDC,lPIvDCΣFC voltage balancing FBSM signal generationFig. 6.3SSMSDS(6.1), (6.3), (6.4),(6.5)PCCvabcsvabctiabcsV ααvDC-pole capacitor balance(a)(b) (c)(d)+++---±iabctΔα2vDC,u-vDC,l00PIαβ1, β2+-vFB,abcvSM,abc(e)() (g)V1h3h,abc1h,abc1h 12218vDC14 SSMcccij polarity reversal, vFC exceeded tolerance band, or transition to MH1,2 or ML1,2? ACBRcharge78H0MH1,2ML1,2LZΔVabcFive-level converter reference voltage and signal generation (Table 6.1 and Fig. 6.3)Cascaded FBSM reference voltage (6.7)α1pi−α2pi−α1 2pi−α22pi−α1pi+α1pi+α2(i)(h)α2With third-order harmonicWithout third-order harmonicvvMH1,2ML1,2α1,2β 1,2 5LC,aVDC14VDC18VDC18-VDC14-v1h,abcv3h,abcFB,abcSDSωtpiωt (rad) 2pi0 21pi 23pipi 2pi0 21pi 23piFig. 4.2. Considered H5LC test system and its control layers: (a) Simplified diagram of test systemshowing the control variables. (b) Generic PQ controller. (c) Look-up table for optimal α1, α2, andv3h,abc. (d) DC pole capacitor balancing control. (e) FBSM energy balancing loop. (f) Flying capacitorvoltage balancing loop. (g) FBSM signal generation and capacitor balance. (h) Idealized phase-a voltagev5LC,a and DS signal generation; and (i) Idealized reference voltage for the phase-a FBSMs with andwithout the injection of the third-order voltage harmonic at the operating point V1h = 0.61VDC.4.2.1 DS Control and FBSM ModulationThe five-level converter in Fig. 4.1 may generate voltage levels as defined in Table 4.1.Thephase-a voltage waveform v5LC,a is shown in Fig. 4.2 (h) with respect to the converter angleωt. There are two unique switching angles corresponding to each AC voltage magnitude togenerate the optimal five-level output which minimizes the blocking voltage required by thecascaded FBSMs. The magnitude of the fundamental voltage component is expressed asV1h =1pi(cos(α1) + cos(α2))vDC (4.1)where α1 and α2 correspond to the 0 → 14VDC and14VDC → 12VDC transition instances,respectively, as shown in Fig. 4.2 (h).For harmonic-free voltages at vabct, the phase-a cascaded FBSM voltage vFB,a is represented79asvFB,a(t) = v5LC,a(t)− V1h sin(ωt)− V3h sin(3ωt), (4.2)where V3h is the magnitude of the third order harmonic voltage used to limit the total blockingvoltage of the cascaded FBSMs 18VDC.To illustrate the effect of the third order harmonic voltage injection, v5LC,a and vFB,a for thefundamental voltage magnitude V1h = 0.61VDC are shown in Figs. 4.2 (h) and (i). For each V1h,the two degrees of freedom in (4.1) lead to an infinitude of options for α1 and α2. However,since a total blocking voltage of 18VDC is desired for the cascaded FBSMs, the local maxima ofvFB,j , i.e., vFB,j(α1ω)and vFB,j(α2ω), may be limited to 18VDC. The addition of the third orderharmonic voltage in (4.2) leads to additional constraints asvFB,a(α1ω)=14vDC − V1h sin(α1)− V3h sin(3α1) = 18vDC, (4.3)vFB,a(α2ω)=12vDC − V1h sin(α2)− V3h sin(3α2) = 18vDC. (4.4)By numerically solving (4.1), (4.3), and (4.4) at each V1h, a look-up table as shown in Fig. 4.2(c) may be populated to give the proper values of α1, α2, and V3h, which enable the cascadedFBSMs to be rated for a total blocking voltage of 18vDC, as can be seen in Fig. 4.2 (i), where theaddition of the third-order harmonic bounds vFB,a to within±18vDC.It is noted that (4.1), (4.3), and (4.4) provide valid results up to the voltage V1h = 0.62VDC,since no third order harmonic voltage exists to bound vFB,a within ±18VDC for the voltagesV1h ∈(0.62VDC, 2piVDC](the third-order harmonic tends towards infinity as V1h approaches2piVDC). Moreover, the five-level waveform, determined by (4.1), (4.3), and (4.4), collapsesto a three-level waveform with α2 ≡ pi2 at approximately V1h =1.12piVDC such that only theMH1,2 and ML1,2 states are used for the voltages below V1h =1.12piVDC. Therefore, for the caseof V1h ≤ 1.12pi VDC, (4.1) and (4.3) are used with α2 =pi2to calculate the third order harmonic80voltage asV3h =18vDC − V1h sin(α1)sin(3α1)(4.5)It is noted that for the case of V1h = 12piVDC and α2 = pi2, α1 can be solved from (4.1) as pi3,which leads to infinity forV3h in (4.5). That is, whenV1h is close to 12piVDC, V3h approaches infinity.Therefore, for V1h ∈[0.92piVDC,1.12piVDC], an exhaustive sweep is used at each voltage to find theoptimal V3h to minimize the peak voltage of vFB,a. However, at V1h = 12piVDC no V3h exists toreduce the peak value of vFB,a. Hence, the peak value of vFB,a at V1h = 12piVDC when V3h = 0is calculated as vˆFB,a =√34piVDC, which is approximately 10% larger than 18vDC. Therefore,for steady-state operation at these voltages, the FBSMs should be sized for vˆFB,a =√34piVDC,or approximately 10% larger than 18VDC. The three-phase symmetrical/uniform third-orderharmonic voltage injections are used in H5LC for normal operations as well as symmetrical andasymmetrical AC-side fault operations. These third-order harmonic voltages are canceled in theconverter line-to-line voltages by connecting the H5LC’s AC-side to∆-connected transformerwindings. Hence, in the case of asymmetrical AC-side faults, the H5LC’s cascaded FBSMs canstill maintain the maximum blocking voltage of 18VDC.4.2.2 Flying Capacitor Voltage BalancingFrom Table 4.1, the two switching states of MH1,2 andML1,2 enable ij to charge or dischargethe FCs. Measurement of the FC voltages and ij enables the FC voltages to be regulated totheir set-points of 14vDC. Fig. 4.3 and Table 4.2 illustrate the FC voltage balancing algorithm(VBA) for phase-a to ensure the FC voltage is maintained within the desired tolerance band,Vtol. Other phases are implemented similarly. Fig. 4.2 (f), Fig. 4.3 and Table 4.2 show that theFC VBA uses comparators to determine if the FC voltage is above or below the set-point of14vDC and the direction of ij . The variable vFC in Fig. 4.2 (f) is a vector of all six of the FCs’81TABLE 4.2Switching States for FC BalanceTransition to: ij > 0 vFC,u,j > 14vDC vFC,l,j >14vDC StateMH1,2 0 0 MH2MH1,2 1 0 MH1MH1,2 0 1 MH1MH1,2 1 1 MH2ML1,2 0 0 ML2ML1,2 1 0 ML1ML1,2 0 1 ML1ML1,2 1 1 ML2voltages, and iabct is a vector of the converter-side phase currents. If ωt < pi [see Fig. 4.2 (h)]then the states MH1,2 are used. Otherwise, if ωt > pi, then the states ML1,2 are used.It is noted that should the FC voltages exceed the allowable tolerance band of 14vDC ± Vtol,whereVtolmay be 10%of 14vDC, theMH1,2 orML1,2 states for the upper or lower FCs, respectively,are alternated to maintain the FC voltages within the allowable range. This increases the overallswitching frequency and losses of the DSs. To retain the fundamental frequency switching ofthe DSs, the FCs’ capacitance should be sufficiently large such that their voltage ripple doesnot exceed, e.g.,±10% of their set-point voltages. It is noted that if the phase current changespolarity during the MH1,2 or ML1,2 states, the FC VBA of Fig. 4.3 and Table 4.2 may again beemployed with zero-current switching of the DSs.4.2.3 DC-side Pole Capacitor BalancingDue to the presence of the two midpoint-connected DC-pole capacitors, an additionalcontrol layer is required to offset any voltage difference between the two, which may arisedue to asymmetries of the converter’s physical construction as well as the tolerances of thedevices used. Out of the seven switching states presented in Table 4.1, four involve the DC-polecapacitors in the conduction path. However, manipulation of only the H and L switchingstates is sufficient for DC-pole capacitor balancing. This is accomplished by applying a slight82(1) Transition to MH1,2 or ML1,2?(2) vFC,u,a or vFC,l,a tolerance band exceeded?(3) Polarity reversal of ia? ωt < pi ?Yes NoMH1MH2Yes NoNoYesYes NovFC,l,a > vDC?14ML1 ML2Yes Noia > 0? ML1ML2Yes Noia > 0? ia > 0? MH1MH2Yes Noia > 0? Negative half-cyclePositive half-cyclevFC,u,a > vDC?14Fig. 4.3. Diagram depicting the FC voltage balancing algorithm for phase-a to determine the MH1,2and ML1,2 states to keep the FC voltages within the desired range.modification to the switching angle α2 such that the turn-on and turn-off instances for theH voltage state are not symmetric with those of the L voltage state, which introduces a smallDC offset to the five-level converter voltages, v5LC,j . Therefore, α2 is replaced by the anglesβ1 = α2 +∆α2 and β2 = α2 −∆α2 such thatv5LC,a(t) =vPC,u ωt ∈ [β1, pi − β1]−vPC,l ωt ∈ [pi + β2, 2pi − β2], (4.6)as can be seen in Figs. 4.2 (d) and (h). The value ∆α2 is determined by the PI controllerin Fig. 4.2 (d) which regulates the voltage difference between the upper and lower DC-polecapacitors, i.e., vPC,u − vPC,l, to zero.4.2.4 Cascaded FBSMTotal Energy Balancing and FBSM CapacitorVoltage BalancingAlthough the cascaded FBSMs do not transmit real power in ideal circumstances due tohaving no fundamental frequency voltage component, the asymmetries present in the five-levelvoltage output and the semiconductor losses of the FBSMs cause their energies to deviate fromthe nominal value cycle-to-cycle. The total energy of the FBSMs can be balanced by injecting asmall fundamental frequency voltage into them, causing them to absorb or generate real power.83The PI controller in Fig. 4.2 (e) generates the injected voltages’ magnitudes,∆Vj (j ∈ {a, b, c}),by regulating the sum of each phase’s cascaded FBSM capacitor voltages, i.e., the vector vcSM,j , toa total voltage of 18vDC. The fundamental frequency voltage∆Vj sin (ωt+ φj) is injected intoeach phase’s cascaded FBSMs, where φj ∈{0,−2pi3, 2pi3}. Therefore, (4.2) may be rewritten inthe general case for the jth phase asvFB,j(t) = v5LC,a(t+ φj)− (V1h +∆Vj) sin(ωt+ φj)− V3h sin(3ωt). (4.7)Although∆Vj ensures that the total FBSM voltage is balanced to 18vDC, the proper selectionof individual FBSMs to insert or bypass ensures their capacitor voltage ripples stay within apredefined limit, e.g., ±10% of 18NvDC. Once the reference voltages for the FBSMs [vFB,j inFig. 4.2 (i)] are determined, modulation methods such as level-shifted PWM (LS-PWM) ornearest level modulation (NLM) generate the switching functions, Nins,j ∈ Z. Nins,j is sentto a voltage balancing algorithm (VBA) [44], which yields the discrete switching signals, SSM[Figs. 4.2 (a) and (g)]. The instantaneous FBSM capacitor voltages and polarity of the phasecurrent enable ascertainment of the suitable FBSMs to insert at proper polarity or to bypass.4.2.5 FBSM IGBT Switching FrequencyFrom Fig. 4.2 (i) and, as will be shown in Section 4.3.1, Fig. 4.5 (g), the FBSMs alternatebetween the positive fully-inserted state and the negative fully-inserted state 8 times perfundamental-frequency cycle. The 8 positive insertions of FBSM capacitors indicate the 8switching cycles (one turn-on event and one turn-off event) for one half-bridge phase leg ofeach FBSM, i.e., a switching pulse number of 8 for each IGBT of the half-bridge phase leg of theFBSM.Thus, the switching frequency of each IGBT is at least 50Hz× 8 = 400Hz. Similarly,there are 8 negative insertions of all the cascaded FBSM capacitors per fundamental cycle.Hence, the other half-bridge phase leg of each FBSM (i.e., each IGBT in the half-bridge phaseleg) also has the minimum switching frequency of 50Hz× 8 = 400Hz.The FBSMs’ IGBT switching frequency can be decided by the detailed switching-based84simulation model, or by an analytical model of the average switching frequency of the H5LC’scascaded FBSMs’ IGBTs.Analytically, the average IGBT switching frequency of the FBSMs is derived using theideal cascaded FBSMs’ voltage, i.e., vFB,j from (4.2). The voltage vFB,j is the superposition ofthe five-level voltage, the fundamental frequency voltage component, and the third-orderharmonic voltage component. By integrating the absolute value of the normalized derivative ofv1,3h,j with respect to ωt, wherev1,3h,j(t) = vFB,j(t)− v5LC,j(t),the average number of FBSM transitions during the continuous portions of vFB,j is obtained.The additional switching instances due to v5LC,j are appended after the analysis. Manipulationof the integration of v1,3h,j enables the calculation of the average pulse number for the IGBTmodules, np, as:np =2VDC∫ 2pi0∣∣∣∣dv1,3h(t)dωt∣∣∣∣ dωt+ 4. (4.8)The detailed derivation of (4.8) is as follows:(1) We start with the continuous portion of the phase-a cascaded FBSMs’ voltage, where thesubscript is omitted for convenience, v1,3h. The insertion function of v1,3h used to generatethe stepped output voltage of the cascaded FBSMs,Nins, is defined onNins ∈ [−NSM, NSM](whereNSM is the total number of SMs per set of cascaded FBSMs) asNins(t) = round(NSM18VDCv1,3h(t))(4.9)For the ideal insertion function, an infinite number of FBSMs—with infinitesimal voltages— is assumed, which sum to a total voltage of 18VDC. This is equivalent to a single FBSM ofvoltage 18VDC that can output fractional voltages within ±18VDC with infinite resolution.85Hence, (4.9) is modified under the assumption of a single FBSM, i.e.,NSM ≡ 1, that canoutput fractional voltages asN ins(t) =8VDC(−V1h sin(ωt)− V3h sin(3ωt)) (4.10)In (4.10),N ins(t) ∈ [−1, 1] represents the fraction of FBSMs which are inserted positively(ifN ins > 0) or negatively (ifN ins < 0). Equivalently stated, (4.10) generates the averagestate of the SMs at each ωt.(2) When (4.10) is differentiated, the resulting expression generates the rate-of-change of theaverage state of the FBSMs at each ωt, which is the average number of FBSM transitionsper ωt. Hence,dN ins(t)dωtis given asdN ins(t)dωt=8VDCdv1,3h(t)dωt=8VDC(−V1h cos(ωt)− 3V3h cos(3ωt)) (4.11)(3) AsdN ins(t)dωtgives the average number of SM transitions per ωt, the integration of theabsolute value ofdN ins(t)dωtover a fundamental frequency cycle gives the average numberof FBSM state transitions-per-FBSM-per-cycle, nSM:nSM =∫ 2pi0∣∣∣∣dN ins(t)dωt∣∣∣∣ dωt=8VDC∫ 2pi0∣∣∣∣dv1,3h(t)dωt∣∣∣∣ dωt (4.12)It is noted that for each FBSM transition, there are two IGBT module switching transitions:One turns on while the other one turns off. Hence, the average number of IGBT moduleswitching events per FBSM is twice of (4.12), i.e., nsw,IGBT = 2 × nSM. However, thecalculation of pulse number assumes that both a turn-on and a turn-off switching event86make up one switch cycle, i.e., pulse number of ‘1’. Hence, under the assumption of a singleIGBT per FBSM, the pulse number is np,IGBT = nSM.(4) However, there are four IGBTs per FBSM. Hence, the pulse number from the continuousportions of v1,3h, np,cont, isnp,cont =nSM4=2VDC∫ 2pi0∣∣∣∣dv1,3h(t)dωt∣∣∣∣ dωt (4.13)(5) Lastly, the 8 discrete switching events of the cascaded FBSMs are considered. During eachof the transitions, all four IGBTs transition once. Hence, two of the discrete switchingevents increment (4.13) by ‘1’. In total, therefore, the 8 discrete switching events of thecascaded FBSMs increment (4.13) by ‘4’. Hence, the total pulse number, np, is, as in (4.8),np = np,cont + 4=2VDC∫ 2pi0∣∣∣∣dv1,3h(t)dωt∣∣∣∣ dωt+ 4It is noted that to obtain the switching frequency, np is multiplied by the fundamentalfrequency, fp — e.g., 50Hz — to give the average SM IGBT switching frequency. That is,f sw,IGBT = fpnp. (4.14)As an example, at V1h = 0.575, (4.8) gives np = 8.198, for an IGBT switching frequency of410Hz. This was verified with a simulation of 256 FBSMs per phase that gave the similarpulse number of np = 8.209.The analytical FBSM switching frequency calculation in (4.8) enables multiple operatingvoltages to be tested rapidly. Fig. 4.4 shows the switching frequencies calculated by the proposed870.475VDC4204605005400.5VDC 0.525VDC 0.55VDC 0.575VDC 0.6VDCOperating Voltage (V1h)Fig. 4.4. Average FBSM IGBT switching frequency for the operating voltages V1h ∈[0.475VDC, 0.62VDC].analytical model for the operating voltages V1h = [0.0475VDC, 0.62VDC]. It is noted that theseFBSM switching frequencies are calculated based on the NLMmethod.Over the range of operating voltages shown in Fig. 4.4, themean value of the IGBT switchingis 420.24Hz. Since the voltages in Fig. 4.4 represent a typical range of operation for theH5LC forVSC HVDC applications, the FBSMs’ IGBT switching frequency of 420Hz is a representativecharacteristic of the proposed H5LC.4.2.6 DC-Fault ProtectionTo suppress DC-side pole-to-pole short circuit faults quickly and safely, the steps for theDC fault handling sequence are given as:(1) Detection of the DC fault by measuring the DC-side voltage or current prompts all theH5LC’s DSs to be blocked. Meanwhile, a number of cascaded FBSMs in each phase areblocked.(2) Immediately after the FBSMs are blocked, the BTVs of all three phases are triggered onto rapidly commutate the FBSM currents to the BTVs.(3) Once the FBSMs’ currents have been commutated to the BTVs, the FMSs of the twophases with the fully-rated BTVs phases are opened, isolating the cascaded FBSMs fromthe AC-side.88(4) The trigger signals to the fully-rated BTVs are removed immediately after the FMSs areopened.(5) Once the two fully-rated BTVs are turned off naturally, which occurs within half afundamental cycle, the trigger signal to the third phase’s BTV, rated for 18vDC, is removed.The rate of current commutation that occurs during step 2., i.e.,dicommdt, depends on theinductance Lcomm of Fig. 4.1 as well as the voltage produced by the number of blocked FBSMsin 1., i.e.,Nblock, and is presented asdicommdt=∑Nblocki=1 vicLcomm, (4.15)where vic is the voltage of the ith FBSM’s capacitor, as in Fig. 4.1.Lcomm can be considered as stray inductance of the loop containing the BTVs and FBSMsand is approximately equal to 0.5mH. To ensuredicommdtdoes not exceed the BTVs’ criticalrate-of-rise of on-state current,dicritdt, which is typically given in a thyristor’s datasheet,Nblockis chosen for a sufficiently smalldicommdt.4.2.7 Post-Fault Capacitor Charge RestorationAfter the DC fault is cleared, the process of recharging the DC-pole capacitors and the FCsbegins. It is noted that the DC-pole capacitors may be charged from the sending end of theDC-link. However, for the sake of completeness, it is assumed that the DC-pole capacitors andthe FCs are charged through the AC resistor, Rcharge, shown in Fig. 4.2 (a). Therefore, once thefault has been cleared, the AC breaker (ACB) is opened under zero current to insert Rchargeinto the circuit. Once inserted, the FMSs are closed and the FBSMs are bypassed, enablingthe line-to-line voltage to drive a rectified current through the free-wheeling diodes of theDSs {T1,j, T2,j, T3,j, T4,j}, thus passively charging the DC-pole capacitors. Once the DC-sidevoltage reaches the nominal value of VDC, the DSs T7,j and T8,j are turned on, driving a rectifiedcurrent to flow through the free-wheeling diodes of DSs T2,j and T3,j and through the DSs T7,j89and T8,j . After one of vFC,u,j or vFC,l,j reaches its nominal voltage of 14VDC, the correspondingphase’s DSs T7,j and T8,j are blocked. When one of vFC,u,j or vFC,l,j reaches 14VDC for each phase— such that each phase has at least one of its FCs charged to the nominal value — the ACbreaker may be closed to resume normal operation.4.3 Performance EvaluationIn this section, the performance of the H5LC is evaluated for normal, DC-side pole-to-polefault, and AC-side single-phase-to-ground fault operations. The H5LC system with parametersgiven in Table 4.3 is assumed to be fed by a 600 kVDC voltage source through a 100 kmDC cable.The H5LC is modeled and simulated with the MATLAB/Simulink 2014b/Simscape/SpecializedPower Systems toolbox at a 20 µs time step. To generate high quality voltage waveforms, eachphase of the H5LC is modeled with ten 7.5 kV FBSMs, each of which require three series-connected 2.5 kV IGBTs in each switch position with the IGBT parameters listed in Table B.3.Without loss of generality, phases b and c are equipped with both FMSs as well as the fully-ratedBTVs while phase-a’s BTV is rated for 18VDC without the FMS.4.3.1 Normal OperationAs shown in Fig. 4.5, the H5LC can effectively regulate real power exchange between theAC- and DC-sides. At t = 0 s the H5LC’s real power follows a ramp command to P = 900MW.The reactive power is kept at Q = 0MVAR to illustrate the H5LC’s ability to transmit realpower. At t = 0.4 s, an additional ramp command is issued to set the power to P = −900MWandQ = 200MVAR to operate as a rectifier with AC-side capacitive reactive power support.Fig. 4.5 (a) illustrates the change in real and reactive powers while Fig. 4.5 (b) shows the voltagedeviation on the DC-side due to the voltage drop across the 100 km DC cable. Fig. 4.5 (c)shows that the FC voltage ripples are around 6.7% which verifies the FC VBA proposed inFig. 3 by alternating the MH1,2 and ML1,2 states. In Fig. 4.5 (d), the FBSMs’ energy balancingalgorithm is seen to effectively maintain the FBSMs’ total voltage to the set-point of 18VDC whilethe VBA ensures that the FBSM voltage ripples is within±10% of the average SM capacitor90TABLE 4.3Simulation ParametersSimulation parametersMaximum power rating 1096MVAMaximum P 1000MWMaximumQ 500MVARDC-side pole capacitorcapacitance500 µFFBSM capacitorvoltage7.5 kVFBSM capacitorcapacitance1.6mFAC-side inductance 25mHDC-side inductance 25mHTransformer leakageimpedance0.001+ j0.18 puTransformer windingratio350 kV/400 kVvoltage. Figs. 4.5 (e) and (f) show the H5LC’s output line-to-ground voltage and the converter’soutput current, respectively, where the line-to-ground voltage has a small third-order harmonicvoltage component produced by the cascaded FBSMs. It is noted that even with the few FBSMs,the voltage in Fig. 4.5 (e) has high quality and requires minimal filtering. Lastly, the cascadedFBSMs’ output voltage is illustrated in Fig. 4.5 (g) where it is noted that despite the largediscrete switching events, the line-to-ground voltage maintains a clean shape due to the strictcoordination between the five-level converter and the cascaded FBSMs.4.3.2 DC-Side Fault OperationNext, the H5LC’s resilience to DC-side pole-to-pole faults is investigated. Prior to the DCfault, the converter is operating at P = 900MW and Q = 0MVAR, as shown in Fig. 4.5 (a).At t = 0.2 s, a 150ms bolted fault is applied across the H5LC’s DC terminals which quicklyreduces the DC-side and FC voltages to zero, as seen in Figs. 4.5 (b) and (c). The DC-sidesurge current in Fig. 4.5 (d) triggers the DC fault detection within 2ms, i.e., at t = 0.202 s. At91this instance, several FBSMs are placed into the blocking state; immediately after, the BTVsare triggered. From Fig. 4.5 (e), the rapid current commutation from the blocked FBSMsto the BTVs enables negligible charging for the FBSMs in Fig. 4.5 (f). After the current hascommutated away from the FBSMs, the phase-b and -c FMSs open at t = 0.204 s. Immediatelyafter, the trigger signals to the phase-b and -c BTVs are removed. Once the phase-b and -cBTVs have turned off naturally, the trigger signal to the phase-a BTV is removed. At thispoint, the phase-b and -c BTVs are blocking the entire line-to-line voltage while the phase-aBTV is blocking no more than 18VDC.Once the DC fault has been cleared, the DC-side voltage is restored to its pre-fault valuePower at PCC (GVA)0.40.0-0.40.8-0.8PQ(a)DC-side Voltage (kV)620640560580600(b)FC Voltages (kV)160140144152156148(c)FBSM Voltages (kV) 8.07.57.06.56.05.55.00.0 0.40.2Time (s)0.80.6 1.0(d)6.757.508.256.757.508.25vFC,u,a vFC,l,avDC,u+vDC,l92Converter Voltages (kV)-400-2002004000(e)Voltage across FBSMs (kV)604080-80-40-60-202000.28 0.29 0.3Time (s)0.31 0.32(g)Converter Currents (kA)2.0-2.01.0-1.00.00.29 0.30Time (s)0.31()vFB,aFig. 4.5. Converter performance in normal operation. (a). Real and reactive powers. (b). DC-sidevoltage. (c). Phase-a flying capacitor voltages. (d). Phase-a FBSMs voltages. (e). Line-to-groundvoltages. (f). Converter currents. (g) Voltage across the phase-a FBSMs.by the sending end. When the DC-side voltage has reached its nominal value of 600 kV att = 0.450 s, the AC breakers are opened to insert the charging resistors. The charging resistorsare chosen to limit the current through the IGBTs to no more than the IGBTs’ rated value,as can be seen in Fig. 4.5 (a) where the power flow momentarily reaches P = −1.1GW atapproximately t = 0.46 s as the FCs charge passively. The DSs T7,j and T8,j are turned on,rectifying the line-to-line voltage through the free-wheeling diodes of DSs T2,j and T3,j thusenabling only a charging current to flow through the FCs, which is seen in Fig. 4.5 (c).934.3.3 AC-side FaultThe following case study considers the H5LC subjected to a single phase-to-ground faulton the grid-side of its interfacing transformer. Without loss of generality, a 140ms singlephase-to-ground unsymmetrical fault is applied to phase-a at t = 0.2 s. The study considersthe two scenarios: 1)The third-order harmonic calculated with (4.1), (4.3), and (4.4) is injectedinto the phase-to-neutral voltages of all three phases with the cascaded FBSMs, and 2) Withoutany third-order harmonic injection.Since the third-order harmonics are injected on the Delta-side of the transformer, it isexpected that they will not influence the transient on the grid-side. This is proven by Fig. 4.5.Fig. 4.5 (a) presents the real powermeasured at the PCC, which shows no perceptible differencesbetween the two scenarios. The phase voltages at the PCC (i.e., the grid/Wye-side of theinterfacing transformer) are presented in Fig. 4.5 (b), which shows that the PCC voltagesPower at PCC (GVA) 2.01.0-1.0-2.0-3.0-4.0-5.00.0(a)PQFC Voltages (kV) 1506090120030(c) vFC,u,c vFC,l,cDC-side Voltage (kV)4002003005006007000100(b) vDC,u+vDC,l0.1 0.2 0.3 0.4Time (s)0.5 0.70.694FBSM CapacitorVoltages (kV)8.07.05.04.06.00.1 0.2 0.3 0.4Time (s)0.5 0.70.66.67.07.47.88.2()Fault Current (kA) 2.0-2.0-4.0-6.0-8.00.0-10.0-4.0-2.0-6.0-8.00.0(e) FBSMs BTVDC-link Current (kA) 0.0-10-30-40-20(d)Fig. 4.5. The H5LC’s transient response to the DC-side pole-to-pole fault event. (a) Real and reactivepowers. (b) DC-side voltage. (c) Phase-c FC voltages (d) DC-side current. (e) Phase-c fault currents. (f)Phase-c cascaded FBSM voltages.show remarkably high agreement, implying that there is no effect from the injection of thethird-order harmonic. Next, the converter line-to-line voltages are shown in Fig. 4.5 (c), whichagain are matching for the two scenarios. In Figs. 4.5 (d) and (e), the PCC and convertercurrents are respectively shown, which show no differences between the cases.Hence, the H5LC is capable of riding through AC-side faults and its cascaded FBSMs canstill benefit from the voltage reduction enabled by the third-order harmonic voltage injection.4.3.4 HardwareVerificationTo verify the proposed H5LC’s operating principle, a lab-scale, 400V three-phase H5LCwas prototyped through cooperation of a five-level converter and the OPAL-RT Technologies®MMC Test Bench [89], as seen in Fig. 4.6. The five-level converter, i.e., the DSs and FCs of theH5LC as in Fig. 4.1, was constructed in-house with discrete components, including MOSFETs,95DC pole capacitors, FCs, gate drivers, and ADCs for voltage measurement of the FCs andthe DC pole capacitors. The H5LC’s cascaded FBSMs were realized through modificationof the control and connections of three of the MMC Test Bench’s OP1210 modules, each ofwhich contains ten FBSMs. On-board the OP1210 modules are 12-bit 500 ksps serial samplingADCs which measure each of the FBSM voltages as well as their currents. The DC-side voltageis supplied by a Chroma 62100H DC power supply. The AC-side load consists of 2.5mHinductors from the MMC Test Bench’s OP1262 Inductance Box in series with 12Ω resistors ina three-phase floating Wye-connected configuration.The H5LC is digitally controlled by the MMC Test Bench’s OP4510 simulator and itson-board FPGA, the Kintex-7, thereby enabling both CPU and FPGA control. The FPGA isprogrammed using the RT-XSG blockset within the MATLAB/Simulink environment. ThePower at PCC (GW)1.00.50PCC Voltages (kV)200400-400-2000With Third-Order Harmonic Without Third-Order Harmonic(b)Without Third-Order HarmonicWith Third-Order Harmonicvas vbs vcsConverter Line-to-lineVoltages (kV) 500-5000Without Third-Order HarmonicWith Third-Order Harmonicvabt vbct vcat(a)(c)0.15 0.25 0.350.300.20 0.40 0.45Time (s)96Currents at PCC (kA)-224600.15 0.25 0.350.300.20 0.40 0.45Without Third-Order HarmonicWith Third-Order Harmonicias ibs icsConverter Currents (kA)Time (s)-2210-1Without Third-Order HarmonicWith Third-Order Harmoniciat ibt ict(d)(e)Fig. 4.5. The H5LC’s transient response to the single-phase-to-ground fault event. (a) Real power. (b)Line-to-ground voltages at the PCC. (c) Converter-side line-to-line voltages. (d) Currents at the PCC.(e) Converter currents.Three-Phase Five-Level ConverterCascaded FBSMsPhase-aPhase-aPhase-bPhase-bPhase-cPhase-cFig. 4.6. Lab-scale experimental setup of the proposed H5LC.operating conditions of the H5LC, i.e., its AC voltage magnitude and frequency, are CPU-controlled parameters that are varied in real-time using MATLAB/Simulink with RT-Labv2019.1. With the AC voltage magnitude and the operating frequency as its inputs, the Kintex-7generates the requested voltage states for both the five-level converters and the cascaded FBSMs.97Converter phase voltage (50V/div)AC-side chain-link voltage (30V/div) (a)SM Voltages (V) 433.52.5210 10.01 10.02 10.06 10.08 10.1(c)Phase Currents (A) 10-100(b)Time (s)Fig. 4.7. Experimental results. (a) Converter AC line-to-neutral voltage and cascaded FBSMs voltage.(b) Converter three-phase AC output currents. (c) Ten FBSM voltages for phase-a.cascaded FBSM voltage balancing is enabled by OPAL-RT’s proprietary method which uses theADC-measured values of the FBSM voltages and current to determine the correct switches toinsert or bypass. For control of the three five-level converters, the Kintex-7 outputs nine bitsserially over a fiber optic cable, which correspond to the five voltage states of each. The fiberoptic cable is terminated by a transceiver which is fed to the Artix-7 FPGA-based BASYS 3development board. The Artix-7 decodes the serial input from the Kintex-7 to generate the24 discrete switching signals required by the five-level converter’s MOSFETs. The BASYS 3also implements the MOSFETs’ dead-time and the FC balancing algorithm of Table 4.2 todetermine which of the MH1,2 or ML1,2 states are chosen. The experimental setup of Fig. 4.6shows the five-level converter on the right side and the cascaded FBSMs on the left side foreach phase.Fig. 4.7 presents the hardware results for the conceptual verification of the proposed H5LC.The upper graph of Fig. 4.7 (a) shows the phase-a five-level voltage, v5LC,a, with the fundamental98voltage component V1h = 0.6VDC; the lower graph is the phase-a FBSM voltage, vFB,a. Fig. 4.7(b) presents the converter phase currents which are high-quality sinusoids due to the use of thecascaded FBSMs. Fig. 4.7 (c) shows the 10 FBSM capacitor voltages of phase-a, which are keptwell-balanced to their set-point level of 18NvDC = 2.75V. Thus, Fig. 4.7 confirms the operationof the proposed converter and its ability to generate sinusoidal voltages and currents in a steadystate.To demonstrate a transient response of the H5LC, a step-increase of the output voltagecommand from V1h = 0.25VDC to V1h = 0.45VDC is considered here. For the transient responsetest, an inductor of 17.6mH is placed in parallel with the 12Ω resistive load while the DC-side voltage is reduced to 150V to ensure the AC-side current does not exceed 15A. Theexperimental results of this study are shown in Fig. 4.8, wherein Fig. 4.8 (a) shows a nearlyinstantaneous transition of the output voltage from V1h = 38V to V1h = 68V. The converterPhase Voltages (V)Line-to-Line Voltages (V)Converter Currents (A)30.5064.03 84.0324.03 44.0330.4063.03 83.03Time (s)99Phase-aFBSM Capacitor Voltages (V)Hardware Sum of Phase-aFBSM Voltages (V)Simulated Sum of Phase-aFBSM Voltages (kV)30.6030.5054.0353.03 04.03 30.55Time (s)30.6030.5054.0353.03 04.03 30.55Time (s)Fig. 4.8. Transient response of experimental hardware setup: (a) Three-phase phase voltages showingthe third-order harmonic. (b) Three-phase sinusoidal line voltages. (c) Three-phase currents. (d)phase-a FBSM individual capacitor voltages. (e) Sum of ten FBSM phase-a voltages and its comparisonagainst the simulation result.phase voltages in Fig. 4.8 (a) clearly show the presence of the third-order harmonic, whichchanges amplitude from V3h = 27.5V to V3h = 18.0V as dictated by solving (4.1), (4.3), and(4.4). The line-to-line voltages in Fig. 4.8 (b) remain sinusoidal as expected.As seen in Fig. 4.8 (c), the phase currents also change from approximately 8A to 15A duringthis transient while remaining sinusoidal. Due to the high current and the low impedanceof the parallel RL load, the ripples of the FBSMs’ capacitor voltages have also become morepronounced, as observed in Fig. 4.8 (d). The OP1210 uses the FBSMs with 5mF capacitors,which is insufficient to keep the ripple below±10% when their average voltage is only 2.2Vwith peak currents of 15A. To further verify the experimental operation of the H5LC, the sumof all ten FBSMs capacitor voltages is compared against the respective simulation in Fig. 4.8 (e),showing high agreement. The matching shapes of the FBSM capacitor voltage ripple obtainedby hardware and simulation, and the sinusoidal currents of Fig. 4.8 (c) verify the proposed100cascaded FBSM capacitor energy balancing and the third-order harmonic voltage injectioncontrols.4.4 Converter ComparisonIn this section, the H5LC is benchmarked with the HBSM- and MBSM-MMCs, the EO-AAC, and the three converters proposed in this thesis — the H3LC, TH3LC, and H5LC.The converters are all sized for the same DC-side voltage of 600 kV with the power ratingof 1GVA. The converters are compared based on key parameters, including semiconductorcounts, semiconductor losses, SM energy storage, and maximum allowable AC-side voltage.The same 4.5 kVWestcode IGBT [90] is used for each converter at the operating voltage of2.5 kV, with its parameters listed in Table B.3.4.4.1 Converter Rating AnalysisIn the “General converter comparison” portion of Table 4.4, a summary of the mainparameters of each of the converters and their general capabilities is presented. The same7.5 kV SM voltage is used for each of the converters for a fair comparison. Therefore, for the2.5 kV IGBT of [90], three series-connected IGBTs are required for each switch position of theSMs. Consequently, the number of cascaded SMs in each converters’ set of cascaded SMs isdetermined by dividing the cascaded SMs’ total required blocking voltage by the SM voltage of7.5 kV. Therefore, each arm of the MMCs requires 600 kV7.5 kV= 80 SMs, for a total of 480 SMs.The EO-AAC’s six sets of cascaded FBSMs each block 23VDC = 400 kV for a total FBSM countof 324. The H3LC, as shown in Chapter 2, requires enough FBSMs to block 0.55VDC to enableDC-fault tolerance, for a total of 44 7.5-kV FBSMs per phase for a total of 132 FBSMs; 60FBSMs are required for normal operation. The TH3LC’s Commutation Branch FBSMs blocka total of 12VDC + vcomm; however, vcomm is a design parameter and is ignored in this analysis.Therefore, for its Commutation Branch FBSMs, the TH3LC requires 40 FBSMs per phase for atotal of 120 FBSMs. Its AC-side Cascaded FBSMs are rated for 14VDC for 20 FBSMs per phase.Therefore, in total, the TH3LC requires 180 FBSMs. Lastly, the H5LC’s cascaded FBSMs are101sized to only 18VDC for a total of 10 FBSMs per phase, and 30 FBSMs total. Its DC-fault toleranceis enabled by its BTVs, as presented in Section 4.2.6. It is noted that due to its reduced numberof FBSMs, the H5LC requires fewer IGBTs than the HBSM-MMC.To provide DC fault resilience, both the HBSM-MMC and the H5LC are equipped withBTVs to protect/bypass the converters’ IGBTs. The accepted H5LC paper [97] assumes the6.5 kV bidirectional controlled thyristor, i.e., the ABB 5STB 18U6500 [98] bidirectionallycontrolled thyristor for its high blocking voltage of 6.5 kV as well as its ability to conductcurrent bidirectionally, which is required for the H5LC’s BTVs. However, for a fair comparisonwith the TH3LC, the 8.5 kV phase-controlled thyristor, the ABB 5STP 27N8500 of [96] is usedfor all converters. The thyristors are de-rated by the same ratio as the IGBTs, i.e., the thyristorblocking voltage is 4.7 kV for the scope of this chapter. The HBSM-MMC requires six thyristorvalves which can each sustain the entire DC-link voltage; therefore, the HBSM-MMC requires2×600 kV4.7 kV= 256 thyristors per arm for a total of 1536 thyristors. The H5LC requires twoBTVs of rating 1.07VDC and one BTV of rating 18VDC, which amounts to a total thyristor countof 584. Nonetheless, the H5LC requires less semiconductor area than the HBSM-MMC, furtherreducing its footprint and capital costs.As noted throughout this chapter, the DSs of the H5LC can operate with fundamental-frequency switching. However, increasing their switching frequency reduces the FCs’ andDC-side pole capacitors’ energy storage, as presented in Table 4.4. By employing the FCbalancing algorithm of Fig. 4.3, only one additional time during each of the four MH1,2 andML1,2 states, the FCs’ energy storage can be significantly reduced. However, for np additionalswitching instances during each of the MH1,2 and ML1,2 states, the average DS switchingfrequency increases by a factor of np + 1 . As in the “General converter comparison” portionof Table 4.4, fundamental frequency operation of the H5LC’s DSs occurs when np = 0. Asexplained in Sections 4.4.2 and 4.4.3, increasing np from 0 to 1 results in significant savings ofthe FCs’ energy storage requirements without incurring high losses.102TABLE 4.4Comparison of Selected ConvertersConverter typeHBSM-MMCMBSM-MMCEO-AACH3LC TH3LC H5LCGeneralconvertercomparisonMaximum ACvoltage, V1h (×VDC) 1/√3 1/√3 2/3 0.63 0.63 0.62DC-side voltage 600 kV 600 kV 600 kV 600 kV 600 kV 600 kVNo. of 7.5 kV SMs 480 480 324 132 180 30No. of IGBTs 2880 4320 4800 3744 2160 2520No. of thyristors 1536 0 0 0 1920 584DC-fault tolerant No Yes Yes Yes Yes YesDS switchingfrequency (Hz)- - 50 50 50 50×(1+np)DS switchingvoltage (kV)- - 0 300 0 150Average SM IGBTswitching frequency (Hz)150 112.5 37.5 240 115 420LossanalysisAC voltage, V1h (×VDC) 0.523 0.523 2/3 0.573 0.5730.564np=0 np=1SM Pcond (MW) 3.68 5.62 3.77 1.75 2.36 0.9 0.9SM Psw (MW) 2.30 2.30 0.95 1.31 1.69 0.96 0.96DS Pcond (MW) - - 1.80 3.42 0.79 3.48 3.46DS Psw (MW) - - - 0.44 0.16 0.40 0.60Total Loss (MW) 5.98 7.92 6.52 6.92 5.00 5.74 5.92Percentage Loss 0.60% 0.79% 0.65% 0.69% 0.50% 0.57% 0.59%Energyanalysis AC voltage, V1h (×VDC) 0.523 0.523 2/3 0.573 0.5730.564np=0 np=1Total nominal energystorage requirements (MJ)30.45 30.45 14.2 3.52 6.28 21.09 10.73Normalized to MMC 1.00 1.00 0.466 0.116 0.201 0.693 0.352103TABLE 4.5Normal Operation Energy Storage and Capacitor Sizing Results of ProposedConvertersConverter type H3LC TH3LC H5LCElement FBs PCs FBs CFBs PCs FBsFCs PCsnp=0 np=1 np=0 np=1AC Voltage, V1h (×VDC) 0.573 0.573 0.564∆E (MJ) perelement0.25 0.16 0.245 0.326 0.219 0.09 0.80 0.22 0.39 0.16NSM per element 20 1 20 40 1 10 1 1 1 1Vnom (kV) 7.5 300 7.5 7.5 300 7.5 150 150 300 300Cc (mF) 1.11 0.0181 1.088 0.724 0.024 0.8 0.18 0.04 0.04 0.02Enom (MJ) perelement0.62 0.81 0.61 0.82 1.09 0.23 2.03 0.50 1.80 0.81Total Energy (MJ) 1.88 1.64 1.84 2.45 2.19 0.69 12.01 3.28 3.60 1.62Converter totalenergy (MJ)3.52 6.48np = 016.30np = 15.59Normalized toMMC’s 30.45MJ0.12 0.21 0.535 0.1834.4.2 Energy Storage ComparisonIn this section, the energy storage calculation method for the H5LC’s pole capacitors andFCs is presented. It is noted that the values of the energy storage of the H5LC given in Table 4.4correspond to a 5% maximum allowable pole capacitor voltage ripple, as in [97]. However,similar to the H3LC in Section A.3, the sizing of the pole capacitors can be reduced if a 5%pole-to-pole DC voltage ripple is allowed.Increasing the DS switching frequency during the MH1,2 and ML1,2 states, i.e., alternatingbetween the MH1 and MH2 or ML1 and ML2 states, enables the FCs’ capacitance to be reduced.Contrasted to the cascaded FBSMs, where the energy deviation occurs irrespective of SM IGBTswitching frequency, the FCs’ capacitance can theoretically be reduced to zero with an infiniteDS switching frequency. It is noted that increasing the DS switching frequency during theMH1,2 and ML1,2 states affects the DC pole capacitor sizing, since the MH1and ML2 use theT1,j and T4,j DSs, respectively.104First, the FCs’ worst-case energy storage requirements are derived by analyzing phase-a’supper FC’s peak-to-peak energy deviation,∆EFC,u,a. Assuming steady-state operation andfundamental-frequency DS switching, two complete electrical cycles are used to ensure vFC,u,adoes not deviate from its set-point of 14VDC. The two MH1,2 levels in the first electrical cyclemay be chosen arbitrarily so long as the second electrical cycle’s MH1,2 levels are opposite tothe first. The selection of MH1,2 states does not influence the worst-case energy storage. Thefour possible combinations for the phase-aMH1,2 states, are given asMH1,2 =MH1 ωt ∈ [α1, α2]MH1 ωt ∈ [pi − α2, pi − α1]MH2 ωt ∈ [2pi + α1, 2pi + α2]MH2 ωt ∈ [3pi − α2, 3pi − α1]MH1,2 =MH1 ωt ∈ [α1, α2]MH2 ωt ∈ [pi − α2, pi − α1]MH2 ωt ∈ [2pi + α1, 2pi + α2]MH1 ωt ∈ [3pi − α2, 3pi − α1]MH1,2 =MH2 ωt ∈ [α1, α2]MH1 ωt ∈ [pi − α2, pi − α1]MH1 ωt ∈ [2pi + α1, 2pi + α2]MH2 ωt ∈ [3pi − α2, 3pi − α1]MH1,2 =MH2 ωt ∈ [α1, α2]MH2 ωt ∈ [pi − α2, pi − α1]MH1 ωt ∈ [2pi + α1, 2pi + α2]MH1 ωt ∈ [3pi − α2, 3pi − α1](4.16)Using the energy deviation calculation of (A.7), the upper FC’s energy deviation,∆EFC,u,a, iscalculated as∆EFC,u,a(ϕ) = max(∫ t014VDCiFC,u,a(τ, ϕ) dτ)−min(∫ t014VDCiFC,u,a(τ, ϕ) dτ)(4.17)where iFC,u,a is defined in Table 4.1. When ϕ is swept across ϕ ∈ [0, 2pi], the worst-case energydeviation occurs at ϕ = ±pi2and corresponds to a peak-to-peak energy deviation of 0.80MJper FC, which is the value recorded in Table 4.5.During the MH1,2 or ML1,2 states, additional switching instances can be introduced toreduce the energy deviation of the FCs’ capacitors. By adding np additional switching instancesto each of the MH1,2 or ML1,2 states, the FCs’ total energy storage can be continually reduced as105the DS switching frequency increases. Table 4.5 presents the FC and pole capacitor energies forvarious additional switching events, np, which shows that with even just one extra switchingevent during each of the MH1,2 or ML1,2 states, the FCs’ energy storage can be reduced 73%from 12.01MJ to 3.28MJ. Table 4.4 shows the DS switching losses with the cases of np=0 andnp=1. Although the DS switching losses increase due to the additional switching events, theconverter loss increase is small (an additional 0.2MW, as in Table 4.4). Hence, the H5LC canachieve overall smaller energy storage without significantly impacting the converter losses.The DC-side pole capacitors’ worst-case energy storage can be found similarly to the FCs’.First, the upper pole capacitor’s current, iC,u, is determined byiC,u(t, ϕ) = iDC(ϕ)−T1,aT1,bT1,c ·iˆAC sin(ωt+ ϕ)iˆAC sin(ωt− 2pi/3+ ϕ)iˆAC sin(ωt+ 2pi/3+ ϕ). (4.18)From Table 4.1, T1,j ≡ 1 during either the H or MH1 states and is 0 otherwise. As in(4.16), there are four unique combinations of MH1and MH2. Hence, there are 43 = 64 possiblecombinations for the MH1and MH2 states among all phases. For each of the 64 combinations,the 64 worst-case ϕ power factor angles and energies can be found. Among these 64 worst-caseenergies, the minimum is chosen, since in steady-state it is assumed that the ordering of theMH1,2 states does not change. Based on the above analysis, the worst-case energy stored withinthe two DC-side pole capacitors is 8.40MJ, which is the value used to determine the totalH5LC energy storage in Table 4.4.A comparison of the H5LC’s nominal energy storage requirements for varying values of npis presented in Table 4.6. The results show that as np increases, the energy storage of the FCsreduces in turn, with the largest reduction in energy occurring between the np = 0 and np = 1cases. The energy storage of the pole capacitors also reduces to its minimum value of 5.61MJwhen a 5% pole capacitor voltage ripple is considered, and to a minimum of 0.51MJ when thepole-to-pole DC voltage ripple is 5%. The results of Table 4.6 again confirm that operating106TABLE 4.6FC and Pole Capacitor Energies versus DS Switching FrequencynpFC totalenergy (MJ)Pole capacitortotal energy(MJ)(5% cap. ripple)Pole capacitortotal energy(MJ)(5% DC ripple)DS switchingfrequency (Hz)0 12.01 8.40 3.60 501 3.28 7.78 1.62 1003 1.64 7.49 0.85 2007 0.82 6.51 0.68 40015 0.41 6.06 0.57 80031 0.20 5.84 0.56 1600→∞ → 0 → 5.61 → 0.51 →∞the H5LC when np = 1 results in the best total energy storage due to the small amount ofincreased losses.It is noted that the DC pole capacitors are rated to the pole-to-pole or pole-to-groundvoltages and thus are often designed to have a cylindrical shapeThe SM capacitors are typicallyrated to 4.5 kV, similar to the blocking voltage of the FBSMs’ IGBTs, in a rectangular shape.The FCs or DC pole capacitors can be concentrated together in a parallel connection thatsignificantly reduces the high-voltage clearance distance requirement compared to the SM-based capacitor energy storage of the MMC. Hence, even for the same amount of energy storedin SM capacitors or DC pole capacitors, different converter footprints are expected. Therefore,the comparisons of converter footprint using total stored energy across different capacitortypes (pole capacitor vs. SM capacitor) is more valuable when considering similar types ofcapacitor types. While the FCs corresponding to the np = 0 case have the sizeable nominalstorage requirement of 21.09MJ, the FCs’ capacitance is not distributed amongst submodules;rather, each FC’s capacitance is grouped together, increasing its compactness.A breakdown of the H5LC’s cascaded FBSMs’ energy storage requirements compared tothe MMC’s, EO-AAC’s, H3LC’s, and TH3LC’s are presented in Table 4.7. The results show that107TABLE 4.7Submodule Energy Storage of H5LC Compared to Other TechnologiesConverter type MMCEO-AACH3LCTH3LCH5LCFBs CFBs∆Ec (MJ) perN elements 2.03 0.95 0.26 0.25 0.33 0.09No. of elements per arm/phase 80 54 20 20 40 10Total energy stored in SMs (MJ) 30.45 14.25 1.93 1.84 2.45 0.69Normalized to MMC 100% 46.8% 6.3% 6.0% 8.0% 2.2%the H5LC’s FBSMs require the least energy, requiring approximately a third of the H3LC’s andTH3LC’s and only 4.7% and 2.2% of the EO-AAC’s and MMC’s, respectively.4.4.3 Semiconductor LossesUsing (B.3) and (B.4) for the semiconductor conduction losses and (B.43) to (B.45) forthe semiconductor switching losses, the losses of the considered converters — obtained fromthe detailed switching-based simulation models of each of the converters — are presented inthe “Loss analysis” portion of Table 4.4. Each of the converters is operated under the sameconditions, with the AC voltages given in Table 4.4 and the real power of 1GW with unitypower factor in inverter mode.The losses of the converters are separated into DS and SM conduction and switching losses.It is observed in Table 4.4 that while the H5LC’s conduction losses are increased compared tothe HBSM-MMC’s, its switching losses are reduced, which improves its total losses comparedto the HBSM-MMC (0.57% compared to 0.60%). It is noted that Table 4.4 also shows theH5LC’s semiconductor losses when np is increased to 1. For np = 1, the DS switching lossesdo not change significantly, with an increase in losses of 0.38MW to 0.58MW for a totalpercentage increase of only 0.02%. Compared to the EO-AAC, the H5LC is noted to have bothimproved losses as well as requiring 48% fewer semiconductor devices. It is noted that, despitethe EO-AAC’s low FBSM IGBT switching frequency of 37.5Hz, it has approximately an orderof magnitude more FBSMs than the H5LC, making the total FBSM IGBT switching lossescomparable. However, the H5LC requires BTVs for the DC-fault blocking.108Although the H5LC’s FBSMs’ IGBTs have a higher average switching frequency than theH3LC’s, its FBSM switching losses are lower than the H3LC’s due to the H5LC having halfas many normal-operation FBSMs. However, the DS conduction and switching losses of theH5LC and H3LC are similar. Because the H3LC operates at a slightly lower voltage than theH5LC, the conduction losses of the H5LC’s DSs are somewhat higher than the H3LC’s for thesame 1GW of power; however, the H5LC’s DS switching losses are slightly improved. Thiscan be explained by the nonlinear relationship between the two switching angles of the H5LCcompared to the single switching angle of the H3LC as follows:At the H5LC’s and H3LC’s operating voltages of V1h = 0.564VDC and V1h = 0.573VDC, thefive- and three-level converter switching angles are {α1, α2} = {0.193, 0.662} and α = 0.451.For the unity power factor tests of Table 4.4, over ωt ∈ [0, pi2], the H5LC’s and H3LC’s DSswitching losses for the H5LC’s AC-side current of ia(t) = iˆAC sin(ωt) are given by (B.81) asP 5LCsw,DS =VDC4pi[(Eon+Erec)(ia(α1ω)+ ia(α2ω))+Eoff(ia(pi − α1ω)+ ia(pi − α2ω))], (4.19)P 3LCsw,DS =0.5640.573VDC2pi[(Eon+Erec)ia(αω)+ (Eoff)ia(pi − αω)], (4.20)where the fraction 0.5640.573scales iˆAC appropriately. Equations (4.19) and (4.20) are simplified toP 5LCsw,DS = 0.354VDCiˆAC, (4.21)P 3LCsw,DS = 0.378VDCiˆAC. (4.22)Hence, despite using a higher slightly higher nominal operating voltage—with proportionatelyreduced AC-side current — the H3LC’s DS losses for the unity power factor current areapproximately 7% higher than the H5LC’s, which matches the data in Table 4.4.1094.5 ConclusionThis chapter proposed a new hybrid five-level converter with AC-side cascaded FBSMs forVSC-HVDC applications. A third-order harmonic voltage injection scheme was proposedto permit a low voltage rating of 18VDC for the cascaded FBSMs. A novel DC fault blockingscheme that uses BTVs was proposed for the H5LC to enable preservation of the H5LC’s IGBTs.Detailed simulation studies of a 600 kV HVDC system demonstrated that the proposed H5LCcan effectively control real and reactive power and suppress DC-side pole-to-pole faults. Alaboratory-scale experimental prototype with ten FBSMs was constructed to demonstrate thefeasibility of the proposed concept. The H5LC features high quality sinusoidal output voltageswhile requiring fewer semiconductors and a smaller footprint than the HBSM-MMC.As an indicator of converter size, energy storage analysis comparing the HBSM-, MBSM-,and FBSM-MMCs, EO-AAC, and the H3LC showed that the cascaded FBSMs of the H5LCrequire only 2.2% as much energy storage as those of the MMCs, 4.7% of the EO-AAC’s, andabout a third compared to the H3LC’s. Moreover, with regard to the total energy storagerequirements of the converters, the H5LC was shown in Table 4.5 to have the low energystorage requirements of 5.59MJ at its nominal operating voltage when np = 1, compared to theMMC’s 30.45MJ — a reduction of 82%. Table 4.5 also shows that the H5LC has similar energystorage requirements to the H3LC (3.52MJ vs. 5.59MJ), but features significantly lower losses(0.69% vs. 0.59%— a 15% decrease). Even when the H5LC uses the np = 1 operating mode,its semiconductor losses are slightly better than even the HBSM-MMC’s (0.59% compared tothe MMC’s 0.60%); when the np = 0 operating mode is chosen, the H5LC’s losses improvefurther to 0.57%.Coupled with its DC-side fault blocking capability— enabled by its BTVs and FMSs scheme— the H5LC features exceptional efficiency and a small converter footprint enabled by its lowenergy storage requirements. Furthermore, compared to the HBSM-MMC, the H5LC requires12.5% fewer IGBT modules such that its expected upfront capital costs are anticipated to beless than the HBSM-MMC’s.1105. Dual-Arm Modular Multilevel ConverterMotivated by the advantages of the AAC over the H2LC and H3LC— namely, the ZVS ofits DSs and its ability to block DC-side faults inherently — the dual-arm converter (DAC) isproposed in this chapter. Compared to the MMC and AAC, which both have six SM-basedstacks, the DAC only requires two stacks. The DAC is able to generate high-fidelity three-phase AC voltages by using its stacks to filter out all but the triplen harmonics in the AC-sidephase-to-voltages, which vanish in the line-to-line voltages.The DAC’s DSs operate under ZVS, and it has inherent DC-fault blocking capability. Thischapter proposes the DAC’s topology and operating principle and provides comparisonsbetween it and other state-of-the-art converters in terms of the number of components, semi-conductor losses, and energy storage requirements.The DAC uses a novel operating principle and structure that enables a single stack ofFBSMs to be multiplexed amongst the available three phases, which reduces the number ofsubmodules required for DC/AC conversion. The DAC is based on a novel building block —the Multiplexed Converter Arm (M-Arm) — which can be used in various configurations toform different converter topologies, as will be shown in subsequent chapters.5.1 Multiplexed Converter ArmSince the initial invention of theMMCs and its subsequent widespread industrial acceptance,there has been continuous research and development focused on the design of more efficientsubmodules, the reduction of losses and energy storage requirements, and the reduction ofthe overall converter size. The recently proposed and patented SO-AAC and EO-AAC [63],[67] represent a notable enhancement over the conventional MMC in terms of operation,This chapter is based on the recently submitted IEEE journal article “Dual-ArmModularMultilevel Converterwith a Compact Footprint for VSC-HVDCApplications,” which was submitted to the IEEE Transactions on PowerDelivery and is under second round of revision [86]. Moreover, the DAC and the multiplexed converter arms,i.e., the M-Arms, that compose it are presently undergoing the patent filing process. At the time of writing, thetechnologies are under provisional patent protection.111wherein each stack of submodules is temporarily turned off (i.e., blocked) for part of thecycle. This operation is enabled by the AAC’s DSs, which are realized as a series connection ofsemiconductors to enable a stack of SMs to be temporarily removed (i.e., electrically isolated)from the phase terminal of the circuit. For the AAC, a converter arm is defined as a stack ofSMs that is in series with the DS. The AAC’s blocking action enables the upper arm to generatevoltage only for the positive portion of the AC voltage, and the lower arm to generate only thenegative voltage, respectively. In contrast, both of the MMC’s arms of each phase-leg must eachgenerate both the positive and negative portions of the AC voltage. This difference allows theAAC’s arms to generate peak voltages that have only half the amplitude of the MMC’s voltages,enabling each arm to only have approximately half as many SMs.In the MMC or the AAC, each arm may be connected to only its own phase terminal. Asa result of this hard-wired configuration, the AAC is required to have six arms to generatethree-phase AC voltages, similar to the MMC.Thus, despite the AAC’s improvements overthe MMC in terms of its size and the total number of SMs (enabled by its novel blockingaction), further improvements to the converter size are possible if a topology with fewerconverter arms and fewer SMs is developed. Such a reduction would garner great savings inthe construction of such a converter, especially if it is to be commissioned many hundreds ofkilometers offshore, where a smaller converter footprint equates to a smaller offshore platformand fewer components to be shipped.To enable a further reduction of a converter’s internal energy storage, and therefore itsoverall footprint, a fundamentally different concept is proposed that is based on the idea of“reusing” each of the converter arms, such that instead of being hard-wired to a single-phase,each armmay connect to any of the phases using appropriate DSs. That is, while the arm is beingdisconnected from a given phase using its DS (as they do for the AAC), it is being immediatelyre-connected to another phase in a complementary manner using other DS, respectively. Thisensures that each of the available arms and its stack of SMs are in continuous use and alwayscontribute to the formulation of the AC voltages. This is a fundamental departure from the112AAC’s blocking phase approach, which results in a wasted potential of the converter’s SMs byhaving them blocked for up to half an electrical cycle.Herein, this new concept is referred to as the “Multiplexed Converter Arm” (M-Arm). Ata very fundamental level, this concept envisions that since such an M-Arm can be reused bydifferent phases, the total number of converter arms can be reduced compared to that of theestablished MMC and AAC technologies. Therefore, the proposed new approach enables thepossibility of designing converters with fewer arms, fewer overall SMs, and a smaller footprint.The M-Arm may be viewed as a building block from which it becomes possible to realizeconverters with a fewer total number of arms.The proposed M-Arm is composed of a single stack of submodules that are connected toa star-connection ofN director switches (DSs), as depicted in Fig. 5.1 (a) (for a three-phasesystem,N = 3). For the topologies considered here, one of the terminals of the stack of SMs(e.g., top terminal in Fig. 5.1) is connected to either the positive or negative DC terminal. Theother terminal of the stack (e.g., bottom terminal in Fig. 5.1) is connected toN DSs that arehard-wired together, thus forming a star-connection. These DSs are able to re-connect thegiven arm to any of the ith AC phases. Here, the AC terminals are indexed as i ∈ {1, . . . , N},as shown in Fig. 5.1 (a). For a typical application, a three-phase system is considered, but othernumbers of phases, as well as different connections of M-Arms, are also possible. A DS can berealized using several semiconductor devices that together can enable bidirectional currentflow via its on/off control.Thus, this configuration enables the stack of SMs to connect to any of the N phasesand conduct current in both directions. Due to its principle of multiplexing enabled by theappropriate operation of the DSs, the stack of SMs can carry current continuously, even whenit is switched among the available converter AC phases. This feature represents a utilizationadvantage over the previous AAC patent, where the currents flowing through the stacks may bezero for up to half of the operating cycle. In this way, the proposed M-Arm approach improvesthe utilization of the most expensive components within the converter, i.e., the converter SMs.113Depending on the application/realization, the submodules in the arm may be of a differenttype, as depicted in Fig. 5.1 (b). Here, the SM output terminal voltage is denoted by vSM, andits internal capacitor voltage is labeled as vc. For some applications, the SMs might need togenerate only positive- or zero-level voltages, i.e., unipolar voltages, such that depending onthe state of SM, we may have vSM = vc or vSM = 0. The half-bridge SM of Fig. 5.1 (b-i) satisfiessuch requirements. For other applications, the SMs capable of generating bipolar voltages,such as the full-bridge sub-modules (FBSM) of Fig. 5.1 (b-ii), might be required. Such FBSMs,depending on the state of their transistors, can generate the output voltages vSM = vc, vSM = 0,as well as vSM = −vc. Depending on the SM type, each SMmay house one or more capacitors,which cumulatively store the energy that is needed for converter operation.It is expected that the proposedM-Arm approach has a great potential to reduce the cost andfootprint of the volume-limited converter stations, such as those used in off-shore installations.We expect that the benefits and novelty of our new methodology will be easily recognized byHVDC converter manufacturers. The three major points may be summarized as follows:(1) The total number of submodules and energy storage elements can be reduced for theconverters in which the M-Arm is utilized (instead of conventional arm);(2) Depending on the implementation, using the M-Arms may lead to a reduction in theoverall converter size. This is because the bulkiest portion of a converter’s constructionis its submodules. Using the M-Arm enables a great reduction of the total number ofneeded SMs for the same equivalent functionality;(3) The initial capital costs of the converter station’s construction can be reduced as well. Thismay be especially relevant for offshore wind energy generation, where HVDC convertersare often constructed many kilometers offshore. Therefore, even a modest reduction inthe converters’ footprints would result in great savings.A plurality of new and compact converters may be constructed using several proposedM-Arms, and possibly other elements (such as capacitors). As it was mentioned, one side of the114      (a)Multiplexed Converter ArmStack of SubmodulesDC terminals(Positive or Negative) Director SwitchesA B N−1 N........+ ++ +++vcvcvcvcvcvcvc vc vcvcvcvcvSMvSMvSMvSMvSMvSM vSM+(i)++(iii)+(ii)(b)++(v)(iv)(vi) (vii)Fig. 5.1. The concept of the multiplexed converter arm and its possible submodules: (a) Topology of theN-phase multiplexed converter arm; (b) Various types of unipolar and bipolar submodules, including:(i) Half-bridge submodule; (ii) Full-bridge submodule; (iii) T-Type NPC submodule; (iv) Semi-full-bridge submodule; (v) Three-level neutral-point-clamped submodule; (vi) Five-level cross-connectedsubmodule; (vii) Clamped-double submodule.M-Arm (i.e., the terminal of the stack of submodules) is connected to the DC-side positive ornegative terminal, while the other side is able to be connected to any one of the AC phases (twoor more) on the AC-side through its DSs. Moreover, the M-Arms may be connected amongstthemselves (typically an Upper and a LowerM-Arms may be connected) in order to establisha path for the DC current to flow. This provides the means for charging and balancing the SMcapacitors inside the arms and allows removing the DC-side pole capacitors. The two mostobvious topologies that may be constructed using the proposedM-Arms include the Dual-ArmConverter (DAC), which will be presented below, as well as theQuad-Arm Converter (QAC)and Multiplexed-Stack Converter (MSC), which are described in Chapter 6 and Chapter 7,respectively.115iDCLDCvDCiC,uiC,lOptionalAC-side stacksFBSMFBSMFBSMFBSMFBSMFBSMvFB,a+-vcFBSMiSu,aSm,aSm,bSm,cSu,b Su,cFBSMFBSMFBSMFBSMUpper M-ArmMidpoint DSsLower M-ArmvuiuSl,cSl,bSl,cvl ilOptional Hybrid DSCuClvaiaibicvbvcvatvbtvctFig. 5.2. The DAC’s topology.5.2 TopologyThe topology of the DAC is presented in Fig. 5.2 wherein its two submodule-based stacks,each rated for 12VDC, are in series with three star-/Y-connected unidirectional DSs, each ratedfor the peak line-to-line voltage. One stack connected to three star-connected DSs is referredto as a multiplexed converter arm (M-Arm), which enables the stacks to connect to any of thethree phases. The cascaded FBSMs of the Upper and Lower stacks synthesize the voltages vuand vl, respectively. The DAC’s Upper and Lower pole capacitors (PCs), Cu and Cl in Fig. 5.2,form the midpoint, n, to which the voltages are referenced. The three Midpoint DSs, i.e., Sm,j,where j ∈ {a, b, c} is reserved to denote the three phases, enable connection between thethree-phase AC terminals and the PCs’ midpoint and are rated for the peak bidirectional value116of the phase-to-midpoint voltages, denoted by vj . The three Upper DSs are denoted by Su,j andthe three Lower DSs by Sl,j. To expand the range of AC output voltage amplitudes, the Upperand Lower stacks can be operated to overlap with the Upper and Lower PCs, respectively, todrive circulating currents that ensure FBSM energy balance. Overlapping operation reducesthe voltage quality at vj, which can be corrected by operating the optional AC-side stacks ofFig. 5.2 as active filters to ensure sinusoidal line-to-line voltages at the AC terminals, denotedby vjt.Without the optional AC-side stacks, vj = vjt.5.3 Operating PrincipleIn this section, the DAC’s operating principle is first derived under the assumption that theoptional AC-side stacks are omitted; then, in Section 5.3.4.2, their operation is described. TheDSs operate sequentially through six topological states determined by the AC voltages to beproduced at the AC terminals. Table 5.1 summarizes the sequence of topological intervals andthe states of the DSs with respect to the converter angle, ωt. The operation of the proposedDAC ensures that the AC line-to-line voltages are stepped-sinusoidal, with each step-sizeequivalent to the voltage generated by a single SM, i.e.,± vic. Hence, increasing numbers ofSMs enables the line-to-line voltages to better approximate the ideal sinusoidal waveformsof Fig. 5.3 (a). The corresponding Upper and Lower stack voltages are presented in Fig. 5.3(b). The transitions from one topology to the next are defined for ωt ∈[−pi6, 11pi6], whichrepresents a 2pi electrical cycle, as in Fig. 5.3 and Table 5.1. The six topological states andintervals are denoted by (i)→ (vi).Every sixth of a 2pi cycle, i.e., every pi3, there is a change in DS states, each corresponding toone of the six zero-crossings of the three-phase line-to-line voltages. For each interval, thepiece-wise definitions of the Upper and Lower stack voltages change to generate the respectiveline-to-line voltages. Despite the piece-wise changes in the Upper and Lower stack voltages,the line-to-line voltages are sinusoidal, as in Fig. 5.3 (a).Fig. 5.4 illustrates the switching states given by Table 5.1 and provides the piece-wisedefinitions of the Upper and Lower stack voltages, vu and vl, for each of the intervals (i)→(vi).117As one of the phases is always clamped to the midpoint through the Midpoint DSs, the Upperand Lower stacks work with the PCs to generate the line-to-line voltages. For example, duringinterval (i), the phase A terminal is connected to the midpoint through Sm,a, while phaseterminals B and C are connected to the Lower and Upper stacks, respectively. During (i),the stack voltages vu and vl follow the portions of the line-to-line voltages offset by half theDC-pole voltage, i.e., 12vDC − vca and 12vDC − vab, respectively, as shown in Figs. 5.3 and 5.4.Hence, for (i), the phase-to-midpoint voltages can be expressed as vb = −vab and vc = vca,while va = 0. Subtraction of the phase-to-midpoint voltages results in sinusoidal three-phaseline-to-line voltages, as in Fig. 5.3 (a).At the end of the interval (i) atωt = pi6, according to Table 5.1, theUpperM-Arm transitionsfrom connecting to phase terminal C to A, while the Midpoint DSs transition from phaseterminals A to C.That is, the UpperM-Arm DSs and Midpoint DSs swap their connections.As in Figs. 5.3 (a) and (b), the end of interval (i) and the beginning of interval (ii) coincidewith the zero-voltage crossing of voltage vca. Hence, the Upper phase-a DS and the Midpointphase-cDS both transition under ZVS. At the beginning of interval (ii), the Upper stack beginsto generate the negative portion of vca.This same principle is applied to all six intervals, as in Fig. 5.4. Fig. 5.4 also provides phasordiagrams of the line-to-line voltages at the beginning of each of the six intervals. Since thetopological transitions occur only when one of the line-to-line voltages changes polarity, ZVSis applied to all DSs for reduced switching losses. Since one of the line-to-line voltages is zeroat the transition instances, the other two line-to-line voltages are equal and opposite. In thispaper, the line-to-line voltages are assumed balanced and given asvab(t) =√3V1h sin(ωt+pi6)vbc(t) =√3V1h sin(ωt− pi2)(5.1)vca(t) =√3V1h sin(ωt− 7pi6)118TABLE 5.1DS Switching States and Topology Intervals for Varying ωt.TopologyIntervalsConv. angle UpperM-Arm DSs LowerM-Arm DSs Midpoint DSsωt Su,a Su,b Su,c Sl,a Sl,b Sl,c Sm,a Sm,b Sm,c(i)[−pi6, pi6)1 1 1(ii)[pi6, pi2)1 1 1(iii)[pi2, 5pi6)1 1 1(iv)[5pi6, 7pi6)1 1 1(v)[7pi6, 3pi2)1 1 1(vi)[3pi2, 11pi6)1 1 1where V1h is the peak-value fundamental-frequency voltage component of the phase-to-midpoint voltages, and vab + vbc + vca ≡ 0. The topological transitions in Fig. 5.4 (as inthe phasor diagrams on the right side of each sub-figure) correspond to the appropriateinstances shown in Fig. 5.3.The phasor diagrams in Fig. 5.4 also depict the rotation of the line-to-line voltage vectors andtheir corresponding projections onto the real axes (herein, the vertical axes), which correspondto the instantaneous values of these voltages at the transition instances at the beginning ofeach interval. For example, Fig. 5.4 shows that at the beginning of interval (i) the voltage vabequals zero, while the voltages vbc and vca are equal and opposite (as noted by their projectionsonto the real axis, “Re”). From the beginning of interval (i), the voltage vab increases positivelywhile vca decreases in value. Once vab and vbc become equal and opposite, and the other linevoltage, vca becomes zero, the topology switches from the interval (i) to the interval (ii). Thesame sequence of swapping the terminals follows for intervals (ii)–(vi), and the process repeatsafter one full 2pi cycle.To further illustrate the operation of the proposed DAC, Fig. 5.5 depicts the rotation of thetriangle of the line-to-line voltages at the beginning and end of each interval. For example,at the beginning of interval (i), it is seen that vbc and vca have equal and opposite amplitudes119(b)(c)ωt (rad)5pi67pi63pi211pi62pi6pi- 6pi(i) (ii) (iii) (iv) (v) (vi)(a)vDC-vDC0vab vbcvcavDC-vDC0Line-to-lineVoltagesvDC-vDC0va vbvcPhase-to-neutralVoltagesStack VoltagesvDC12vuvlvDC12- vDC−1.5V1h12Fig. 5.3. Ideal voltage waveforms explaining the operation of the DAC. (a) Generated sinusoidalline-to-line voltages; (b) Upper and LowerM-Arm voltages forming the pieces of sinusoids that areshifted by 12VDC; (c) Phase-to-neutral voltages.(with vca > 0 and vbc < 0) while vab = 0. However, at the end of this interval, vca becomeszero, and vab and vbc have equal and opposite amplitudes, with vab > 0 and vbc returning to thesame negative value as it was at the beginning of this interval, as seen in Fig. 5.3 (a). At thisinstance, vca = 0 such that terminals A and C with the same potential are swapped using thecorresponding DSs; consequently, the converter enters topology (ii). Specifically, the UpperDS transitions from phase-c to phase-a, while the Midpoint DS transitions from phase-a tophase-c, which implements the swap of these two terminals. This transition starts the interval(ii). As it was mentioned, this transition occurs when vca = 0, thus enabling the ZVS operationwith reduced switching losses. Once the phase terminals A and C are swapped, the UpperM-Arm stack voltage vu starts to decrease (pulling the terminal A upward), and the LowerM-Arm stack voltage vl starts to increase, which implements the rotation of the line-to-line120aAACBBCbcvab = 0vbcVabVabVbcVbcVcaVcaVcaVab VbcvcaReVabVabvabVbcVbcvbcVcaVcavca = 0 ReBACBCAvbc = 0vcavabRe vab = 0vcavbcReCBACABvca = 0vabvbcReVcaVabVbcvbc = 0vabvcaRe vl = vDC − vab−12 vl = vDC − vbc−12 vl = vDC − vca−12 vl = vDC + vbc−12 vl = vDC + vca−12 vl = vDC + vab−12 vu = vDC − vca−12 vu = vDC − vab−12 vu = vDC − vbc−12 vu = vDC + vca−12 vu = vDC + vab−12 vu = vDC + vbc−12 iC,u =iDC−ic iC,l =iDC+ib iu = ic il =− ib iC,u =iDC−ia iC,l =iDC+ib iu = ia il =− ibabcabcabcabcabc iC,u =iDC−ia iC,l =iDC+ic iu = ia il =− ic iC,u =iDC−ib iC,l =iDC+ic iu = ib il =− ic iC,u =iDC−ib iC,l =iDC+ia iu = ib il =− ia iC,u =iDC−ic iC,l =iDC+ia iu = ic il =− iaiDC iDCiDCiDCiDC iDC+++−+−−−+++−+−−−+++−+−−−+++−+−−−+++−+−−−+++−+−−−(ii)(i)(iii) (iv)(v) (vi)Fig. 5.4. Six topological states of the DAC corresponding to the six intervals of operation forming acomplete electrical cycle. The bold line indicates the path of the currents. Each subfigure correspondsto its respective interval, as defined by the converter angles ωt ∈ (i) [−pi/6, pi/6); (ii) [pi/6, pi/2); (iii)[pi/2, 5pi/6); (iv) [5pi/6, 7pi/6); (v) [7pi/6, 3pi/2); and (vi) [3pi/2, 11pi/6).voltage phasors upward as depicted in Fig. 5.5 (ii). At the end of interval (ii), the voltage vbcbecomes zero, and the terminals B and C are then swapped, starting the interval (iii). Duringthis interval, the UpperM-Arm stack voltage increases, and the LowerM-Arm stack voltagedecreases, thus implementing rotation of the phasor triangle downward as depicted in Fig. 5.5(iii). This sequence of swapping the two-phase terminals with the same voltage and rotating thetriangle of phase voltages up and down repeats as depicted in Fig. 5.5 (i)-(vi), which completesone electrical cycle.121ACB A CBCABC ABBAC B ACABCA BCCBA C BABCAB CA(i)(iii)(v) (vi)(iv)(ii)Transitions at Interval Boundaries(i) → (ii): vca=0 ⇒ A and C swapped(ii) → (iii): vbc=0 ⇒ B and C swapped(iii) → (iv): vab=0 ⇒ A and B swapped(iv) → (v): vca=0 ⇒ A and C swapped(v) → (vi): vbc=0 ⇒ B and C swapped(vi) → (i): vab=0 ⇒ A and B swappedvbcvcavuvl vl vl vlvl vl vl vlvl vl vl vlvu vu vuvu vu vu vuvu vu vu vuvcavabvabvcavbcvab vbcvcavbc vbcvcavabvabvbcvbcvcavcavbc vcavabvca vbcvabvbcvbcvcavcavbcvabvca vabvbcvab vcavDC12vDC12vDC12vDC12vDC12vDC12vDC12vDC12vDC12vDC12vDC12vDC12vDC12vDC12vDC12vDC12vDC12vDC12vDC12vDC12vDC12vDC12vDC12vDC12Fig. 5.5. Six topological states and operating principle of the DAC depicting rotation of the line-to-linevoltage phasors. Each subfigure corresponds to the topological state defined by the converter angleωt ∈ (i) [−pi/6, pi/6); (ii) [pi/6, pi/2); (iii) [pi/2, 5pi/6); (iv) [5pi/6, 7pi/6); (v) [7pi/6, 3pi/2); and (vi)[3pi/2, 11pi/6).5.3.1 AC Output Voltage and Current DefinitionFig. 5.6 presents the key voltage waveforms of the DAC’s stacks and DSs. The phase-aMidpoint DS voltage of Fig. 5.6 (b) represents the phase-to-neutral voltage of phase-a, i.e., va,which, as a consequence of theMidpointDSs clamping the phase terminals to the neutral point,is defined to be equal to zero for two pi3intervals. That is, va ≡ 0whenωt ∈[−pi6, pi6]∨[5pi6, 7pi6].The phase-to-neutral voltages contain a fundamental-frequency component of V1h such that122the phase-to-neutral voltage for the jth phase isvj(t) = V1h sin(ωt+ φj)− vtri(t), (5.2)where j ∈ {a, b, c}, φj ∈{0,−2pi3, 2pi3}, and vtri is a quasi-triangular voltage, revolvingthree times per fundamental cycle in each of the three-phase phase-to-midpoint voltages as aconsequence of theMidpointDSs’ clamping the phase terminals to the midpoint. According tothe states ofSm,j of Table 5.1, vtri(t) is equal to the respective phases’ fundamental-frequencyACvoltage component when the switches Sm,j are on. Therefore, vtri can be expressed piece-wisebased on the switching states of Sm,j asvtri(t) = V1h sin(ωt− k 2pi3)ωt ∈ [−pi6 + k 2pi3 , pi6 + k 2pi3 ]V1h sin(ωt+ (1− k) 2pi3)ωt ∈ [pi6 + k 2pi3 , pi2 + k 2pi3 ] (5.3)where k ∈ {0, 1, 2}, such that vtri has peak values±12V1h.Hence, the phase-to-neutral voltages,i.e., the voltages across the Midpoint DSs, have peak values±1.5V1h as seen in Fig. 5.6 (b).The piece-wise definitions of the Upper and LowerM-Arm stack voltages, as illustrated inFig. 5.6 (a), are given in Fig. 5.3. Meanwhile, the stack currents are defined asiu(t, ϕ) =iˆAC sin(ωt− ϕ) ωt ∈[pi6,5pi6)iˆAC sin(ωt− 2pi3− ϕ)ωt ∈[5pi6,3pi2)iˆAC sin(ωt+2pi3− ϕ)ωt ∈[3pi2,13pi6) , (5.4)il(t, ϕ) =−iˆAC sin(ωt− 2pi3− ϕ)ωt ∈[−pi6,pi2)−iˆAC sin(ωt+2pi3− ϕ)ωt ∈[pi2,7pi6)−iˆAC sin(ωt− ϕ) ωt ∈[7pi6,11pi6) , (5.5)1235pi67pi63pi211pi62pi6piM-Arm StackvoltagesMidpointDS voltageM-ArmDS voltagevDC12vDC−1.5V1h12000vvul1.5V1h1.5V1hvDC12vDCvDC 3V1hvDC23vDC13-6pi(a)(b)(c)ωt (rad)vDC12-vDC-Fig. 5.6. TheDAC’s key waveforms. (a) Upper and LowerM-Arm stack voltages; (b) phase-aMidpointDS voltage; (c) phase-a DS voltage of the UpperM-Arm.while the pole capacitor currents are defined asiC,u(t, ϕ) =iDC − iˆAC sin(ωt− ϕ) ωt ∈[pi6,5pi6)iDC − iˆAC sin(ωt− 2pi3− ϕ)ωt ∈[5pi6,3pi2),iDC − iˆAC sin(ωt+2pi3− ϕ)ωt ∈[3pi2,13pi6) (5.6)iC,l(t, ϕ) =iDC + iˆAC sin(ωt− 2pi3− ϕ)ωt ∈[−pi6,pi2)iDC + iˆAC sin(ωt+2pi3− ϕ)ωt ∈[pi2,7pi6)iDC + iˆAC sin(ωt− ϕ) ωt ∈[7pi6,11pi6) , (5.7)where iAC is the peak AC-side load current and ϕ is the power factor angle.The maximum and minimum voltages that the Upper and Lower M-Arm stacks mustgenerate are 12vDC and 12vDC− vˆj , respectively, where vˆj = 1.5V1h, as deduced by (5.2) and (5.3).124Hence, the DAC’s maximum output voltage is V1h = 23VDC, which results in the stacks’ voltagesbeing bounded by±12VDC.It is noted that the DAC possesses DC-side short-circuit fault blocking capability, which isenabled by simply turning the switches of its submodules off. With stacks rated for±12VDC,DC fault blocking is available for peak line-to-line voltages of vDC, which corresponds to theoperating voltage V1h = 1√3VDC, thus defining the DAC’s maximum operating voltage. It isfurther noted that the DAC can operate as a STATCOMwhen the DC-side voltage collapsesduring faults, but with stacks rated for±12VDC, the maximum output voltage in STATCOMmode when vDC = 0 is V1h = 13VDC. Redundant unidirectional SMs such as half-bridge SMscan increase the DAC’s AC output voltage during DC-side faults.5.3.2 Naturally Balanced Operating PointSimilar to the SO-AAC of [63], there exists only one operating point where the averageenergies of the DAC’s DC-side pole capacitors and SM stacks remain constant in steady-state.Such an operating point can be determined by integrating the powers through any of the DAC’sUpper/Lower stacks or PCs to determine the net cycle-to-cycle energy deviation. The Upperstack’s and Upper PC’s net energy deviations are equal and opposite at the end of each 2pi3period if losses are ignored. The energy deviations of the Upper stack and Upper PC, i.e.,∆Euand∆EC,u, respectively, for each power factor angle, ϕ, are derived by∆Eu(t, ϕ) =∫ tt0vu(τ)iu(τ, ϕ) dτ, (5.8)∆EC,u(t, ϕ) =∫ tt0vC,u(τ)iC,u(τ, ϕ) dτ, (5.9)The Upper stack and PC currents, iu and iC,u, are given in (5.4) and (5.6), while the stackvoltages are given in Fig. 5.4.The net energy deviations of the Upper stack and Upper PC over any 2pi3cycle, e.g., over125ωt ∈ [pi/6, 5pi/6], are respectively given by∆Eu(t0 +2pi3ω, ϕ)=∫ pi2ωpi6ω(12vDC + vca(τ))iˆAC sin(ωτ − ϕ) dτ+∫ 5pi6ωpi2ω(12vDC − vab(τ))iˆAC sin(ωτ − ϕ) dτ= − iˆAC cos(ϕ)pi2ω(V1h −√3piVDC)(5.10)∆EC,u(t0 +2pi3ω, ϕ)=∫ 5pi6ωpi6ω12vDC(iDC(ϕ)− iˆAC sin(ωτ − ϕ))dτ=iˆAC cos(ϕ)pi2ω(V1h −√3piVDC)(5.11)where iDC(ϕ) =32vDCV1hiˆa cos (ϕ), and vca and vab are defined in (5.1). Equating either (5.10)or (5.11) with zero yields the DAC’s naturally balanced operating point asV bal1h =√3piVDC or ϕ = ±pi2 . (5.12)At V bal1h , no additional control or balancing currents are required to ensure the DC-side PCsand M-ARM stacks remain balanced to their set-points.5.3.3 Hybrid Director SwitchesEnabled by the DSs’ ZVS, the DAC can employ the hybrid DSs of Fig. 5.2, which havesignificantly lower on-state losses than equivalently-rated IGBTs due to thyristors’ lower on-state voltage drops and slope resistances. The “upward” facing thyristors, through whichnegative M-Arm currents flow, may be replaced by diodes or kept in the on-state. The IGBT ofthe Upper and Lower hybrid DSs is responsible for their turn-off if the DS/M-Arm current ispositive, i.e., downward.At the instance of turn-off, which for the Upper phase-aDS is at ωt = 5pi/6, the IGBTscontained within the hybrid DSs are turned off such that positive M-Arm current is quicklyhalted. The IGBT holds the DS current below the thyristors’ holding current, IH, which is given1265pi67pi63pi211pi62pi6piM-ArmDS voltage0vDC 3V1hvDC23vDC13-6piωt (rad)θq=ωTq√3V1hsin(θq)Fig. 5.7. DS voltage of the DS, showing rating of IGBTs.in their datasheets, for a time equal to at least Tq, i.e., for ωTq radians, as in Fig. 5.7. After Tq haselapsed, the thyristors have regained their forward and reverse blocking capability. Therefore,the IGBTs can be again turned on at ωt = 5pi/6+ ωTq, such that the thyristors block the entireDS voltage; or, they can remain in the off state to share the blocking voltage with the thyristors.The latter case requires a more sophisticated voltage-sharing snubber circuit. For the formercase, the thyristors are rated to block the peak DS voltage of√3V1h; for the latter case, thethyristors are rated to block the DS voltage less the IGBT voltage, vˆIGBT, which is determined asfollowsvˆIGBT,ul =√3V1h sin(ωTq),vˆdownwardthy.,ul =√3V1h − vˆIGBT,ul,vˆupwardthy.,ul =√3V1h.(5.13)Tq is the duration required by the thyristors to turnoff, and is typically around 500 µs. Therefore,the sizing of the IGBTs for a 600 kV DC-side voltage is approximately 90 kV.Unlike the Upper M-Arm and LowerM-Arm, the Midpoint hybrid DSs are required toblock bidirectional voltages; hence, anti-parallel thyristors can be used to provide such blocking.Their turn-off is accomplished by the anti-series IGBTs of Fig. 5.2. Their operating principle isthe same as above, but they require bidirectional current-breaking capability, unlike the Upperand Lower DSs. Therefore, the anti-series IGBTs and anti-parallel thyristors are rated for the127bidirectional voltagesvˆIGBT,m =√3V1h sin(ωTq),vˆthy.,m = 1.5V1h − vˆIGBT,m.(5.14)Hence the component count and loss analysis for the DAC assume both the IGBT-based DSsas well as the thyristor and IGBT hybrid DSs.5.3.4 Stack and Pole Capacitor Energy Balancing Strategy5.3.4.1 Reactive Power Control to Maintain Optimal OperatingVoltageWhen connected to a strongACgrid, theDACcan remain at its naturally balanced operatingvoltage defined in (5.12). From (5.10) and (5.11), the polarity and amplitude of the energydeviations of the stacks and pole capacitors depend on both the power factor angle as well asthe fundamental-frequency AC phase-to-midpoint voltage amplitude, V1h.Hence, there aretwo scenarios where the energies of the stacks and PCs stay balanced: 1) the operating voltageis controlled to its naturally balanced value, V bal1h =√3pivDC, or 2) the real power is zero suchthat the DAC operates as a STATCOM to generate only reactive power.Reactive power is typically regulated by the error signal eQ = Qmeas −Qref, which is sent tothe PQ closed-loop controller [31]. An increase in reactive power,Q, leads to an increase inV1h, and vice-versa. To ensure capacitor energy balance of the Upper and Lower stacks, theDAC can control its reactive power with the error signaleQ = sgn(cos(ϕ))(NSM∑i=1(vic,u + vic,l)− VDC), (5.15)whereNSM is the number of SMs in each stack, vic,u and vic,l are the ith capacitor voltages of theUpper and LowerM-Arm stacks, and sgn(cos(ϕ)) is 1 for cos(ϕ) > 0 and−1 for cos(ϕ) < 0.With (5.15), the reactive power of the system ensures that the sum of the FBSM voltages arecontrolled to be equal to the sum of the DC-side pole capacitors’ voltages. In steady-state,therefore, when eQ → 0, V1h → (5.12). Controlling eQ of (5.15) to zero requires the AC-side128voltage to remain sufficiently stable such that the DAC’s injection of reactive power does notsignificantly impact the grid voltage.5.3.4.2 Overlap PeriodThe SO-AAC [63] is another such converter that experiences balanced capacitor energiesat a single operating voltage (for the SO-AAC, the so-called “sweet-spot” is at V1h = 2pivDC).When operated away from this voltage, the SO-AAC’s Upper and Lower stacks are brieflyoperated together instead of separately, i.e., in “overlap mode,” to drive balancing currents fromthe DC-side pole capacitor to the stacks for net-zero cycle-to-cycle energy deviation. Sincethe SO-AAC’s arms are unused (blocked) for half the fundamental cycle at the “sweet-spot”operating voltage, such an overlap mode is trivial to implement and requires only a slightincrease in the stacks’ voltage ratings.A similar method of overlap operation can be adopted for the DAC. However, unlike theSO-AAC: 1) none of the DAC’s stacks are unused at any time; 2) the DAC’s Upper and Lowerstack voltages do not at any time sum to the DC-side voltage [see Fig. 5.3 (b)]. Hence, the DAC’sstacks cannot connect to the same phase simultaneously. In contrast to the SO-AAC havingonly one PC, the DAC’s Upper and Lower stacks can individually overlap with the Upper andLower DC-side PCs, respectively, by increasing the intervals during which vu and vl equal12vDC, where it is noted according to Fig. 5.3 (b) that the stack voltage in normal operation onlymomentarily equal 12vDC. In doing so, balancing currents can flow from the PCs to the stacksthrough the Midpoint DSs.This is accomplished bymodifying the stack voltages of Fig. 5.3 (b) to include regions duringwhich the stack voltages are held at 12vDC for a duration of θΩ, which is a design parameterthat can be chosen based on the allowable total harmonic distortion (THD) and SM capacitorbalancing current magnitude. Such a modification to the Upper stack voltage, vu, is depicted inFig. 5.8 (a), which is denoted by v?u when the θΩ overlap period is included. During the overlapperiod, the Midpoint DSs are turned on simultaneously with either the Upper or Lower DSsfor a period of θΩ. Using the transition from interval (iii) to (iv) at ωt =5pi6as an example, v?u129of Fig. 5.8 (a) equals 12vDC during ωt ∈[5pi6− θΩ/2, 5pi6 + θΩ/2], but is otherwise equal tovu. For this range, all the Sm,a and Sm,b DSs and Su,a and Su,b DSs are turned on. Hence, thephase-a and -b phase-to-midpoint voltages with overlap, v?a and v?b , both equal zero during thisinterval, as in Fig. 5.8 (b), such that the line-to-line voltage, v?ab, also equals zero and takes theform of the blue dotted waveform in Fig. 5.8 (c).The fundamental-frequency component of v?j , i.e., V?1h is calculated by Fourier analysis ofthe desired terminal voltage, vat, less the regions of overlap, i.e., v?a, asV ?1h =4ωpi∫ pi2ω0v?a(t) sin(ωt) dt=4ωpi∫ pi2ωpi6ω+θΩ2ωvat(t) sin(ωt) dt=V1h2pi(√3(cos(θΩ)− 1) + 3(sin(θΩ)− θΩ) + 2pi). (5.16)It is observed in (5.16) that V ?1h marginally reduces from the desired reference value V1h. Tocompensate for the fundamental-frequency voltage reduction in v?j due to the overlap operation,v?j is scaled by the factormΩ such that vj of Fig. 5.2 contains the correct fundamental-frequencyvoltage component, V1h.Hence, vj = mΩv?j , wheremΩ =2pi√3(cos(θΩ)− 1) + 3(sin(θΩ)− θΩ) + 2pi. (5.17)By multiplying v?j by (5.17), the fundamental-frequency voltage component of vj and vjt areensured to be equivalent.The THD in v?ab of Fig. 5.8 (c) depends on the value of θΩ. For the exaggerated case of θΩ =20◦ in Fig. 5.8, the THD is 6.48%, but when θΩ = 10◦, the THD reduces to 2.32%. Therefore, asmall overlap period is preferred to minimize the THD. Depending on the acceptable amountof THD, given by the grid-code, AC-side filtering may not be necessary.However, to minimize the THD, the optional AC-side cascaded FBSM stacks depicted inFig. 5.2 can be implemented. For virtually harmonic-free line-to-line voltages, the voltage of130θΩUpper stack voltagePhase-to-midpoint voltageLine-to-line voltagevDC1200vDC12vDC(a)(b)5pi67pi63pi211pi62pi6pi-6piωt (rad)vDC12-vDC-θΩ120vDC12vDCvDC12-vDC-vuvu(c)vabtvabvDC16vDC16vDC112vDC1120(d)AC-side FBSMvoltagevatvavb⋆⋆⋆⋆Fig. 5.8. The DAC’s key waveforms with and without an exaggerated overlap period of 20◦. (a) Upperstack voltage; (b) phase-a and -b phase-to-midpoint voltages; (c) phase-ab line-to-line voltage; and (d)phase-a optional AC-side FBSM stack voltage.the phase-j cascaded FBSM stack of Fig. 5.2, vFB,j , is given byvFB,j(t) = vj(t)− vjt(t). (5.18)That is, the cascaded FBSMs compensate the voltage difference between vj and vjt such thatthe output line-to-line voltages are harmonic-free. The phase-a cascaded FBSM voltage when131θΩ = 20◦ is shown in Fig. 5.8 (d). Its peak voltage is given byvˆFB,a =∣∣∣∣va( pi6ω + 12ωθΩ)− vat(pi6ω+12ωθΩ)∣∣∣∣= vat(pi6ω+12ωθΩ)=√3V1h sin(12θΩ). (5.19)Since vj and vjt have the same fundamental-frequency voltage component of V1h, thecascaded FBSMs have no fundamental-frequency voltage component and therefore do notcontribute to the real power flow. Therefore, ignoring losses, their energy stays balancedcycle-to-cycle. To correct the voltage decay of the AC-side stacks’ FBSM capacitors due tothe semiconductors’ and capacitors’ resistive losses, a small fundamental-frequency voltagecomponent that is determined by a PI controller, i.e.,∆vj(t) = ∆Vj sin (ωt+ φj), is injectedinto (5.18) to ensure their balance, as in [83].The small number of switches in the AC-side cascaded FBSMs contributes little to theconverter’s overall losses and footprint. Even with the exaggerated overlap period of θΩ = 20◦,the AC-side stacks are rated for approximately 16vDC, as in Fig. 5.8 (d). It is further noted thatother voltage shapes for the cascaded FBSM stacks can be considered via the injection of triplenharmonics, which can reduce their blocking voltage.5.4 Performance EvaluationIn this section, the DAC is tested under normal operation and DC-side pole-to-pole faultoperating conditions. TheMATLAB/Simulink Simscape toolbox is used to model the DACwith a time step of 20 µs. The AC-side of the converter is connected to a 400 kV grid through a∆−Y transformer. The DC-side of the DAC is supplied with the DC-side voltage of 600 kV.With the rated FBSM voltage of 5 kV, the number of FBSMs required per arm is determined by300 kV/5 kV = 60 FBSMs. The simulation parameters are given in Table 5.2. The simulationassumes the Westcode IGBT from Chapter A such that the DS and FBSM on-state resistances132TABLE 5.2Simulation ParametersSimulation parametersMaximum power rating 1096MVAMaximum P 1000MWDC-side voltage 600 kVUpper/Lower stackFBSM capacitor voltage5 kVUpper/Lower stackFBSM capacitance2.2mFOptional Overlap BranchesFBSM capacitor voltage5 kVOptional Overlap BranchesFBSM capacitance0.6mFPole capacitorcapacitance110 µFDC-side inductance 25mHTransformer leakageimpedance0.001+ j0.18 puTransformer windingratio (Y /∆)400 kV/400 kVare provided in Table B.3. If they are used, the FBSMs of each phase of the Optional OverlapBranches of Fig. 5.2 are assumed to block the total voltage of 110VDC = 60 kV, such that eachOptional Overlap Branch uses 12 5-kV FBSMs.5.4.1 Normal Operation — No OverlapIn Figs. 5.9 (a)–(e), the DAC operates in inverter mode. Fig. 5.9 (a) shows the three currentsof the DAC’s upper DSs, with their sum equaling iu of Fig. 5.2. Figs. 5.9 (b) and (c) show thevoltage across the phase-a upper DS, Su,a and the voltage produced by UpperM-Arm’s stack,respectively. Fig. 5.9 (d) shows the phase-a output voltage, va and the line-to-line voltage, vab.Fig. 5.9 (e) shows the capacitor voltages of the DAC’s UpperM-Arm’s stack submodules, wherethey are seen to be well-balanced.In Figs. 5.10 (a)–(e), the DAC is shown to change from inverter to rectifier mode. At t = 0 s,the DAC is commanded to operate in inverter mode, where the real power of Fig. 5.10 (a)and the DC-side current of Fig. 5.10 (b) both increase linearly in response to the change in1330120.22 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.3Time (s)3002001000-100-200i u (kA)v u (kV)v Su,a (kV)42004600500054000600300-600-400-2000200400600 (V)vi ciSu,a iSu,b iSu,c(a)(b)(c)(d)(e)vabv a,Ω & vab (kV) va,ΩFig. 5.9. The DAC’s normal operation when no overlap period is considered. (a) UpperM-Arm’s stackcurrent, partitioned into the three upper DSs; (b) The voltage across the upper DS, Su,a; (c) The voltageacross Upper M-Arm’s stack; (d) The phase-a DAC outputvoltage, va,Ω and the phase-a to phase-bline-to-line voltage, vab; (e) Voltages of UpperM-Arm’s stack’s submodules’ capacitors.reference power. The increasing real power causes a transient voltage deviation in both thestack voltages of Fig. 5.10 (c) and the DC-side pole capacitor voltages of Fig. 5.10 (e), which ispromptly controlled back to the steady-state value due to the controller of (5.15). Fig. 5.10 (d)shows the AC-side current of the DAC.At t = 0.4 s, the DAC is commanded to operate in rectifier mode, where the real powerand DC-side current both follow the reference power command. It is noted that after theconverter stabilizes in rectifier mode at approximately At t = 0.6 s, the reactive power,Q, is134-100001000P (MW) & Q (MVAR)v C,u & vC,l (kV)i DC (kA)i abc (kA)-2021-12803003202903000-200020003100 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Time (s)(e)P QΣv c,u & Σv c,l (kV)ii(d)(a)(c)(b)Fig. 5.10. The DAC’s normal operation when no overlap period is considered. (a) Real and reactivepower; (b) DC-side current; (c) Summation of the capacitor voltages of each of the Upper and LowerM-Arm’s stacks; (d) Three-phase current as measured on the grid-side of the transformer; (e) Voltage ofthe Upper and Lower DC-side pole capacitors.higher than it was in inverter mode due to the increase of the DC-side voltage. Since (5.12)must be maintained in order to ensure capacitor energy balancing, there must be a proportionalincrease in AC-side voltage to compensate for the rising DC-side voltage in rectifier mode.Hence, the DAC generates more reactive power in rectifier mode than in inverter mode.135-0.50.511.502.00.22 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.3Time (s)3002001000-100-200i u (kA)v u& vFB,a (kV)v Su,a (kV)47504850495050500600300-600-400-2000200400600 (V)vi c(b)(c)(d)vabv a,Ω & vab (kV) vatiSu,avu vFB,aiSu,b iSu,c(a)(e)Fig. 5.11. The DAC’s normal operation when a 10° overlap period considered. (a) Upper M-Arm’sstack current, partitioned into the three upper DSs; (b) The voltage across the upper DS, Su,a; (c) Thevoltage across UpperM-Arm’s stack and the voltage across the phase-a AC-side cascaded FBSMs of theoverlap branch; (d) The phase-a DAC voltage, vat and the phase-a to phase-b line-to-line voltage, vab;(e) Voltages of UpperM-Arm’s stack’s submodules’ capacitors.136-100001000P (MW) & Q (MVAR)v C,u & vC,l (kV)i DC (kA)i abc (kA)-2021-12803003202953000-200020003050 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Time (s)P QΣv c,u & Σv c,l (kV)ii(c)(a)(b)(d)(e)Fig. 5.12. The DAC’s normal operation when a 10° overlap period considered. (a) Real and reactivepower; (b) DC-side current; (c) Summation of the capacitor voltages of each of the Upper and LowerM-Arm’s stacks; (d) Three-phase current as measured on the grid-side of the transformer; (e) Voltage ofthe Upper and Lower DC-side pole capacitors.5.4.2 Normal Operation —With OverlapNext, the DAC is tested with its optional overlap branch. In Fig. 5.11, the DAC with anoverlap period of 10° is commanded to operate first as an inverter from t = 0 s until t = 0.4 s,after which it is commanded to operate as a rectifier. Moreover, the reactive power is nowa controllable variable since the overlap branches enable the stack voltages to be balanced.In Fig. 5.11 (a), the Upper DS currents are shown. During the periods of overlap, which are137denoted by the flat-top of the UpperM-Arm stack voltage of Fig. 5.11 (c), a charging currentflows upward from the stacks to the pole capacitors, which discharges the stack voltages andcharges the pole capacitors. The effect of the balancing current is seen in the FBSM capacitorvoltages of Fig. 5.11 (e), wherein the time instances corresponding to the negative DS currentscorrespond to a short discharging period. Figs. 5.11 (b) and (d) show the Upper phase-aDSvoltage and the AC voltages of the DAC measured at the AC terminals. In Fig. 5.11 (d), nosuch overlapping period is seen, due to the voltages that the cascaded FBSMs of Fig. 5.11 (c) onthe AC-side generate.Fig. 5.12 (a) shows the real and reactive powers of the test system. It is noted that sincethe overlap period is employed, the real and reactive power can be decoupled, contrary to thepowers shown in Fig. 5.10 (a). The DC current of Fig. 5.12 (b) is clean and follows the realpower. Figs. 5.12 (c) and (e) show that throughout the power changes, the stack voltages andpole capacitor voltages stay well-balanced. Lastly, Fig. 5.12 (d) shows well-balanced AC-sidecurrents throughout the transient study.5.4.3 DC-Fault OperationThe response to a DC-side pole-to-pole across the DAC’s DC-side terminals is shown inthis section. At t = 0.5 s, the bolted short-circuit fault is applied across the DAC’s DC-sideterminals. At 2ms after the fault occurs, the switches of the DSs and submodules are opened,which enables the capacitor voltages within the submodules to apply a reverse blocking voltageagainst the AC-side grid, preventing AC-side currents from continually ramping up.The results show that the DAC is able to quickly and safely respond to DC-side bolted faults.The Upper stack and DS currents of Fig. 5.13 (a) show a spike through the DS diodes caused bythe PCs rapidly discharging during the fault, which is quickly suppressed by the blocking modeof the stack’s FBSMs. Fig. 5.13 (b) shows the phase-a upper DS’s voltage where it is noted thatdespite having all switches opened, the DS voltage retains the same shape. Fig. 5.13 (c) showsthat the stack voltages apply a negative voltage against the AC-side grid, thus isolating it fromthe DC-side. Fig. 5.13 (d) shows the phase-a voltage and the line-to-line voltage from phase-a1380-2-420.48 0.49 0.50 0.51 0.52Time (s)4002000-200-40042004600500054000600300-600-3000300600900(a)(b)(c)vabvat(d)(e)i u (kA)v u (kV)v Su,a (kV) (V)vi cΣv c,u & Σv c,l (kV)v a,Ω & vab (kV)iSu,a iSu,b iSu,cFig. 5.13. The DAC’s DC fault operation. (a) UpperM-Arm’s stack current, partitioned into the threeupper DSs; (b) The voltage across the upper DS, Su,a; (c) The voltage across UpperM-Arm’s stack; (d)The phase-a DAC voltage, vat and the phase-a to phase-b line-to-line voltage, vab; (e) Voltages of UpperM-Arm’s stack’s submodules’ capacitors.to -b. It is seen that despite the spike in voltage at t = 0.502 s, the DAC’s output voltage, va,does not exceed 1.5V1h. Fig. 5.13 (e) shows that the individual submodule capacitor voltagesdo not overcharge throughout the fault.Figs. 5.14 (a) and (b) show the real and reactive power and the DC-side current, respectively,where the DC-side current falls in accordance with the real power, P . Fig. 5.14 (c) shows thatthe summation of the submodule capacitor voltages for both the Upper and Lower stacksdoes not exceed +10% and voltages quickly return to their set-point values after the fault is13901000-550-1028030032001002000-200020003000.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Time (s)P Q(b)(a)(c)(d)(e)P (MW) & Q (MVAR)v C,u & vC,l (kV)i DC (kA)i abc (kA)Σv c,u & Σv c,l (kV)iiFig. 5.14. The DAC’s DC fault operation. (a) Real and reactive power; (b) DC-side current; (c)Summation of the capacitor voltages of each of Upper M-Arm’s stack and LowerM-Arm’s stack; (d)Three-phase current as measured on the grid-side of the transformer; (e) Voltage of the Upper andLower DC-side pole capacitors.resolved. Fig. 5.14 (d) shows the AC-side currents quickly going to zero with the real power andreturning to their set-point values promptly upon the clearing of the fault. Lastly, Fig. 5.14 (e)shows the DC-side pole capacitors’ voltages. In response to the fault, they quickly drop downsuch that their sum is zero. The DC-side voltage is restored with a ramp function, wherein theripple due to the LC resonance is seen. Upon the resumption of real power flow, the DC-sidevoltage quickly returns to its nominal value.140vab vavu vl0 0.01 0.02 0.03 0.04 0.05 0.06v ab & va (V)v u & vl (V)v Su,a (V)i a (A)Time (s)-200-1000100200-8-40480100200-50050100(a)(b)(c)(d)Fig. 5.15. Results from the hardware verification of the DAC from the Tektronix oscilloscope. (a)Line-to-line voltage and line-to-neutral voltage; (b) Upper and LowerM-Arm stack voltages; (c) UpperM-Arm phase-a DS voltage; (d) phase-a current.5.4.4 HardwareVerificationA lab-scale DAC with a DC-side voltage of 200V was prototyped using a combination oftwo of OPAL-RT Technologies’ MMC Testbench’s OP1210 modules, each of which contains10 FBSMs, and built in-house DSs. The AC load is composed of three-phase 12Ω resistorsconnected in a floating-Wye configuration. The DSs are digitally controlled by the MMC TestBench’s OP4510 simulator and onboard FPGA, enabling both CPU and FPGA control. TheKintex-7 is programmed with OPAL-RT Technologies’ RT-XSG toolbox in MATLAB/Simulink.The DSs’ operating voltage amplitude and frequency are controlled in real-time using MAT-LAB/Simulink with RT-LAB v2019.1.Fig. 5.15 presents the results, as measured by the Tektronix oscilloscope. Fig. 5.15 (a)presents the phase-ab line-to-line voltage at the DAC’s terminals overlaid with the phase-aline-to-neutral voltage. The shape of the results match Fig. 5.9 (d). Fig. 5.15 (b) shows theUpper and LowerM-Arm stack voltages, which match the shape of Fig. 5.9 (c). Fig. 5.15 (c)14110 10.01 10.02 10.03 10.04 10.05 10.067.28.810.4127.28.810.412889296100104108v c,u (V)iΣv c,u (V)i889296100104108Σv c,l (V)iv c,l (V)iTime (s)(a)(b)(c)(d)Fig. 5.16. Results from the hardware verification of the DAC as measured by the OP4510 simulator. (a)Upper stack FBSM voltages; (b) Lower stack FBSM voltages; (c) Sum of Upper stack FBSM voltages; (d)Sum of Lower stack FBSM voltages.presents the phase-a DS of the UpperM-Arm, which matches the shape of Fig. 5.9 (b). Lastly,the phase-a current is shown in Fig. 5.15 (d), which is effectively sinusoidal.Fig. 5.16 presents the FBSM voltages of the Upper and LowerM-Arms’ stacks as measuredby the OP4510 simulator. Figs. 5.16 (a) and (b) present the ten FBSM capacitor voltages ofthe Upper and LowerM-Arm stacks, respectively, and Figs. 5.16 (c) and (d) present the sumof the respective stacks’ FBSMs. The results of Figs. 5.16 (a) and (b) show that the FBSMcapacitors remain closely balanced to their set-point voltage of 10V, which is more clearly seenby the overall stack voltage ripples of Figs. 5.16 (c) and (d), which have the mean voltage of thecapacitor summations over the 0.06 s window of 98V.5.5 Converter ComparisonIn this section, the DAC is compared against the HBSM-MMC, MBSM-MMC, EO-AAC,and the proposed H3LC based on general capabilities, semiconductor losses, and energystorage requirements. Such information is presented in Table 5.3. The comparison assumes142the Westcode T1800 GB45A IGBT [90] and the ABB 8.5 kV 5STP 27N8500 [96]. For the lossanalysis, the same 1GW at the provided operating voltages is assumed.In the “General converter comparison” of Table 5.3, it is shown that even when its IGBT-based DSs are used (i.e., without the thyristor component), the DAC requires fewer IGBTs(3,534) than the H3LC and the MBSM-MMC (3,744 and 4,320, respectively); when its hybridDSs are used, it requires the least number of all the tested converter, needing only 1,394.However, its hybrid DSs require a total of 1,872 thyristors. Like the H3LC, the DAC needsDC-side pole capacitors to form its midpoint. Nonetheless, the blocking action of the DAC’sFBSMs grants it DC fault blocking capability.The DAC is shown in the “Loss analysis” portion of Table 5.3 to have somewhat higherlosses than the H3LC when its IGBT-based DSs are used (0.79% compared to 0.69%), butwhen its hybrid DSs are used, its efficiency exceeds the HBSM-MMC. Due to having twice asmany FBSMs in the conduction path as the H3LC, the DAC’s overall SM conduction losses areapproximately 87% greater than the H3LC’s. However, due to their slower switching frequency,their switching losses are approximately the same. Compared to the H3LC, the DAC’s DSswitching losses are negligible due to its ZVS; moreover, its Upper and Lower DSs are rated for√3V1h =3piVDC ≈ 0.95VDC, which is 5% lower than the H3LC’s. Therefore, its DSs conductionlosses are improved compared to the H3LC’s, even without the hybrid DS.Lastly, the DAC is shown in the “Energy analysis” portion of Table 5.3 to have similar energystorage requirements as the H3LC, albeit somewhat larger. When a 5% DC-side pole-to-polevoltage ripple is considered, the DAC requires 18.3% as much energy storage as the MMC,while the H3LC requires 11.6%. However, the DAC needs fewer components than the H3LCand is inherently DC fault tolerant.Therefore, despite the DAC’s inflexibility regarding operating voltage (which is mitigatedby the use of the Optional Overlap Branches), it is expected to have a highly reduced converterfootprint enabled by using only two submodule-based stacks for three-phase AC/DC voltageconversion. Its energy storage requirements are less than one-fifth of the MMC’s, while its143TABLE 5.3Comparison of Selected ConvertersConverter typeHBSMMMCMBSMMMCEO-AAC H3LC DACGeneralconvertercomparison Max AC voltage, V1h (×VDC) 1/√3 1/√3 2/3 0.63√3/piDC-side voltage 600 kV 600 kV 600 kV 600 kV 600 kVNo. of IGBTs 2880 4320 4800 37443534(1394)No. of thyristors 1536 0 0 00(1872)No. of 5 kV SMs 720 720 480 198 120DC-side pole capacitor No No No Yes YesDC fault blocking No Yes Yes Yes YesLossanalysisAC voltage, V1h (×VDC) 0.523 2/3 0.573√3/piSM Pcond (MW) 3.68 5.62 3.77 1.75 3.27SM Psw (MW) 2.30 2.30 0.95 1.31 1.32DS Pcond (MW) - - 1.80 3.423.31(1.18)DS Psw (MW) - - - 0.44 0Total Loss (MW) 5.98 7.92 6.52 6.927.90(5.77)Percentage Loss 0.60% 0.79% 0.65% 0.69%0.79%(0.58%)EnergyanalysisAC voltage, V1h (×VDC) 0.523 2/3 0.573√3/piEnom(J · radVA · s)9.565 4.50 1.106SMs PCs1.040.713.01†Normalized to MMC 1.00 0.471 0.1160.1830.424†∗Bracketed values assume the hybrid DSs for the DAC.†For 5% individual pole capacitor ripple.component count is lower than the MBSM-MMC. Its efficiency is comparable to all of thetested converters, which is bolstered further by the use of its hybrid DSs that are enabled dueto the DSs’ ZVS.1445.6 ConclusionThe DAC is the first multilevel VSC-HVDC converter topology to use only two submodule-based stacks for filterless operation. Such a reduction implicates its use for volume-limitedconverter station applications. Moreover, as shown in Table 5.3, the DAC has competitivesemiconductor efficiency: when the hybridDSs are considered, theDAC’s semiconductor lossesrival the HBSMMMC’s. The DAC’s optimal operating voltage was derived in Section 5.3.2,which defines the voltage that enables natural balancing of its Upper and LowerM-Arms’ stacksand its DC-side pole capacitors. Methods were proposed in Section 5.3.4 that enable the DAC’scapacitive components to be balanced to their set-points when the operating voltage driftsaway from the optimal value. The methods include a reactive power controller scheme and theOptional Overlap Branches. The DAC’s normal and DC-side fault operations were verifiedin Section 5.4, wherein an HVDC test system was constructed in MATLAB/Simulink thatverifies the DAC’s operating principle during such operations. The DAC’s main advantage is itsminimized footprint, which may enable it to replace the HBSM-MMC or MBSM-MMC forapplications in remote locations due to the favorable cost profile enabled by a smaller converter.1456.Quad-Arm ConverterMotivated by the advantages of the AAC, this chapter proposes a new type of converter,i.e., theQuad-Arm Converter (QAC), which enables the reduction of converter arms from sixto four. Moreover, the QAC shares some of the AAC’s main features — namely, its absenceof arm inductors and DC-link capacitors, its continuous DC-side current, its DC-side faultblocking capability due to its FBSM-based arms, and its small energy storage requirements.Furthermore, the QAC presents advantages which may improve its efficacy compared to theHCMCs or MMCs, including the usage of thyristors and IGBTs for director switches (DSs),which reduce on-state conduction losses, and its four-arm structure, which enables simplerinsulation, a significantly reduced number of FBSMs, and a reduced cost and smaller physicaldesign and footprint. Overall, the contributions of this chapter are summarized as follows:(1) In Sections 6.2.1 and 6.2.2, a detailed explanation of the QAC’s topology and operatingprinciple is provided and the control and sizing of its bidirectional hybrid DSs composedof thyristors and IGBTs are proposed;(2) Section 6.2.3 defines the QAC’s optimal operating voltage as 23VDC, while Sections 6.2.4and 6.2.5 propose a third-order harmonic injection scheme which enables the QAC’s fourFBSM-based arms to be rated for a minimum of 0.5VDC or, if DC fault blocking is required,≈0.577VDC;(3) Simulations are performed in Section 6.3 which feature the converter’s ability to transferreal and reactive power as well as to ride through DC-side short-circuit pole-to-pole faults;6.1 TopologyThe topology of the QAC is shown in Fig. 6.1, wherein its two Upper and two LowerMultiplexed Converter Arms (M-Arms) are presented with their respective DSs. UpperM-ArmPresently, the technology forming the QAC is undergoing the patent filing process, and is under provisionalpatent protection at the time of writing.146vaA B Cvb vcUpper M-Arm 1 Upper M-Arm 2Lower M-Arm 1 Lower M-Arm 2vu1iu1iDC iu2il1 il2Su1,a Su1,bvu2Su2,a Su2,b Su2,cvDC+Sl1,a Sl1,b Sl2,a Sl2,b Sl2,cvl1 vl2Phase terminalsNegative DC terminalPositive DC terminalNeutral-pointvDC-12vDC12vDCLDCSu1,cSl1,c(b)DS structuresvSkn,jvSkn,j(i)(a)(ii)StackofsubmodulesvknSMSMFBSMstructure+vivicSMFig. 6.1. TheQuad-ArmConverter. (a) Possible topologies of QAC’s bidirectional DSs: (a–I) Anti-seriesIGBTs; (a–II) Hybrid anti-parallel thyristor with IGBT. (b) FBSM topology used to form the M-ArmStacks. k ∈ {u, l}; n ∈ {1, 2}; and j ∈ {a, b, c}.1 and UpperM-Arm 2 are connected from the positive DC terminal to the phase terminals A,B, and C, through their respective DSs, {Su1,a, Su1,b, Su1,c} and {Su2,a, Su2,b, Su2,c}. Likewise,LowerM-Arm 1 and LowerM-Arm 2 are connected from the negative DC terminal to thephase terminals through their respective DSs, {Sl1,a, Sl1,b, Sl1,c} and {Sl2,a, Sl2,b, Sl2,c}. Theoutput phase voltages, va, vb, and vc, are referenced to the virtual neutral-point, which isequipotential from the positive and negative DC terminals. As in Fig. 6.1, the QAC can manageall three phase terminals without needing DC pole capacitors, which is a consequence of itsoperating principle to be discussed. The QAC’s symmetric four M-Arm structure enables the147Phase voltages M-Arm stackvoltages 0.5V1hV1h0va vb vcωt (rad)- 5pi67pi63pi211pi613pi65pi217pi619pi67pi223pi62pi6pi6pi(xii)(xi)(x)(ix)(viii)(vii)(vi)(v)(iv)(iii)(ii)(i)V1h1.5V1h0.5V1h00.5V1hvu1 vl1 vu2 vl2(c)(a)-Line-to-line voltages 0vcavbcvab√3V1h√3 2V1h(b)√3V1h-√3 2V1h-V1h-0.5V1h-Fig. 6.2. Idealized voltages explaining the operation of the QAC over two electrical cycles: (a) Thephase voltages, as measured from the AC terminals to the virtual midpoint across the DC-side voltage ofFig. 6.1; (b) The line-to-line voltages; (c) The stack voltages of the two Upper and two LowerM-Arms.AC- and DC-sides to be decoupled, which additionally grants it the capability to generatesymmetrical AC-side voltages of any amplitude within the limits imposed by the ratings of itsSMs and DSs.6.2 Operating Principle6.2.1 Generation of Output Voltage and Operation of Director SwitchesSince the M-Arms are multiplexed among all three phases, each M-Arm sequentially par-ticipates in creating the voltage of each of the phases. Moreover, since its DSs change statesonly when the line-to-line voltages have zero crossings, they experience zero-voltage switch-ing (ZVS) for reduced switching losses. In this topology, each of the M-Arms contributes toeach phase for 4pi3intervals. Such conduction intervals enables one Upper and one LowerM-Arm to simultaneously connect to the same phase terminal (i.e., to overlap), enabling a148va vb vcA B Cva vb vcA B Cva vb vcA B Cva vb vcA B Cva vb vcA B Cva vb vcA B Cva vb vcA B C(i)vu1 = vDC −va121212121212121212121212va vb vcA B Cvl1 = vDC +vbvu2 = vDC −vcvl2 = vDC +vava vb vcA B Cva vb vcA B Cva vb vcA B Cva vb vcA B C(ii)vu1 = vDC −vavl1 = vDC +vbvu2 = vDC −vcvl2 = vDC +vc(v)(iv)(vii) (viii) (ix)(x) (xi) (xii)(vi)vu1 = vDC −vavl1 = vDC +vbvu2 = vDC −vbvl2 = vDC +vcvu1 = vDC −vavl1 = vDC +vavu2 = vDC −vbvl2 = vDC +vcvu1 = vDC −vcvl1 = vDC +vavu2 = vDC −vbvl2 = vDC +vcvu1 = vDC −vcvl1 = vDC +vavu2 = vDC −vbvl2 = vDC +vbvu1 = vDC −vcvl1 = vDC +vavu2 = vDC −vavl2 = vDC +vbvu1 = vDC −vcvl1 = vDC +vcvu2 = vDC −vavl2 = vDC +vbvu1 = vDC −vbvl1 = vDC +vcvu2 = vDC −vavl2 = vDC +vbvu1 = vDC −vbvl1 = vDC +vcvu2 = vDC −vavl2 = vDC +vavu1 = vDC −vbvl1 = vDC +vcvu2 = vDC −vcvl2 = vDC +vavu1 = vDC −vbvl1 = vDC +vbvu2 = vDC −vcvl2 = vDC +va(iii)vu1 vu2vl1 vl2vu1 vu2vl1 vl2vu1 vu2vl1 vl2vu1 vu2vl1 vl2vu1 vu2vl1 vl2vu1 vu2vl1 vl2vu1 vu2vl1 vl2vu1 vu2vl1 vl2vu1 vu2vl1 vl2vu1 vu2vl1 vl2vu1 vu2vl1 vl2vu1 vu2vl1 vl21212121212121212121212121212121212121212121212121212121212121212Fig. 6.3. Twelve topological states of the QAC corresponding to the twelve intervals of operationforming a complete electrical cycle. The dotted line indicates path of conducting the DC current.Each subfigure corresponds to its respective interval, as defined by the converter angles ωt ∈ (i)[−pi/6, pi/6); (ii) [pi/6, pi/2); (iii) [pi/2, 5pi/6); (iv) [5pi/6, 7pi/6); (v) [7pi/6, 3pi/2); (vi) [3pi/2, 11pi/6);(vii) [11pi/6, 13pi/6); (viii) [13pi/6, 5pi/2); (ix) [5pi/2, 17pi/6); (x) [17pi/6, 19pi/6); (xi) [19pi/6, 7pi/2);(xii) [7pi/2, 23pi/6).149TABLE 6.1Director Switching States, Topology Intervals, andM-Arm Currents vs. theConverter Angle, ωtConv. Angle UpperM-Arm1 LowerM-Arm1 UpperM-Arm2 Lower M-Arm2 M-ArmCurrentsInterval ωt ∈ Su1,a Su1,b Su1,c Sl1,a Sl1,b Sl1,c Su2,a Su2,b Su2,c Sl2,a Sl2,b Sl2,c iu1 il1 iu2 il2(i)[−pi6 , pi6 ) 1 1 1 1 iDC−ic −ib ic iDC+ib(ii)[pi6 ,pi2)1 1 1 1 ia −ib iDC−ia iDC+ib(iii)[pi2 ,5pi6)1 1 1 1 ia iDC+ic iDC−ia −ic(iv)[5pi6 ,7pi6)1 1 1 1 iDC−ib iDC+ic ib −ic(v)[7pi6 ,3pi2)1 1 1 1 iDC−ib −ia ib iDC+ia(vi)[3pi2 ,11pi6)1 1 1 1 ic −ia iDC−ic iDC+ia(vii)[11pi6 ,13pi6)1 1 1 1 ic iDC+ib iDC−ic −ib(viii)[13pi6 ,5pi2)1 1 1 1 iDC−ia iDC+ib ia −ib(ix)[5pi2 ,17pi6)1 1 1 1 iDC−ia −ic ia iDC+ic(x)[17pi6 ,19pi6)1 1 1 1 ib −ic iDC−ib iDC+ic(xi)[19pi6 ,7pi2)1 1 1 1 ib iDC+ia iDC−ib −ia(xii)[7pi2 ,23pi6)1 1 1 1 iDC−ic iDC+ia ic −iabalancing DC-side current to flow through the stacks of SMs. Therefore, the QAC experiences12 topological changes over its operating cycle of two electrical cycles, i.e., 4pi.To better understand the operating principle, Fig. 6.2 presents ideal waveforms of theQAC, referenced to the converter angle ωt over two fundamental frequency cycles from−pi/6intervals to 23pi/6, split into 12 equidistant intervals. Fig. 6.2 (a) shows the phase voltages,va, vb, and vc, which are defined for each phase terminal to the virtual neutral-point on theDC-side of Fig. 6.2 between 12vDC and −12vDC. The line-to-line voltages vab, vbc, and vca areshown in Fig. 6.2 (b), and the voltages of the four M-Arms, vu1, vl1, vu2, and vl2, are shown inFig. 6.2 (c), respectively.The sequence of the 12 topological intervals and the states of all the DSs are summarizedin Table 6.1 with respect to the converter angle, ωt. Table 6.1 shows that each of the M-Armsconnects to each AC phase for four consecutive pi3intervals for a total period of 4pi3spenton each of the phases. During the first and fourth pi3intervals of each of these 4pi3periods, agiven M-Arm connected to the positive DC terminal (e.g., UpperM-Arm 1 or UpperM-Arm2) overlaps with another M-Arm connected to the negative DC terminal (e.g., LowerM-Arm1 or Lower M-Arm 2). Hence, at any given time, an Upper M-Arm overlaps with a Lower150M-Arm. During these overlapping intervals, one Upper and one LowerM-Arm are connectedto the same AC phase terminal, which forms a path for the DC current to flow. Since theoverlapping M-Arms are connected in series with the DC-side, the sum of the overlappingUpper and LowerM-Arms equals the DC-side voltage, vDC. The remaining two M-Arms, i.e.,the other Upper and LowerM-Arms that are not overlapping, connect to the other two ACphase terminals and conduct their respective phase currents. In addition to enabling the SMcapacitor voltages of each stack to be charged and balanced, the overlapping action of theQAC allows the removal of the DC-side pole capacitors. After the presented sequence of 12topologies finishes, all M-Arms will have made their complete rotation through all phasesduring two electrical cycles of AC voltages, and the sequence repeats.The 12 topological states, as defined by the states of the DSs in Table 6.1, are illustrated inFig. 6.3. The bold lines of Fig. 6.3 indicate the flow of current while the thin lines indicate itsabsence. The bold lines are coloured according to the phase they are presently conducting for,where the red, green, and blue lines correspond to phases A, B, and C, respectively. The boldlines are further separated into solid and dotted lines. When solid, the bold lines indicate thatthe M-Arm current is determined solely by the AC phase current; when dotted, the bold linesindicate that the respective M-Arms carry the DC current.The definitions of the M-Arm currents for each of the 12 intervals are presented in Table 6.1.As an example, during Interval (i), the Upper M-Arm 2 and Lower M-Arm 1 currents, iu2and il1, respectively correspond to the phase-c and phase-b currents, ic and -ib, but do nothave the DC current component, iDC . Since Upper M-Arm 2 and Lower M-Arm 1 do notcarry iDC, they are not overlapping for Interval (i). However, Upper M-Arm 1 and LowerM-Arm 2 [which are shown by the dotted red line of Interval (i)] respectively carry the currentsiu1 = iDC − ic and il2 = iDC + ib. Since both UpperM-Arm 1 and LowerM-Arm 2 have theiDC component, these two M-Arms overlap during Interval (i), which is apparent from Fig. 6.3.It is noted that for overlapping Upper and LowerM-Arms, the subtraction of their currents151yields the phase current by Kirchhoff ’s Current Law. For UpperM-Arm 1 and LowerM-Arm2, the subtraction of their currents during Interval (i) yields ia.From Fig. 6.3 and Table 6.1, it is evident that eachM-Arm remains in the same DS switchingstate for four consecutive pi3intervals. Taking the intervals (i) to (iv) as an example, we see thatUpperM-Arm 1 conducts for phase-a for four intervals, i.e., 4pi3, before transitioning to phase-c.For the first and last of these four intervals, i.e., (i) and (iv), the UpperM-Arm 1 conducts theDC current with the LowerM-Arm 2 [in (i)] and then with the LowerM-Arm 1 [in (iv)]. Forthe second and third of these intervals, i.e., (ii) and (iii), the UpperM-Arm 1 conducts only thephase-a current.During intervals (ii) and (iii) when the Upper M-Arm 1 is not conducting DC current,the UpperM-Arm 2 conducts the DC current with LowerM-Arm 2 for interval (ii) and theLowerM-Arm 1 for interval (i). The path of DC current (denoted by the dotted line of Fig. 6.3)changes every topological transition, i.e., every pi3. Hence, one can see that during any of thetwelve intervals, there is always one Upper and one LowerM-Arm that are overlapping, i.e.,two M-Arms are always conducting DC-side current.The information presented in Fig. 6.3 and Table 6.1 can also be illustrated in a form ofphasor diagrams of rotating triangles of line-to-line voltages. Specifically, Fig. 6.4 presentsthe 12 topological intervals and line-to-line voltages of the QAC at both the beginning andend of each interval. The method of depicting the time-varying line-to-line voltages as therotating triangle of phasors makes it easy to see visually when the appropriate line voltagegoes through zero (i.e., has its zero-crossing), at which instances DSs are used to change theconverter topology from one state to the next under ZVS.As shown in Fig. 6.4, during interval (i), the Upper M-Arm 1 and Lower M-Arm 2 areoverlapping and connected to phase-a. At the beginning of this interval, the line-to-linevoltage vab is zero (horizontal phasor) while vbc and vca have equal amplitudes but oppositepolarity, with vbc being negative and vca positive. These definitions are consistent with the idealline-to-line voltages of Fig. 6.2 (b). Then, during interval (i), the triangle of line voltage phasors152is being rotated clockwise such that the voltage vab increases while the voltage vbc decreases toits minimum (at ωt = 0) before returning to its starting value at ωt = pi6. For vca, we note thatit rotates from being positive (and equal and opposite to vbc) at the start of the interval, to bezero at the end of interval (i), i.e., at ωt = pi6. Since vca becomes zero at the end of interval (i),the LowerM-Arm 2 can now transition from phase-a to phase-c with ZVS, which begins theinterval (ii).During interval (ii), the LowerM-Arm 2 now overlaps with the UpperM-Arm 2 insteadof UpperM-Arm 1. At the beginning of interval (ii), vca = 0 while vab and vbc are equal andopposite with vab > 0 and vbc < 0. We continue rotating the triangle of line voltage phasorsclockwise, such that at the middle of interval (ii) at ωt = pi3, vab passes through its peak positiveA BC(i) (ii)vu1vu2vl2 vl1ABCvu1 vu2vl2vl1ABCvu1 vu2vl1vl2AB Cvu2vu2vu1vl2vl1vl2C AB(v) (vi)vu1vu2vl2 vl1CABvu1 vu2vl2vl1CABvu1 vu2vl1vl2CA Bvu2vu2vu1vl2vl1vl2B CA(iii) (iv)vu2vu1vl1 vl2BCAvu2 vu1vl1vl2BCAvu2 vu1vl2vl1BC Avu1vu1vu2vl1vl2vl1vu1 = vDC-vl2 vl1 = vDC-vu2+vbc vu2 = vDC-vl1+vbc vl2 = vDC-vu1vu1= vDC-vl2+vca vl1 = vDC-vu2vu2 = vDC-vl1vl2 = vDC-vu1+vcavu1 = vDC-vl1vl1 = vDC-vu1vu2 = vDC-vl2 -vbc vl2= vDC-vu2-vbc vu1 = vDC-vl2vl1 = vDC-vu2+vab vu2 = vDC-vl1+vab vl2 = vDC-vu1 vu1 = vDC-vl1-vca vl1 = vDC-vu1-vca vu2 = vDC-vl2vl2 = vDC-vu2 vu1 = vDC-vl1-vab vl1 = vDC-vu1-vab vu2 = vDC-vl2 vl2 = vDC-vu2153A BC(vii) (viii)vu2vu1vl1 vl2ABCvu2 vu1vl1vl2ABCvu2 vu1vl2vl1AB Cvu1vu1vu2vl1vl2vl1C AB(xi) (xii)vu2vu1vl1 vl2CABvu2 vu1vl1vl2CABvu2 vu1vl2vl1CA Bvu1vu1vu2vl1vl2vl1B CA(ix) (x)vu1vu2vl2 vl1BCAvu1 vu2vl2vl1BCAvu1 vu2vl1vl2BC Avu2vu2vu1vl2vl1vl2vu1 = vDC-vl2+vbc vl1 = vDC-vu2 vu2 = vDC-vl1 vl2 = vDC-vu1+vbc vu1 = vDC-vl2 vl1 = vDC-vu2+vcavu2 = vDC-vl1+vca vl2 = vDC-vu1 vu1 = vDC-vl1-vbcvl1 = vDC-vu1-vbcvu2 = vDC-vl2 vl2 = vDC-vu2 vu1 = vDC-vl2+vabvl1 = vDC-vu2vu2 = vDC-vl1 vl2 = vDC-vu1+vab vu1 = vDC-vl1vl1 = vDC-vu1vu2 = vDC-vl2-vcavl2 = vDC-vu2-vca vu1 = vDC-vl1 vl1 = vDC-vl1vu2 = vDC-vl2-vab vl2 = vDC-vu2-vab Fig. 6.4. Twelve topological states and operating principle of the QAC depicting rotation of theline-to-line voltage phasors. The subfigures correspond to the topological states defined by ωt ∈ (i)[−pi/6, pi/6); (ii) [pi/6, pi/2); (iii) [pi/2, 5pi/6); (iv) [5pi/6, 7pi/6); (v) [7pi/6, 3pi/2); (vi) [3pi/2, 11pi/6);(vii) [11pi/6, 13pi/6); (viii) [13pi/6, 5pi/2); (ix) [5pi/2, 17pi/6); (x) [17pi/6, 19pi/6); (xi) [19pi/6, 7pi/2);(xii) [7pi/2, 23pi/6).value before settling back to its initial value at ωt = pi2. Meanwhile, vca reduces from zeroand becomes negative. After an additional pi3radians, vbc becomes zero at the end of interval(ii), which prompts the UpperM-Arm 2 to transition from conducting for phase-c to phase-b.Hence, interval (iii) begins when the UpperM-Arm 2 transitions from phase-c to phase-b suchthat instead of overlapping with the LowerM-Arm 2, it is now overlapping with the LowerM-Arm 1. This process continues until the converter goes through all twelve intervals, at whichpoint interval (i) begins again, and process keep repeating.It is noted that intervals (i)→ (vi) and intervals (vii)→ (xii) each constitute one complete154electrical cycle. This can be seen by the identical positioning of the phase-a→ phase-c→phase-b triangles for the intervals (i)→ (vi) and the intervals (vii)→ (xii). However, comparing,e.g., intervals (i) and (vii), the difference is that the UpperM-Arm 1 and UpperM-Arm 2 areswapped, as well as LowerM-Arm 1 and LowerM-Arm 2 are also swapped, respectively. Thesame holds true for: intervals (ii) and (viii); (iii) and (ix); (iv) and (x); (v) and (xi); and (vi) and(xii), and so on.6.2.2 Director Switch Switching Operation and SizingTable 6.1 presents which of the M-Arms’ DSs are turned on for each of the pi3intervals overthe 4pi operating range. Since the DSs connect to each phase for 4pi3intervals, the DSs have anaverage duty cycle of 1/3. One period of the phase-a DS voltage of UpperM-Arm 1, i.e., vSu1,aof Fig. 6.1, is shown in Fig. 6.5 and is defined byvSu1,a(t) =12vDC − vu1(t)− va(t). (6.1)Using Fig. 6.3, (6.1) may be defined piece-wise asvSu1,a(t) =0, ωt ∈[−pi6, 7pi6),vca(t), ωt ∈[7pi6, 5pi2),−vab(t), ωt ∈[5pi2, 23pi6),(6.2)where the line-to-line voltages are defined in (5.1).Since vu1 contains the DC voltage component 12vDC, the DC-side voltage has no effect onthe DS voltage of (6.1) and Fig. 6.5. Moreover, vSu1,a is unaffected by the injection of triplenharmonic voltages, as they appear equally and oppositely in vu1 and va, as will be shown inSections 6.2.4 and 6.2.5. Hence, the sizing of the DSs and the shapes of their voltages is afunction of only the converter’s operating voltage, V1h. Fig. 6.5 indicates that the DSs arerequired to block bidirectional voltages of peak amplitudes√3V1h and−1.5V1h.155DS Voltage1.5V1h0.5V1hV1h0θq=ωTqθon=ωTon1.5V1h-V1h-0.5V1h-√3V1hsin(θq) √3V1hsin(θon)√3V1hωt (rad)- 5pi67pi63pi211pi613pi65pi217pi619pi67pi223pi62pi6pi6piFig. 6.5. Ideal DS voltage of Sa of UpperM-Arm 1.Next, the operation and sizing of the hybrid DSs of Fig. 6.1 (a-II) is investigated. Sincethe anti-parallel thyristors of the hybrid DSs have only a controllable turn-on, the DSs’ IGBTmodules ensure their reliable turn-off. The IGBT modules enable turn-off irrespective of thepolarity of the M-Arm currents and their operation is valid for all operating voltages. For theirturn-off, it is required that the thyristor current remains below its holding current, IH, for theduration of its turn-off time, Tq. Although the operation of the IGBT module is unaffected bythe polarity of the M-Arm currents, the physical process of thyristor turn-off does depend ontheir polarities, as is discussed below.From Fig. 6.5 and (6.2), the two intervals ωt ∈ [7pi/6, 13pi/6) and ωt ∈ [17pi/6, 23pi/6)ensure that vSu1,a is positive such that the IGBTmodule’s diode and upward-facing thyristor arereverse-biased. That is, immediately after the turn-off instance at ωt = 7pi/6, vSu1,a becomespositive. At the turn-off instance, the IGBTmodule is turned off and remains so for the entireoff-state interval, ωt ∈ [7pi/6, 23pi/6]; outside of this interval, the IGBT module is turned on.Since thyristors only gradually regain bidirectional voltage blocking capability, until fullbidirectional voltage blocking capability is regained Tq after turn-off, the IGBT module issized under the safe assumption that the thyristors have negligible blocking voltage untilωt = 7pi/6+ θq. Therefore, the IGBT modules are sized tovSu1,a(7pi6ω+θqω)=√3V1h sin(θq), (6.3)156as in Fig. 6.5, where θq = ωTq and ω is the fundamental angular frequency. Hence, the sizingof the IGBT module corresponds directly to the thyristor’s turn-off time.Next, the thyristors’ turn-on and -off operation is described for the M-Arm/DS currentpolarities:• When iu1 < 0, such that the M-Arm current flows through the upward-facing thyristor,the negligible inductance of the QAC’s M-Arms and DSs enables the line-to-line voltageacross Su1,a to quickly force the DS current to below IH over the interval ωt ∈ [7pi/6, 13pi/6],allowing ample time for Tq to elapse. Hence, the turn-off of the upward-facing thyristors is anatural consequence of the normal operation of the QAC’s M-Arms, and is allotted up to pi radaccomplish.•When iu1 > 0, theM-Arm current flows through the downward-facing thyristor such that thecurrent is reduced to below IH by turning the IGBT module off. In this case, the downward-facing thyristor of Su1,a is to be completely turned off by ωt = 7pi/6+ θq such that the IGBTmodule voltage remains below√3V1h sin(θq). Since the IGBT module is designed to hold theDS current below IH, turn-off is ensured by ωt = 7pi/6+ θq. It is noted that should iu1 changepolarity immediately prior to the turn-off event, the method remains valid since both theanti-parallel thyristors’ currents are held below IH.An important feature of the hybridDSs’ structure is its ability to nullify the thyristors’ criticalrate-of-rise of on-state current (di/ dtcrit) operating limitation. In addition to supporting theDS voltage during turn-off, the IGBT module can support the DS voltage for the Su1,a DSduring the interval ωt ∈[ωTon − 23pi6 ,23pi6], where Ton ≤ Tq, such that the thyristors’ triggersignals can propagate throughout the thyristors before load current flows. Such capabilityreduces the thyristors’ switching losses as well as simplifies the DSs’ gate signal design, sinceminor discrepancies in the arrival time of the thyristor gate signals will not cause failure.Assuming that the DS snubber circuits can ensure the maximum voltage of (6.3) across theIGBT module, the IGBT module’s reverse blocking capability can contribute to the blocking ofvSu1,a > 0; no such contribution is available when vSu1,a < 0. Therefore, assuming anti-parallel157thyristors of equal positive andnegative voltage blocking capability, the IGBTmodule can reducethe thyristors’ voltage blocking capability from√3V1h, as in Fig. 6.5, to√3(1− sin(θq))V1h, orto a minimum of 1.5V1h. Hence, the minimum thyristor voltage can be expressed asvˆthy. = max(1.5V1h,√3(1− sin(θq))V1h). (6.4)For the thyristor considered herein [96], with Tq = 550 µs, (6.4) results in the minimumblocking voltage of vˆthy. = max(1.5V1h, 1.43V1h) = 1.5V1h.6.2.3 Arm Currents and Optimal Operating PointWhen an M-Arm is not overlapping with another M-Arm, the current through it is equiva-lent to the phase current. When the M-Arm is overlapping with another arm, its current willcontain the DC-side current. The DC-side current can be defined in terms of the Upper orLowerM-Arm currents asiDC =iu1(t) + iu2(t)il1(t) + il2(t). (6.5)Equation (6.5) shows that the current of the overlapping M-Arm is equivalent to iDC subtractedby the M-Arm that is conducting only the phase current. Hence, with Fig. 6.2 and (6.5), theM-Arm currents may be defined with respect to the converter angle, ωt, as in Table 6.1.As the M-Arm currents presented in Table 6.1 are defined piece-wise, discontinuities in theM-Arm currents may arise when the current definitions change. Since the DC-side current’svalue is a function of only the real power and the DC-side voltage, but the phase current isinversely proportional to the operating voltage, careful choice of V1h can enable the M-Armcurrents to remain continuous throughout the transitions.For determining the value of V1h that results in continuous M-Arm current, the UpperM-Arm 1 current, iu1, at the transition of ωt = pi/6 is considered. By ensuring equality oneither side of the transition boundary, the V1h that enables continuous M-Arm currents can be158found. That is,iu1(pi6ω-)= iu1(pi6ω+)⇐⇒ iDC − ic( pi6ω) = ia( pi6ω), (6.6)⇒ iDC + ib(pi6ω)= 0, (6.7)where (6.7) results from the three-phase symmetry of the phase currents. With a peak phasecurrent of I1h and a power factor angle of ϕ, the AC/DC power balance principle is invokedsuch that (6.7) may be rewritten as32(V1hI1h cos (ϕ))vDC+ I1h sin(pi6− 2pi3− ϕ)= 0, (6.8)where the solutions to (6.8) result inV1h =23vDC, (6.9)ϕ = ±pi2. (6.10)With (6.9), continuous M-Arm currents are ensured for all ϕ, while (6.10) suggests thatreactive current enables continuous M-Arm currents irrespective of the operating voltage.Hence, in addition to the DSs’ ZVS, which is available for any value of V1h, as shown in Fig. 6.5,the operating voltage of (6.9) enables ZCS for the DSs. Due to the continuous M-Arm currentsand the ZVS/ZCS operation for the DSs, the voltage proposed in (6.9) may be considered theoptimal operating voltage of the QAC.It is noted that the left-hand side (LHS) of (6.7) describes the current for LowerM-Arm2 at ωt = pi/6, i.e., il2 = iDC + ib, as specified in Table 6.1, as Lower M-Arm 2 transitionsfrom conducting for phase-a to phase-c. Therefore, the LHS of (6.7) defines the magnitudeof the current at which the DSs are turned on or off. Consequently, the magnitude of thejump-discontinuity at ωt = pi/6, i.e., the subtraction of the LHS and RHS of (6.6), is equivalentto the current at which the DSs are turned on or off. Hence, (6.7) can be rewritten and159simplified to ∣∣∣ˆisw∣∣∣ = ∣∣∣∣ 12vDC (3V1h − 2vDC)I1h cos(ϕ)∣∣∣∣, (6.11)where∣∣∣ˆisw∣∣∣ = ∣∣∣il2( pi6ω)∣∣∣ describes both the magnitude of the jumps that occur in the M-Armcurrents as well as the current under which the DSs are turned on or off. It is further notedthat setting∣∣∣ˆisw∣∣∣ = 0 results in V1h and ϕ of (6.9) and (6.10).Fig. 6.6 shows iu1 of UpperM-Arm 1 for voltages above and below the optimal voltage of(6.9), as well as for the three power factor angles ϕ ∈{0, pi4, pi2}. The operating voltages testedare V1h ∈{12VDC,23VDC,56VDC}. The apparent power is assumed to be the same in all cases,such that the phase currents are scaled to maintain the same power. The current is normalizedto the peak AC phase current of the optimal voltage case, I1h,nom.. Fig. 6.6 shows that thereactive power cases have no discontinuities irrespective of the operating voltage; meanwhile,jump-discontinuities are seen twice per 4pi3cycle when considering operating voltages otherthan V1h = 23VDC at the other power factor angles.6.2.4 Triplen Harmonic Voltage InjectionTriplen harmonics may be injected into the QAC’s M-Arm stack voltages to reduce theirpeak absolute values, thereby enabling a reduction in the number of IGBTs, the converterfootprint, and the semiconductor conduction losses. The proposed triplen harmonic schemeenables the voltages supplied by the QAC’sM-Arm stacks to be limited to within±12vDC duringnormal operation.From Fig. 6.2 (c), the M-Arm stacks’ peak voltages occur when they generate the negativeportion of the phase voltages. For Upper M-Arm 1’s generation of phase-a, vu1 experiencesits peak voltages when ωt ∈ {−pi/6, 7pi/6}, which correspond to the peak voltage vˆu1 =12VDC − va(− pi6ω). When V1h = 23VDC, vˆu1 = 56VDC, where va(− pi6ω) = 13VDC.To reduce the voltage generation requirements of the M-Arm stacks to their minimum,i.e., 12VDC, a triplen harmonic, vtri, is injected into the phase voltages to make them equal tozero during the overlap periods. Such a triplen harmonic equals the fundamental-frequency160i u1 (×I1h,nom.)i u1 (×I1h,nom.)i u1 (×I1h,nom.)0-110-110-11ϕ = 0 ϕ = V =1h VDC 12V =1h VDC 23V =1h VDC 56(a)(b)(c)pi4 ϕ = pi2ωt (rad)- 5pi67pi63pi211pi613pi65pi217pi619pi67pi223pi62pi6pi6pi(xii)(xi)(x)(ix)(viii)(vii)(vi)(v)(iv)(iii)(ii)(i)Fig. 6.6. Current of UpperM-Arm 1 for different operating voltages and power factor angles where thered, blue, and green overlays respectively correspond to UpperM-Arm 1’s contribution to phases-a, -b,and -c.voltage component of va for ωt ∈ [−pi/6, pi/6], i.e., when UpperM-Arm 1 overlaps with LowerM-Arm 2, and it equals the fundamental-frequency voltage component of vc when UpperM-Arm 2 overlaps with LowerM-Arm 2 for ωt ∈ [pi/6, pi/2].Hence, vtri is defined on the range ωt ∈ [−pi/6, pi/2] and is therefore periodic with 2pi3 . Itcan be expressed asvtri(t) =V1h sin(ωt), ωt ∈[−pi6,pi6),V1h sin(ωt+ 2pi/3), ωt ∈[pi6,pi2).(6.12)It is noted that vtri repeats itself six times over a 4pi cycle and has peak values of ±12V1h, asseen in Fig. 6.7. With the addition of (6.12), the voltage vu1(− pi6ω) may be reduced fromvˆu1 =12vDC +12V1h to 12vDC, enabling a significant reduction of the number of FBSMs.1610Arm VoltageNo TriplenWith Triplenvu1vDC + V1h12 12vDC12V1h12vDC - V1h12vDC12-− 5pi62pi37pi62pi3pi6pi06pi pitrivu1vtriωt (rad)Fig. 6.7. Ideal M-Arm voltage of UpperM-Arm 1 both with (vtriu1) and without (vu1) the injection of thetriplen harmonic voltage, vtri.Although the phase voltages vj presented to the Delta-connected transformer have peakvalues of±1.5V1h, the triplen harmonic cancels in the line-to-line voltages. To illustrate theeffect of the triplen harmonic of (6.12), Fig. 6.7 verifies the reduction in required blockingvoltage of the M-Arms, where it is noted that the UpperM-Arm 1 stack voltage with the triplenharmonic voltage injection, vtriu1, can be represented asvtriu1(t) = vu1(t) + vtri(t). (6.13)It is noted that the triplen harmonic of (6.12) enables the M-Arm stack voltages to bebounded by the positive peak value 12VDC for all values of V1h, but it is only for the optimaloperating point of (6.9) that the stack voltages’ negative peak value matches the positive, i.e.,−12VDC. Values of V1h less than the optimal value still require the M-Arms to be sized to 12VDC,which results in underutilization of the QAC’s FBSMs.6.2.5 DC-side Fault Ride-Through CapabilityTheQAC is inherently capable of supporting the AC-side voltage as a STATCOM in DC-side pole-to-pole fault scenarios when the DC-side voltage collapses to zero. To minimize thevoltage requirement of the QAC’s M-Arms while ensuring straightforward converter controlthroughout normal and DC-side fault operations, a multiplicative factor ktri modifies vtri such1620VDC,nom VDC,nomM-Arm StackVoltage V1hV1h V1hNo TriplenWith Triplen12121232√---− 5pi62pi37pi62pi3pi6pi06pi piωt (rad)Fig. 6.8. Ideal M-Arm voltage of UpperM-Arm 1 during a DC-side fault, i.e., when vDC ≡ 0.that the UpperM-Arm 1 stack voltage of (6.13) changes tovtriu1(t) = vu1(t) + ktrivtri(t). (6.14)From Fig. 6.7, it is noted that vtri(pi3ω)= 0 and therefore the triplen harmonic has no effect onvu1 at t = pi3ω. Hence, during a DC-side fault, i.e., when vDC ≡ 0, the UpperM-Arm 1 stackvoltage at t = pi3ωequals vu1(pi3ω)= −√32V1h.During DC-side faults when vDC ≡ 0, the line-to-line voltages at the AC terminals are inseries with an Upper and LowerM-Arm stacks such that the sum of the voltage generationcapabilities of an Upper and LowerM-Arm stacks should equal the peak line-to-line voltage.Since vu1(pi3ω)= −√32V1h during DC-side faults, which is half the line-to-line voltage, theUpper and LowerM-Arm stacks should be sized for bidirectional voltages of√32V1h to enableDC fault ride-through capability; for V1h = 23VDC, the M-Arm stacks should be sized for√33vDC.Hence, ktri should be chosen such that the minimum value of vu1 is−√32V1h during DC-side fault operation. From inspection of Fig. 6.7, which corresponds to the operating voltageV1h =23vDC, it is seen thatvtriu1(− pi6ω)= −vtriu1(pi2ω). (6.15)By ensuring the validity of (6.15) during both normal and DC-side fault operating modes,163ktri can be derived as a function of the DC-side voltage under the assumption of the optimaloperation voltage V1h = 23VDC,nom., where VDC,nom. is the nominal DC-side voltage in normaloperation. Hence, (6.15) can be solved with vtriu1 defined in (6.14) asktri(vDC) =32vDCVDC,nom.− 12. (6.16)The theoretical stack voltage of UpperM-Arm 1 when vDC ≡ 0 is shown in Fig. 6.8, wherethe inclusion of ktri shows a reduction in the stack voltage from |vˇu1| = V1h to∣∣vˇtriu1∣∣ = √32 V1h.At the optimal operating voltage of V1h = 23VDC,nom., this implies the QAC’s M-Arms are to berated for√33VDC,nom..6.3 Performance EvaluationIn this section, the dynamic performance of the QAC is tested under various operationscenarios, including steady-state normal operation, changing converter power transfer, anda DC-side pole-to-pole fault. The MATLAB/Simulink/Simscape Specialized Power Systemstoolbox is used to model the QAC with a time step of 20 µs. The AC-side of the converter isconnected to a 400 kV grid through the∆-side terminals of a∆−Y transformer for the third-order harmonic cancellation. The DC-side of the QAC is supplied with the DC-side voltage of600 kV. Hence, for the operating voltage V1h = 23VDC, the nominal converter-side phase voltageamplitude is 400 kV for a line-to-line RMS voltage 490 kV. With the rated FBSM voltage of 5 kV,the number of FBSMs required per M-Arm stack is given by√32×400 kV/5 kV = 70 FBSMsto enable adequate reverse-blocking voltage in the event of a DC-side pole-to-pole fault. Anadditional two FBSMs are added for redundancy and to enable increased reactive power supportduring DC-side faults. Hence, 72 FBSMs rated for the total bidirectional voltage of 360 kV areused for each M-Arm stack.For the simulation, the 4.5-kVWestcode T1800GB45A IGBT [90] of Chapter B is assumedfor the DSs’ turn-off as well as the FBSMs; it has on-state parameters given in Table B.3. The8.5-kV ABB 5STP 27N8500 thyristor is assumed to compose the DSs [96], where its on-state164TABLE 6.2Simulation ParametersSimulation parametersMaximum power rating 1096MVAMaximum P 1000MWMaximumQ 500MVARDC-side voltage 600 kVFBSM capacitorvoltage5 kVFBSM capacitorcapacitance2.7mFDC-side inductance 25mHTransformer leakageimpedance0.001+ j0.18 puTransformer windingratio (Y /∆)400 kV/490 kVcharacteristics are provided in (3.16). The converter parameters used in the simulation arefound in Table 6.2.6.3.1 Steady-State Normal OperationFirst, the QAC is assumed to operate as an inverter with 1GW power flow from the DC- toAC-side. Two 4pi cycles of UpperM-Arm 1’s key measurements are presented in Fig. 6.9. Fromtop to bottom, Fig. 6.9 (a) shows that the M-Arm current depends on the DSs’ switching states,e.g., the M-Arm current is equivalent to the phase-a DS’s current when the phase-a DS’s is on.Consequently, the voltage of the phase-a DS is zero until the DS is turned off, as shown inFig. 6.9 (b). The M-Arm stack voltage in Fig. 6.9 (c) proves that the triplen harmonic voltageinjection limits the voltage range between ±12vDC, as explained in Section 6.2.4. It is notedthat the effect of the triplen harmonic voltage injection disappears in the line-to-line voltage;therefore, the voltage from phase-a to phase-b is a perfect sinusoidal waveform, as shown inFig. 6.9 (d). Moreover, the scheme of using each M-Arm to generate power equally for eachphase, as well as the individual generic capacitor voltage balancing algorithm, ensures the1650120.22 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.3Time (s)iSu1,a iSu1,b iSu1,c4002000-200-400 (kV)v u (kV)v Su1,a (kA)i u1480050005200100001000(a)(b)(c)(e)-800-600-400-2000200400600800 (kV)vab(d) (V)vi cFig. 6.9. Key waveforms of UpperM-Arm 1 during normal operation. (a) M-Arm and DSs’ currents;(b) phase-a DS’s voltage; (c) M-Arm stack voltage; (d) Phase-to-phase voltage; (e) Individual FBSMvoltage.166-100001000 (kA)i DC-2023503603700 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Time (s)(a)(b)(c)P Q (MW) & P (MVAR)Q (kV)v ciΣFig. 6.10. Key waveforms of the QAC during a power change. (a) Active and reactive powers; (b)DC-side current; (c) Summation of the FBSM capacitors’ voltage.balance between individual FBSM capacitor voltages. The FBSM voltage variation is within 8%,as shown in Fig. 6.9 (e).6.3.2 Converter Power TransferThis subsection focuses on the QAC’s performance during a power flow direction reversal.Fig. 6.10 illustrates the dynamic transient responses of the QAC as it changes its power output.Initially, zero power is transferred through the converter until a 1GW active power and200MVAR reactive power reference command at t = 0 s is given. As shown in Figs. 6.10 (a) and(b), the instantaneous powers follow the change in power reference while the DC-side currentgradually rises in response. Fig. 6.10 (c) contains the summation of the FBSMs’ capacitorvoltages for each of the four M-Arm stacks. Although the variation of the summation of thecapacitors’ voltages increases for higher power levels, the zoomed-in subfigure shows the167balance between the four M-Arms is maintained. At t = 0.4 s, the QAC’s operating modeis changed from inversion to rectification such that the QAC follows a ramp command toshift its real and reactive power outputs from 1GW and 200MVAR to −1GW and −200MVAR,respectively. Fig. 6.10 exhibits a smooth transition while the power flow changes directionswhile the DC-side current follows suit.6.3.3 DC-Side Pole-to-Pole FaultThe DC fault ride-through capability of the QAC is verified in this section. The test systemis assumed to be subjected to a 150ms DC-side pole-to-pole fault at t = 0.5 s across the QAC’sDC-side terminals. The dynamic performances of QAC are presented in Fig. 6.11. The DC-sidevoltage drops to zero immediately after the fault, as shown in Fig. 6.11 (c), which triggers theprotection scheme of the QAC at t = 0.502 s. In response to the falling DC-side voltage, acommand is issued to reduce the real power to 0GW, as shown in Fig. 6.11 (a). Setting thereal power to zero limits the AC-side contribution to the fault and ensures that the energywithin the M-Arm stacks is not dissipated to the AC-side. Fig. 6.11 (d) shows the DC current’srapid descent to 0A in response to the power command. Fig. 6.11 (a) also shows that despite afalling real power, the QAC’s reactive power contribution remains unaffected. This is due to themultiplicative factor, ktri, that is multiplied to the triplen harmonic from (6.16) of Section 6.2.5.That is, instead of simple blocking of the converter, the QAC is able to support the AC-sidethroughout DC fault scenarios. Lastly, Fig. 6.11 (e) proves that throughout the fault, the energycontained within UpperM-Arm 1 does not deviate significantly from its set-point.At t = 0.650 s, the DC fault is cleared and the DC fault recovery begins. The DC-sidevoltage is gradually restored to the pre-fault level from the DC-side as shown in Fig. 6.11 (c).Thereafter, the converter’s real power is restored to 1GW. It is noted that no special control isrequired for the QAC to handle faults: all that is necessary is to reduce the power commandupon detection of the fault in order to prevent the M-Arm stacks from over- or under-charging.Hence, the converter benefits from a larger DC-side inductance (LDC of Fig. 6.1), which enables1680600400200 (kA)i a (kV)v DC (kV)i DC0123503603700.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Time (s)P Q05001000-2-1012 (MW) & P (MVAR)Q(a)(b)(c)(d)(e) (kV)v ciΣFig. 6.11. The performance of the QAC during the DC-side fault. (a) Active and reactive power; (b)phase-a current; (c) DC voltage; (d) DC current; (e) Summation of UpperM-Arm 1 FBSMs’ capacitorvoltages.1690200-200-40040000.2-0.2-0.40.40.58 0.585 0.59 0.595 0.6 0.605 0.61 0.615 0.62Time (s) (kV)v u1 (kA)i u1(a)(b)Fig. 6.12. The performance of Upper M-Arm 1 during DC-side fault operation. (a) M-Arm stackvoltage; (b) M-Arm current.ample time to detect the DC-side fault, although sufficiently fast measurement and controlachieves the same goal.Fig. 6.12 presents three cycles of Upper M-Arm 1’s voltage and current during the fault.With the implementation of the triplen harmonic voltage injection, the M-Arm stack voltage inFig. 6.12 (a) can be limited between 12VDC and−√33VDC, as in Fig. 6.8. This further proves theDC-side fault ride-through capability of the QAC proposed in Section 6.2.5. As the converter isoperated with pure reactive power, the shape of the M-Arm current in Fig. 6.12 (b) is triangularas in Fig. 6.6 when ϕ = 0. Therefore, the QAC has been shown to be a robust converter whensubjected to DC-side pole-to-pole faults and can quickly resume operation post-fault, due toits DC-fault ride-through capability.6.4 Converter ComparisonThis section quantitatively and qualitatively benchmarks the QAC against other state-of-the-art VSC-HVDC converters, i.e., the HBSM-MMC, MBSM-MMC, EO-AAC, H3LC,and the DAC with regard to: converter semiconductor losses; approximate relative sizingof the converters, through inspection of nominal energy storage requirements; and general170converter attributes including the converters’ operational voltage limits, required number ofsemiconductors, and DC fault blocking capability. The results of the comparison are presentedin Table 6.3.6.4.1 Converter General Capabilities and Semiconductor RequirementsFor a high-level comparison, the QAC is compared against the HBSM-MMC,MBSM-MMC,EO-AAC, H3LC, and the DAC based upon their general capabilities as well as their numberof 5 kV SMs and semiconductor devices under the assumption of a 600 kV DC-side voltage.The same Westcode T1800 GB45A IGBT [90] and the ABB 8.5 kV 5STP 27N8500 [96] ofSection 5.5 are used. As a practical safety factor, the semiconductors are de-rated by a ratio of2.5 kV:4.5 kV as in [83]. To satisfy the DS or SM voltage blocking ratings, the required numberof semiconductors are connected in series. The QAC is assumed to use the hybrid DSs ofFig. 6.1 (a-II), as implementing the anti-series IGBTs of Fig. 6.1 (a-I) results in substantialconduction losses.Table 6.3 presents the general comparison and shows that, while the QAC does have ahigher requirement for semiconductors, its number of 5 kV SMs is significantly lower than theEO-AAC, HBSM-MMC, and MBSM-MMC. It is noted that bidirectional thyristors could beused instead of the phase-control thyristors such that approximately half as many thyristorscould be used. However, bidirectional thyristors typically have higher on-state losses. It is alsonoted that the limits of operation for the converters, i.e., V1h, show that the QAC and EO-AACcan achieve 15% higher voltages than the MMCs. It is further noted that while a hard limit onthe AC voltage exists for the HBSM-MMC and H3LC, the addition of extra FBSMs enablestheoretically unlimited voltage scalability for the EO-AAC, MBSM-MMC, DAC, and QAC.6.4.2 Converter Semiconductor LossesIn the “Loss analysis” portion of Table 6.3, the converters’ efficiencies, based on theirsemiconductor conduction and switching losses, are compared. The QAC’s semiconductorconduction and switching losses are calculated and compared quantitatively against those of171TABLE 6.3Comparison of Selected ConvertersConverter typeHBSM-MMCMBSM-MMCEO-AACH3LC DAC QACGeneralconvertercomparison Max AC voltage, V1h (×VDC) 1/√3 1/√3 2/3 0.63√3/pi 2/3DC-side voltage 600 kV 600 kV 600 kV 600 kV 600 kV 600 kVNo. of IGBTs 2880 4320 4800 37443534(1394)2816No. of thyristors 1536 0 0 00(1872)3072No. of 5 kV SMs 720 720 480 198 120 280DC-side pole capacitor No No No Yes Yes NoDC fault blocking No Yes Yes Yes Yes YesLossanalysisAC voltage, V1h (×VDC) 0.523 2/3 0.573√3/pi 2/3SM Pcond (MW) 3.68 5.62 3.77 1.75 3.27 3.30SM Psw (MW) 2.30 2.30 0.95 1.31 1.32 1.35DS Pcond (MW) - - 1.80 3.423.31(1.18)1.39DS Psw (MW) - - - 0.44 0 0Total Loss (MW) 5.98 7.92 6.52 6.927.90(5.77)6.04Percentage Loss 0.60% 0.79% 0.65% 0.69%0.79%(0.58%)0.60%EnergyanalysisAC voltage, V1h (×VDC) 0.523 2/3 0.573√3/pi 2/3Enom(J · radVA · s)9.565 4.50 1.106SMs PCs1.040.713.01†2.97Normalized to MMC 1.00 0.471 0.1160.1830.424† 0.311∗Bracketed values assume the hybrid DSs for the DAC.†For 5% individual pole capacitor ripple.172the HBSM-MMC, MBSM-MMC, EO-AAC, H3LC, and the DAC.The losses are calculatedfrom the detailed time-domain converter simulations using the MATLAB/Simulink/SimscapeSpecialized Power Systems toolbox with each of the converters transferring 1GW of real powerto the PCC at a DC-side voltage of 600 kV. The AC-side voltage magnitudes used for each ofthe converter simulations were chosen to enable a 10% increase in the converters’ modulationindices without exceeding their respective limits of operation. In the cases of the EO-AAC,DAC, and QAC, their optimal value of V1h was used, due to their natural capability to operateabove it.The losses are presented in Table 6.3, wherein they are categorized into conduction andswitching losses for each of the converters’ DSs and SMs. The results show that the QAC’slosses are 7.7% and 24.1% less than the EO-AAC’s andMBSM-MMC’s, and virtually equivalentto the HBSM-MMC’s. When the DAC’s hybrid DS is used, its efficiency also matches theQAC’s.Therefore, among the modular converters, i.e., those which do not require DC-side polecapacitors, the QAC features competitive efficiency.6.4.3 Energy Storage AnalysisCompared to the MMCs’ or EO-AAC’s six-arm structures, the QAC is expected to feature acompact footprint enabled by its four M-Arm structure and lower energy storage requirements.The analysis presented herein is based upon the methods proposed in Chapter A, wherein thenominal energy storage requirements of the converters are calculated numerically based onthe maximum energy deviations experienced by the converters’ arms. For an emphasis ongenerality, the energy storage requirements are normalized with respect to the three-phasepower and system frequency, i.e., in units ofJ·radVA·s , which removes any dependencies thereon.Table 6.3 presents the normalized nominal energy storage requirements of the comparedmodular converters with an allowable voltage deviation of ∆Vc = 10%, and shows that, inaddition to requiring fewer arms than either the MMCs or the EO-AAC, the QAC also requiresthe least total energy storage.It is noted that compared to the H3LC and DAC, the QAC has a 168% and 70% higher173energy storage requirement, respectively. However, the H3LC and DAC need DC-side polecapacitors, which influences their design complexity. The QAC, on the other hand, requiresonly modular FBSMs and DSs.6.5 ConclusionProposed in this chapter was a new type of VSC-HVDC converter topology, theQAC, whichfeatures high efficiency, DC-side pole-to-pole fault ride-through capability, and a compactfootprint enabled by its: four-arm structure, small energy storage requirements (as derived inSection 6.4), and absence of discrete arm inductors and DC-side pole capacitors. In Section 6.1,the QAC’s thyristor/IGBT hybrid DSs, optimal operating point, and triplen harmonic injectionscheme were proposed. The triplen harmonic enables seamless transition between normal-and fault-operation modes while reducing the arms’ peak voltage requirements to√33VDC.Simulation studies of a 600 kV test-system verified the QAC’s operating principle, effectivenessin regulating real and reactive powers, and DC fault ride-through capability. Comparisonsbetween other VSC-HVDC converters were presented and showed that the QAC has similarsemiconductor losses to the HBSMMMC while having smaller energy storage requirementsthan the EO-AAC. Therefore, among the modular VSC-HVDC converters with DC faultblocking capability and no DC-side pole capacitors, the QAC offers competitive efficiency andhigh compactness enabled by its small capacitive energy storage requirement.1747.Multiplexed-Stack ConverterThis chapter proposes a significant modification to the DAC of Chapter 5, which is namedthe Multiplexed-Stack Converter — the MSC. Its DC-side is spanned by four series-connectedstacks and it does not need DC-side PCs for some operating modes as the DAC does. Therefore,its DC-side current can be free of low-order harmonics.The MSC features inherent DC-fault ride-through capability enabled by its HBSM-basedUpper Inner and Lower Inner stacks such that it can supply reactive power with a collapsedDC-side voltage. TheMSC is also shown to require less than a quarter of the energy storageas the MMC.This, combined with its reduced number of SMs, suggests the MSC will have asignificantly reduced footprint compared to the MMC.7.1 TopologyTheMSC is presented in Fig. 7.1, wherein its Upper and Lower Outer FBSM-based stacks(denoted by the voltages vuo and vlo) andUpper and Lower InnerHBSM-based stacks (denotedby the voltages vui and vli) are shown to span the DC-side, while a three-level T-type NPCcomposed of DS valves multiplexes the stacks among the three-phase terminals for sinusoidalAC line-to-line voltage generation. On the MSC’s DC side are two optional PCs, which areoptionally connected to the MSC’s midpoint with an FMS, that are used to ensure energybalance for the stacks for all AC operating voltages. The optional FMS is used to disconnect theMSC’s midpoint from the PCs during DC-side faults, which enables the Inner stacks to operateduring DC-side fault for DC-fault ride-through capability. However, it will be demonstratedin later sections, that the PCs can be all together omitted if the MSC is chosen to operate atthe phase-to-midpoint fundamental-frequency voltage amplitude of V1h =√3pi9vDC, whichis the AC voltage at which the Outer stacks have no DC voltage component. The Upper,This chapter is based on the to-be-submitted IEEE journal article “Multiplexed-Stack Converter withDC-FaultRide-Through Capability and High Compactness,” which will be submitted to the IEEE Transactions on IndustrialElectronics [99].175LDCRfault LbalLbaliDCvDC+vDC-vDC,uvPC,uCuClvDC,lvaSm,avbSm,bvcSm,cvuiiuiilivuovli+−+−++++−− −vPC,l+−−+−vloSu,cSu,a Su,biuUpperOuterStackUpperInnerStackOptionalPoleCapacitorsOptionalFMSLowerInnerStackLowerOuterStackiuoiloilinnibal,uibal,lSl,cSl,a Sl,biaibicFBSMFBSMFBSMFBSMHBSMHBSMHBSMHBSMFBSMvc,uosSuo,1sSui,1sSuo,2sSui,2sSuo,4sSuo,3sCFBSM+−HBSMvc,uis CHBSM+−Fig. 7.1. The topology of the MSC.Midpoint, and Lower DSs are respectively denoted by Su,j, Sm,j, and Sl,j, where the subscriptj ∈ {a, b, c} is reserved to denote the three phases. The AC phase voltages, vj, are measuredwith reference to the Midpoint of the T-type NPC, which is denoted by n in Fig. 7.1, and arereferred to as the phase-to-midpoint voltages.7.2 Operating PrincipleThis section presents the operating principle of the MSC under all operating modes. First,theMSC’s operating principle with themidpoint clamped through the optional FMS is presented.176TABLE 7.1DS Switching States and Topology Intervals for Varying ωt.TopologyIntervalsConv. angle Upper DSs Lower DSs Midpoint DSsωt Su,a Su,b Su,c Sl,a Sl,b Sl,c Sm,a Sm,b Sm,c(i)[−pi6, pi6)1 1 1(ii)[pi6, pi2)1 1 1(iii)[pi2, 5pi6)1 1 1(iv)[5pi6, 7pi6)1 1 1(v)[7pi6, 3pi2)1 1 1(vi)[3pi2, 11pi6)1 1 1Then, its operating principle with a floating midpoint, and no FMS, is presented. The controlflow of the MSC is presented, as well as its DC-fault operation.7.2.1 Sinusoidal AC Line-to-LineVoltage GenerationFor the MSC topology, the stack voltages are synthesized over 2pi cycles, i.e., ωt ∈[−pi/6, 11pi/6], to sequentially participate in generating portions of the three-phase line-to-line voltages. Using the DSs of the three-level T-type NPC converter of Fig. 7.1, the stacksare multiplexed to each of the phases according to the DS states of Table 7.1, as with theDAC.The DS states for the six topology intervals (i)→ (vi) are outlined in Table 7.1, whereit is seen that the Upper and Lower DSs are each in the on-state for 2pi/3 intervals while theMidpoint DSs are operated for pi/3 intervals. When the Midpoint DSs are in the on-state, thephase-to-midpoint voltages are clamped to the midpoint such that the Inner stacks generatethe line-to-line voltages.Fig. 7.2 presents the key operational voltage waveforms of the MSC, while Fig. 7.3 presentsthe voltage and current definitions of the MSC for the six topological intervals. Fig. 7.3 alsopresents phasor diagrams of the line-to-line voltages at the beginning of each of the intervals.As stated, the stacks sequentially contribute to intervals of the AC line-to-line voltage. As anexample, for interval (i), the interval begins when the phase-a to -b voltage, vab, is zero. For this177InnerStack voltages(b)(a)vDC-vDC0vab vbcvcavDC-vDC0Line-to-linevoltages(d)vDC0va vbvcPhase-to-midpointvoltagesvDC12vuovlovDC12-(c)vDC-vDC-vDC0OuterStack voltagesvDC12vuivlivDC12-1.5V1hvDC−1.5V1h12ωt (rad)5pi67pi63pi211pi62pi6pi- 6pi(i) (ii) (iii) (iv) (v) (vi)Fig. 7.2. Idealized voltages explaining the operation of the MSC: (a) line-to-line phase voltages; (b)Upper and Lower Outer stack voltages when optional FMS is used; (c) Upper and Lower Inner stackvoltages; and (d) phase-to-midpoint voltages.interval, the Upper Inner and Outer stacks generate voltages for the line-to-line voltage, vca,while the Lower Inner and Outer stacks generate voltages for vab.During this interval, thephase-a terminal is clamped to the midpoint such that va = 0 for interval (i). Meanwhile, thephase terminals B and C are respectively clamped to the Lower and Upper stacks, respectively.Once the line-to-line voltage vca crosses zero at ωt = pi/6, interval (ii) begins while the voltagedefinitions of the stacks change. The information regarding the MSC’s currents and voltages isalso respectively summarized in Tables 7.2 and 7.3.It is noted that at each interval boundary, one of the three-phase line-to-line voltages crosses178ABCAACBBCvab = 0vbcVabVabVbcVbcVcaVcaVcaVab VbcvcaReVabVabvabVbcVbcvbcVcaVcavca = 0 ReBACBCAvbc = 0vcavabRe vab = 0vcavbcReCBACABvca = 0vabvbcReVcaVabVbcvbc = 0vabvcaRe vuo = vDC− vca−12 vui = vca vli = vab in = ia iui = iDC − ic− ibal,uiuo = iDC− ibal,u iuo = iDC− ibal,uilo = iDC− ibal,l (ii)(i)(iii) (iv)(v) (vi) ili = iDC + ib− ibal,l il = −ibilo = iDC− ibal,lilo = iDC− ibal,l iu = ic il = −ia iu = ib il = −ia iu = ic il = −ib iu = ia il = −ic iu = ia il = −ic iu = ib vlo = vDC− vab−12iaibicABC vuo = vDC+ vca−12 vui = −vca vli = −vbc in = ic iui = iDC − ia− ibal,u ili = iDC + ib vlo = vDC+ vbc−12iaibicABC vuo = vDC− vab−12 vui = vab vli = vbc in = ib iui = iDC − ia− ibal,uiuo = iDC− ibal,u ili = iDC + ic− ibal,l vlo = vDC− vbc−12iaibicABC vuo = vDC+ vab−12 vui = −vab vli = −vca in = ia iui = iDC − ib− ibal,uiuo = iDC− ibal,u ili = iDC + ic− ibal,l vlo = vDC+ vca−12iaibicABC vuo = vDC− vbc−12 vui = vbc vli = vca in = ic iui = iDC − ib− ibal,uiuo = iDC− ibal,u ili = iDC + ia− ibal,l vlo = vDC− vca−12iaibicABC vuo = vDC+ vbc−12 vui = −vbc vli = −vab in = ib iui = iDC − ic− ibal,uiuo = iDC− ibal,u ili = iDC + ib− ibal,l vlo = vDC+ vab−12iaibicilo = iDC− ibal,lilo = iDC− ibal,lilo = iDC− ibal,lFig. 7.3. Six topological states of the MSC corresponding to the six intervals of operation forming acomplete electrical cycle. The bold lines indicate the paths of the currents. Each subfigure correspondsto its respective interval, as defined by the converter angles ωt ∈ (i)[−pi6, pi6]; (ii)[pi6, pi2); (iii)[pi2, 5pi6);(iv)[5pi6, 7pi6); (v)[7pi6, 3pi2); and (vi)[3pi2, 11pi6).zero at the same time that a DS transition occurs, according to Table 7.1. Hence, the DSs areonly operated at the instances of zero-voltage crossings of the line-to-line voltages, whichenables each of the Upper, Lower, and Midpoint DSs to experience zero-voltage-switching(ZVS) at each topology transition. Such functionality enables 1) the switching losses of theMSC’s DSs to be negligible, and 2) simpler design of the DS valves, as hard-switching of theseries-connected IGBT/diode modules and the associated EMI and synchronization issuesinherent to it are removed. It is noted that since the MSC and DAC both use DSs that operate179TABLE 7.2Currents of theMSC for Varying ωt.Topology Conv. Angle MSC Current DefinitionsIntervals ωt ∈ iu il in iuo iui ilo ili(i)[−pi6, pi6)ic ib ia iDC − ibal,u iDC − ic − ibal,u iDC − ibal,l iDC + ib − ibal,l(ii)[pi6, pi2)ia ib ic iDC − ibal,u iDC− ia− ibal,u iDC − ibal,l iDC + ib − ibal,l(iii)[pi2, 5pi6)ia ic ib iDC − ibal,u iDC− ia− ibal,u iDC − ibal,l iDC + ic − ibal,l(iv)[5pi6, 7pi6)ib ic ia iDC − ibal,u iDC − ib − ibal,u iDC − ibal,l iDC + ic − ibal,l(v)[7pi6, 3pi2)ib ia ic iDC − ibal,u iDC − ib − ibal,u iDC − ibal,l iDC + ia − ibal,l(vi)[3pi2, 11pi6)ic ia ib iDC − ibal,u iDC − ic − ibal,u iDC − ibal,l iDC + ia − ibal,lTABLE 7.3Stack Voltages of theMSC for Varying ωt.Topology Conv. Angle MSC Voltage DefinitionsIntervals ωt ∈ vuo vui vlo vli(i)[−pi6, pi6)12VDC − vca vca 12VDC − vab vab(ii)[pi6, pi2)12VDC + vca −vca 12VDC + vbc −vbc(iii)[pi2, 5pi6)12VDC − vab vab 12VDC − vbc vbc(iv)[5pi6, 7pi6)12VDC + vab −vab 12VDC + vca −vca(v)[7pi6, 3pi2)12VDC − vbc vbc 12VDC − vca vca(vi)[3pi2, 11pi6)12VDC + vbc −vbc 12VDC + vab −vabwith ZVS, the MSC can also employ the same IGBT/thyristor hybrid DSs that the DAC uses toimprove its DSs’ conduction losses.7.2.2 Inner StackVoltage DefinitionsSpanning the DC-side, the voltages of the Outer and Inner stacks sum to vDC at all times.For straightforward controllability, the voltages of the stacks can be described in terms of thephase-to-midpoint voltages with the injection of a quasi-triangular voltage that ensures thezero-level voltages of Fig. 7.2 (d). For a fundamental-frequency AC voltage amplitude of V1h,180the phase-to-midpoint voltage for the jth phase can be described asvj(t) = V1h sin(ωt+ φj)− vtri(t), (7.1)where φj ∈{0, −2pi3, 2pi3}are the three-phase balanced phase-shifts, and vtri is the quasi-triangular voltage ensuring vj is zero when the jth phase Midpoint DS is on. The quasi-triangular voltage is the same as that defined for the DAC in (5.3), and is equal to thefundamental-frequency AC voltage component of the jth-phase when the respective Mid-point DS is on. Hence, vtri is described piece-wise asvtri(t) = V1h sin(ωt− k 2pi3)ωt ∈ [−pi6 + k 2pi3 , pi6 + k 2pi3 ]V1h sin(ωt+ (1− k) 2pi3)ωt ∈ [pi6 + k 2pi3 , pi2 + k 2pi3 ] (7.2)where k ∈ {0, 1, 2}, such that vtri has peak values±12V1h.Therefore, the Inner stack voltages can be defined as the sum of the Upper/Lower DSswitching states, as given in Table 7.1, multiplied by the respective phase-to-midpoint voltages[defined in (7.1)], asvui(t) =∑j∈{a,b,c}Su,j · vj(t),vli(t) = −∑j∈{a,b,c}Sl,j · vj(t).(7.3)From Fig. 7.2 (c), the Inner stack voltages generate the unipolar voltages between 0 and 1.5V1h.Therefore, the Inner stacks are composed of unipolar SMs; herein, HBSMs are assumed.The voltage definitions of the Outer stacks depend on whether the midpoint is floating,i.e., whether the optional FMS of Fig. 7.1 is used; hence, their voltage definitions are presentedin the subsequent section.1817.2.3 Energy Balance and Outer StackVoltage DefinitionsBy using the optional DC-side PCs of Fig. 7.1, theMSC can achieve anyAC output operatingvoltage, i.e., of arbitrary V1h, within the limits and ratings of its SMs’ and DSs’ semiconductorsas well as the acceptable voltage deviation of the SMs’ capacitors. Moreover, when the optionalFMS is used, the MSC’s neutral-point can be clamped to the DC-side PCs’ midpoint; withoutthe optional FMS, the DC-side PCs’ midpoint is floating.7.2.3.1 Midpoint Clamped with Optional FMSWhen the optional FMS of Fig. 7.1 is used, the MSC has two options of operating modesavailable to it. In Option #1, the MSC’s Outer stacks carry only the DC-side current, iDC,and balancing currents from the optional DC-side PCs, while the Inner stacks carry the loadcurrents as well as balancing currents. In Option #2, the Outer stacks carry the load currentsas well as balancing currents, while the Inner stacks carry only the balancing currents and noload currents.With the optional FMS, the Upper Outer and Inner stacks collectively sum to half theDC-side, i.e., vPC,u; the Lower Outer and Inner stacks sum to vPC,l. Hence, the Outer stackvoltages are derived using the definition of the Inner stack voltages of (7.3) byvuo(t) = vPC,u − vui(t),vlo(t) = vPC,l − vli(t).(7.4)Since the Inner stacks generate voltages within [0, 1.5V 1h], the Outer stack voltages arebounded by the peak positive voltage of {vPC,u, vPC,l} ≈ 12vDC and the peak negative voltageof ({vPC,u, vPC,l} − 1.5V1h); hence, the Outer stacks require the bipolar voltage generationenabled by FBSMs.To find the optimal balancing currents to synthesize from the optional DC-side PCs, it isconducive to derive expressions for the harmonic content within the stack voltages. For theUpper Outer stack, the nth odd and even harmonics, i.e., bn, where n ∈ {3, 9, 15, . . . } and an,182where n ∈ {6, 12, 18, . . . }, are respectively calculated using the Fourier series expansion of vuoon the interval ωt ∈(pi6, 5pi6)by the expressionsbn =3ωpi∫ 5pi6ωpi6ωvuo(t) sin (nωt) dt (7.5)an =3ωpi∫ 5pi6ωpi6ωvuo(t) cos (nωt) dt (7.6)The amplitude of the nth odd harmonic, bn, is given by the Fourier series expansion of theUpper Outer stack voltage asbn =3√3V1h(2 cos(n 2pi3)+ 1)sin(npi6)pi(n2 − 1) (7.7)where the first-, third-, ninth-, and fifteenth-order harmonics respectively have amplitudes ofb1 = 0,b3 =9√38piV1h ≈ 0.62V1h,b9 = −9√380piV1h ≈ −0.062V1h,b15 =9√3224piV1h ≈ 0.022V1h.(7.8)The nth even harmonic, an, has amplitudean =3√3V1h(2 cos(npi3)− 1)2 cos(npi6 )pi(n2 − 1) (7.9)183such that the sixth-, twelfth-, and eighteenth-order harmonics have amplitudesa6 = −3√335piV1h ≈ −0.047V1h,a12 =3√3143piV1h ≈ 0.012V1h,a18 = − 3√3323piV1h ≈ −0.005V1h.(7.10)As the harmonic order increases, their amplitudes reduce further. Hence, the largest odd-order harmonic of the stack voltages is b3 =9√38piV1h and the largest even-order harmonic isa6 = −3√335piV1h.For completeness, the DC component of Upper Stack 1, a0, is given bya0 =3ω2pi∫ 5pi6ωpi6ωvuo(t) dt (7.11)a0 =3√32pi(√3pi9vDC − V1h), (7.12)where it is noted that a0 = 0 results in V1h =√3pi9vDC.7.2.3.1.1 Stack Energy Balancing — Option #1As stated, the MSC’s stacks are naturally balanced at the AC voltage that results in theOuter stacks having no DC voltage component, i.e., when the Outer stacks’ mean voltage iszero. However, by using the optional DC-side PCs both with and without a floating midpoint,the MSC can generate any AC voltage amplitude.Flowing through both the Upper stacks, the balancing current for the Upper Outer stack,i.e.,−ibal,u of Fig. 7.1, is the same as that superimposed onto the current of the Upper Innerstack; hence ibal,u is calculated for only the Upper Outer stack.From (7.8), it is evident that the voltage of the Upper Outer stack, vuo, has a dominantthird-order harmonic voltage component due to its 2pi3periodicity. Hence, for maximumenergy exchange between the Upper stacks and the Upper PC, the balancing current also has184third-order periodicity and takes the form ofibal,u(t, ϕ) = I3h(ϕ) sin(3ωt). (7.13)Similarly, since the Upper and Lower stacks are phase-shifted by pi3, the Lower balancingcurrent is represented asibal,l(t, ϕ) = −I3h(ϕ) sin(3ωt). (7.14)The value of I3h is determined by setting the cumulative energy deviation of the UpperOuter stack,∆Euo, to zero. For varying power factor angles, ϕ,∆Euo is given as∆Euo(t, ϕ) =∫ t0vuo(τ)(iDC(ϕ)− ibal,u(τ, ϕ)) dτ . (7.15)Calculating (7.15) over a 2pi3cycle yields the net energy deviation, as∆Euo(2pi3ω, ϕ)=13·{iDC(ϕ)ω(pivDC − 3√3V1h)− I3h(ϕ)8ω9√3V1h}(7.16)For∆Euo = 0, (7.16) results in the balancing current amplitude ofI3h(ϕ) =83iDC(ϕ)(√3pi9vDCV1h− 1)(7.17)From (7.17), the value of I3h is shown to increase as the operating voltage deviates from theoperating voltage ofV bal1h =√3pi9vDC, (7.18)which is the AC voltage amplitude resulting in natural balance of the Outer and Inner stackSMs. Equation (7.18) also suggests that if the MSC is desired to operate at the fixed voltage of185V1h = Vbal1h , no DC-side PCs are necessary. This is because at (7.18), the Outer stack voltageshave no DC voltage component, as in (7.12), such that their interaction with the DC-sidecurrent does not result in a net energy deviation.When the midpoint is clamped with the FMS, since the Upper and Lower balancingcurrents of (7.13) and (7.14) are in anti-phase, their effect on the voltage ripples of the Upperand Lower PCs completely cancels, such that the MSC experiences minimal DC-side pole-to-pole voltage ripple even with large PC voltage ripples. Hence, the MSC’s DC-side current alsohas minimal ripple in this operating mode.For a reduction in the sizing of the DC-side PCs, a combination of third-order and ninth-order harmonics in the balancing current can reduce the overall voltage ripple of the DC-sidePCs, and hence their capacitor sizing. Recall that a third-order harmonic voltage with amplitude16V1h can be injected into each of the phase-to-neutral AC-side voltages of a three-phase systemto reduce their peak values from V1h to 0.866V1h [31]. A similar method can be adopted here.With a sinusoidal balancing current containing third- and ninth-order harmonics, i.e.,ibal,u(t, ϕ) = I3h(ϕ) sin(3ωt) + I9h(ϕ) sin(9ωt), (7.19)the energy deviation of the Upper DC-side PC,∆EPC,u, is given by∆EPC,u(t, ϕ) =∫ t012vDC(I3h(ϕ) sin(3ωτ) + I9h(ϕ) sin(9ωτ) dτ)∆EPC,u(t, ϕ) = −vDC2ω(13I3h(ϕ) cos (3ωt) +19I9h(ϕ) cos (9ωt))+ C, (7.20)where C is a constant to ensure∆Ec,u(0, ϕ) = 0. The minimum energy deviation of the UpperPC follows from (7.20) under the condition that13I3h = −619I9h⇒ I9h = −12I3h, (7.21)186which follows from the condition that the ninth-order current component is one-sixth that ofthe third-order current component.Hence, for the minimum DC-side PC energy deviation — and likewise, their minimumphysical sizing — the balancing current is defined asibal,u(t, ϕ) = I3h(ϕ)(sin(3ωt)− 12sin(9ωt)), (7.22)where I3h is determined by setting the energy deviation of the Upper Outer stack with theinjection of ibal,u to zero:∆Euo(ϕ) =∫ 5pi6ωpi6ωvuo(τ)(iDC(ϕ)− ibal,u(τ, ϕ)) dτ = 0 (7.23)⇒ I3h(ϕ) = 16063 iDC(ϕ)(√3pi9vDCV1h− 1). (7.24)The balancing current amplitude of (7.24) ensures the minimum capacitor voltage ripplefor the DC-side PCs, but it is not the minimum RMS current and hence may contribute tohigher losses.7.2.3.1.2 Stack Energy Balancing — Option #2TheMSC can adopt a mode of operation like the DAC’s. That is, rather than the UpperOuter and LowerOuter stacks carrying the DC current at all times, they can be used to carrythe respective phase currents, as in Table 5.1, (5.4), and (5.5).In this operating mode, i.e., Option #2, the only currents flowing through the Upper Innerand Lower Inner stacks serve to balance the Upper and Lower Outer stacks and PCs if andonly if the operating voltage drifts away from the DAC’s optimal operating voltage, i.e., that of(5.12): V1h =√3piVDC. In this mode, the DC-side PCs contribute to the load current instead ofsimply serving to ensure the balance of the stacks’ FBSM capacitors. Hence, this operatingmode enables the stacks to require less overall energy storage by shifting the energy storage187requirement to the DC-side PCs, but removes the ripple-free DC-side current and voltage ofthe Option #1 operating mode. It is noted for the Option #2 operating mode that the balancinginductance, Lbal of Fig. 7.1, should be placed in series with the Inner stacks instead of theOuter stacks. The current to be synthesized through the Upper Inner and Lower Inner stackshas a DC and third-order harmonic component, where the DC component ensures balance ofthe DC-side PCs and the third-order harmonic component keeps the stacks balanced.From (5.11), the real power and operating voltage determine the energy deviation of theUpper or Lower DC-side PCs over a 2pi3interval. Hence, for the, e.g., Upper DC-side PC tostay balanced cycle-to-cycle, a DC current between the PC and the Upper Outer stack andUpper Inner stacks is synthesized. Assuming the current flows upward through the PC, thevalue of the DC current to be synthesized is equal to the mean value of iui and is derived using(5.11) asiui(ϕ) = −∆EPC,u(ϕ)(2pi3ωvDC2)−1,⇒ iui(ϕ) = iDC(ϕ)(1−√3pivDCV1h), (7.25)where∆EPC,u is from (5.11).The amplitude of the third-order harmonic current to balance the UpperOuter and UpperInner stacks can be determined by integrating the power of either of the stacks. The derivationof the third-order harmonic amplitude using the Upper Inner stack is simpler since its currentfor this mode of operation is equal to only the balancing DC and third-order harmonic currents.Therefore, the energy deviation of the Upper Inner stack is defined as∆Eui(ϕ) =∫ 5pi6ωpi6ωvui(τ)(iui(ϕ)− ibal,u(τ, ϕ))dτ (7.26)⇒ ∆Eui(ϕ) = 1ω pi(iDC(ϕ)(√3piV1h − 3vDC)+ 3√38piV1hI3h), (7.27)188where ibal,u is defined in (7.13). From (7.27), it follows from solving∆Eui = 0 thatI3h(ϕ) =83iDC(ϕ)(√3pivDCV1h− 1). (7.28)7.2.3.2 Midpoint FloatingTheMSC can also operate with a single balancing current, i.e., ibal,u = ibal,l, that simultane-ously flows through all four stacks and the two DC-side PCs. As stated, the Upper and LowerOuter stacks generate voltages are mutually pi3out-of-phase; the same is true for the Upperand Lower Inner stacks. Hence, the 6n harmonics contained within the Upper and LowerOuter stacks are equal; similarly, the 6n harmonics contained within the Upper and LowerInner stacks are also equal, but in anti-phase with those of the Outer stacks. This enablesthe same sixth-order harmonic balancing current to balance all four of the Upper and Lowerstacks.It is noted that if the midpoint is floating, the midpoint voltage floats such that there is nolonger the requirement for the DC-side pole-to-midpoint voltages to equal±12vDC. Instead, theOuter stacks’ voltages can be derived based on the assumption that the pole-to-pole DC-sidevoltage equals vDC. Hence, the Upper and Lower Outer stack voltages can be expressed asvuo,r = vlo,r =12(vDC − (vui + vli)), (7.29)where the subscript r, standing for “reduced,” differentiates the reduced Outer stack voltagesfrom those defined in (7.4).With (7.29), the Upper and Lower Outer stack voltages are equal and contain only 6nharmonics, while the definitions of vui and vli remain determined by (7.3). The voltages of theUpper and Lower Outer stacks both with and without the floating midpoint are illustratedin Fig. 7.4. From Fig. 7.4, deriving vuo and vlo with (7.29) enables a significant reductionin the Outer stacks’ voltage ratings. From their peak positive value for the case with the189(a)vDC-vDC0vDC12vDC12-Outerstack voltages vuo,rvlo,rωt (rad)5pi67pi63pi211pi62pi6pi- 6pi(i) (ii) (iii) (iv) (v) (vi)(b)vDC-vDC0vDC12vuovlovDC12-Outerstack voltages6pi- 6pi0Fig. 7.4. Outer stack voltages of theMSC for (a) floating midpoint; and (b) midpoint clamped throughthe FMS.optional FMS of vˆu,lo = 12vDC, (7.29) enables a reduction to vˆu,r,lo = 12vDC − 34V1h; fromthe peak negative value of vˇu,lo = 12vDC − 1.5V1h, (7.29) enables a reduction to vˇu,r,lo =12vDC −√32V1h. Hence, at V1h = Vbal1h , the positive and negative peaks of the Outer stackvoltages are reduced by, respectively, 90.7% and 94.1%. Therefore, by using (7.29) to define theOuter stack voltages, their numbers of FBSMs can be reduced by approximately 90%, whichhas significant implications regarding the MSC’s size and efficiency.However, the sixth-order harmonic voltage present in the stacks has a significantly loweramplitude than that of the third-order harmonic in the previous case, which limits the amountof exchangeable energy between the stacks and PCs. Hence, while no balancing current isrequired when V1h = Vbal1h , as in the previous case, the magnitude of the sixth-order harmonicbalancing current is higher for the same voltage deviation from V1h = Vbal1h . The sixth-orderbalancing current is defined asibal,u(t, ϕ) = ibal,l(t, ϕ) = I6h(ϕ) sin(6 ·(ωt+pi4)). (7.30)190which is in-phase with the dominant sixth-order harmonic of the stack voltages. Reusing (7.15)with the substitution of ibal,u(τ, ϕ) defined in (7.30) and setting the resulting energy deviationover a 2pi3cycle to zero, the value of I6h is found asI6h(ϕ) = 35iDC(ϕ)(√3pi9vDCV1h− 1)(7.31)which is noted to have an amplitude 35/(8/3) = 13.125 times greater than that of I3h.With (7.31), balance of the stacks is guaranteed with the single pole-to-pole DC-side PC,but the amplitude of the balancing current, and therefore the semiconductor conduction losses,is increased compared to the case with the optional FMS. However, for voltages near V1h=Vbal1h ,the balancing current and losses are small.7.2.4 Control and Balancing Current SynthesisUsing the stack voltage definitions of (7.3) with (7.4) or (7.29), the MSC can use a genericouter-loop PQ controller with an inner-loop dq current controller to generate the outputvoltage amplitude, V1h, and converter angle, ωt, for independent PQ control. However, theMSC needs an additional control layer to synthesize the balancing currents that ensure SMcapacitor energy balance.It is noted that in the Option #1mode of operation, the MSC’s load currents are suppliedprincipally by the Inner stacks due to their negligible impedance compared to the path contain-ing the Outer stacks and PCs due to the presence of the Lbal inductances. Hence, to preservethe line-to-line voltage fidelity, the Outer stacks are used to synthesize the sinusoidal balancingcurrents that flow through the Outer and Inner stacks. Hence, any superimposed voltages thatthe Outer stacks synthesize for balancing current generation are not reflected to the AC-side.In this thesis, PR controllers are used to generate such superimposed voltages.The reference current amplitude, i.e., I3h, can be calculated analytically using (7.17), orit can be generated by PI controllers that ensure SM capacitor voltage balance. Herein, thelatter is used to remove any steady-state error within the SM capacitor voltages, which arises191P Q vabcsiabcsωtPQ controllerPower controller Stack voltage reference generation andDS signal generation V1hBalancing current amplitude generation(a) (b)(c)ωt TABLE 10.1 Sk,abcV1h vui,vliSk,abc (10.1)-(10.3),(10.4), (10.29)vuo,vlo+vc,uovc,uivc,lovc,li+I3h,uPII3h,lPIBalancing current generation (d)(f)ibal,uibal,lωtvbal,uvbal,l++ PRsinsin PRI3h,uI3h,l3Submodule switching signal generation (e)LS-PWM or NLM & SM voltagebalancing algorithmSuoSloSuiSlivc,kmikmvuo+vbal,uvlo+vbal,lvuivliMSCvc,km ikm ibal,uliabctPCCvabcs+VDCDC cable+vDCSuo, Slo, Sui, SliSk,abck∈{u,m,l}iabcs 3vPC,u,vPC,lFig. 7.5. Control flow diagram for the MSC using Option #1 control with the midpoint connectedthrough the FMS.from the semiconductors’ on-state losses and snubber circuits. It is noted that the control flowdiagram assumes the Option #1mode of operation, and not the Option #2mode of operation.Fig. 7.5 presents the overall control-flow diagram of the MSC, wherein the figure of theoverall test system is provided in Fig. 7.5 (f). In Fig. 7.5 (a), a generic PQ controller thattakes as inputs the desired reference real and reactive powers, P ? andQ?, and the grid-sidevoltage and current, vabcs and iabcs, is presented, where boldfaced variables denote vectorquantities. The outputs of the PQ controller are the reference operating voltage amplitude, V1h,and the converter angle, ωt. Fig. 7.5 (b) presents the stack reference voltage generation andswitching signal generation for the DSs. According to Table 7.1, the DS switching signals needonly the converter angle, ωt, to generate the vector containing the nine signals, Sk,abc, wherek ∈ {u,m, l}.The stack voltage references are determined with Sk,abc, V1h, vPC,u, vPC,l, and ωtaccording to (7.3), and (7.4).In Fig. 7.5 (c), the PI controllers that determine the amplitudes of the balancing currents,192ibal,u and ibal,l, are shown for both operatingmodes to generate the amplitudes of the third-orderor sixth-order balancing currents. Assuming that the Outer and Inner stacks use SMs ofequal voltage rating, the instantaneous mean values of the SM capacitor voltages, i.e., vc,km(k ∈ {u, l},m ∈ {o, i}) are compared. For operation with the optional FMS, two balancingcurrent amplitudes are produced, I3h,u and I3h,l, which are produced by comparison of theUpper and Lower stacks’ capacitor voltages, respectively.Once I3h,u and I3h,l are produced, they are multiplied by third-order sine waves, as inFig. 7.5 (d), which are then compared to the measured PC balancing current, ibal,u and ibal,l,to produce error signals. These error signals are subsequently fed into the PR controllers ofFig. 7.5 (d) to generate the signals vbal,u and vbal,l, which are superimposed onto the Outerstack voltage references.Fig. 7.5 (e) shows the stack reference voltages, the stack currents, and the vector containingthe stacks’ capacitor voltages being fed into the voltage balancing algorithm that uses eithernearest-level modulation (NLM) or level-shifted pulse-width-modulation (LS-PWM) to gener-ate the discrete switching signals for the stacks’ SMs [13]. The output of this block are the fourvectors, Skm, which contain the individual SM switching signals.It is noted that for the other two operating modes, i.e., Option #2 and the mode with thefloating midpoint, Fig. 7.5 (a), (b), and (f) hold. However, for the mode with the floatingmidpoint and reduced Outer stack voltages, Fig. 7.5 (c) is modified to provide the singlebalancing current amplitude, I6h, which is determined by comparing the sum of the meancapacitor voltages of the Outer stacks with that of the Inner stacks and feeding the result into aPI controller; forOption #2, an additional PI controller produces the DC offset of the balancingcurrent to correct the DC-side PC voltage difference, i.e., ∆vPC. For Option #2, Fig. 7.5 (d)holds, but the resulting vbal,u and vbal,l are summed with the resulting∆vPC from Fig. 7.5 (c).For the mode with the floating midpoint, Fig. 7.5 (d) is modified by adding pi4to ωt [as in(7.30)] while ibal,u and ibal,l are equal such that the same balancing voltage, vbal,u = vbal,l, issuperimposed onto both the Upper and Lower Outer stack voltages. Lastly, Fig. 7.5 (e) holds193for the mode with the floating midpoint; but for the Option #2 operating mode, the balancingvoltages are superimposed onto the Inner stack voltages instead of the Outer stack voltages.7.2.5 DC-Side Fault-Blocking and Ride-ThroughWith appropriately rated Outer stacks, the MSC can both block and ride through DC-sidefaults. By using the reverse-blocking capability of its Outer stacks, the MSC can apply reversevoltages against the AC- and DC-grids to quickly suppress the flow of AC- and DC-side faultcurrents. For such capability, the Upper and Lower Outer stacks should be together rated forthe peak line-to-line voltage, i.e.,√3V1h, such that each of the Outer stacks is rated for√32V1h.For the rated voltage of V1h =√3pi9vDC, the Outer stacks should be rated for approximately0.52vDC. Since 0.52vDC is close to the normal-operation voltage rating of the Outer stacks of0.5vDC when the optional FMS is used, DC-fault ride-through capability favors the mode ofoperation with the optional FMS.A salient feature of the MSC is its ability to block its Outer stacks while continuingoperation of the Inner stacks. That is, during DC-side faults, the Outer stacks can be blockedto effectively decouple the AC- and DC-sides while the Inner stacks can continue to supportthe grid by supplying reactive power. Hence, the MSC has DC-fault ride-through capability.However, since the Inner stacks generate voltages within [0, 1.5V1h], the FMS must be in theopened state if STATCOM operation during DC-side faults is desired. By opening the FMS, theDC-side PCs are disconnected from the MSC’s midpoint, such that the Outer stacks need tocollectively block only the sum of the Inner stack voltages, and not their voltages individually.Without opening the FMS, the Outer stacks would need to block the entire 1.5V1h generatedindividually by the Inner stacks. But by opening the FMSs, the Outer stacks each need toblock only half the Inner stacks’ voltage sum, i.e.,√32V1h.7.3 Performance EvaluationIn this section, HVDC-scale simulation studies of the MSC’s normal and DC-fault opera-tions are presented both with and without the optional FMS of Fig. 7.1, where it is noted that194DC fault blocking is only enabled in the case of using the optional FMS due to the Outer stacks’higher voltage rating. For the simulation studies, the MATLAB/Simulink 2022a Simscape Spe-cialized Power Systems toolbox is used tomodel theMSC.TheDC-side is fed by a 600 kV voltagesource throughDC lines with 60mH of inductance. For the case studies, theMSC is assumed tooperate up to V1h = 400 kV, such that the Inner stacks are each rated for 1.5V1h = 600 kV andthe Outer stacks with the optional FMS are rated for√32V1h ≈ 345 kV for DC fault blocking.Without the optional FMS, the Outer stacks are rated for∣∣∣∣12vDC −√32V1h∣∣∣∣ ≈ 47.5 kV as givenin Section 7.2.3.2. The studies assume that the IGBT/diode module composing the DSs andSMs is the 4.5 kVWestcode T1800GB45A [90], which is assumed to operate with the de-ratedvoltage of 2.5 kV. Hence, the Inner stacks each need 240 HBSMs while the Outer stacks inthe two operating modes require either 140 FBSMs or 19 FBSMs, respectively. The simulationparameters are presented in Table 7.4. In addition to the HVDC-scale simulation studies, ahardware verification is presented to further validate the MSC’s operating principle.7.3.1 Normal Operation with Midpoint Clamped through FMS7.3.1.1 Operating Mode — Option #1First, the MSC’s normal operation with the optional FMS is presented in Fig. 7.6. The realpower and operating voltage are varied over a 2.5 s simulation. During positive and negative realpower flow, the operating voltage is varied by±7.5% to keep the balancing current amplitudeconstant, which proves the validity of the balancing current of (7.13). At t = 0 s, the MSC iscommanded to operate as an inverter with P = 1GW and V1h =√3pi9vDC.Then, at t = 0.4 s,the operating voltage is increased to V1h = 1.075√3pi9vDC; at t = 0.8 s, the operating voltage isreduced to V1h = 0.925√3pi9vDC.TheMSC is then commanded to operate as a rectifier withP = −1GW at t = 1.25 s while the operating voltage is maintained at V1h = 0.925√3pi9vDC.Then, at t = 1.7 s and t = 2.1 s, respectively, the operating voltage is changed to V1h =√3pi9vDCand V1h = 1.075√3pi9vDC.Figs. 7.6 (a) and (b) respectively show the real and reactive powers measured at the MSC-195TABLE 7.4Simulation ParametersSimulation parametersOperating modeMidpoint Clampedwith FMSMidpointFloatingMaximum power rating (MVA) 1096 1096Maximum P (MW) 1000 1000DC-side voltage (kV) 600 600DC-side PC capacitances, Cu and Cl (µF)Option #1 Option #215 50100HBSM/FBSM rated voltages (kV) 2.5 2.5No. of FBSMs in Upper/LowerOuter stacks140 19No. of HBSMs in Upper/LowerOuter stacks240 240Upper/Lower Outerstack FBSM capacitance, CFBSM (mF)7.29 1.16Upper/Lower Innerstack HBSM capacitance, CHBSM (mF)2.08 2.08Fault resistance,Rfault (Ω) 10 10DC-side inductance, LDC (mH) 25 25DC cable length (km) 100 100Balancing inductance, Lbal (mH) 5 5Transformer leakage impedance (pu) 0.001+ j0.18 0.001+ j0.18Transformer winding ratio (∆/Y) 440 kV/400 kV 440 kV/400 kVside of the interfacing transformer and the DC-side current, where the DC-side current is seento have low ripple. Fig. 7.6 (c) shows the pole-to-pole DC-side voltage and the Upper/Lowerpole capacitor voltages, which show that despite the capacitor voltages’ 8% ripple, the pole-to-pole DC-side voltage has a voltage ripple of less than 1%; this is due to the pole capacitors’voltage ripples canceling. Fig. 7.6 (d) shows the summation of both the Upper Outer andInner stacks’ SM capacitors, where it is seen that their total voltage ripple is maintained tounder±10% of their set-point values, which are respectively set at 350 kV and 600 kV. Figs. 7.6(e) and (f) respectively show the Upper Outer and Inner stack currents, where it is noted thatwhen operating at V bal1h =√3pi9vDC, the Upper Outer stack carries only the DC-side currentwith minimal ripple, as seen in the subfigure of Fig. 7.6 (e). Meanwhile, the Upper Innerstack carries the DC-side current less the current entering the DSs, iu. Fig. 7.6 (g) shows the196Upper Outer and Inner stack voltages, while Fig. 7.6 (h) presents the converter-side phase-ato phase-b voltage and the phase-a to midpoint voltage, which are seen to overlap when theUpper or Lower stack generate± vab. Fig. 7.6 (i) shows the voltage across the Upper phase-aDS voltage, which is noted to block only positive voltages of peak amplitude√3V1h. Fig. 7.6 (j)0-0.50.51.02.0-2.06005254503753002253004005006007001.0-1.00-1.00.0 0.5 1.0 1.5 2.0 2.5Time (s)iDC-2.5-1.251.252.50-2.5-1.251.252.501.71.6751.651.00.60.2-0.2iuiP Q(a)(b)(c)330300270vPC,u vPC,l380320340360660580620(d)(e)(f)Σvc,uo Σvc,ui601600599vDCP (GW) & Q (GVAR)i DC (kA)i uo (kA)i ui (kA)v DC, v PC,u, vPC,l (kV)Σvc,k m (kV) ss s-1.5-1.7-2.1iuo197-300-1500150300450600-600-30003006006004503001502.02.72.62.62.52.42.52.42.31.51.00.50.000.3 0.31 0.32 0.33 0.34Time (s)vuo vuivab vanvSu,aiSu,aiu iSu,b iSu,c(g)(j)(k)(l)(h)(i)v ab & van(kV)v c,uo (kV)ssv c,ui (kV)i u (kA)v uo & vui (kV)v Su,a (kV)Fig. 7.6. MSC normal operation with optional FMS in Option #1mode. (a) Real and reactive powers;(b) DC-side current; (c) DC-side pole-to-pole voltage and Upper/Lower pole-to-midpoint voltages; (d)summation of Upper Outer FBSM and Inner HBSM capacitor voltages (k ∈ {u, l},m ∈ {o, i}); (e)Upper Outer stack current; (f) Upper Inner stack current; (g) Upper Outer and Inner stack voltages;(h) phase-a to -b line-to-line voltage and phase-a to midpoint voltage; (i) voltage across Upper phase-aDS; (j) Upper DS currents; (k) twelve FBSM capacitor voltages of the Upper Outer stack; (l) twelveHBSM capacitor voltages of the Upper Inner stack.198presents the currents flowing through the Upper DSs as well as the total Upper DS current, iu.Lastly, Figs. 7.6 (k) and (l) show twelve of the SM capacitor voltages of the Upper Outer andInner stack, respectively, which show that the capacitor voltages stay well-balanced to theirset-point of 2.5 kV.7.3.1.2 Operating Mode — Option #2Next, the MSC with the Option #2 operating mode is studied, where. Fig. 7.7 presents thesteady-state and transient behaviours of the MSC in this mode. It is noted that due to loadcurrent flowing through the DC-side PCs, the capacitances of the PCs are increased from 15 µF,as in the Option #1mode, to 50 µF, as shown in Table 7.4. The same tests are performed as inSection 7.3.1.1, where the output voltage is varied by±7.5% while the MSC is operated as firstan inverter and then a rectifier. The same key waveforms of Fig. 7.6 are presented for Option#2 in Fig. 7.7.In Figs. 7.7 (a), the overall shape of the real and reactive powers matches that of Fig. 7.6(a). In Fig. 7.7 (b), the DC-side current is seen to have significantly higher ripple than theprevious case, since the currents of the PCs do not cancel in the Option #2 operating mode,thereby causing a significant DC-side voltage ripple, as seen in Fig. 7.7 (c). Fig. 7.7 (c) alsoshows the individual PC voltages, wherein even with over three times the capacitance, the PCvoltages show significant ripple. In Fig. 7.7 (d), the summation of the SM capacitor voltagesof the Upper Outer and Inner stacks are presented, which show significantly less ripple thanthose presented in Fig. 7.6 (d).Figs. 7.7 (e) and (f) show the Upper Outer and Inner stack currents, where it is noted thatthe Outer stack current shows a higher peak value than the previous case due to it carryingthe load current. However, the Inner stack’s current is reduced compared to the previous casesince it only carries a balancing DC current and the third-order harmonic current. It is notedthat the Inner stack current reduces to almost zero when the operating voltage is reduced toV1h = 0.925√3pi9vDC ≈ 0.59vDC since this voltage is very close to the DAC’s naturally-balanced199operating voltage of V1h =√3pivDC, at which the Inner stacks do not synthesize balancingcurrents.Figs. 7.7 (g)–(l) present waveforms that very closely match those of Figs. 7.6 (g)–(l). IniDCiuoiuiP Q(b)(d)(e)(f)Σvc,uo Σvc,ui6505506006255752.01.61.2320345370(a)610600580590vDC330300270vDC,u vDC,l0.60.30.0-0.30-0.50.51.02.0-2.06005254503753003004005006007001.0-1.00-1.00.0 0.5 1.0 1.5 2.0 2.5Time (s)-2.5-1.251.252.50-2.5-1.251.252.50P (GW) & Q (GVAR)i DC (kA)i uo (kA)i ui (kA)v DC (kV)Σvc,k m (kV) ss s(c)200vSu,avuo vuivab vaniSu,aiu iSu,b iSu,c-300-1500150300450600-600-30003006006004503001502.02.72.62.62.52.42.52.42.31.51.00.50.000.3 0.31 0.32 0.33 0.34Time (s)(i)v ab & van(kV)v c,uo (kV)ssv c,ui (kV)i u (kA)v uo & vui (kV)v Su,a (kV)(l)(k)(j)(h)(g)Fig. 7.7. MSC normal operation with optional FMS in Option #2. (a) Real and reactive powers; (b)DC-side current; (c) DC-side pole-to-pole voltage and Upper/Lower pole-to-midpoint voltages; (d)summation of Upper Outer FBSM and Inner HBSM capacitor voltages (k ∈ {u, l},m ∈ {o, i}); (e)Upper Outer stack current; (f) Upper Inner stack current; (g) Upper Outer and Inner stack voltages;(h) phase-a to -b line-to-line voltage and phase-a to midpoint voltage; (i) voltage across Upper phase-aDS; (j) Upper DS currents; (k) twelve FBSM capacitor voltages of the Upper Outer stack; (l) twelveHBSM capacitor voltages of the Upper Inner stack.201Figs. 7.7 (k) and (l), the SM capacitor voltage ripples are seen to be slightly smaller than theprevious case and remain well-balanced to their set-points.0-0.50.51.02.0-2.062060058056054052001002003004005006007001.0-1.00-1.00.0 0.5 1.0 1.5 2.0 2.5Time (s)-2.5-1.251.252.50-2.5-1.251.252.50iuoiui(b)(d)Σvc,uo Σvc,ui1.00.60.2-0.2620580600504547.5610605600590595vDCP Q(a)iDC(c)1.71.6751.65(e)(f)P (GW) & Q (GVAR)i DC (kA)i uo (kA)i ui (kA)v DC (kV)Σvc,k m (kV) ss s-1.5-1.7-1.9202-300-1500150300450600-600-30003006006004503001502.02.62.62.72.52.32.42.52.41.51.00.50.000.3 0.31 0.32 0.33 0.34Time (s)vSu,aiSu,aiu iSu,b iSu,c(j)(g)vab vanvuo vui(h)(i)(k)(l)v ab & van(kV)v c,uo (kV)ssv c,ui (kV)i u (kA)v uo & vui (kV)v Su,a (kV)Fig. 7.8. Normal operation without optional FMS. (a) Real and reactive powers; (b) DC-side current;(c) DC-side pole-to-pole voltage and Upper/Lower pole-to-midpoint voltages; (d) summation of UpperOuter FBSM and Inner HBSM capacitor voltages (k ∈ {u, l}, m ∈ {o, i}); (e) Upper Outer stackcurrent; (f) Upper Inner stack current; (g) Upper Outer and Inner stack voltages; (h) phase-a to -bline-to-line voltage and phase-a to midpoint voltage; (i) voltage across Upper phase-aDS; (j) UpperDS currents; (k) twelve FBSM capacitor voltages of the Upper Outer stack; (l) twelve HBSM capacitorvoltages of the Upper Inner stack.2037.3.2 Normal Operation with Floating MidpointNext, the MSC’s operation without the optional FMS is presented, as in Fig. 7.8. In thisscenario, the operating voltage is restricted to a deviation from V bal1h =√3pi9vDC of7.513.125≈0.57%, which keeps the amplitude of the sixth-order harmonic balancing current equal tothat of the third-order harmonic balancing current of the previous scenario, as suggested in(13). The same waveforms as the previous case are shown. Fig. 7.8 (a) shows the real andreactive powers, where it is noted that the reactive power shows a smaller deviation from zerothan the previous case due to the smaller operating voltage range. Figs. 7.8 (b) and (c) showthe DC-side current and voltage, respectively, where it is noted that the DC-side voltage hasa significantly larger voltage ripple than the previous scenario since the ripple of the Upperand Lower pole capacitors due to the balancing current do not cancel. Fig. 7.8 (d) shows thesummation of the SM capacitor voltages of the Upper Outer and Inner stacks, wherein it isnoted that theOuter stack capacitor voltage summations are balanced around their set-point of47.5 kV while the Inner stack capacitor voltage summations keep balanced to 600 kV. Figs. 7.8(e) and (f) show the Upper Outer and Inner stack currents, respectively, where it is notedthat when V bal1h =√3pi9vDC, the Upper Outer stack current has very low ripple. Fig. 7.8 (g)shows the Upper Outer and Inner stack voltages, where it is seen that the Upper Inner stackvoltage matches that of Fig. 7.6 (g), but the Upper Outer stack voltage takes the reduced shapeof Fig. 7.4. Figs. 7.8 (h)–(j) respectively present the output voltages, the Upper phase-a DSvoltage, and the DS currents; their shapes match those presented in Figs. 7.6 (h)–(j). Lastly,in Figs. 7.8 (k) and (l), twelve SM capacitor voltages of each of the Upper Outer and Innerstacks, respectively, are presented, where the voltages are seen to remain well-balanced to theirset-point value of 2.5 kV.7.3.3 DC-Fault OperationLastly, the MSC’s operation throughout a DC-side fault is presented. Prior to the fault, theMSC is assumed to transmit the real and reactive powers of P = 1GW andQ = 250MVAR,204respectively, until the fault occurs at t = 0.5 s. The DC fault is detected once the DC-sidevoltage drops to 50% of its nominal value, at which all the IGBT/diode modules of the DSsand SMs are opened, thereby placing the stacks into the blocking mode. Once blocked, thecurrent flowing through the FMS is quickly brought to zero, enabling the FMS to open underzero voltage and zero current. Once the FMS opens, the IGBT/diode modules of the Innerstacks and DSs resume operation to provide Q = 250MVAR of reactive power during theDC fault. At t = 0.75 s, the fault is cleared such that the DC-side voltage is ramped up to itsnominal value of 600 kV; 200ms later, the Outer stacks are de-blocked and normal operationis resumed.The MSC’s response to the DC-side fault is presented in Fig. 7.9. Fig. 7.9 (a) shows thatupon detection of the fault, the real and reactive powers are both quickly brought to zero.Fig. 7.9 (b) shows the DC-side current during the fault, wherein LC resonance causes a highdegree of oscillation that is not reflected to the MSC’s output. In Fig. 7.9 (c), the DC-sidevoltage displays similar oscillation as the voltage across the pole capacitors oscillates with LCresonance but decays due to the fault resistance, Rfault, in parallel with the DC-side inductor.Fig. 7.9 (d) presents the summation of the Outer and Inner stacks’ SM capacitor voltages,which shows that the overall capacitor voltages of the stacks do not exceed a 10% deviationfrom their set-points. Figs. 7.9 (e) and (f) show the Upper Outer and Inner stack currents,respectively, which are noted to never exceed their pre-fault value.In Fig. 7.9 (g), the voltages generated by the Upper Outer and Inner stacks are presentedduring the fault instance, where it is noted that once the Outer stacks are placed into theblocked state, their voltages apply negative DC voltages to counteract the Inner stacks’ positivevoltage generation. In Fig. 7.9 (h), both the current and the voltage of the Optional FMS arepresented, wherein it is noted that the FMS current, iFMS quickly decays to zero due to theblocking mode of the MSC. When iFMS becomes zero, the FMS is opened under zero voltageand zero current. In Fig. 7.9 (i), the voltage across the Upper phase-a DS is shown, whichdisplays nominal voltages throughout the fault instance. In Fig. 7.9 (j), the DS currents are205shown, wherein their amplitudes are kept below the nominal value throughout the fault instance.Lastly, in Figs. 7.9 (k) and (l), twelve of the Upper Outer and Inner SM voltages are shown,which stay below a 10% voltage deviation of their set-points.0-0.50.51.02.0-4.06003000-300300400500600700-2.00-1.00.0 0.5 1.0 1.5Time (s)P (GW) & Q (GVAR)i DC (kA)i uo (kA)i ui (kA)v DC (kV)-2.5-1.251.252.50-2.5-1.251.252.50iuoiuiP Q(c)(e)(f)1.50.0-1.01.02.0-1.00.0-2.06605805003753603303452.04.0-2.00.0-4.0300600-3000.0-600iDCΣvc,uo Σvc,li(d)(b)Σvc,ui Σvc,liΣvc,k m (kV) ss sss(a)206-400-2000200400600-400-20002004006006004503001502.02.82.62.52.42.52.62.72.41.00.0-1.0-2.000.49 0.50 0.51 0.52Time (s)vSu,a(j)(g)iFMS vFMS(h)(i)(k)vuo vuiiSu,aiu iSu,b iSu,c(l)v c,uo (kV)ssv c,ui (kV)i u (kA)i FMS (A) & vFMS (kV)v uo & vui (kV)v Su,a (kV)Fig. 7.9. DC fault operation. (a) Real and reactive powers; (b) DC-side current; (c) DC-side pole-to-pole voltage and Upper/Lower pole-to-midpoint voltages; (d) summation of Upper Outer FBSMand Inner HBSM capacitor voltages (k ∈ {u, l},m ∈ {o, i}); (e) Upper Outer stack current; (f) UpperInner stack current; (g) Upper Outer and Inner stack voltages; (h) current and voltage of the FMS;(i) voltage across Upper phase-aDS; (j) Upper DS currents; (k) twelve FBSM capacitor voltages of theUpper Outer stack; (l) twelve HBSM capacitor voltages of the Upper Inner stack.207ia (10 A/div)(b)vab (200 V/div)vui (70 V/div) & vuo (70 V/div) ibal,u (7 A/div)(a)vab (100 V/div), van (100 V/div) & vuo (100 V/div) Fig. 7.10. Hardware verification results. Tektronix-measured: (a) line-to-line voltage, Upper Outerand Inner stack voltages, and Upper balancing current; (b) phase-to-midpoint voltage and load current.7.3.4 HardwareVerificationUsing four OP1210modules of OPAL-RT Technologies’ MMCTestbench [89], each contain-ing 10 FBSMs, with built-in-houseMOSFET-basedDSs, a lab-scaleMSCwith aDC-side voltageof VDC = 200V is prototyped. The three-phase AC load is composed of Wye-connected 12Ωresistors with a floating neutral. The switching signals for the OP1210 modules and the DSs aredigitally controlled by the MMC Testbench’s on-board OP4510 simulator, which enables bothCPU and FPGA controllability. The OP4510’s internal Kintex-7 FPGA is programmed with theOPAL-RT Technologies’ RT-XSG toolbox and the Verilog hardware description language inMATLAB/Simulink. The MSC’s operating voltage amplitude and frequency are controlled inreal-time using MATLAB/Simulink with RT-LAB v2019.1. For the hardware verification, thepole capacitors are connected to the MSC’s midpoint, corresponding to the normal operationwith the optional FMS case.Fig. 7.10 and 7.11 present the hardware verification results. In Figs. 7.10 (a) and (b), resultsmeasured by the Tektronix oscilloscope are presented, wherein in Fig. 7.10 (a), the line-to-linevoltage, the voltages of the Upper Outer and Inner stacks, and the Upper balancing current2086080100120140180160200220Σvc,k m (V) s(a)68101214(b)v c,uo (V) s1819202122(c)v c,ui (V) sΣvc,ui Σvc,lis s Σvc,uo Σvc,lis sFig. 7.11. Hardware verification results. OP4510-measured: (a) Summation of stack SM capacitorvoltages; (b) SM capacitor voltages of Upper Outer stack; (c) SM capacitor voltages of Upper Innerstack.are shown. The balancing current is seen to be approximately sinusoidal and in-phase withthe stack voltages. Fig. 7.10 (b) also presents the line-to-line voltage and the Upper Innerstack voltage as well as the phase-a to midpoint voltage; also shown is the sinusoidal loadcurrent. Figs. 7.11 (a)–(c) show the SM capacitor voltages as measured by the OP4510 simulator,wherein it is seen in Fig. 7.11 (a) that the summation of all four stacks’ capacitor voltages remainbalanced to their set-points of 200V and 100V for the Inner and Outer stacks, respectively.Figs. 7.11 (b) and (c) show the individual SM capacitor voltages of the Upper Outer stack’sFBSMs and the Upper Inner stack’s HBSMs, respectively, which are noted to represent verysmall deviation from the mean value.7.4 Converter ComparisonsIn this section, the HBSM-MMC, MBSM-MMC, EO-AAC, DAC, and QAC are comparedagainst the MSC based on general qualitative converter capabilities, expected semiconductorlosses, and energy storage requirements. The semiconductor loss and energy storage analyseswere discussed at length in Chapters A and B and therefore will not be discussed here. Table 7.5209presents the comparison, where it is noted that the DC-side voltage of VDC = 600 kV and thepower level of P = 1GW are used for all of the converters.7.4.1 Converter General ComparisonIn the “General converter comparison” portion of Table 7.5, first the numbers of HBSMs andFBSMs are compared. The HBSM-MMC requires (600 kV/2.5 kV)×6 = 1,440HBSMs whiletheMBSM-MMCuses a 50/50mixture ofHBSMs andFBSMs and therefore requires 360HBSMs.As in [67], the EO-AAC’s stacks of FBSMs are each rated for 23VDC; therefore, it requires(400 kV/2.5 kV)×6 = 960 FBSMs. The QAC’s M-Arms’ stacks of submodules, as presentedin Section 6.2.5, are rated to block√33VDC for DC fault ride-through capability. Therefore,the QAC requires (350 kV/2.5 kV)×4 = 560 FBSMs. The DAC’s stacks of submodules arerated for 12VDC such that it requires (300 kV/2.5 kV)×2 = 240 FBSMs. Lastly, the FBSMsof the MSC’s Upper Outer and Lower Outer stacks are cumulatively rated for√32V bal1h forDC-fault blocking when the midpoint is clamped with the FMS, as in Section 7.2.5. Therefore,the MSC requires (315 kV/2.5 kV)×2 = 252 FBSMs when the FMS is used. Without theFMS, i.e., with a floating midpoint, the MSC’s FBSM stacks are each cumulatively rated for300 kV− 34V bal1h = 27.5 kV, which follows from Section 7.2.3.2. Meanwhile, the MSC’s HBSM-based Upper Inner and Lower Inner stacks each are rated for the voltage 1.5V bal1h such that(545 kV/2.5 kV)×2 = 436HBSMs are required.It is noted that the MSC can use either IGBT-based DSs, or hybrid DSs composed of acombination of IGBTs and thyristors. For the MSC, the blocking voltage ratings required ofthe IGBT and thyristor portions of the hybrid DSs are given in (5.13) and (5.14) asvˆIGBT,ul =√3V bal1h sin(ωTq)= 100 kV,vˆdownwardthy.,ul =√3V bal1h − vˆIGBT,ul = 530 kV,vˆupwardthy.,ul =√3V bal1h = 630 kV,(7.32)210TABLE 7.5Comparison of Selected ConvertersConverter typeHBSM-MMCMBSM-MMCEO-AACDAC QAC MSCGeneralconvertercomparisonRated ACvoltage, V1h (×VDC) 1/√3 1/√3 2/3√3/pi 2/3√3pi/9Midpoint Clampedwith FMSMidpointFloatingOption #1 Option #2No. of 2.5 kV HBSMs 1440 720 0 0 0 436 436 436No. of 2.5 kV FBSMs 0 720 960 240 560 252 252 24No. ofIGBTs2880 4320 4800 3534(1394)2816 4700(2360)4700(2360)3788(1448)No. ofthyristors1536 0 0 0(1872)3072 0(2052)0(2052)0(2052)DC-fault blocking No Yes Yes Yes Yes Yes Yes NoDC-fault ride-through No No Yes No Yes Yes Yes NoDS switching frequency (Hz) - - 50 50 25 50 50 50DS switching voltage (kV) - - 0 0 0 0 0 0DC-sidepole capacitorsNo No No Yes No Optional Yes OptionalLossanalysis(P=1GW)AC voltage, V1h (×600 kV) 0.523 0.523 2/3√3/pi 2/3√3pi/9SM Pcond (MW) 3.68 5.62 3.77 3.27 3.30 3.44 3.71 0.56SM Psw (MW) 2.30 2.30 0.95 1.32 1.35 1.74 1.53 0.51DS Pcond (MW) - - 1.803.31(1.18)1.39 3.46(1.23)3.46(1.23)3.46(1.23)DS Psw (MW) - - 0 0 0 0 0 0Totalloss (MW)5.98 7.92 6.52 7.90(5.77)6.04 8.64(6.42)8.70(6.47)4.53(2.30)Percentageloss0.60% 0.79% 0.65% 0.79%(0.58%)0.60% 0.86%(0.64%)0.87%(0.65%)0.45%(0.23%)Energyanalysis(S=1GVA) AC voltage, V1h (×600 kV) 0.523 0.523 2/3√3/pi 2/3√3pi/9Enom,HBSM (MJ) 30.45 15.23 0 0 0 3.15 0.98 3.15Enom,FBSM (MJ) 0 15.23 14.25 3.32 9.47 3.88 3.80 0.15Enom,PC (MJ) 0 0 02.259.61† 0 4.39 0 0Enom,tot (MJ) 30.45 30.45 14.255.5712.93† 0 7.03 9.17 3.30Normalized to MMC 1.00 1.00 0.4660.1830.424† 0.311 0.231 0.301 0.108∗Bracketed values assume the hybrid DSs for the DAC and MSC.†For 5% individual PC ripple. 211andvˆIGBT,m =√3V bal1h sin(ωTq)= 100 kV,vˆthy.,m = 1.5Vbal1h − vˆIGBT,m = 445 kV.(7.33)Hence, using the ABB 8.5 kV 5STP 27N8500 thyristor [96] with a Tq = 500 µs turn-off timewith the de-rated voltage factor 4.5 kV:2.5 kV, the MSC’s DSs need 2052 thyristors and 480of the Westcode T1800 GB45A [90] 4.5 kV IGBTs with the same de-rating factor. Therefore,in total, the MSC needs 2052 thyristors and 2,360 IGBTs if the hybrid DSs are used. If theIGBT-based DSs are used, the MSC needs 4,700 IGBTs and no thyristors.Concerning the numbers of semiconductors, the DAC, QAC, and MSC all require fewerIGBTs than the HBSM-MMC when their hybrid DSs are used. Even when they are not used,the DAC and MSC still have a lower IGBT count than the EO-AAC. In any case, the seriesconnection of the many hundreds of IGBTs required to form DSs is more spatially efficientthan distributing the IGBTs among each submodule. Although they do require a significantnumber of thyristors, thyristors are a mature technology that shows well-proven reliability anda small footprint when series-connected. Since the QAC, DAC, and MSC all experience ZVS oftheir DSs, DS technology will mature further to ensure reliable turn-off operation and lowloss of the thyristors.Each of the proposed converters is tolerant to DC-side faults, while the QAC andMSC wereshown to provide reactive power support during faults, i.e., they possess DC-fault ride-throughcapability. The DAC is the only one of the proposed converters to require a DC-side PC fornormal operation, while the MSC can operate at a higher voltage with a decoupled AC- andDC-side voltage.7.4.2 Semiconductor LossesIn the “Loss analysis” section of Table 7.5, the MSC with its various operating modes atthe AC voltage of V1h = Vbal1h is presented against the other converters. In Option #1, the totalconduction losses of the SMs are seen to be lower than inOption #2, which arises from the lowerRMS current flowing through the Outer stacks in the case of Option #1 [see the subfigures of212Fig. 7.6](e) and Fig. 7.7 (e)]. However, the switching losses are somewhat lower in the case ofOption #2 due to the lower switching current flowing through the Inner stacks. Meanwhile,the losses of the DSs are the same in each case since the same operating point was chosen. Thetotal losses of the Options #1 and #2, therefore, are very similar at the same operating voltageof V1h = Vbal1h .The losses of the MSC were also tested with the floating midpoint, by removing the optionalFMS. The results show that the SM conduction and switching losses are significantly lowerwith a floating midpoint since the Outer stacks can be significantly de-rated by approximately90% (i.e., from 252 to 24 total FBSMs). This mode of operation reduces the MSC’s voltagerange. But when it operates in the close neighbourhood of V1h = Vbal1h , the MSC displays thehighest efficiency of any of the tested converters with only 0.45% losses with conventional DSsand 0.23% losses with the hybrid DSs.With DC-fault blocking enabled, the losses of the MSC are similar to the MBSM-MMC’s,while remaining functionally identical despite requiring significantly fewer SMs and having amuch reduced energy storage requirement.7.4.3 Energy Storage AnalysisThe converter energy storage analysis method is based on the same methods proposedin Chapter A, wherein the nominal energy storage requirements of a capacitive element isproportional to the peak-to-peak energy deviation of the element, and inversely proportionalto the allowable per-unit voltage deviation. Due to symmetry, the energy deviations of onlythe Upper stacks and PC are calculated, with the final result multiplied by two. The energydeviations of the Upper Outer stack, Upper Inner stack, and Upper PC at the power factor213angle, ϕ, are respectively given by∆Euo(t, ϕ) =∫ tt0vuo(τ)iuo(τ, ϕ) dτ,∆Eui(t, ϕ) =∫ tt0vui(τ)iui(τ, ϕ) dτ,∆EPC,u(t, ϕ) =∫ tt0vPC,u(τ)ibal,u(τ, ϕ) dτ.(7.34)The definitions of the stack currents and voltages are given in Fig. 7.3 and Tables 7.2 and 7.3.The energy analysis assumes the Option #1 operating mode, such that ibal,u is given by (7.13)and vPC,u is assumed to be constant, such that vPC,u = 12VDC.The nominal energy storages of the stacks and PC are then found with (A.6) and (A.7) for2,000 values of ϕ ∈ [0, 2pi]. The nominal energy storage values at V1h = V bal1h are presentedin Table 7.5 for only the Option #1 operating mode, as well as the operating mode withoutthe optional FMS. The energy storages for varying operating voltages and the three operatingmodes are presented in Table 7.6.For the “Energy analysis” portion of Table 7.5, the converters at the operating voltagespresented are all entirely SM-based except for the DAC, which has its nominal energy storagerequirements separated into its DC-side PCs (PCs) as well as its SMs. It is noted that thisanalysis uses the same triangular triplen harmonic for theQAC that is used for the EO-AAC [67].Under this condition, the nominal energy requirement of the QAC is exactly two-thirds that ofthe EO-AAC, which suggests the QAC will have a smaller converter footprint.When a 5% pole-to-pole DC-side voltage ripple is enabled, the DAC has the lowest totalenergy storage requirement among the DC-fault tolerant variations of the converters of 5.56MJ,representing only 18.3% of the MMC’s. However, for a 5% individual PC voltage ripple,these values become 12.93MJ and 42.4%. TheMSC has the second smallest energy storagerequirement at 7.03MJ, which is 23.1% of the MMC’s, while being able to control the DC-sidecurrent to be free of any harmonic content. Despite its requiring more SMs than the QAC andDAC, most of the MSC’s SMs are HBSMs, which use half as many IGBTs as FBSMs. Moreover,214TABLE 7.6Energy Storage for Varying Operating Voltages and Different OperatingModesOperating mode Option #1 Option #2MidpointFloatingV1h=√ 3 piv DC Enom,HBSM (MJ) 3.15 0 15.18Enom,FBSM (MJ) 3.39 3.32 0.73Enom,PC (MJ) 1.37 4.81 17.94Enom,tot (MJ) 7.91 8.13 33.85V1h=0.58v DC Enom,HBSM (MJ) 3.15 0.53 7.35Enom,FBSM (MJ) 3.68 3.60 0.08Enom,PC (MJ) 0.60 4.57 7.88Enom,tot (MJ) 7.43 8.70 15.31V1h=√ 3pi9v DC Enom,HBSM (MJ) 3.15 0.98 3.15Enom,FBSM (MJ) 3.88 3.80 0.15Enom,PC (MJ) 0 4.39 0Enom,tot (MJ) 7.03 9.17 3.30V1h=0.63v DC Enom,HBSM (MJ) 3.15 1.45 6.31Enom,FBSM (MJ) 4.05 3.97 0.11Enom,PC (MJ) 0.57 4.21 7.49Enom,tot (MJ) 7.77 9.63 13.91V1h=2 3v DC Enom,HBSM (MJ) 3.15 2.13 16.31Enom,FBSM (MJ) 4.26 4.17 0.74Enom,PC (MJ) 1.32 3.98 17.29Enom,tot (MJ) 8.73 10.28 34.34its smaller energy storage suggests each of its SMs is physically lighter and smaller. Furthermore,if the MSC is operated without the FMS, it can achieve the lowest energy storage requirementof 3.30MJ; however, the MSC without the FMS is not DC-fault tolerant.In Table 7.6, the nominal energy storages of the stacks and PCs are shown for varyingvalues of V1h and the three operating modes. The results show that, when the optional FMS isused, theOption #1 operating mode results in smaller overall energy storage requirements thanthe Option #2 operating mode. However, this operating mode enables a significant reductionin the energy requirements of the Inner stacks, but has an increased energy requirement ofthe PCs. When operated at V1h = Vbal1h , the operating mode without the floating midpoint is215shown to have the lowest energy storage requirements. However, the energy storage requiredby the Inner stacks and PCs quickly increases as V1h deviates away from Vbal1h .Since the capacitors of the DC-side PCs can be grouped together compared to those of theSMs, the Option #2mode of operation might enable a smaller footprint than the Option #1mode. However, due to the Inner stacks’ lower energy requirement, the Option #2mode ofoperation will result in the Inner stacks experiencing significantly higher voltage ripple duringSTATCOM operations during DC-side faults. The larger PC capacitance in Option #2 will alsocontribute to proportionally more energy being distributed to the stacks and fault resistanceduring DC-side faults.7.5 ConclusionThis chapter proposed the novel MSC, which is composed of four FBSM- or HBSM-basedstacks that grant it filterless operation without DC-side PCs. TheMSC can control the DC-sidecurrent to be free of harmonics, which was demonstrated in the case study of Section 7.3.1,such that it possesses DC pole-to-pole short-circuit fault ride-through capability, which wasdemonstrated in Section 7.3.3.The MSC’s optimal operating voltage was derived to be V1h =√3pi9VDC, which is theAC voltage magnitude that enables Upper Outer and Lower Outer to have no DC voltagecomponent, thereby enabling natural balance of its stacks. To operate the MSC freely at anyV1h, the DC-side PCs and optional FMS of Fig. 7.1 enables balancing third-order and/or ninth-order circulating currents to flow being the stacks and PCs. Three methods of balancing wereproposed: the first method assumes that the only currents flowing through the PCs are thebalancing currents, such that they never carry the load current. The second method assumes amode of operation similar to the DAC’s wherein the PCs carry load current while the Innerstacks carry only the balancing currents, which have a third-order component and a DCcomponent. The third method removes assumes a floating midpoint without the optional FMSsuch that the same balancing current flows through all four stacks at once. This mode enables asignificant reduction in the total Outer stack voltage rating for much improved semiconductor216losses. However, this mode has a narrower range of operation due to the increased amplitudeof the balancing current compared to the previous two cases.2178. Conclusion8.1 High-Level Converter ComparisonThe proposed VSC-HVDC converter topologies in this dissertation possess unique charac-teristics that make them suitable for specific applications, but may also limit their applicabilityin other situations. To assist in the selection of an appropriate converter for a given scenario, ahigh-level comparison of the main attributes and limitations of each converter is presented inthis section. The goal is to provide a clear understanding of the advantages and disadvantagesof each converter, thereby facilitating informed decision-making for the reader.When selecting an appropriate converter topology for VSC-HVDC systems, it is crucial toconsider a range of key metrics, including the semiconductor losses, energy storage require-ments, the numbers and topologies of submodules, the number of semiconductors used, andthe expected AC voltage range. The importance of these metrics can vary depending on thespecific application, such as front-to-front DC/DC converter schemes or interfacing with verystrong grids. In addition to these metrics, it is also important to evaluate the converters’ binarycharacteristics in order to fully understand their suitability for a given application. Thesecharacteristics include whether the converters have: 1) inherent DC-fault blocking capability,2) inherent DC-fault ride-through capability, 3) zero-voltage-switching of their DSs, and 4) theneed for DC-side pole capacitors.Several suggestions for varying operation scenarios are presented below.8.1.1 Onshore HVDC Converter StationsFor onshore HVDC converter stations, the size of the converter is typically not a crucialfactor in determining the economic feasibility of its implementation. As such, the ability for aconverter to ride-through unsymmetrical AC-side faults and DC-side pole-to-pole faults, whilemaintaining a high level of semiconductor efficiency, are the primary metrics to be consideredfor such converters. Additionally, onshore HVDC converter stations, which do not have size218limitations, can implement passive AC- and DC-side filtering if necessary, thus allowing forthe consideration of converters with DC-side voltage ripples.Converters that fit these criteria include:TH3LC: TheTH3LC boasts high efficiency throughout its operating range and has the inherentability to ride-through unsymmetrical AC-side faults and DC-side pole-to-pole faults.However, the TH3LC employs thyristor DSs that require dedicated circuitry for turn-off,which some VSC-HVDCmanufacturers may view as a potential risk to reliability or astoo complex to implement.H5LC: TheH5LC also has very high efficiency, but uses only IGBT-based semiconductors,which makes it a more feasible option for VSC-HVDC manufacturers to construct.It also has a lower count of semiconductors and SMs, despite requiring high energystorage. However, it comes with added control complexity due to its FCs and does nothave DC-fault ride-through capability, only DC-fault blocking capability. Despite theselimitations, when space is not a concern, the H5LC may be an attractive choice due to itshigh efficiency and low semiconductor count.MSC: TheMSC is capable of operating in a mode that offers exceptional efficiency, when itsFMS is open. However, this mode precludes the MSC from providing DC-fault blockingor ride-through capabilities. On the other hand, when operated in its other mode,the MSC’s efficiency is only mediocre but it can provide DC-fault blocking and ride-through capabilities. Additionally, the MSC features inherent zero-voltage-switching ofits DSs, which greatly simplifies their design. However, the MSC is unable to inherentlyrespond to unsymmetrical AC-side faults due to its ability to generate only balancedthree-phase voltages without a negative-sequence voltage component. This limitationcan be addressed by incorporating supplementary STATCOM setups, but this comes atthe cost of integrating another converter into the design.It is worth noting that future research for the MSC should focus on developing a hybrid219model that combines the two operatingmodes, in order to provide theMSCwithDC-sidefault ride-through capability while also enabling best-in-class efficiency during normaloperation.8.1.2 Offshore HVDC Converter StationsFor offshore VSC-HVDC systems, the size of the converter station is a crucial factor, as itheavily affects the economic feasibility of its implementation. As such, the ability for a converterto ride-through DC-side faults while retaining its compact size is of paramount importance.Therefore, converters that prioritize compact size and DC-fault ride-through capabilities aremost suitable for offshore VSC-HVDC systems.Given these considerations, the following converters are the most suitable for such anapplication:H3LC: For offshore VSC-HVDC systems, the H3LC converter topology is a highly suitableoption due to its minimal energy storage requirements, which results in a smallerconverter footprint. However, it is important to note that the H3LC requires a protectionbranch in order to provide DC-fault ride-through capability, which may result in anincreased footprint. Additionally, the H3LC’s hard-switching of its DSs presents a designchallenge in terms of ensuring equal voltage sharing among the IGBT/diodemodules andensuring a high degree of synchronization among them. Despite these challenges, theH3LC has the potential to become the most compact solution for offshore VSC-HVDCconverter stations, potentially surpassing the MMC in terms of its small size.DAC: In the context of offshore VSC-HVDC systems, the DAC converter topology is particu-larly well-suited due to its compact design, which is achieved through the use of onlytwo stacks of submodules. Furthermore, the DAC boasts ZVS of its DSs, which greatlysimplifies their design and reduces the complexity of the overall system. However, itshould be noted that the DAC’s energy is balanced at a single operating voltage, whichrequires the use of an overlap period, thereby resulting in an increase in its output voltage220THD. While this increase may be a concern, it might not cause operational difficultiesfor wind turbines in certain designs, as each turbine can be equipped with an on-boardAC/DC/AC converter that effectively isolates it from the increased THD. Additionally,the DAC possesses inherent DC-fault blocking capabilities, although it lacks inherentride-through capabilities. Despite this limitation, the DAC may be an attractive choicefor highly-compact converter stations where size constraints are of utmost importance.QAC: TheQAC is an attractive option for offshore VSC-HVDC systems because of its reducednumber of submodules compared to the MMC and its ability to maintain harmonic-freeDC-side current without the need for DC-side pole capacitors. Additionally, the QACcan generate AC voltage over an unlimited range of amplitudes, enabling it to respond toAC- or DC-side fault scenarios reliably. However, it should be noted that the QAC’s DSsrequire bidirectional voltage blocking capability, necessitating the use of anti-parallelthyristors for high efficiency or anti-series IGBTs for their proven track record, whichmay pose challenges for VSC-HVDC converter manufacturers.MSC: TheMSC is a desirable choice for offshore VSC-HVDC systems as it has low energystorage requirements, and is capable of providing DC-fault blocking and ride-throughcapabilities. Additionally, the MSC requires fewer submodules compared to the MMC,which greatly reduces the size of the converter station. Despite itsmediocre efficiency, thistrade-off is offset by the savings in converter size enabled by this technology. Furthermore,the MSC incorporates DC-side pole capacitors, however, the voltage ripples of the upperand lower pole capacitors completely cancel out, allowing the MSC to operate withharmonic-free DC-side current. TheMSC is based solely on IGBT/diode technologyand features ZVS of its DSs, which greatly simplifies its overall design and utilizes widelyavailable components with a proven track-record.2218.1.3 Front-to-Front DC/DC Converter ApplicationsWhen operating as front-to-front DC/DC converters with an interfacing transformerbetween them, the criteria for converter selection shifts. In this scenario, the AC-side voltagesare guaranteed to be balanced, thus the primary design considerations are to utilize convertersthat result in clean DC input and output voltages. This restriction limits the choice to twoconverters: the QAC and the MSC.TheMSC should employ the topology with the clampedmidpoint, due to its net-zero pole-to-pole DC-side voltage ripple. The decision between the twoof these converters ultimately depends on their feasibility of implementation. Both convertersare functionally equivalent and can operate over any AC voltage, but the MSC has an advantageas it requires only IGBT-based DSs, which simplifies the design process. Therefore, at thepresent state of semiconductor development, the MSC remains the best option for DC/DCconverter applications.8.1.4 STATCOM ApplicationsWhen it comes to STATCOM applications, the H3LC and DAC are among the mostsuitable options due to their low energy storage requirements in normal operation. In theseapplications, DC-side fault protection is not necessary, as there is no DC-side transmission lines.Furthermore, the DAC is capable of operating at any AC voltage amplitude when supplyingonly reactive power without any real power with a deviation in its energy. However, it shouldbe noted that while the DAC features ZVS of its DSs, it is unable to generate negative-sequencevoltages during, for example, unsymmetrical AC-side faults. On the other hand, the H3LCdoes not have ZVS of its DSs, which increases the difficulty of implementation, but it is able tosupply negative-sequence voltages. Therefore, while the DAC offers the advantage of a simplerconverter design, the H3LC offers higher utility.8.2 Overview of Main ContributionsThe first part of this dissertation presented three significant contributions to the field ofVSC-HVDC, including the H3LC, TH3LC, and H5LC converters, which are part of the class of222converters known as HCMCs. In addition to providing detailed simulation results—and in thecases of the H3LC and H5LC, hardware verifications—analyses were also provided to enableapproximate sizing of the converters based on their capacitive energy storage requirements aswell as to determine their semiconductor losses. The methods of such analyses were derivedin-depth in Chapters A and B, after the H3LC was presented.In addition to the three hybrid VSC-HVDC converter topologies discussed earlier, thisdissertation also proposed three additional topologies with distinct operating principles. Theseinclude the DAC, QAC, and MSC, which utilize the principle of multiplexing their stacks ofsubmodules to achieve filterless AC voltages. These converters have a reduced number ofsubmodules compared to the MMC, with the DAC requiring only two submodule-based stacks.These converters also possess the key feature of zero-voltage-switching in their DSs, whichgreatly simplifies the voltage sharing among their constituent IGBT/diode modules and reducesthe need for perfect synchronization, resulting in an overall improvement in the reliability oftheir DSs.8.2.1 Conclusions on the Hybrid Three-Level ConverterTheH3LC was the first of the converters proposed in this dissertation, in Chapter 2. TheH3LC uses cascaded FBSMs in tandem with a slow-switching three-phase T-type NPC three-level converter for filterless AC-side voltage. Comparative analysis in Section 2.4 shows thatnot only does the H3LC have 12.7% lower semiconductor losses than the MBSM-MMC—i.e.,the MMC variant that uses HBSMs and the minimal number of FBSMs to provide DC-fault tol-erance for minimized additional semiconductor conduction losses—but its total energy storagerequirements when allotting a±5% DC-side pole-to-pole voltage deviation was found in Ta-ble 2.3 to be only 11.6%of theMBSM-MMC’s (9.565 J rad/VA/s compared to 1.106 J rad/VA/s).Such a reduction in energy storage requirements suggests a reduction in the H3LC’s footprintcompared to the MBSM-MMC’s. Moreover, the H3LC features a 13.3% reduction in thenumber of IGBTs compared to the MBSM-MMC and a 72.5% reduction in the number of SMs,for a further reduction in upfront costs.223One motivation for the design of the H3LC was to improve upon the previously proposedH2LC, which was originally presented as a compact solution to the MBSM-MMC’s largefootprint. However, the H2LC needs twice as many normal-operation FBSMs compared tothe H3LC, while its capacitive energy storage requirements are increased by 173.3%. Such anincrease is in part due to (1)The H3LC’s cascaded FBSMs’ lower output voltage of 14VDC, whichenables a significant reduction in their peak-to-peak energy deviation, as in (A.9), and (2) theH3LC’s symmetrical operation enables its upper and lower pole capacitors’ currents to be inantiphase, which enables their voltage ripples to largely cancel.However, to supply the voltages necessary to counteract the AC-side’s contribution to DC-side short-circuit pole-to-pole faults, the H3LC uses additional FBSMs (or one asymmetricalFBSM) within its “protection branches” of Fig. 2.1. Since the amount of capacitance requiredby the protection branches depends mainly on the amount of inductive energy they needto absorb from the grid, the protection branches’ energy storage—and, consequently, theirsize—is highly variable and was not presented, since it is a parameter of the grid to which theH3LC is connected and not the converter itself.In addition to the HVDC-scale simulation with a 600 kV DC-side voltage and 1096MVApower rating, a lab-scale 400V H3LC was constructed using the OP1210 cascaded FBSMscontained within OPAL-RT Technologies’ MMC Testbench and a built-in-house three-phaseT-type NPC three-level converter. The HVDC-scale simulation and lab-scale hardware provedthe validity of the H3LC’s theoretical operating principle, including its novel third-orderharmonic voltage injection scheme in (2.6) and the coordination among the three-level voltagetransitions and the cascaded FBSMs.8.2.2 Conclusions on the Thyristor-based Hybrid Three-Level ConverterWith their unmatched efficiency, bidirectional voltage-blocking capability, and the maturetechnology they employ, the TH3LC proposed in Chapter 3 uses thyristor valves to composeits DSs. The TH3LC employs a Commutation Branch—composed of cascaded FBSMs anda commutation inductor—to ensure its thyristor-based turn off reliably. Meanwhile, the224Commutation Branch’s cascaded FBSMs enable a trapezoidal output voltage for the TH3LC’squasi-three-level converter that enables ZVS for the DSs as well as a low dvdtacross them,ensuring they remain reliably in the off-state. Compared to the H3LC, the trapezoidal outputvoltage of the TH3LC better-approximates the desired fundamental-frequency sinusoidalvoltages such that the AC-side cascaded FBSMs can be rated for significantly reduced peakvoltages, depending on the transition interval of the trapezoidal voltage, . Table 3.1 showsthat the AC-side cascaded FBSMs can be rated for 0.11VDC when  = 0.6 rad, which is a 56%reduction compared to the H3LC’s cascaded FBSMs. However, longer transition intervalscontribute to a larger energy deviation for the Commutation cascaded FBSMs, as in (3.12),which requires a larger DC current to be modulated between the pole capacitors and the FBSMs,as in (3.13), thereby increasing the TH3LC’s conduction losses. The optimal third-orderharmonic of the TH3LC was derived in (3.8), which was shown to be valid over the voltagesV1h ∈ [0.49VDC, 0.6VDC] for  ∈ [0, 0.5]. It is the optimal third-order harmonic because itresults in minimal sizing for the AC-side cascaded FBSMs, which is demonstrated in Fig. 3.5.Semiconductor loss analysis was conducted in Section 3.4 that shows that the TH3LC’ssemiconductor losses closely match the HBSM-MMC’s when both converters operate at theHBSM-MMC’s nominal operating voltage, V1h = 0.523VDC, with the HBSM-MMC’s andTH3LC’s total losses being 5.98MW and 6.31MW, respectively, such that they are within 5% ofeach other. However, the TH3LC can reach peak voltages 9.6% higher than the HBSM-MMC,making its nominal operating voltage V1h = 0.573VDC. With the higher nominal operatingvoltage, the TH3LC’s semiconductor losses reduce to 5.00MW, which is a 16.4% reductioncompared to the HBSM-MMC’s 5.98MW.Energy storage requirements were determined for the TH3LC for itsCommutation Branch’scascaded FBSMs, AC-side cascaded FBSMs, and DC-side pole capacitors with the transitionduration of  = 0.035; as well, Fig. 3.9 presents the energies for  ∈ [0, 0.8]. The results indicatethat the TH3LC requires 78.7% less capacitive energy storage than the MMC when  = 0.035.However, it requires 83.4% more energy storage than the H3LC. The expected footprint is still225expected to be much smaller than the MMC’s, while its efficiency is significantly higher thaneven the HBSM-MMC’s.A key feature of the TH3LC is its inherent DC-side pole-to-pole fault-blocking capabilitythat is enabled by the bidirectional blocking capability of its thyristors. During DC-side faults,the commutation and AC-side cascaded FBSMs can work together to support the AC-sidevoltage even when the DC-side voltage collapses during faults. Such functionality improves thegrid’s stability during fault events.8.2.3 Conclusions on the Hybrid Five-Level ConverterTheH5LC of Chapter 4, which was the last of the converters proposed in this dissertation,was shown to display both high efficiency and a compact footprint. The H5LC improves someof the downsides of the H3LC, while proposing a novel DC-fault blocking scheme that employsBTVs and FMSs to timely and safely respond to faults. Typically, BTVs are used as only a meansto bypass the IGBTs for MMC applications; for the H5LC, both the conduction and blockingstates of the BTVs are employed, which is a novel implementation. The H5LC employs a novelthird-order harmonic voltage injection scheme that not only decides the amplitude of thethird-order harmonic that limits the H5LC’s cascaded FBSMs to the bidirectional voltagesof±18VDC (i.e., halved compared to the H3LC), but also determines the optimal, and unique,five-level converter switching angles, α1 and α2, to enable such a limit.An HVDC-scale detailed simulation alongside a lab-scale hardware verification of a 400VH5LC with 10 FBSMs per phase provided confirmation of the H5LC’s theoretical operatingprinciple and proved that the third-order harmonic voltage injection scheme gives the cascadedFBSMs the low blocking voltage of±18VDC. Moreover, the FCs’ voltage balancing algorithmwas shown to effectively maintain their voltages to 14VDC.Its small number of FBSMs enables the H5LC’s FBSM conduction and switching losses tobe 48.6% and 26.7% lower the H3LC’s, respectively. The H5LC has 17.1% and 4.0% less totallosses than the H3LC and HBSM-MMC, respectively, for the np = 0 operating mode, whichchanges to 14.5% and 1.0% for the np = 1 operating mode.226TheH5LC is also expected to have a reduced converter footprint compared to the MMC.Especially for the np = 1 case, the H5LC requires only 18.3% the energy storage as the MMC aswell as 12.8% less energy than the TH3LC. Moreover, the energy contained within its cascadedFBSMs is 63.3% less than the H3LC’s. The capacitive energy storage that is distributed amongthe SMs is expected to require a larger footprint than the energy storage required by the polecapacitors or the FCs, which can be physically grouped together and connected in parallel.Hence, the capacitive energy storage savings had by the H5LC’s cascaded FBSMs—along withtheir fewer total numbers—suggests a small footprint. It is noted that the H5LC has the leastnumber of semiconductors compared to the other tested converters. Especially comparedto the EO-AAC that uses 4800 2.5-kV IGBTs, the H5LC requires only 2520. However, theH5LC uses BTVs and FMSs for safe and timely fault protection, but with only two of the phasesrequiring fully-rated BTVs, only 584 4.7-kV thyristors are required such that their contributionto the H5LC’s size is small.8.2.4 Conclusions on the Dual-Arm ConverterTheDAC is a novel converter topology that can generate sinusoidal line-to-line voltageswith only two FBSM-based stacks. Using only two stacks for three-phase sinusoidal voltagegeneration has not yet been presented in the literature, making such a reduction highly noveland unique to the DAC. Moreover, the DAC features very low energy storage requirementscompared to the MMC, requiring only 18.3% of its energy storage if a 5% pole-to-pole DC-sidevoltage deviation is allotted.The DAC’s ability to generate sinusoidal voltages using only two stacks is a consequence ofone of the phase-to-neutral voltages being clamped to the neutral-point of the DC-side polecapacitors at any time. With one of the phase-to-neutral voltages set at the zero-level voltage,the Upper and Lower stacks can respectively generate the positive and negative portions ofthe other two phase-to-neutral voltages. Structurally similar the T-type three-level converterwith the addition of the Upper and Lower stacks, the DAC requires only one-sixth the number227of SMs as the MMC while being DC-fault tolerant by virtue of its FBSMs’ reverse-blockingcapability.The operating voltage that enables inherent balance of its FBSM-based stacks was definedin (5.12). If it is desired for the AC voltage to deviate from (5.12), then the Optional OverlapBranches of Fig. 5.2 can be employed to enable the Upper and Lower stacks to overlap andtherefore be balanced. The Overlap Branches are used to remove the harmonic content causedby the balancing process. The peak voltage to be blocked by the Overlap Branches’ cascadedFBSMs is given in (5.19). It is a design parameter that depends on the peak allowable balancingcurrent and the overlap period. For a typical overlap period of 10°, the peak AC-side cascadedFBSM voltage is vˆFB ≈ 112VDC, which contributes little to the overall size of the converter.Owing to the ZVS of its DSs, the DAC can also use hybrid DSs that are a combination ofthyristors and IGBTs. By employing the hybrid DSs, the DAC’s semiconductor losses rivalthe HBSM-MMC’s, while using IGBT-based DSs gives it similar semiconductor losses as theMBSM-MMC, at a much smaller converter footprint.8.2.5 Conclusions on theQuad-Arm ConverterThe operating principle of the QAC, as presented in Chapter 6, presents a fundamentaldeparture from the first three converters’ in that it uses only DC-side FBSMs instead of the AC-side FBSMs that the H3LC, TH3LC, and H5LC all use. Its operating principle combined withits novel M-Arms, and their ability to multiplex the DSs amongst each of the phases, provides apath for the DC current to flow, which enables its removal of DC-side pole capacitors.A hybrid DS composed of IGBTs and thyristors was proposed that uses IGBTs to blockthe current flowing through the DSs and maintain it below the thyristors’ holding currentfor a time of at least Tq for their turn-off. Such a scheme is enabled by the inherent ZVS ofthe QAC’s DSs as well as the negligible arm inductance, which enables the IGBTs to nearlyinstantaneously halt the DS current for the thyristors’ turn-off. Moreover, to obviate the hybridDSs’ critical rate-of-rise of on-state current, di/ dtcrit, the thyristor turn-on signal can fully228propagate throughout the thyristor such that it is fully turned on before current flows throughit.Table 7.5 presented the comparison of the QAC against the HBSM-MMC, MBSM-MMC,and EO-AAC, as well as the proposed DAC and MSC. The results showed that the QAChas two-thirds the energy storage requirements of the EO-AAC (since the same triangularharmonic voltage injection scheme of [67] was assumed) due to its having fourM-Arms insteadof the EO-AAC’s six arms (14.2MJ compared to 9.47MJ). While the EO-AAC’s arms spendone-third of each fundamental-frequency cycle in a blocked/inserted state, the QAC’s M-Armsare continuously operated and multiplexed amongst the three phases for 4pi3intervals. Thisdoubles the number of DSs required by the QAC compared to the EO-AAC, but DSs comewith a mechanically and electrically advantageous design compared to FBSMs, since they arestacked and operated in unison.A triplen harmonic scheme was developed for the QAC to reduce its normal-operationpeak operating voltage to ±12VDC and its fault-operation peak to a peak negative value of√33VDC ≈ 0.577VDC such that it needs 280 FBSMs compared to the EO-AAC’s 480 FBSMs,which has obvious implications regarding their relative converter station sizes.8.2.6 Conclusions on the Multiplexed-Stack ConverterTheMSC is a significant modification of the DAC that enables the removal of the DC-sidepole capacitors by the addition of two HBSM-based stacks. This modification enables theMSC to have control over the DC current, which not only enables the DC current to be freeof low-order harmonics, but it also grants the MSC DC-fault ride-through capability. TheMSC’s DC-side fault ride-through capability was presented in Section 7.3.3, wherein the MSCwas shown to provide reactive power compensation during the fault and to quickly resumeoperation after the DC-side fault. As in Section 7.4, the MSC was shown to have the lowenergy storage requirement of 7.03MJ, which is approximately 25% greater than the DAC’s.However, the DAC’s use of pole capacitors restricts its ability to provide reactive power during229DC-side fault. Compared to the MMC, the MSC requires less than one-quarter the energystorage, putting its energy storage requirements within a similar range as the H5LC and TH3LC,although approximately twice as much as the H3LC. Meanwhile, when using the hybrid DSsthat the DAC and QAC use, its efficiency is 0.64%, which is similar to the HBSM-MMC’s andEO-AAC’s.The MSC was proposed with an optional FMS and optional PCs, which enable operation atany arbitrary AC voltage amplitude; without the PCs, the MSC operates at the AC voltage thatenables its Outer stacks to be without a DC voltage component, i.e., at V1h =√3pi9VDC. Whileusing the PCs with a floating midpoint, the Outer stacks were shown to generate voltageswithin 12vDC − 34V1h and12vDC −√32V1h, which significantly reduces their voltage rating (atV1h = Vbal1h , the Outer stacks can be reduced by approximately 90%, as in Section 7.2.3.2).When the optional FMS is employed, the MSC was shown to have the two operating modes:MSC mode and DACmode, as presented in Sections 7.2.3.1.1 and 7.2.3.1.2, where the DACmode reduces the voltage ripple of the stacks but increases that of the PCs. Moreover, inSection 7.2.3.1.1, a ninth-order harmonic injection into the balancing currents enables theirpeak energy deviation to be reduced to 86.6%, but increases the RMS value of the balancingcurrents.8.3 Potential FutureWork8.3.1 Further VSC-HVDC Converter ResearchAs shown throughout this dissertation, the potential benefits of the proposed technologiesare numerous. However, this dissertation only presented six converter topologies out ofcountless possibilities for VSC-HVDC applications. The concept of hybrid converters can beexpanded to converters with:• More main-converter voltage levels for a further reduction in the number of cascadedFBSMs for improved semiconductor losses;• A reduced number of semiconductors;230• Further reduced energy storage requirements;• Higher employment of thyristor-based technology for its superior efficiency;• Soft-switching of the semiconductor switches for reduced switching losses and EMI/insu-lation requirements;• Higher modularity;• No DC-side pole capacitors and inherently harmonic-free DC current.8.3.2 Accelerated CPU and CPU/FPGA Simulation FrameworksTheCPU/FPGA co-simulation uses an FPGAmodel that I wrote using the Verilog hardwaredescription language (HDL), which can implement the voltage calculations, sorting functions,and switching functions for up to 1,536 FBSMs, although only 192 FBSMs were presented inthe chapter as it is a more practical number for VSC-HVDC systems. The same FPGA modelalso implements the FCs’ VBA, composes the five-level converter voltages for the H5LC, andperforms the discretized capacitor equations for the FCs and PCs once every 16 ns. Real-timesimulator manufacturers and designers, such as OPAL-RT Technologies, RTDS® Technologies,and Typhoon HIL all employ FPGA technology. However, the HDL code for their FPGAmodels is typically proprietary and kept hidden from the user.Having written the FPGA code for the CPU/FPGA co-simulation myself, it is envisionedthatmethods can be developed to reduce the FPGA’s resource consumption for such simulationsby optimizing the sorting functions, switching functions, and voltage calculation methods. TheFBSM sorting method is the most resource-intensive part of the FPGAmodel, and as such isan active research problem.8.3.3 STATCOM Schemes and Renewable Energy IntegrationWith the increased proliferation of renewable energy sources distributed throughout thegrid, the rotational mass/inertia of the grid continues to decrease, which increases the risk of231cascading grid failures/blackouts. Synchronous condensers, i.e., free-wheeling synchronousmachines, can correct the rotational inertia problemwith their significant rotationalmass. Theirnormal-operation kinetic energy can be more than 400MJ, which helps to maintain the gridfrequency throughout fluctuating load conditions, such as during AC-side fault scenarios or theintermittent but immense power demand of electric-arc furnaces [100]. Moreover, variationof synchronous condensers’ field currents enables reactive power/voltage control. However,synchronous condensers are outfitted with flywheels that can weigh over 40 tonnes [101] andhence have significant, and constant, frictional losses in addition to their winding andmagneticlosses, such that their total losses are approximately of their MVAR rating 5% [102]. Moreover,their rotating components require regular maintenance.For medium-voltage (MVDC) applications, i.e., the 1.5 kV—100 kV range, there is a sig-nificant and growing interest regarding the use of multilevel converter technology for staticsynchronous reactive compensation systems, i.e., STATCOM systems. Compared to syn-chronous condensers, STATCOMs offer a much lighter solution with losses that are approxi-mately an order of magnitude lower than synchronous condensers’. Moreover, STATCOMs’integrated energy storage can be bolstered with the addition of more capacitors, which arerelatively inexpensive and compact for MVDC applications; however, their active power outputcapability—and hence their ability to resist changes to the grid frequency—is significantlylower than synchronous condensers’.Compared to the state-of-the-art STATCOMs that use cascaded FBSMs in a∆ configuration(∆-MMC) [102], the H3LC, TH3LC, and H5LC all feature very high efficiency even withtheir significantly reduced energy storage requirements compared to the∆-MMC’s. With thesame 10% voltage ripple that was assumed for the proposed converters’ cascaded FBSMs, theH3LC, TH3LC, and H5LC respectively require 2.32 kJ/MVA, 4.53 kJ/MVA, and 2.58 kJ/MVA ifthey operate in STATCOMmode. Similarly, the QAC, DAC, and MSC respectively require8.80 kJ/MVA, 4.2 kJ/MVA, and 3.15 kJ/MVA in STATCOMmode. Moreover, in STATCOMmode, the MSC’s Upper Outer and Lower Outer are not required. Meanwhile, the∆-MMC232requires 7.96 kJ/MVA. Hence less energy storage is required for the proposed converters, exceptthe QAC, for normal operation. For active power support during faults, such reductions donot hold.Due to their reduced normal-operation energy storage requirements—and in the casesof the TH3LC and H5LC, their improved efficiency compared to the HBSM-MMC—theseconverters should be thoroughly analyzed to determine their aptitude as grid-connectedSTATCOMs.8.3.4 VSC-HVDC Scale DC/DC ConvertersWith the increasing number of HVDC transmission links, there will be an increasing desireto combine the transmission networks of offshore VSC-HVDC schemes as well as point-to-point HVDC schemes, which will improve the proliferation of e.g., wind power into the grid.However, there is not yet a standardized DC-side voltage at which VSC-HVDC convertersoperate. Moreover, LCC-HVDC technology uses constantly varying DC voltages to regulateits power flow. VSC-HVDC scale DC/DC converters can rectify the issue of interconnectingisolated DC networks of different DC-side voltages. Front-to-front VSC-HVDC convertersseparated by an interfacing transformer, i.e., in a configuration known as a dual-active bridge,can serve this purpose due to their high controllability and reasonably high efficiency. However,two full-sized converters are required for such schemes.Using a single VSC-HVDC-scale converter to perform the DC/DC conversion would bea more efficient solution both spatially and in regard to semiconductor losses. A modifiedversion of the MMC has been proposed [103] to fit this need, which clamps its three-phaseAC-side outputs together. Although electrical isolation is not provided in such a scheme, theefficiency of DC/DC conversion is improved. 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Marquardt, “New transformerless, scalable modular multilevelconverters for hvdc-transmission,” in 2008 IEEE Power Electronics Specialists Conference,pp. 174–179, 2008.[109] ABB semiconductor application notes 5SYA2053-04, “Applying IGBTs,” Sep. 2013.[110] J. Han, L. Bieber, Y. Zhang, L. Wang, W. Li, and J. Belanger, “Detailed equivalent and averagevalue models of hybrid cascaded multilevel converters for efficient and accurate emt-typesimulation,” IEEE Transactions on Power Delivery, vol. 35, no. 6, pp. 2951–2962, 2020.241Appendices242A. Energy StorageRequirements forHybrid CascadedMultilevel ConvertersCorresponding to my accepted conference manuscript titled “A Quantitative Analysis ofEnergy Storage Requirements for Hybrid Cascaded Multilevel Converters” of [82], this chapterfocuses on the overall capacitive energy storage requirements of the H3LC, including the capaci-tive energy storage required by its cascaded FBSMs and DC-side pole capacitors; moreover, theanalysis is extended to the H2LC, briefly presented in Section 1.2.2. The methodology expandsupon what was presented in Chapter 2 and [83] and provides the reader with the numericaland analytical means to derive the expected capacitor ratings for the H3LC and H2LC.In this section, derivations of the general energy storage requirements of the differentcircuit structures (i.e., the DC-side pole capacitors and the cascaded FBSMs) will be shown.A.1 Nominal Energy Storage CalculationThe nominal amount of capacitive energy storage that a capacitive element requires canbe calculated by first determining its peak-to-peak energy deviation and then specifying theallowable amount of voltage ripple. For an ideal capacitor, the nominal energy, Ec,nom, is givenat the nominal voltage, Vc,nom, asEc,nom =12CcV2c,nom. (A.1)A positive voltage deviation,∆Vc, causes a positive energy deviation,∆Ec,up, while an equaland opposite negative voltage deviation,∆Vc, results in a negative energy deviation,∆Ec,down,i.e.,Ec,nom +∆Ec,up =12Cc(Vc,nom(1+∆Vc))2, (A.2)Ec,nom −∆Ec,down = 12Cc(Vc,nom(1−∆Vc).)2 (A.3)243where∆Vc denotes the per-unit change in voltage (e.g.,∆Vc = 0.1 pu). It is noted that∆Ec,up 6=∆Ec,down.The subtraction of (A.2) by (A.3) nets the peak-to-peak energy deviation,∆Ec, of a capacitorthat is assumed to vary between a positive and negative voltage deviation of∆Vc as∆Ec = 2CcV2c,nom∆Vc, (A.4)where∆Ec = ∆Ec,up +∆Ec,down. (A.5)Hence, the peak-to-peak energy deviation of a capacitor is related to its capacitance, Cc,its nominal voltage, Vc,nom, and its per-unit voltage deviation. Substitution of (A.4) into (A.1)producesEc,nom =∆Ec4∆Vc. (A.6)Equation (A.6) suggests that the energy storage of a capacitor is proportional to its peak-to-peak energy deviation over the allowable per-unit voltage deviation, where the peak-to-peakenergy deviation,∆Ec, may be determined analytically or numerically through the cumulativeintegration of the power through the capacitor. In the case of converters with discrete switchingevents, which have nth order harmonics for n→∞, numerical methods provide high accuracy.The numerical calculation of∆Ec is derived by the cumulative integration of the powerthrough the capacitor, i.e., the instantaneous voltage of the capacitor multiplied by the instanta-neous current flowing through it. That is,∆Ec = max(∫ t0Vc(τ)ic(τ) dτ)−min(∫ t0Vc(τ)ic(τ) dτ). (A.7)In (A.7), it is noted that Vc(τ) is approximated to be constant when a simple discrete244capacitor is considered. For the aforementioned cascaded FBSMs, Vc(τ) is a variable parameter,determined by the voltage that the cascaded FBSMs generate.For a fair comparison between converters, it is conducive to represent the peak-to-peakenergy deviation,∆Ec, as a normalized quantity to the apparent power, S, of the system, i.e.,∆Ec [81], [104]. To obtain the normalized energy deviation irrespective of the operatingfrequency, (A.7) may be multiplied by ω, where ω is the test frequency. Therefore,∆Ec =ω∆EcS(A.8)or, equivalently,∆Ec =1S·[max(∫ θ0Vc(ρ)ic(ρ) dρ)−min(∫ θ0Vc(ρ)ic(ρ) dρ)](A.9)whereρ =τω(A.10)and θ ∈ [0, 2pi].With (A.8), (A.6) may be modified to give the normalized nominal energy byEc,nom =∆Ec4∆Vc, (A.11)or,Ec,nom =∆Ecω4S∆Vc. (A.12)A.2 Capacitor SizingIn this section, a general equation is provided for the simple sizing of either discretecapacitors or the capacitors within the converters’ SMs. With (A.6), the capacitance of a DCside245pole capacitor, or of a single SM, is derived as follows. By substitution of (A.6) into (A.1),the component’s capacitance is given in terms of the energy deviation, voltage deviation, andnominal voltage asCc =∆Ec2∆VcV 2c,nom. (A.13)It is noted in (A.13) that Vc,nom corresponds to the nominal voltage of either (1) a pole capacitor,or (2) the summation of all of the voltages across all the SMs’ capacitors contained within astack of cascaded SMs. Therefore, forNSM SMs per stack, each of voltage VSM,nom, Vc,nom maybe replaced by Vc,nom = NSMVSM,nom asCc =∆Ec2∆Vc(NSMVSM,nom)2 . (A.14)Assuming that the energy contained withinNSM SMs is equivalent to that contained withina single equivalent capacitor of voltage Veq, nom = NSMVSM,nom and capacitanceCeq, the followingis derived:NSM2CSMV2SM,nom =12CeqV2eq,nom,=12Ceq(NSMVSM,nom)2, (A.15)⇒ CSM = NSMCeq, (A.16)where (A.16) implies that the equivalent capacitance of NSM SMs is Ceq =CSMNSM. Therefore,each SM’s capacitance for a per-unit voltage deviation of∆VSM is given asCSM =∆Ec2∆VSMNSMV 2SM,nom(A.17)Although the subscript SM suggests that (A.17) is valid for only SMs, the case of pole capacitors246++vu CuClIDCIDCvlv3LC,av3LC,bv3LC,cvFB,avbvavcFBSM FBSMFBSM FBSMFBSM FBSMTu,a Tu,b Tu,cTl,a Tl,b Tl,ciuiconv,uiaibiciconv,lilFig. A.1. The hybrid three-level converter.corresponds toNSM = 1 with VSM,nom being the capacitor voltage. For clarity, it is noted that∆Ec in (A.17) is the total peak-to-peak energy deviation of allNSM SMs.A.3 Energy Storage Sizing of the H3LCIn this section, the energy requirements for the H3LC in Figs. A.1 and 2.1 are derivednumerically. The H3LC’s control and operating principle was discussed at length in Chapter 2and hence will not be reiterated herein. For the reader’s reference, example voltage waveformsof the H3LC are given in Fig. A.2. The topology of the H3LC in Fig. A.1 does not include the“Protection Branches” of Fig. 2.1 nor the inductances, since this chapter focuses only on thenormal-operation energy storage requirements; for the energy storage requirements throughoutDC-side fault scenarios, additional parameters affect the energy storage requirements, such asthe time-until-detection of the DC fault as well as the AC- and DC-side inductances.A.3.1 DC-Side Pole Capacitor Energy Storage SizingFrom Fig. A.1, the upper and lower-position pole capacitors’ energy storage requirementsare calculated under the assumption of constant voltages, vu and vl. The energy of the polecapacitors, across which the DC-side voltage of VDC is applied, is computed numerically overthe H3LC’s nominal operating range. As the H3LC is designed for a maximum voltage of24700piωt (rad)2piv3LC,a(t)−V1hsin(ωt)v3LC,a(t)−V1hsin(ωt)−V3hsin(3ωt)(a)(b)α1Without 3rd Order HarmonicWith 3rd Order Harmonic02pi−α2pi−α1 pi+α2v3LC,a(t)V1hsin(ωt)V3hsin(3ωt)VDC12VDC12−VDC14pi23pi2VDC14−Fig. A.2. Example voltage waveforms of the H3LC.V max1h = 0.63VDC (see Section 2.2.1), its nominal operating voltage corresponds to a levelenabling 10% headroom, i.e.,V nom1h =11.10.63VDC = 0.573VDC. (A.18)A 10% reduction in the nominal value defines the H3LC’s minimum normal-operation operat-ing voltage asV min1h = 0.9Vnom1h = 0.515VDC, (A.19)giving the nominal operating range of the H3LC asV1h ∈ [0.515VDC, 0.63VDC]. (A.20)The mean voltages across the pole capacitors as well as the mean value of the DC-sidecurrent are used for this analysis. Since the H3LC has symmetrical operation, its currents iuand il flowing through the upper and lower pole capacitors are identical except for a phase-shiftof pi/3. Due to the phase-shifted capacitor currents, the energy deviations of the upper andlower pole capacitors — and consequently, their voltage deviations — are also phase-shifted by248pi/3. Hence, the sum of the pole capacitors’ instantaneous voltage deviations is smaller thantheir voltage deviations individually.For the DC-side voltage, a voltage ripple of±5% is the typical allowable value. Below, thepole capacitors’ energy requirements will be calculated under the two conditions: (1) The totalpole-to-pole voltage has a 5% allowable ripple, and (2) The individual pole capacitor voltageshave a 5% ripple.A.3.1.1 Calculation for 5% Pole-to-Pole Voltage RippleFirst, we assume that the pole-to-pole DC-side voltage has a 5% allowable voltage ripple.From the normalized cumulative integration presented in (A.9), the instantaneous energydeviation at the power factor angle ϕ of the upper and lower pole capacitors,∆Eul, is inspectedto gain the normalized energy deviation:∆Eul(ϕ) =1S·[max(∫ θ0vuiu(ρ, ϕ) + vlil(ρ, ϕ) dρ)−min(∫ θ0vuiu(ρ, ϕ) + vlil(ρ, ϕ) dρ)], (A.21)where vu and vl are the mean voltages of the upper and lower capacitor voltages, vu and vl, andare assumed constant cycle-to-cycle and ρ is defined in (A.10). From Fig. A.1, iu and il aredetermined asiu(t, ϕ) = iDC(ϕ)− iconv,u(t, ϕ), (A.22)il(t, ϕ) = iDC(ϕ) + iconv,l(t, ϕ), (A.23)where iDC(ϕ) =S cos(ϕ)vu + vlis assumed to be a constant DC current, dependent on the powerfactor angle, while iconv,u and iconv,l are the currents entering the converter, as in Fig. A.1.The current iconv,u and iconv,l are the summations of all of the currents entering the upperDS and lower DS, respectively, of each phase. As an example, the current entering the phase-a249upper DS is iTu,a(t, ϕ) = ia(t, ϕ) when Tu,a ≡ 1, whereij(t, ϕ) = iˆAC sin(ωt+ φj − ϕ), (A.24)where iˆAC is the peak value of the balanced three-phase sinusoidal currents, ij (j ∈ {a, b, c}).Conversely, iTu,a(t) = 0 while Tu,a ≡ 0. Therefore, the upper converter current, iconv,u is theresult of the dot-product of the upper DS switching states and the phase currents:iconv,u(t, ϕ) =Tu,aTu,bTu,c ·iˆAC sin(ωt− ϕ)iˆAC sin(ωt− 2pi/3− ϕ)iˆAC sin(ωt+ 2pi/3− ϕ). (A.25)Similarly, for iconv,l:iconv,l(t, ϕ) =Tl,aTl,bTl,c ·iˆAC sin(ωt− ϕ)iˆAC sin(ωt− 2pi/3− ϕ)iˆAC sin(ωt+ 2pi/3− ϕ). (A.26)By varying the values of V1h ∈ [0.515VDC, 0.63VDC] andϕ ∈ [0, pi/2], but keepingS constant,(A.25) and (A.26) are used to solve (A.21) for theH3LC’s entire nominal operating range. Doingso results in a three-dimensional plot of the H3LC’s energy storage requirements on the rangeV1h ∈ (A.20) and ϕ ∈ [0, pi/2]. The plot is presented in Fig. A.3, wherein the allowable pole-to-pole voltage deviation was set at∆vul = 0.05 pu. Ten evenly spaced values of V1h and ϕ arealso presented in Table A.1.A.3.1.2 Calculation for 5% Individual Pole Capacitor Voltage RippleFor this analysis, it is assumed that the upper and lower pole capacitors individually areallotted a ±5% voltage ripple. Therefore, the calculation of only the upper pole capacitor’senergy storage requirements is necessary, since its energy deviation equals the lower polecapacitor’s with a phase-shift. The instantaneous energy deviation of the upper pole capacitor,2500.520.540.560.580.60.62 00.20.40.60.8100.20.40.6AC voltage, V1h (×VDC) Power factor, cos(ϕ)Normalizedenergystorage( J·radVA·s)Fig. A.3. The normalized energy contained within the two DC-side pole capacitors of the H3LC with5% DC-side voltage deviation.∆Eu, is inspected to gain the instantaneous normalized energy deviation at each ϕ:∆Eu(ϕ) =1S·[max(∫ θ0vuiu(ρ, ϕ) dρ)−min(∫ θ0vuiu(ρ, ϕ) dρ)], (A.27)where iu is given in (A.25).Using (A.22) and (A.25) gives the upper pole capacitor’s current. The results of the numericalanalysis are shown in Figs. A.4 and Table A.2, where the allowable voltage deviation was set to∆vu = 0.05 pu. The results show that the energy stored within the H3LC’s DC pole capacitorhas a strong dependence on both the power factor as well as the operating voltage, with ageneral trend of increasing energy storage requirements with a reduced operating voltage anda worsening power factor.A.3.2 Cascaded FBSM Energy Storage SizingWith the cascaded FBSM voltage derivation as in (2.4), (A.9) may be used with the substitu-tion of Vc(ρ) = vFB,a(ρ), wherein the nominal energy of each phase is identical such that the cal-2510.520.540.560.580.60.62 00.20.40.60.810123AC voltage, V1h (×VDC) Power factor, cos(ϕ)Normalizedenergystorage( J·radVA·s)Fig. A.4. The normalized energy contained within the two pole capacitors of the H3LC when eachcapacitor is allotted a 5% voltage ripple.culation can be applied to only phase-a. The same operating range of V1h ∈ [0.515VDC, 0.63VDC]is evaluated. For the phase-a cascaded FBSMs, ic(ρ) = ia(ρ, ϕ). The normalized cascadedFBSM energy deviation and nominal energy are respectively found by (A.28) and (A.11), andthe results are shown in Fig. A.5. It is noted that compared to the pole capacitors’ 5%, theFBSM capacitors are allotted the more flexible voltage deviation of∆Vc = 10%.∆EFB,a(ϕ) =1S·[max(∫ θ0vFB,a(ρ)ia(ρ, ϕ) dρ)−min(∫ θ0vFB,a(ρ)ia(ρ, ϕ) dρ)]. (A.28)The results shown in Fig. A.5 show that the H3LC’s cascaded FBSMs’ total energy decreaseswith an increasing operating voltage until the H3LC is operated near its maximal voltages,whereupon the cascaded FBSM energy increases rapidly. Therefore, limiting the H3LC’smaximum operating voltage to V max1h = 0.62VDC results in smaller sizing of its cascaded FBSMs.It is noted that compared to the pole capacitors, redundant SMs are typically used in stacksof cascaded SM such that the individual SMs’ capacitor voltage ripple does not appear in theoutput voltage.2520.520.540.560.580.60.62 00.20.40.60.810.10.20.30.4AC voltage, V1h (×VDC) Power factor, cos(ϕ)Normalizedenergystorage( J·radVA·s)Fig. A.5. Normalized energy of phase-a of the H3LC’s cascaded FBSMs.A.3.3 Total Energy Storage SizingLastly, a summation of the energy storage requirements of the cascaded FBSMs and thepole capacitor is shown under the two cases for the sizing of the DC-side pole capacitors. Itis noted that the normalized energy of Fig. A.5 corresponds to only one phase; therefore, itis required for three times the cascaded FBSM normalized energy to be added to the polenormalized energy. The results are shown in Figs. A.6 and A.7 and show a general trendthat as the operating voltage increases, the normalized energy storage reduces. Hence theH3LC benefits from operating near its maximal voltage where not only are its energy storagerequirements minimized, but its efficiency is improved.Comparing Figs. A.6 and A.7 reveals that the DC-side pole capacitors’ complementaryoperation results in significantly lower pole-to-pole energy deviation than comparing thepole capacitors’ energy deviations separately. Values of the energy deviations are presented inTables A.1 and A.2.2530.520.540.560.580.60.62 00.20.40.60.81123AC voltage, V1h (×VDC) Power factor, cos(ϕ)Normalizedenergystorage( J·radVA·s)Fig. A.6. The total normalized energy required by the H3LC across its nominal operating range whenthe DC pole-to-pole voltage ripple is set at 5%.0.520.540.560.580.60.62 00.20.40.60.81123AC voltage, V1h (×VDC) Power factor, cos(ϕ)Normalizedenergystorage( J·radVA·s)Fig. A.7. The total normalized energy required by the H3LC across its nominal operating range wheneach pole capacitor’s voltage ripple is set at 5%.254TABLE A.1H3LC’s Total Normalized Energy(J · radVA · s)for 5%DC-Side Voltage RippleOperating Voltage, V1h (×VDC)0.515 0.528 0.541 0.554 0.566 0.579 0.592 0.605 0.617 0.63PowerFactor1.0 0.953 0.779 0.617 0.497 0.509 0.554 0.55 0.477 0.33 1.290.985 0.952 0.813 0.712 0.623 0.596 0.563 0.542 0.471 0.348 1.3020.94 0.996 0.928 0.858 0.79 0.75 0.7 0.631 0.528 0.402 1.2970.866 1.071 1.03 0.986 0.938 0.883 0.816 0.728 0.6 0.455 1.2590.766 1.123 1.106 1.088 1.059 0.989 0.908 0.803 0.658 0.499 1.220.643 1.193 1.159 1.159 1.149 1.065 0.971 0.855 0.698 0.532 1.2710.5 1.231 1.217 1.202 1.205 1.11 1.005 0.881 0.717 0.549 1.2840.342 1.235 1.239 1.244 1.225 1.12 1.009 0.88 0.715 0.552 1.260.174 1.203 1.225 1.249 1.243 1.097 0.982 0.853 0.691 0.539 1.1970 1.136 1.175 1.218 1.226 1.064 0.925 0.8 0.648 0.51 1.099TABLE A.2H3LC’s Total Normalized Energy(J · radVA · s)for 5%DC-Side Pole Capacitor VoltageRippleOperating Voltage, V1h (×VDC)0.515 0.528 0.541 0.554 0.566 0.579 0.592 0.605 0.617 0.63PowerFactor1.0 1.919 1.66 1.418 1.214 1.075 0.932 0.774 0.58 0.353 1.290.985 2.016 1.759 1.559 1.37 1.191 1.065 0.944 0.78 0.577 1.4340.94 2.301 2.112 1.919 1.736 1.612 1.476 1.315 1.112 0.854 1.5570.866 2.62 2.481 2.338 2.192 2.037 1.866 1.67 1.426 1.116 1.640.766 2.894 2.804 2.712 2.603 2.417 2.214 1.985 1.704 1.349 1.7090.643 3.149 3.068 3.02 2.948 2.734 2.504 2.246 1.935 1.544 1.8540.5 3.327 3.29 3.253 3.214 2.976 2.723 2.443 2.11 1.694 1.9440.342 3.418 3.425 3.432 3.389 3.133 2.863 2.569 2.223 1.793 1.9750.174 3.416 3.464 3.515 3.503 3.2 2.92 2.619 2.271 1.84 1.9470 3.321 3.408 3.498 3.519 3.198 2.892 2.592 2.251 1.831 1.861255-FBSMTwo-Level ConverterCascaded FBSMsFBSMFBSMFBSMFBSM+-v2LC,cv2LC,bv2LC,a vavFB,avbvcS2S1S4S3FBSMFBSMTu,a Tu,b Tu,cTl,a Tl,b Tl,cIDC iconv,uicapCcapiaibicFig. A.8. The hybrid two-level converter alongside the topology of a FBSM.With 3rd Order HarmonicWithout 3rd Order Harmonicv2LC,a(t)−V1hsin(ωt)v2LC,a(t)−V1hsin(ωt)−V3hsin(3ωt)v2LC,a(t)V1hsin(ωt)V3hsin(3ωt)(a)(b)πωt (rad)2π0 π23π200VDC12VDC12−VDC12VDC12−Fig. A.9. H2LC operational figures.A.4 Energy Storage Sizing of the H2LCTo compare the H2LC against the H3LC, this section presents similar analysis as aboveapplied to the H2LC of Fig. A.8.The voltages presented by both the two-level converter portion and the cascaded FBSMsare shown respectively in Figs. A.9 (a) and (b). The two-level voltage, v2LC,j (j ∈ {a, b, c}) is256defined by the switching angle α, such thatV1h =4pi(cos(α)− 12)VDC, (A.29)α = cos−1(pi4V1hVDC+12). (A.30)where V1h is the fundamental component of the two-level voltage. Therefore, the phase-avoltage to be generated by the cascaded FBSM, vFB,a is given by the same equation as in (2.4),where the third-order harmonic, V3h is derived differently than the H3LC’s and is given by [74]asV3h =−4V 2DCV1hpi2 + 4piVDC. (A.31)Since the H2LC reaches the slightly higher maximum operating voltage of V1h = 2piVDC, itsoperating range is defined asV1h ∈[0.52VDC,2piVDC]. (A.32)A.4.1 DC-Side Pole Capacitor Energy Storage SizingWithout the midpoint connection, the H2LC only uses one DC-side pole capacitor thatspans the DC-side such that (A.9) is modified by Vc(ρ) = VDC. The capacitor current for theH2LC, icap, is derived the same as the H3LC’s upper capacitor current, iu, in (A.22). Hence,ic = icap, where iconv,u is given by the same definition as in (A.25). The normalized energy ofthe H2LC’s pole capacitor is shown in Fig. A.10, wherein a similar trend to the H3LC is seen asthe required energy storage decreases with an increasing operating voltage.2570.540.560.580.60.62 00.20.40.60.8100.511.52AC voltage, V1h (×VDC) Power factor, cos(ϕ)Normalizedenergystorage( J·radVA·s)Fig. A.10. Normalized energy of the H2LC’s DC pole capacitor.A.4.2 Cascaded FBSM Energy Storage SizingWith the cascaded FBSM voltage derivation as in (A.28), (A.9) may be used with thesubstitution of Vc(ρ) = vFB,a(ρ), wherevFB,a(t) = v2LC,a(t)− V1h sin(ωt)− V3h sin(3ωt), (A.33)as in Fig. A.9. The same operating range of V1h ∈[0.52VDC,2VDCpi]is tested. The H2LC’scascaded FBSM normalized energy storage is presented in Fig. A.11.The results shown in Fig. A.11 indicate that an opposite trend is seen for the energy storagerequirements of the cascaded FBSMs compared to the pole capacitor. With an increasingoutput voltage, it is required that the cascaded FBSM is sized continually larger.A.4.3 Total Energy Storage SizingLastly, a summation of the energy storage requirements of the cascaded FBSMs and theDC-side pole capacitor is shown. Again, it is noted that the normalized energy of Fig. A.112580.540.560.580.60.62 00.20.40.60.810.60.8AC voltage, V1h (×VDC) Power factor, cos(ϕ)Normalizedenergystorage( J·radVA·s)Fig. A.11. Normalized energy of the phase-a cascaded FBSMs of the H2LC.corresponds to only one phase. Therefore, it is required for three times the cascaded FBSMnormalized energy to be added to the pole normalized energy. The results are shown inFig. A.12 which indicate that, although the H2LC’s most efficient operating point is at itsmaximum operating voltage, i.e., when the phase current is minimized, the operating voltagethat corresponds to the least amount of energy storage is at the minimum operating voltage ofV1h = 0.52VDC. Values of the H2LC’s total energy deviations are also presented numerically inTable A.3.A.5 DiscussionSome of the most well-known multilevel converters are the MMC [36], [44]–[46] and theAAC [63], [65]–[67]. Three-dimensional plots of the normalized energy storage requirementsof the MMC over its operating range V1h ∈[0.471VDC,√33VDC]and the extended-overlapalternate-arm converter (EO-AAC) over the range V1h ∈ [0.6VDC, 0.733VDC] are presented. Itis noted that the EO-AAC uses triangular triplen harmonic injection [67]; for this analysis, thesame triangular harmonic is used.2590.540.560.580.60.62 00.20.40.60.81234AC voltage, V1h (×VDC) Power factor, cos(ϕ)Normalizedenergystorage( J·radVA·s)Fig. A.12. Total normalized energy that the H2LC requires for varying V1h and ϕ.Thenormalized energy storage requirements of theMMC and the EO-AAC on the specifiedranges are shown in Figs. A.13 and A.14, respectively. By a significant margin, the H3LC’s totalnormalized energy is smaller than either the MMC’s or the EO-AAC’s. It is noted that theMMC’s energy requirements show a decreasing trend as the operating voltage approaches itsmaximum and as the power factor approaches unity. Hence, for a smaller physical size, theMMC should be operatedwith a high voltage and power factor. TheEO-AAC, on the other hand,shows increasing normalized energy requirements as the voltage increases, suggesting thatthe operating point corresponding to its smallest physical size is below its nominal operatingrange.It is noted that throughout this analysis, no actual values of energy storage are given— onlythe normalized values. This is because these converters may be commissioned under variableoperating conditions. Using theJ · radVA · s nomenclature enables the designer to multiply thenormalized energy by the system three-phase power (e.g., 1 GVA), and divide by the systemfrequency, in radians (e.g., 2pi · 50 rad) to ascertain the real-world value of the converters’energy storages.2600.480.50.520.540.56 00.20.40.60.8146810AC voltage, V1h (×VDC) Power factor, cos(ϕ)Normalizedenergystorage( J·radVA·s)Fig. A.13. The total normalized energy required by the MMC.0.60.620.640.660.680.70.72 00.20.40.60.81345AC voltage, V1h (×VDC) Power factor, cos(ϕ)Normalizedenergystorage( J·radVA·s)Fig. A.14. The total normalized energy required by the EO-AAC.261TABLE A.3H2LC’s Total Normalized Energy(J · radVA · s)Operating Voltage, V1h (×VDC)0.521 0.534 0.547 0.559 0.572 0.585 0.598 0.611 0.624 0.637PowerFactor1.0 1.678 1.772 1.855 1.924 1.984 2.03 2.062 2.077 2.065 2.0520.985 1.844 1.89 1.934 1.968 1.999 2.023 2.037 2.049 2.063 2.0720.94 2.307 2.251 2.197 2.139 2.113 2.108 2.09 2.062 2.021 2.0930.866 2.733 2.655 2.581 2.504 2.43 2.359 2.284 2.212 2.14 2.4420.766 3.076 2.979 2.886 2.793 2.704 2.62 2.535 2.455 2.379 2.7950.643 3.326 3.213 3.104 2.997 2.897 2.802 2.708 2.623 2.545 3.0630.5 3.547 3.348 3.228 3.11 3.002 2.899 2.8 2.711 2.634 3.240.342 3.738 3.432 3.253 3.129 3.015 2.908 2.806 2.717 2.643 3.3180.174 3.816 3.503 3.191 3.053 2.937 2.829 2.727 2.641 2.571 3.2960 3.778 3.467 3.157 2.884 2.771 2.663 2.565 2.484 2.422 3.174A.6 ConclusionThis chapter presented a methodology of calculating the energy storage requirements fortwo hybrid multilevel converters — the H2LC and the H3LC. Another analysis showing theMMC’s and EO-AAC’s energy storage requirements was also presented. Compared to the otherconverters, the H3LC’s energy storage requirements are significantly reduced, as presented inFig. A.6 and Table A.1, especially when a 5% peak-to-peak voltage ripple for the DC-side isdesired.Equations for the nominal energy storage requirements for one pole capacitor or cascadedFBSM— both in real units and normalized — as well as their capacitor requirements weregiven throughout this chapter. Equations of the reference voltages and the capacitor currentsfor the H2LC and H3LC were provided, which enabled their energy storage requirements to beplotted for varying values of V1h and ϕ in 3-D plots. The 3-D plots enabled the effects that avarying operating voltage and power factor have on the energy storage requirements for theconverters’ cascaded FBSMs and pole capacitors to be readily visualized.262B. Analytical Semiconductor Conduction and Switch-ing Loss Calculation for H3LCIn this chapter, the analytical means to calculate the semiconductor losses of the H3LC arepresented in detail. The methodology proposed is applicable to other converters as well, andis applied to the EO-AAC [67] in Section B.4. Analytically calculating the semiconductors’conduction and switching losses enables their losses to be programmatically estimated overthe converters’ entire operating range and varying power levels, which improves the overalldesign-to-commissioning time for converters.The per-phase topology of the H3LC is given in Fig. B.1 and Table B.1 presents the currentsthrough the DSs and FBSMs. In Table B.1, it is noted that the polarity of the phase current, ij ,influences which of the DS currents of Fig. B.1 are zero and which carry the load current.V1h =2picos(α)VDC, (B.1)⇒ α = cos−1(pi2V1hVDC). (B.2)B.1 Semiconductor Conduction Loss CalculationIn general, the average conduction loss of a semiconductor device depends on its instanta-neous voltage and current. For IGBTs and diodes, the average conduction losses are derivedasPcond,T =12pi∫ 2pi0iC(ρ)vCE(iC(ρ)) dρ, (B.3)Pcond,D =12pi∫ 2pi0iF(ρ)vF(iF(ρ)) dρ. (B.4)The analytical semiconductor conduction loss derivations of this chapter are based upon the methodsproposed in the accepted conference paper, [87], whereas the analytical switching loss methods are in theto-be-submitted paper, [105].263vjtTu,jTl,jvFB, jijIDCVDCvuvlTm,jFBSM FBSMiu,jiu,jim,jil,jil,jv3LC,jvSMvc+S4S2S3S1+ij++UpperDSMidpointDSLowerDSFig. B.1. A per-phase illustration of the hybrid three-level converter (H3LC).In (B.3) and (B.4): Pcond,T and Pcond,D are the average conduction losses over a fundamentalfrequency cycle, 2pi, for the IGBT and diode, respectively; iC and iF are the instantaneous IGBTcollector and diode forward currents; and vCE(iC(ρ)) and vF(iF(ρ)) are the IGBT’s and diode’son-state voltage drops at their instantaneous currents.Using the widely adopted methods of [106]–[109], the nonlinearities of vCE(iC(ρ)) andvF(iF(ρ)) can be approximated by their piece-wise linear expressions, which use their sloperesistances (RT and RD) and threshold voltages (VT0 and VD0). References [106]–[108] showthat (B.3) and (B.4) can be approximated byPcond,T ≈ 12pi∫ 2pi0iC(ρ)VT0 + i2C(ρ)RT dρ, (B.5)Pcond,D ≈ 12pi∫ 2pi0iF(ρ)VD0 + i2F(ρ)RD dρ, (B.6)wherevCE(iC(ρ)) ≈ VT0 + iC(ρ)RT, (B.7)vF(iF(ρ)) ≈ VD0 + iF(ρ)RD. (B.8)Since (B.5) and (B.6) effectively produce the average conduction losses of an IGBT or diode264TABLE B.1Director Switch CurrentsDS CurrentsPolarity i+u,j i−u,j im,j i+l,j i−l,jij > 0 ij 0 ij 0 ijij < 0 0 −ij ij −ij 0over a fundamental cycle, 2pi, the IGBT and diode currents may be replaced by their averageand RMS values asPcond,T = iC,avgVT0 + i2C,RMSRT, (B.9)Pcond,D = iF,avgVD0 + i2F,RMSRD. (B.10)For the calculation of the average and RMS IGBT and diode currents in (B.9) and (B.10), thecurrents through the IGBT and diode are complementary, i.e., whenever one is conductingcurrent, the other is blocked.The following analysis is performed on the semiconductors of only phase-a, which producesidentical results for the other phases. Hence, the variables referring to the average or RMSvalues omit the phase variable for improved readability.The phase current used for this chapter, ij , is defined asij(t) = iˆAC sin(ωt+ φj − ϕ), (B.11)where iˆAC is the peak AC-side converter current, φj ∈{0,−2pi3, 2pi3}refers to the three-phasebalanced phase-shifts, and ϕ is the power factor angle and is determined from the measuredreal and reactive powers, P andQ, as ϕ = tan−1(QP). With S =√P 2 +Q2 and V1h known,iˆAC is calculated asiˆAC =23SV1h. (B.12)Since the H3LC’s three phases have symmetric operation, the entirety of the analysis265focuses on the H3LC’s phase-a, such that the per-phase losses are multiplied by three to givethe converter’s total losses.B.1.1 Upper and Lower DS Semiconductor Conduction LossesDepending on the power factor angle,ϕ, the average and RMS values of the currents flowingthrough the IGBT portions of the Upper and Lower DSs, i.e., i+u,j and i+l,j , do not equal thoseof the currents flowing through the diode portions, i.e., i−u,j and i−l,j . With the IGBT and diodehaving different threshold voltages and slope resistances, the power factor angle ϕ influencesthe total conduction losses. As an example, for real power with unity power factor in invertermode, a large V1h (and small α angle) will result in the DSs’ IGBTs conducting significantlylonger than the diodes. This is because when V1h is close to 0.63VDC, the H3LC’s MidpointDSs conduct for very short intervals; hence, almost all the current flows through the Upperand Lower DSs’ IGBTs — since real power with ϕ = 0 means only i+u,j and i+l,j conduct whilei−u,j and i−l,j are zero.The Upper and Lower DSs conduct only on the intervals ωt ∈ (α, pi − α) and ωt ∈(pi+α, 2pi−α), respectively; theMidpoint DSs conduct for all other ωt, i.e., for ωt ∈ [−α, α]∪[pi − α, pi + α]. It is noted that for sinusoidal and periodic phase current, ij , the average andRMS values of i+u,j and i+l,j are equivalent; the same is true for i−u,j and i−l,j . Hence, the conductionlosses of the Upper and Lower DSs are equivalent by (B.9) and (B.10). Therefore, only thephase-a Upper DS is analyzed.The average and RMS values of the IGBT and diode currents of the phase-a Upper DSdepend on ϕ for the following four cases:Case (1): The current flowing through Tu,a is positive for the entire on-time. Hence, the currentflows only through the IGBTs such that only i+u,a is non-zero. That is ϕ ∈ [−α, α].Case (2): The current begins negative (diode) and finishes positive (IGBT). That is, for ϕ ∈[α, pi − α], the current flows through the Upper phase-aDS’s diode for ωt ∈ [α, ϕ]and then through the IGBT for ωt ∈ [ϕ, pi − α].266Case (3): The current flowing through Tu,a is negative for the entire DS on-time. Hence, thecurrent flows only through the diodes such that only i−u,a is non-zero. Hence, forCase (3), ϕ ∈ [pi − α, pi + α].Case (4): The current begins positive (IGBT) and finishes negative (diode). That is, for ϕ ∈ [pi+α, 2pi−α, the current flows first throughphase-a’sUpperDS’s IGBT forωt ∈ [α, ϕ−pi]and then through the diode for ωt ∈ [ϕ− pi, pi − α].For Cases (2) and (4), the average and RMS IGBT and diode currents are calculated separately.Table B.1 presents the UpperDS IGBT and diode currents, i.e., i+u,j and i−u,j , as well as the Lower(i+l,j and i−l,j) and Midpoint (im,j) DS currents.Case (1)⇒ ϕ ∈ [−α, α]:When ia > 0 for all ωt ∈ (α, pi − α), then ϕ ∈ [−α, α]. Fig. B.2 presents a sample currentfor Case (1) with ϕ ∈ [−α, α]. Hence, the Upper DS current flows only through the IGBTsuch that i−u,j ≡ 0 for this range. For these ϕ, the average and RMS currents for the positivehalf-cycle are calculated asi+u,avg =1pi∫ pi−ααia(t) dωt=2ˆiACpicos(α) cos(ϕ), (B.13)i+u,RMS =√1pi∫ pi−ααi2a(t) dωt=iˆAC√2pi√sin(2α) cos(2ϕ)− 2α + pi. (B.14)Hence, the semiconductor conduction losses for the Upper (and Lower) DS are given asPcond,DS = i+u,avgV+u + i2+u,RMSR+u , (B.15)267v3LC,aCase (1)ϕpiωt (rad) 2pi2pi −αpi +αpi −αα0021pi 23pi21VDCiACˆiACˆ−21VDC−Fig. B.2. Example current waveform for phase-a with ϕ angles corresponding to Case (1).whereV +u = VT0Nul, R+u = RTNul, (B.16)andNul = VDC/Vref (B.17)is the number of series-connected IGBT modules, each with the rated voltage Vref, within theupper and lower DSs to give them their rated blocking voltage of VDC, as in Table 2.1. Hence,in (B.16), V +u and R+u are the sum of the threshold voltages and slope resistances of the totalnumber of series-connected IGBT modules that compose a single DS.Case (2)⇒ ϕ ∈ [α, pi − α]:When the power factor angle is ϕ ∈ [α, pi − α], the Upper DS current begins negative andthen becomes positive before pi − α, as shown in Fig. B.3, which shows a sample current withϕ ∈ [α, pi − α]. For the negative portion, ωt ∈ (α, ϕ), the average and RMS diode currents are268calculated asi−u,avg = −1pi∫ ϕαia(t) dωt=iˆACpi(1− cos(ϕ− α)), (B.18)i−u,RMS =√1pi∫ ϕαi2a(t) dωt=iˆAC2√pi√sin(2(α− ϕ)) + 2(ϕ− α). (B.19)For the positive portion, i.e., ωt ∈ (ϕ, pi−α), we calculate the average and RMS IGBT currentsasi+u,avg =1pi∫ pi−αϕia(t) dωt=iˆACpi(1+ cos(ϕ+ α)), (B.20)i+u,RMS =√1pi∫ pi−αϕi2a(t) dωt=iˆAC2√pi√sin(2(ϕ+ α)) + 2(pi − ϕ− α). (B.21)For the currents with superscript “−”, the Upper DS current flows through the diode such thatwe derive V −u and R−u asV −u = VD0Nul, R−u = RDNul, . (B.22)The conduction loss calculation now has both an IGBT and diode component such that theUpper and Lower DS conduction losses are given byPcond,DS = i−u,avgV−u + i2−u,RMSR−u + i+u,avgV+u + i2+u,RMSR+u . (B.23)269piCase (2)ωt (rad) 2pi2pi −αpi +αpi −αα0021pi 23pi21VDCiACˆiACˆ−21VDC−ϕv3LC,aFig. B.3. Example current waveform for phase-a with ϕ angles corresponding to Case (2).Case (3)⇒ ϕ ∈ [pi − α, pi + α]:Case (3) matches Case (1) with a change in polarity; the amplitudes are the same. Hence,when the Upper DS current flows only through the diode, the average and RMS currents aregiven byi−u,avg = −1pi∫ pi−ααia(t) dωt= − 2ˆiACpicos(α) cos(ϕ), (B.24)i−u,RMS =√1pi∫ pi−ααi2a(t) dωt,=iˆAC√2pi√sin(2α) cos(2ϕ)− 2α + pi, (B.25)Since Case (3) corresponds to only diode current, (B.22) provides V −u andR−u such that theconduction losses are given byPcond,DS = i−u,avgV−u + i2−u,RMSR−u . (B.26)Fig. B.4 presents a sample current with ϕ(3) ∈ [pi − α, pi + α].270Case (3)ϕv3LC,apiωt (rad) 2pi2pi −αpi +αpi −αα0021pi 23pi21VDCiACˆiACˆ−21VDC−Fig. B.4. Example current waveform for phase-a with ϕ angles corresponding to Case (3).Case (4)⇒ ϕ ∈ [pi + α, 2pi − α]:When the DS current is first positive and then becomes negative, i.e., whenϕ ∈ [pi+α, 2pi−α], the average and RMS IGBT and diode currents of Case (2) are modified such that thepositive average and RMS IGBT currents on the interval ωt ∈ (α, ϕ− pi) becomei+u,avg =1pi∫ ϕ−piαia(t) dωt=iˆACpi(1+ cos(ϕ− α)), (B.27)i+u,RMS =√1pi∫ ϕ−piαi2a(t) dωt=iˆAC2√pi√sin(2(α− ϕ)) + 2(ϕ− pi − α). (B.28)For the negative portion, ωt ∈ (ϕ− pi, pi − α), the average and RMS diode currents arei−u,avg = −1pi∫ pi−αϕ−piia(t) dωt=iˆACpi(1− cos(ϕ+ α)) (B.29)i−u,RMS =√1pi∫ pi−αϕ−pii2a(t) dωt=iˆAC2√pi√sin(2(ϕ+ α)) + 2(2pi − ϕ− α). (B.30)271Case (4)ϕv3LC,apiωt (rad) 2pi2pi −αpi +αpi −αα0021pi 23pi21VDCiACˆiACˆ−21VDC−Fig. B.5. Example current waveform for phase-a with ϕ angles corresponding to Case (4).Equation (B.23) holds for the Upper and Lower DS conduction power losses. Fig. B.5 presentsa sample current with ϕ ∈ [pi + α, 2pi − α].B.1.2 Midpoint DS Semiconductor Conduction LossesFor the Midpoint DSs, i.e., Tm,j of Fig. B.1, the anti-series IGBT modules always conductwith both IGBTs and diodes such that the polarity of the current is not important. Theconduction losses for the Midpoint DSs are tested on the interval ωt ∈ (−α, α), whichaccounts for half of their on-time. The Midpoint DSs’ RMS current for all power factor angles,ϕ, is calculated asim,RMS =√1pi∫ α−αi2a(t) dωt=iˆAC√2pi√2α− sin(2α) cos(2ϕ). (B.31)If the current through the Midpoint DSs reverses polarity on ωt ∈ (−α, α), we calculatethe mean of the absolute value of the current over each of the positive and negative portionsand sum them together. Hence, there are four cases again:272Case (1)⇒ ϕ ∈ [−α, α]:For ϕ ∈ [−α, α], the current is negative for ωt ∈ (−α, ϕ) and positive for ωt ∈ (ϕ, α).Hence, the average current isim,avg =1pi(−∫ ϕ−αia(t) dωt+∫ αϕia(t) dωt)=2ˆiACpi(1− cos(α) cos(ϕ)). (B.32)Case (2)⇒ ϕ ∈ [α, pi − α]:For ϕ ∈ [α, pi − α], the current is negative for ωt ∈ (−α, α) such thatim,avg = − 1pi∫ α−αia(t) dωt=2ˆiACpisin(α) sin(ϕ). (B.33)Case (3)⇒ ϕ ∈ [pi − α, pi + α]:For ϕ ∈ [pi − α, pi + α], the current is positive for ωt ∈ (−α, ϕ − pi) and is negative forωt ∈ (ϕ− pi, α) such thatim,avg =1pi(∫ ϕ−pi−αia(t) dωt−∫ αϕ−piia(t) dωt)=2ˆiACpi(1+ cos(α) cos(ϕ)). (B.34)273Case (4)⇒ ϕ ∈ [pi + α, 2pi − α]:Lastly, for ϕ ∈ [pi + α, 2pi − α], the average absolute value of the current is identical to(B.33) with the pi phase-shift. Hence,im,avg =1pi∫ α−αia(t) dωt= − 2ˆiACpisin(α) sin(ϕ). (B.35)For all the preceding cases, the conduction losses of the Midpoint DSs are given byPcond,DS = im,avgVm + i2m,RMSRm, (B.36)whereVm =(VD0 + VT0)VDC2Vref, Rm =(RD +RT)VDC2Vref. (B.37)B.1.3 Cascaded FBSM Semiconductor Conduction LossesBeing connected to the AC-side, the currents ij of Fig. B.1 continually flow through therespective FBSMs at all times. Although the proportion of IGBTs conducting compared todiodes varies with the power factor, it is assumed herein that ij flows through the FBSMs’ IGBTsand diodes equally. This approximation is valid since 1) vFB,a of Fig. 2.3 takes both negative andpositive values for each half-cycle, for approximately equal intervals, and 2) bypassed FBSMshave both a diode and IGBT in the conduction path at all times.Hence, the on-state semiconductor conduction losses of theNSM FBSMs is presented asPcond,FB = iavgVFB + i2RMSRFB, (B.38)274whereVFB = NSM(VT0 + VD0), RFB = NSM(RT +RD),iavg =2piiˆAC, iRMS =1√2iˆAC, and NSM =⌈VDC4Vref⌉.(B.39)In (B.39),NSM is the total number of FBSMs per phase while Vref is the voltage that one FBSMis rated to block, which is taken to be the same as the voltage that one IGBT module is rated toblock, such that four IGBT modules correspond to a single FBSM.For completeness, a derivation for the expression for conduction losses without the assump-tion of current flowing equally through the IGBTs and diodes is provided asPcond,FB =∫ 2pi0|ia(t)|Vtot(t) + i2a(t)Rtot(t) dωt, (B.40)whereVtot(t)=1Vref{[vˆFB,a+sgn(ia(t))vFB,a(t)]VT0 +[vˆFB,a−sgn(ia(t))vFB,a(t)]VD0}, (B.41)Rtot(t)=1Vref{[vˆFB,a+sgn(ia(t))vFB,a(t)]RT +[vˆFB,a−sgn(ia(t))vFB,a(t)]RD}. (B.42)Closed-form solutions of (B.40) exist, although they contain many terms. However, (B.40)to (B.42) can be implemented programmatically.In (B.41) and (B.42), vˆFB,a = 14VDC for the H3LC.The threshold voltages and slope resis-tances are maximally multiplied byVDC2Vrefwhen vFB,a = ±14VDC, which accounts for the twodevices conducting when the cascaded FBSMs are fully inserted positively or negatively. Whenall FBSMs are bypassed, i.e., when vFB,a = 0, the threshold voltages and slope resistances forthe IGBT and diode are each multiplied byVDC4Vref. As will be shown in Section B.3, the FBSMconduction losses obtained from the detailed-equivalent model simulation are essentiallyconstant for all ϕ ∈ [0, 2pi] (assuming constant power, S), such that ϕ negligibly influences theFBSM conduction losses.275B.2 Semiconductor Switching Loss CalculationThe semiconductor switching losses are found by summing together the switching energiesat each transition of the IGBTmodules. The switching losses are divided into the IGBT turn-on,IGBT turn-off, and diode reverse recovery losses, i.e., Pon,T, Poff,T, and Prec,D, respectively. Theswitching energies may be functions of the current and the voltage prior to or after the switchinginstance; for the IGBT turn-on, IGBT turn-off and the diode’s reverse recovery, the energiesare presented as Eon, Eoff, and Erec. Hence, the semiconductor switching losses are representedanalytically asPon,T =12piNi∑i=1Eon(von,T(θiω), iC(θiω)), (B.43)Poff,T =12piNj∑j=1Eoff(voff,T(θjω), iC(θjω)), (B.44)Prec,D =12piNk∑k=1Erec(vrec,D(θkω), iF(θkω)). (B.45)For easily reproducible results and straightforward verification, the switching energies canbe assumed to vary linearly with voltage and current. Hence, a reference voltage and current isused by which the energies can be scaled, which is a well-adopted assumption of [106]–[108].Hence, (B.43) to (B.45) can be approximated asPon,T ≈ 12piEon(Vref, Iref)VrefIrefNi∑i=1von,T(θiω)iC(θiω), (B.46)≈ 12piEonNi∑i=1von,T(θiω)iC(θiω), (B.47)276Poff,T ≈ 12piEoff(Vref, Iref)VrefIrefNj∑j=1voff,T(θjω)iC(θjω), (B.48)≈ 12piEoffNj∑j=1voff,T(θjω)iC(θjω), (B.49)Prec,D ≈ 12piErec(Vref, Iref)VrefIrefNk∑k=1vrec,D(θkω)iF(θkω). (B.50)≈ 12piErecNk∑k=1vrec,D(θkω)iF(θkω), (B.51)In (B.43) to (B.51): θi,j,k correspond to the IGBT turn-on, IGBT turn-off, and diode reverserecovery switching instances, whileNi,j,k are the total numbers of switching instances of each ofthe switching instances within a single 2pi cycle; von,T is the voltage across the IGBT immediatelyprior to the turn-on switching instance, while voff,T and vrec,D are the voltages across the IGBTor diode, respectively, immediately after the turn-off switching instance; iC and iF are theIGBT collector and diode forward currents; Vref and Iref are the reference values of the voltageand current from which the reference energies Eon, Eoff, and Erec are derived. As in (B.47),(B.49) and (B.51), Pon,T, Poff,T, and Prec,D can be simplified under the assumption of constantswitching energies withEγ =Eγ(Vref, Iref)VrefIrefγ ∈ {on, off, rec}. (B.52)B.2.1 Cascaded FBSM Semiconductor Switching LossesFor the phase-j FBSMs, ij of Fig. B.1 flows at all times. Hence, (B.47), (B.49), (B.51)and (B.52) can be applied to the cascaded FBSMs asPsw,FB =12pivcNs∑s=1EFBSM(θsω)∣∣∣∣ij(θsω)∣∣∣∣, (B.53)277where vc is the FBSM capacitor voltage and is assumed to be constant irrespective of turn-onor turn-off; θs is the sth FBSM switching instance; EFBSM(θsω)is the switching loss incurredat each θs, which may take combinations of Eon, Eoff, and Erec; andNs is the total number ofFBSM switching events over a 2pi cycle.Due to the FBSMs’ four discrete switching events per cycle, the switching losses are foundin two parts. They are first calculated under the assumption of a continuous cascaded FBSMvoltage, i.e., with the three-level transitions ignored. Then, they are calculated only at thediscrete three-level switching events of v3LC,a. The results are summed together for the totalcascaded FBSM switching losses.With many FBSMs per phase, as in typical HVDC systems, the instantaneous number ofFBSMs to insert (positively or negatively) or to bypass, Nins,j ∈ Z, is typically provided bythe nearest-level modulation (NLM) method due to its minimal number of switching eventscompared to, e.g., LS-PWM. Without the discrete three-level voltage transitions, Nins,a forphase-a is given with NLM asNins,a(t) = round(v1,3h,a(t)vc), (B.54)wherev1,3h,a(t) = −V1h sin(ωt)− V3h sin(3ωt) (B.55)is vFB,a of (2.4) less v3LC,a.For the ideal switching losses, the SM capacitor voltages are assumed to be infinitesimalsuch that the number of SMs becomes infinitely large. Hence,Nins,a becomesNins,a(t) = limvc→0v1,3h,a(t)vc. (B.56)With infinitesimal capacitor voltages, the rounding function is redundant.278The rate-of-change ofNins,a, gives the instantaneous number of FBSM switching transitionsand is derived asdNins,a(t)dωt= limvc→01vcdv1,3h,adωt⇒ N ′ins,a(t) = limvc→01vc·(−V1h cos(ωt)− 3V3h cos(3ωt)), (B.57)where the cumulative integration of the absolute value ofN ′ins,a,∣∣N ′ins,a∣∣, over a 2pi cycle givesthe total number of switching events.With an infinitesimal vc, the summation operator of (B.53) becomes an integral overωt ∈ [0, 2pi] such that the ideal switching losses for phase-a are found by integrating theabsolute value of the phase current, ia, multiplied byN′ins,a asP(1)sw,FB = limvc→012pivc∫ 2pi0EFBSM(t)∣∣ia(t)N ′ins,a(t)∣∣ dωt=12pi∫ 2pi0EFBSM(t)∣∣ia(t)v′1,3h,a(t)∣∣ dωt (B.58)where limvc→0vcN′ins,a = v′1,3h,a from (B.57) and instantaneous value of EFBSM(t) depends on thetwo criteria:(1) Whether the number of inserted FBSMs is increasing (i.e., becoming increasingly positiveas v′1,3h,a > 0) or decreasing (i.e., becoming increasingly negative as v′1,3h,a < 0).(2) Whether the FBSM current is positive (ia > 0) or negative (ia < 0).When v′1,3h,a and ia have the same polarity, EFBSM = Eoff. For example, if v′1,3h,a > 0 andia > 0, the FBSM transitions from either the negative to the bypassed state, or from thebypassed state to the positive. In either case, either of the S2 or S3 switches of the sample FBSMof Fig. B.1 turn off while current is flowing through them, thereby sustaining Eoff losses; thediodes of the S1 or S4 switches experience lossless turn-on. Conversely, when v′1,3h,a and iahave different polarities, EFBSM = Eon+Erec. If v′1,3h,a > 0 and ia < 0, when either of the S2 or279S3 switches turn off, their diodes will experience reverse recovery loss, while the IGBTs of S1or S4 experience turn-on loss.Equation (B.58) can be simplified such that the regions of constant polarity of iav′1,3h,a, i.e.,between its zero-crossings, are calculated separately:P(1)sw,FB =12piNr∑r=1EFBSM(Ψrω)(f(t)∣∣∣θr+1/ωt=θr/ω), (B.59)wheref(t) = sgn(ia(t)v′1,3h,a(t)) ∫ia(t)v′1,3h,a(t) dωt⇒ f(t) = iˆAC8sgn(ia(t)v′1,3h,a(t))(V1h(4 sin(ϕ)ωt+ 2 cos(ϕ− 2ωt))+ V3h(3 cos(ϕ− 4ωt)− 6 cos(ϕ+ 2ωt))). (B.60)In (B.59): Ψr ∈ (θr, θr+1) is any element within the rth region between the θrω andθr+1ωzero crossings of iav′1,3h,a;Nr is the total number of discrete regions of constant polarity; andEFBSM(Ψrω)is the type of switching loss incurred over the rth region, such thatEFBSM(t) =Eoff ia(t)v′1,3h,a(t) > 0,Eon+Erec ia(t)v′1,3h,a(t) < 0.(B.61)The polarity of iav′1,3h,a at the initial instance, θ1 = 0 — and therefore the value of EFBSM(t) onthe first interval of (B.59) between θ1 and θ2 — depends on ia(0) = − sin(ϕ) and v′1,3h,a(0)),which itself depends on the value of V1h asv′1,3h,a(0) < 0 ⇒ V1h ∈ {(0.232VDC, 0.287VDC) ∪ (0.402VDC, 0.63VDC)} (B.62)v′1,3h,a(0) > 0 ⇒ V1h ∈ {(0, 0.232VDC) ∪ (0.334VDC, 0.402VDC)} (B.63)280Moreover, iav′1,3h,a has either two or four zero crossings in the positive half-cycle, corre-sponding toNr = 5 andNr = 9 in (B.59), which is determined by the operating voltage, V1h,or more specifically, the value of V3h of (2.6), which varies nonlinearly with V1h. If v′1,3h,a hasconstant polarity on ωt ∈ [0, pi/2), then the zero crossings of iav′1,3h,a are at ωt = {ϕ±kpi, pi/2},k ∈ Z. However, if v′1,3h,a changes polarity on ωt ∈ [0, pi/2), the zero crossings of iav′1,3h,a are atωt = {ϕ± kpi, pi/2, β, pi − β}, whereβ = cos−1(√−3V3h(V1h − 9V3h)6V3h). (B.64)Where β is a real-valued function yields the ranges ofV1h that iav′1,3h,a has four zero crossings,asV1h ∈ [0, 0.232VDC] ∪ [0.334VDC, 0.402VDC] ∪ [0.603VDC, 0.630VDC]; (B.65)all other values of V1h correspond to only two zero crossings on the positive half-cycle. Thezero-crossings are presented asia(t)v′1,3h,a(t) = 0⇒ωt ={ϕ, pi/2} ϕ ∈ [0, pi) ∧ V1h /∈ (B.65),{ϕ−pi, pi/2} ϕ ∈ [pi, 2pi) ∧ V1h /∈ (B.65),{ϕ, pi/2, β, pi−β} ϕ ∈ [0, pi) ∧ V1h ∈ (B.65),{ϕ−pi, pi/2, β, pi−β} ϕ ∈ [pi, 2pi) ∧ V1h ∈ (B.65).(B.66)As an example, the FBSM switching losses are presented below for the ranges of V1h with twozero crossings for iav′1,3h,a andwith negative initial polarity of v′1,3h,a, i.e., the values ofV1h given in(B.62). Hence, the following example considers the voltages V1h ∈ (0.402VDC, 0.603VDC). Thereare four ranges of ϕ angles to consider for determining the switching losses. For the following281calculations, the half-wave symmetry of the voltages and currents enables the switching lossesto be calculated on the positive half cycle, i.e., ωt ∈ [0, pi), with the result multiplied by two.Case (I)⇒ ϕ ∈ [0, pi/2]:For ϕ ∈ [0, pi/2], the initial polarity of iav′1,3h,a, i.e., at ωt = 0, is positive such thatia(t)v′1,3h,a(t) > 0 for ωt ∈ (0, ϕ). Hence, until the next zero-crossing at ωt = ϕ, Eoff losses areincurred, from (B.61). Next, for ωt ∈ (ϕ, pi/2), iav′1,3h,a becomes negative, such that Eon+Ereclosses are incurred. The next (and last, for the positive half-cycle) zero-crossing is at ωt = pi/2such that for ωt ∈ (pi/2, pi), iav′1,3h,a is again positive for Eoff losses. Hence, the closed-formswitching loss calculation for the phase-a FBSMs for the power factor angles ϕ ∈ [0, pi/2] isgiven byP(1)sw,FB =1pi(f(t)∣∣∣ϕ/ω0Eoff + f(t)∣∣∣pi/(2ω)ϕ/ω(Eon+Erec) + f(t)∣∣∣pi/ωpi/(2ω)Eoff), (B.67)Case (II)⇒ ϕ ∈ [pi/2, pi]:When ϕ ∈ [pi/2, pi], the switching losses are derived asP(1)sw,FB =1pi(f(t)∣∣∣pi/(2ω)0Eoff + f(t)∣∣∣ϕ/ωpi/(2ω)(Eon+Erec) + f(t)∣∣∣pi/ωϕ/ωEoff). (B.68)Case (III)⇒ ϕ ∈ [pi, 3pi/2]:For ϕ ∈ [pi, 3pi/2], the ϕ angle is subtracted by pi compared to Case (I), as specified in(B.66), and the Eoff and Eon+Erec losses are interchanged, asP(1)sw,FB =1pi(f(t)∣∣∣(ϕ−pi)/ω0(Eon+Erec) + f(t)∣∣∣pi/(2ω)(ϕ−pi)/ωEoff + f(t)∣∣∣pi/ωpi/(2ω)(Eon+Erec)). (B.69)282TABLE B.2Summary of Equations to Find DSs’ Average and RMS Currents and to Find DSs’ andFBs’ Power LossesAverage and RMS DS Currents Conduction and Switching LossesΦ ϕ ∈ i+u,avg i−u,avg i+u,RMS i−u,RMS im,avg im,RMS Pcond,DS Pcond,FB Psw,DS Psw,FBΦ1 [0, α] (B.13) 0 (B.14) 0 (B.32) (B.31) 3×((B.15)+(B.36)) 3×(B.38) 3×(B.81) 3×((B.75)+(B.67))Φ2[α, pi/2](B.20) (B.18) (B.21) (B.19) (B.33) (B.31) 3×((B.23)+(B.36)) 3×(B.38) 3×(B.82) 3×((B.76)+(B.67))[pi/2, pi − α] 3×((B.76)+(B.68))Φ3[pi − α, pi]0 (B.24) 0 (B.25) (B.34) (B.31) 3×((B.26)+(B.36)) 3×(B.38) 3×(B.83) 3×((B.77)+(B.68))[pi, pi+α] 3×((B.77)+(B.69))Φ4[pi+α, 3pi/2](B.27) (B.29) (B.28) (B.30) (B.35) (B.31) 3×((B.23)+(B.36)) 3×(B.38) 3×(B.84) 3×((B.78)+(B.69))[3pi/2, 2pi − α] 3×((B.78)+(B.70))Φ1 [2pi − α, 2pi] (B.13) 0 (B.14) 0 (B.32) (B.31) 3×((B.15)+(B.36)) 3×(B.38) 3×(B.81) 3×((B.75)+(B.70))Case (IV)⇒ ϕ ∈ [3pi/2, 2pi]:Lastly, for ϕ ∈ [3pi/2, 2pi], the FBSMs’ switching losses are given asP(1)sw,FB =1pi(f(t)∣∣∣pi/(2ω)0(Eon+Erec) + f(t)∣∣∣(ϕ−pi)/ωpi/(2ω)Eoff + f(t)∣∣∣pi/ω(ϕ−pi)/ω(Eon+Erec)). (B.70)B.2.1.1 Discrete Switching EventsNext, the discrete switching events atΨα ∈ {α, pi−α, pi+α, 2pi−α} are considered by wayof modifying (B.58) and (B.59). Instead of using the continuous portion of vFB,a, i.e., v1,3h,a, thediscontinuous portion, i.e., v3LC,a = vFB,a − v1,3h,a, is substituted into (B.58) and (B.59) asP(2)sw,FB =12pi4∑r=1EFBSM(Ψα,rω)(f(t)∣∣∣(Ψα,r+ 2 )/ωt=(Ψα,r− 2)/ω), (B.71)wheref(t) = sgn(ia(t)v′3LC,a(t)) ∫ia(t)v′3LC,a(t) dωt. (B.72)In (B.71) and (B.72): Ψr,α refers to the rth element ofΨα, i.e., the rth discrete switching event ofvFB,a;  is the rise/fall time of v3LC,a (in radians), such that v′3LC,a is defined as283v′3LC,a(t) =VDC2ωt ∈{[α− 2, α +2],[2pi−α− 2, 2pi−α + 2]},−VDC2ωt ∈{[pi−α− 2, pi−α + 2],[pi + α− 2, pi + α +2]},0 else;(B.73)and EFBSM is defined the same as in (B.61) with the replacement of v′1,3h,a = v′3LC,a.In (B.71) and (B.73), the limit as  → 0 can be taken such that f(t) of (B.72) may beevaluated at one point. Hence, (B.71) and (B.72) becomeb (B.74)Only the positive half-cycle needs to be considered, with the result being multiplied by two.Hence, the FBSM switching losses are represented below over varying ranges of ϕ asP(2)sw,FB =VDC2pi×Eoffia(αω)+ (Eon+Erec)ia(pi−αω)ϕ ∈ Φ1,(Eon+Erec)(−ia(αω)+ ia(pi−αω))ϕ ∈ Φ2,− (Eon+Erec)ia(αω)− Eoffia(pi−αω)ϕ ∈ Φ3,Eoff(ia(αω)− ia(pi−αω))ϕ ∈ Φ4,(B.75)(B.76)(B.77)(B.78)where Φ1 ∈ [−α, α], Φ2 ∈ [α, pi − α], Φ3 ∈ [pi − α, pi + α], and Φ4 ∈ [pi + α, 2pi − α] corre-spond to Cases (1) to (4) of Section B.1.1, as in Table B.2.The FBSMs’ total switching loss per phase is given by Psw,FB = P(1)sw,FB + P(2)sw,FB.284B.2.2 DS Semiconductor Switching LossesThe DSs’ switching losses are calculated similarly to the FBSMs’ in ?? with a differentdefinition of EDS compared to EFBSM. Hence, the losses may be represented asPsw,DS =12pi4∑r=1EDS(Ψα,rω)f(Ψα,rω), (B.79)with the same definitions of Ψr,α and f(t) as above. However, the discrete loss, i.e., EDS, isdefined asEDS(t) =Eon+Erec ia(t)v′3LC,a(t) > 0,Eoff ia(t)v′3LC,a(t) < 0.(B.80)Hence, the DS switching losses are calculated asPsw,DS =VDC2pi×(Eon+Erec)ia(αω)+ Eoffia(pi−αω)ϕ ∈ Φ1,Eoff(−ia(αω)+ ia(pi−αω))ϕ ∈ Φ2,− Eoffia(αω)− (Eon+Erec)ia(pi−αω)ϕ ∈ Φ3,(Eon+Erec)(ia(αω)− ia(pi−αω))ϕ ∈ Φ4.(B.81)(B.82)(B.83)(B.84)In Table B.2, a summary is presented of the applicable Upper and Midpoint DSs’ averageand RMS currents as well as the applicable equations referenced throughout the chapter todetermine the semiconductor conduction power losses for the DSs and FBSMs. The totalconverter semiconductor conduction losses are determined by the summation of the last twocolumns of Table B.2, where the specific equations are multiplied by 3, i.e., 3×, to include thelosses from the other two phases, since the power losses for only phase-a were derived.285B.3 Comparison to Detailed-Equivalent ModelIn this section, theH3LC’s semiconductor losses are calculated using the detailed-equivalentmodel (DEM) as derived in [110] with 256 FBSMs per phase. The results are compared againstthe analytical loss method proposed in this chapter. For verification of the proposed method,two values of V1h are chosen, and at each voltage the power factor angle ϕ is varied in pi/4increments in the range ϕ ∈ [0, 2pi].The H3LC is assumed to transmit a maximum apparent power of Smax = 1GVA with themaximum and minimum reactive powers of Qmax = 500MVAR and Qmin = −700MVAR.Hence, for a desired power factor angle, ϕ, ifQ exceeds these bounds, then S = Q/ sin(ϕ) andP = Q/ tan(ϕ); otherwise,Q = Smax sin(ϕ) and P = Smax cos(ϕ).The DEM test system of the H3LC is simulated in the MATLAB/Simulink 2020b environ-ment with the Simscape/Specialized Power Systems toolbox. The H3LC’s DC-side terminalsare connected to a 600 kV DC source through DC cables. The impedance of the DC cables issmall such that varying iDC only negligibly affects the H3LC’s DC-side voltage, VDC. The realand reactive powers, P andQ, are measured on the converter-side of the transformer, i.e., vjt ofFig. B.1, such that ϕ = tan−1(P/Q) gives the correct power factor angle, ϕ. For the followingDEM simulation tests, maintaining the desired operating voltages, V1h, was accomplishedby varying the grid voltage after each change in P and Q. The simulated H3LC losses arecalculated with the same switching-based loss calculation method as in [83].The Westcode T1800GB45A [90] IGBT module is used for the following analysis. Theconduction loss calculations use the approximations of (B.5) and (B.6), wherein Table B.3presents the slope resistances (RT and RD) and threshold voltages (VT0 and VD0) of the IGBTand diode. The reference voltage and current used are Vref = 2.5 kV and Iref = 1.8 kA,respectively, at which the switching energiesEon,Eoff, andErec are approximately 11 J, 11 J, and2.8 J. Equation (B.52) gives the values of Eon, Eoff, and Erec asThe first operating voltage tested is V1h = 0.5VDC, where the results for the simulated H3LCmodel are compared with the proposed analytical method in Fig. B.6. Fig. B.6 shows the286TABLE B.3Semiconductor ParametersRT = 1.21mΩ RD = 1.07mΩ VT0 = 1.82VVD0 = 2.27V Vref = 2.5 kV Iref = 1.8 kAEon = 2.44µJVAEoff = 2.44µJVAErec = 0.64µJVA810126420Losses (MW)Ptotalproposed PtotalDEM Pcond,DSproposed Pcond,DSDEM Pcond,FBDEMPcond,FBproposedPsw,DSproposed Psw,DSDEM Psw,FBproposed Psw,FBDEMϕ (rad) 2pipi0 23pi21piFig. B.6. Comparison between the proposed analytical loss method and the DEM at V1h = 0.5VDC atthe maximum apparent power of Smax = 1GVA withQ boundsQmax andQmin for ϕ ∈ [0, 2pi).cascaded FBSMs’ and DSs’ conduction, switching, and total losses of both the proposedmethod,i.e., the continuous lines of Fig. B.6, and of the DEM, i.e., the scattered circles. The proposedmethod is instantiated 600 times over the range of ϕ ∈ [0, 2pi) to generate the continuouscurves. At the simulated values of ϕ, the proposed method shows exceptional agreement withthe DEM.The largest relative errors for the FBSMs’ conduction and switching losses are 0.16%and 0.46%, respectively. For the DSs’ conduction and switching losses, the largest relativeerrors are 0.44% and 0.16%, respectively.The next voltage tested is V1h = 0.575VDC. Fig. B.7 presents the results, wherein exceptionalaccuracy is again seen. The highest relative errors for the FBSMs’ conduction and switchinglosses are, respectively, 0.17% and 0.76%. For the DSs’ conduction and switching losses,the highest relative errors are 0.11% and 0.50%, respectively. This further validates that theproposed method produces reliable results.The continuous curves of Figs. B.6 and B.7 are cross-sections of the generated 3D plot287ϕ (rad) 86420Losses (MW)Ptotalproposed PtotalDEM Pcond,DSproposed Pcond,DSDEM Pcond,FBDEMPcond,FBproposedPsw,DSproposed Psw,DSDEM Psw,FBproposed Psw,FBDEM2pipi0 23pi21piFig. B.7. The proposed analytical loss method compared to the DEM at V1h = 0.575VDC at themaximum apparent power of Smax = 1GVA withQ boundsQmax andQmin for ϕ ∈ [0, 2pi).in Fig. B.8, which assumes the same maximum apparent power Smax = 1GVA under thebounds ofQmin = −700MVAR andQmax = 500MVAR. Fig. B.8 presents a range of 200 evenlyspaced operating voltages, V1h ∈ [0.5VDC, 0.63VDC], at 600 evenly spaced power factor angles,ϕ ∈ [0, 2pi), for a total of 120, 000 data points. Hence, Fig. B.8 demonstrates the flexibility ofthe proposed method to generate highly detailed results .Moreover, the proposed method can quickly produce remarkably reliable results over theH3LC’s entire operating range. For the DEM tested here with 256 FBSMs per phase, simulatinga single 50Hz took 3.39 s with an Intel Xeon E5-2560 CPU at 2.00GHz. Calculating the losses ateach of the 120, 000 points tested within Fig. B.8 would take the DEM, minimally, an estimated406, 320 s, i.e., approximately 5 days. Conversely, the proposed method took only 28.47 s tocalculate all 120, 000 data points. Hence, the proposed method provides results approximately14,000-fold quicker than the DEM.B.4 Application to the EO-AACTo show that the derived analytical loss calculation methods can be applied to otherconverter topologies, the analytical losses of the EO-AAC [67] are provided herein as furtherproof of the methods. The EO-AAC uses cascaded FBSMs on the DC-side in series withDSs to generate sinusoidal line-to-line voltages. An important feature of the EO-AAC is thezero-voltage switching (ZVS) of its DSs and low arm inductance. Triangular triplen harmonic2880.50.520.540.560.580.60.620pi2pi3pi22pi468AC voltage, V1h (×VDC)Power factor angle, ϕSemiconductorlosses(MW)Fig. B.8. The total semiconductor losses of the H3LC on V1h ∈ [0.5VDC, 0.63VDC] and ϕ ∈ [0, 2pi).voltage injection with k3 = 0.5 is used to bound the peak arm and DS voltages within 23VDC asin [67]. The EO-AAC’s optimal operating voltage is at V1h = 23VDC, which enables zero-currentswitching (ZCS) of the DSs, continuous arm currents, and an equivalent voltage rating for theDSs and cascaded FBSMs; hence, this chapter considers V1h = 23VDC as the operating voltage.It is noted that the following analysis is performed on the Upper arm of phase-a, with the finalresults being multiplied by six.The phase-a Upper arm current, iu, is piece-wise continuous when V1h = 23VDC and isdefined over the 2pi interval ωt ∈ [−pi/6, 11pi/6], as in [67], asiu(t) =iDC − ic(t) ωt ∈ [−pi/6, pi/6),ia(t) ωt ∈ [pi/6, 5pi/6),iDC − ib(t) ωt ∈ [5pi/6, 7pi/6),0 ωt ∈ [7pi/6, 11pi/6).(B.85)289The phase-a Upper arm voltage, vu, is defined for k3 = 0.5 asvu(t) =12VDC − (v1h(t) + vtri(t)) ωt ∈ [−pi/6, 7pi/6),23VDC ωt ∈ [7pi/6, 11pi/6),(B.86)where v1h(t) = V1h sin(ωt), vtri(t) = 14V1htri(3ωt), and tri(3ωt) is the triangle function withpeak values±1.With both ZVS and ZCS enabled for its DSs at V1h = 23VDC, the EO-AAC’s DS switchinglosses can be considered negligible.B.4.1 Cascaded FBSM Semiconductor Conduction LossesThe FBSM conduction losses of the EO-AAC are found with the same expression as theH3LC, i.e., (B.38), with the average and RMS currents found asiu,avg =12pi∫ 11pi/6−pi/6|iu(t)| dωt, (B.87)iu,RMS =√12pi∫ 11pi/6−pi/6i2u(t) dωt, (B.88)with Von = N(VT0 + VD0), Ron = N(RT +RD), andN =⌈2VDC3Vref⌉.B.4.2 DS Semiconductor Conduction LossesSimilar to the DSs of the H3LC, the EO-AAC’s DSs experience notably different conductionlosses depending on the polarity of the arm current. The positive and negative DS currents, i+uand i−u , are complementary and defined as i+u = iu for all iu > 0 and i−u = −iu for all iu < 0.290Hence, the average and RMS values for the positive and negative DS currents are derived asi+u,avg =12pi∫ 11pi/6−pi/6i+u (t) dωt, (B.89)i−u,avg =12pi∫ 11pi/6−pi/6i−u (t) dωt, (B.90)i+u,RMS =√12pi∫ 11pi/6−pi/6i2+u (t) dωt, (B.91)i−u,RMS =√12pi∫ 11pi/6−pi/6i2−u (t) dωt. (B.92)The conduction loss calculation of (B.23) holds for the EO-AAC’s DSs. However, theparameters are changed as V +u =2VT0VDC3Vref, V −u =2VD0VDC3Vref, R+u =2RTVDC3Vref, and R−u =2RDVDC3Vref.B.4.3 Cascaded FBSM Semiconductor Switching LossesUnder the assumption of many FBSMs, Psw,FB of (B.59) holds for the EO-AAC as it does forthe H3LC, but its nomenclature changes toPsw,FB =12piNr∑r=1EFBSM,u(Ψrω)(f(t)∣∣∣θr+1/ωt=θr/ω), (B.93)wheref(t) = sgn(iu(t)v′u(t))∫iu(t)v′u(t) dωt. (B.94)For the assumption of the EO-AAC operating at its optimal operating of V1h = 23VDC, v′u(t)is negative for ωt ∈ [−pi/6, pi/2) and positive for ωt ∈ [pi/2, 7pi/6) and has a zero-crossing atωt = pi/2.Meanwhile, the zero-crossings of iu depend on the power factor angle, ϕ, and the piece-wisedefinition of iu. If ϕ ∈ (pi/6, 5pi/6), the zero-crossings of iu are the same as the phase current,i.e., at ωt = kpi + ϕ, since iu(t) = iˆAC sin(ωt− ϕ) on ωt ∈ (pi/6, 5pi/6).291For ωt ∈ [−pi/6, pi/6) ∪ (5pi/6, 7pi/6], iu can be defined for operation at V1h = 23VDC asiu(t) =iˆAC(cos(ϕ)− sin(ωt− 2pi3− ϕ)), ωt ∈[−pi6,pi6),iˆAC(cos(ϕ)− sin(ωt+2pi3− ϕ)), ωt ∈(5pi6,7pi6].(B.95)Equation (B.95) has zero-crossings at ωt = −pi/6 + 2ϕ for ωt ∈ [−pi/6, pi/6) and at ωt =−5pi/6 + 2ϕ for ωt ∈ (5pi/6, 7pi/6]. Therefore, iu has zero-crossings on ωt ∈ [−pi/6, pi/6)when ϕ ∈ [kpi, kpi + pi/6] and zero-crossings on ωt ∈ (5pi/6, 7pi/6] when ϕ ∈ [kpi + 5pi/6, kpi].Therefore, in total, the zero-crossings of iu(t)v′u(t) are given byiu(t)v′u(t) = 0⇒ωt ∈{ϕ+ kpi,pi2+ kpi}ϕ ∈[pi6+ kpi,5pi6+ kpi),{−pi6+ 2ϕ+ kpi,pi2+ kpi}ϕ ∈[kpi,pi6+ kpi),{−5pi6+ 2ϕ+ kpi,pi2+ kpi}ϕ ∈[5pi6+ kpi, kpi).(B.96)For each region of constant polarity between the zero-crossings of iu(t)v′u(t), closed-formsolutions exist for the calculation of f(t) of (B.94). However, the solutions on each regioninvolve many terms. Therefore, the closed-form solutions of the cases of (B.87) to (B.94) forvarying V1h and ϕ are not presented herein.B.4.4 Comparison to Detailed-Equivalent ModelBy numerically solving (B.85) to (B.94) at V1h = 23VDC and VDC = 600 kV, Fig. B.9 presentsthe semiconductor conduction and switching losses of the EO-AAC at the same real andreactive powers as in Section B.3. That is, ϕ is swept over [0, 2pi) while the reactive poweris limited to within Qmin = −700MVAR and Qmax = 500MVAR. Fig. B.9 shows that theproposed analytical method produces results that very closely match that of the EO-AAC’s29286420Losses (MW)Ptotalproposed PtotalDEM Pcond,DSproposed Pcond,DSDEM Pcond,FBDEMPcond,FBproposedPsw,FBproposed Psw,FBDEMϕ (rad) 2pipi0 23pi21piFig. B.9. Comparison of the EO-AAC’s DEM at V1h =23VDC at the maximum apparent power ofSmax = 1GVA withQ boundsQmax andQmin for ϕ ∈ [0, 2pi).DEM, with the worst relative error of 0.94%. Hence, the analytical method proposed in thischapter can easily be applied to other VSC-HVDC converter topologies.For the IGBT module considered [90], the results presented in Fig. B.9 show that the EO-AAC has similar total losses to the H3LC atϕ = 0 and V1h = 0.575VDC, where the H3LC’s lossesare 6.30MW at ϕ = 0 and the EO-AAC’s are 6.47MW. However, the EO-AAC has improvedlosses when operated as a STATCOM,with losses of 2.39MWcompared to theH3LC’s 3.18MW.Hence, the EO-AAC may be better suited for high reactive power applications.The losses for 200 evenly spaced voltages V1h ∈[0.53VDC, 23VDC]at 600 evenly spacedpower factor angles ϕ ∈ [0, 2pi) are presented in Fig. B.10, wherein this range of voltagesapproximately represents the EO-AAC’s Upper 20% of operating voltages. The apparent poweris the same as in Fig. B.6 to B.8 with Smax = 1GVA under the bounds ofQmin = −700MVARandQmax = 500MVAR.B.5 ConclusionThis chapter proposed an analytical method to rapidly calculate the semiconductor powerlosses for VSC-HVDC converters. The method was applied to the proposed H3LC topologyas well as to the EO-AAC topology. Mathematical expressions were derived throughout thechapter to provide the average and RMS currents flowing through the H3LC’s DSs’ IGBTs and2930.540.560.580.60.620.640.660pi2pi3pi22pi2468AC voltage, V1h (×VDC)Power factor angle, ϕSemiconductorlosses(MW)Fig. B.10. The total semiconductor losses of the EO-AAC for the ranges V1h ∈[0.53VDC, 23VDC]andϕ ∈ [0, 2pi).diodes at all power factor angles, ϕ. The resulting expressions are summarized in Table B.2,which also presents expressions for the semiconductor conduction and switching losses forthe H3LC’s DSs and cascaded FBSMs at varying values of ϕ. The proposed method displayedexceptional agreement with the results obtained from the DEM of the H3LC, with the worst-case relative error of only 0.76%. The methods were also applied to the EO-AAC, althoughclosed-form solutions were not provided. The method again showed high agreement withthe EO-AAC’s DEM, with a maximum relative error of 0.94%. The method takes as inputs:the converters’ real and reactive powers on the converter-side of the AC-side terminals forstraightforward calculation of ϕ; the pole-to-pole DC voltage, VDC; the operating voltage, V1h;and the semiconductor on-state and switching parameters. The proposed analytical conductionand switching loss calculation method is the first of its kind for hybrid converters such as theH3LC and EO-AAC, and will help to improve the design-to-implementation time of suchprojects.294
Thesis/Dissertation
eng
Electrical Engineering
Vancouver : University of British Columbia Library
Attribution-NonCommercial-NoDerivatives 4.0 International
Graduate
Wang, Liwei
Jatskevich, Juri
DC-fault tolerant multilevel voltage source converters with hybrid and multiplexed-arm structures for high voltage direct current applications
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