Applied Science, Faculty of
Engineering, School of (Okanagan)
DSpace
UBCO
Dadashzadeh, Hoda
Master of Applied Science - MASc
University of British Columbia
Wireless Power Transfer (WPT) system has the advantage of delivering power through a medium without using physical conductors to make an electrical connection. Two categories of WPT systems are Inductive Power Transfer (IPT) and Capacitive Power Transfer (CPT). In this thesis, the focus is on CPT. The work is motivated by challenges associated with obtaining efficient power transfer over relatively large gaps ranging from a few centimeters up to 20 cm. A dual-band CPT system is proposed that operates at frequencies of 13.56 MHz and 27.12 MHz. Depending on the gap distance, a specific frequency is selected. The primary focus in this research is the design of the high efficiency power amplifiers and rectifiers that are required to implement the dual-band system. The class-E circuit topology is selected for the designs. The theory of time-reversal duality is applied to convert the power amplifier circuits into synchronous rectifier circuits. The rectifier converts the Radio Frequency (RF) power to DC power and the rectification efficiency depends on load resistance. A variable load circuit board is implemented using a DC-DC power converter to track the maximum power efficiency of the rectifier. A buck converter is selected for the design and duty cycle is used to change the input resistance of the converter. In the last part of this work, the power amplifiers and the rectifiers are connected to a capacitive coupling network with an adjustable load resistance. The power and efficiency of the CPT system is simulated for gap distances ranging from 5 cm to 20 cm. Simulation results show that for maintaining high efficiency operation of the CPT the system, it needs to operate at 27.12 MHz for small gap separations and the frequency is switched to 13.56 MHz for larger gap separations.
Design and Implementation ofClass-E Power Amplifiersand Rectifiers for a Dual-BandCapacitive Wireless PowerTransfer SystembyHoda DadashzadehA THESIS SUBMITTED IN PARTIAL FULFILLMENT OFTHE REQUIREMENTS FOR THE DEGREE OFMASTER OF APPLIED SCIENCEinThe College of Graduate Studies(Electrical Engineering)THE UNIVERSITY OF BRITISH COLUMBIA(Okanagan)February 2022© Hoda Dadashzadeh 2022The following individuals certify that they have read, and recommendto the College of Graduate Studies for acceptance, a thesis/dissertation en-titled:Design and Implementation of Class-E Power Amplifiers andRectifiers for a Dual-Band Capacitive Wireless Power Trans-fer Systemsubmitted by Hoda Dadashzadeh in partial fulfilment of the requirementsof the degree of Master of Applied Science in Electrical Engineering.Dr. Thomas Johnson, Faculty of Applied ScienceSupervisorDr. Lo¨ıc Markley, Faculty of Applied ScienceSupervisory Committee MemberDr. Mohammad Hossein Zarifi, Faculty of Applied ScienceSupervisory Committee MemberDr. Alyse Hawley, Faculty of Applied ScienceUniversity ExamineriiAbstractWireless Power Transfer (WPT) system has the advantage of deliveringpower through a medium without using physical conductors to make anelectrical connection. Two categories of WPT systems are Inductive PowerTransfer (IPT) and Capacitive Power Transfer (CPT). In this thesis, thefocus is on CPT. The work is motivated by challenges associated with ob-taining efficient power transfer over relatively large gaps ranging from a fewcentimeters up to 20 cm.A dual-band CPT system is proposed that operates at frequencies of13.56 MHz and 27.12 MHz. Depending on the gap distance, a specific fre-quency is selected. The primary focus in this research is the design of thehigh efficiency power amplifiers and rectifiers that are required to implementthe dual-band system. The class-E circuit topology is selected for the de-signs. The theory of time-reversal duality is applied to convert the poweramplifier circuits into synchronous rectifier circuits. The rectifier convertsthe Radio Frequency (RF) power to DC power and the rectification efficiencydepends on load resistance. A variable load circuit board is implementedusing a DC-DC power converter to track the maximum power efficiency ofthe rectifier. A buck converter is selected for the design and duty cycle isused to change the input resistance of the converter.iiiAbstractIn the last part of this work, the power amplifiers and the rectifiers areconnected to a capacitive coupling network with an adjustable load resis-tance. The power and efficiency of the CPT system is simulated for gapdistances ranging from 5 cm to 20 cm. Simulation results show that formaintaining high efficiency operation of the CPT the system, it needs to op-erate at 27.12 MHz for small gap separations and the frequency is switchedto 13.56 MHz for larger gap separations.ivLay SummaryWireless power transfer systems have been recognized as a game-changingtechnology in the electrical sector. In this thesis, a research gap is identi-fied for wireless power transfer systems that takes advantage of the electricfield for the coupling network. Previous work presented in literature has fo-cused on systems that operate at a single frequency for fixed gap distancestypically in the range of millimetres. In this thesis, electrical circuits aredesigned for two different operating frequencies to achieve high power andhigh efficiency operation of a capacitive wireless power system. A specificoperating frequency is selected for a range of gap distances. In this way,power transmission is obtained over a range of up to 20 cm. The theory,simulation, and experimental results are described for the amplifier and rec-tifier components that are needed to implement the system.vPrefaceThis research is supervised by Dr. Thomas Johnson, an associate professorin School of Engineering at the University of British Columbia. All the re-search work is conducted at the School of Engineering. This thesis containsresearch work that is to be published in the future. Hoda Dadashzadeh is theprincipal contributor to the work described in this thesis. Hoda designedclass-E amplifier and rectifier circuits for a dual-band capacitive wirelesspower transfer system. She also built and conducted all the experimentalwork to verify the amplifier and rectifier designs. Masoud Ahmadi has pro-vided the filter-theory-based model for capacitive wireless power transfersystem. Dr. Thomas Johnson managed the team and provided the conceptand instructions both for design and practical implementations.viTable of ContentsAbstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiiLay Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vPreface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viTable of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiList of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xList of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiiAcknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . xxAcronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 History of Wireless Power Transfer Systems . . . . . . . . . . 21.2 Review of Previous Literature on Capacitive Power TransferConverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.2.1 Full-Bridge Converters . . . . . . . . . . . . . . . . . 81.2.2 Single Active Switch Converters . . . . . . . . . . . . 11viiTable of Contents1.2.3 Resonant RF Converters . . . . . . . . . . . . . . . . 121.2.4 Summary of Literature Review on CPT converters . . 151.3 Research Objectives . . . . . . . . . . . . . . . . . . . . . . . 161.4 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Class-E Power Amplifier . . . . . . . . . . . . . . . . . . . . . 192.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 192.2 Class-E Power Amplifier Theory . . . . . . . . . . . . . . . . 202.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . 252.4 Considerations For Practical Circuit Implementations . . . . 302.4.1 Inductor Winding . . . . . . . . . . . . . . . . . . . . 312.4.2 Thermal Management . . . . . . . . . . . . . . . . . . 362.4.3 PCB Layout Capacitance . . . . . . . . . . . . . . . . 392.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . 402.6 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . 463 Class-E Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . 473.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 473.2 Class-E Rectifier Theory . . . . . . . . . . . . . . . . . . . . 483.2.1 Time Reversal Duality . . . . . . . . . . . . . . . . . 483.2.2 Synchronous Rectifier . . . . . . . . . . . . . . . . . . 503.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . 533.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . 573.5 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . 62viiiTable of Contents4 DC-DC Converter Load Circuits . . . . . . . . . . . . . . . . 644.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 644.2 Converter Selection . . . . . . . . . . . . . . . . . . . . . . . 654.3 Buck Converter Theory . . . . . . . . . . . . . . . . . . . . . 704.4 PWM Controller . . . . . . . . . . . . . . . . . . . . . . . . . 734.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . 754.6 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . 835 Capacitive Wireless Power Transfer System . . . . . . . . . 855.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 855.2 Capacitive WPT . . . . . . . . . . . . . . . . . . . . . . . . . 855.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . 895.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . 955.5 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . 1046 Conclusion and Future Work . . . . . . . . . . . . . . . . . . 106Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112ixList of Tables1.1 Brief comparison of IPT and CPT systems. . . . . . . . . . . 71.2 Previous research on CPT system converters are summarizedand compared based on the gap distance, frequency, and con-verter topology. . . . . . . . . . . . . . . . . . . . . . . . . . . 152.1 Class-E power amplifier component values that are used forcircuit simulations at 13.56 MHz and 27.12 MHz. . . . . . . . 272.2 The required number of turns for three toroidal cores for a1.4 µH inductor at 13.56 MHz. . . . . . . . . . . . . . . . . . 322.3 Measured quality factor and the equivalent shunt resistancefor three different core materials for a 1.4 µH inductor. . . . . 353.1 A comparison of electrical parameters in the original circuitand the equivalent circuit obtained after time reversal con-cepts are applied to the original network [1]. . . . . . . . . . . 503.2 Third order Butterworth filter component values for two dif-ferent frequency bands. . . . . . . . . . . . . . . . . . . . . . 524.1 Basic DC-DC converter topologies with their correspondingvoltage gain both in DCM and CCM operational modes. . . . 68xList of Tables4.2 Buck converter circuit parameters and components selectedfor the experimental circuit. . . . . . . . . . . . . . . . . . . . 755.1 Inter-plate separation distances for the six-plate CPT network. 875.2 Resonator characteristics when the plates are infinitely farapart (g →∞). . . . . . . . . . . . . . . . . . . . . . . . . . . 100xiList of Figures1.1 In a near field WPT system (a), a transmitter and receiver arelinked by a coupling (non-radiating) field that may be electricand/or magnetic. In a CPT system (b), the transmitter andreceiver are coupled by an electric field. . . . . . . . . . . . . 41.2 Categorization of wireless power transfer (WPT) systems. . . 51.3 An example of full-bridge inverter and rectifier used in CPTsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.4 Single-ended primary-inductor converter (SEPIC) is an ex-ample of single active switch DC-DC converters used in CPTsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.5 Class-E2 amplifier and rectifier circuit is an example of RFresonant converters used in CPT system. . . . . . . . . . . . . 131.6 ISM band spectrum; 13.56 MHz and 27.12 MHz are the op-erating ISM bands in the CPT system. . . . . . . . . . . . . . 172.1 A simplified class-E power amplifier circuit model is shownfor both switch states. . . . . . . . . . . . . . . . . . . . . . . 21xiiList of Figures2.2 A signal generator (clock oscillator) feds a pulse to the LMG1020gate driver integrated with the class-E power amplifier circuit[2]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222.3 Examples of ideal class-E power amplifier switch voltage andswitch current waveforms. The waveforms show that the volt-age and current are both zero at the switching points. . . . . 242.4 Simulated drain voltage and drain current waveforms for class-E power amplifiers at 27.12 MHz and 13.56 MHz. The simu-lated gate waveform is scaled by a factor of twenty. . . . . . . 282.5 Simulated results for efficiency versus power of class-E ampli-fiers designed for 13.56 MHz and 27.12 MHz frequency bands. 292.6 VNA impedance measurement for a 1.4 µH inductor woundon a FT87-67 ferrite core. . . . . . . . . . . . . . . . . . . . . 332.7 Equivalent circuit model for an inductor. . . . . . . . . . . . . 332.8 Coupled inductor circuit model. . . . . . . . . . . . . . . . . . 342.9 Illustration of a heatsink attachment with corresponding ther-mal resistance dissipation for a typical FET device. . . . . . . 382.10 Experimental test bed to verify the power class-E power am-plifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412.11 Photos of the experimental test bench for characterizing theclass-E power amplifier (a) and an assembled class-E poweramplifier (b). . . . . . . . . . . . . . . . . . . . . . . . . . . . 422.12 Measured class-E power amplifier drain voltage, gate, andoutput voltage waveforms for amplifiers at 13.56 MHz and27.12 MHz. The gate voltage is scaled by a factor of sixteen. 44xiiiList of Figures2.13 Experimental drain efficiency versus output power of the class-E amplifiers at 13.56 MHz and 27.12 MHz. . . . . . . . . . . 453.1 In a class-E amplifier, power flows from the DC supply tothe RF load. In a class-E rectifier, power flow is reversed;power flows from the RF input source to a DC load therebyconverting RF power to DC power. . . . . . . . . . . . . . . . 493.2 Synchronous class-E rectifier circuit; the feedback loop cre-ates the desired pulsating waveform for the gate drive oscil-lator from the input RF voltage. . . . . . . . . . . . . . . . . 513.3 The simulated drain voltage and current waveforms in theinverter and rectifier. The waveforms confirm that the in-verter and rectifier are time reversed circuit duals. The volt-age waveform (a) and current waveform (b) are for 13.56 MHz,while (c) and (d) are the voltage and current waveforms for27.12 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543.4 Simulated drain and gate voltage waveforms for the synchronousclass-E rectifiers: (a) 13.56 MHz; (b) 27.12 MHz. . . . . . . . 553.5 Simulated results showing the DC load power and overall sys-tem efficiency as a function of DC load resistance. . . . . . . 563.6 The simulated overall system efficiency versus DC outputpower of the rectifier in a back-to- back configuration. Overallsystem efficiency includes the inverter and rectifier loss. . . . 573.7 The block diagram of the rectifier test system. . . . . . . . . 58xivList of Figures3.8 The photo of a class-E inverter (left) connected to the RFinput port of a class-E rectifier (right) in a back-to-back con-figuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593.9 The drain and gate waveforms of the synchronous class-Erectifiers are measured at 13.56 MHz and 27.12 MHz. Thegate-source voltage is scaled by a factor of 10. . . . . . . . . . 593.10 Measured load power and overall efficiency of the class-E am-plifier and synchronous rectifier as a function of DC load re-sistance with 19 V input DC voltage. . . . . . . . . . . . . . . 603.11 Overall efficiency of the back-to-back rectifier and inverter fordifferent output power levels is measured with 30 Ω and 40 Ωload at 13.56 MHz and 27.12 MHz, respectively. . . . . . . . . 624.1 DC-DC converter shown as an interface device between theload and power source. . . . . . . . . . . . . . . . . . . . . . . 654.2 Equivalent resistance of the DC-DC converter from the sourceside. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674.3 Effective input resistance Rin comparison of boost, buck, andbuck-boost DC-DC converters operating in DCM as a func-tion of duty cycle D. Results are shown for L = 5 µH,RLoad = 20 Ω, and fs = 500 kHz. . . . . . . . . . . . . . . . . 694.4 DCM switching states in a buck converter: (a) Step 1 [0, DTS ],(b) Step 2 [DTs, (D+D2)Ts], and (c) Step 3 [(D+D2)Ts, Ts]. 704.5 Typical inductor waveforms for the DCM buck converter op-eration: (a) inductor current and (b) inductor voltage. . . . . 73xvList of Figures4.6 Illustration of the concept of pulse width modulation (PWM). 744.7 Circuit to generate PWM with a comparator. . . . . . . . . . 744.8 A laboratory prototype of the buck converter including thePWM controller. . . . . . . . . . . . . . . . . . . . . . . . . . 754.9 Circuit schematic of the LM3477 PWM controller and theINA138 current sensor integrated with the buck converter. . . 784.10 The buck converter is connected to the Agilent E3634A DCpower supply to validate the circuit. The input voltage of thebuck converter is set to 15 V. . . . . . . . . . . . . . . . . . . 794.11 Measured waveforms in the variable DC load circuit. Thegate waveform has a duty cycle of 0.73 and converts a DCinput voltage of 15 V to an output of 11 V. . . . . . . . . . . 804.12 The measured equivalent input resistance of the buck con-verter versus the duty cycle ratio. . . . . . . . . . . . . . . . . 814.13 The buck converter is connected to the back-to-back RF poweramplifier and rectifier (RF DC-DC) system to validate the in-tegrated operation. . . . . . . . . . . . . . . . . . . . . . . . . 81xviList of Figures5.1 A six-plate CPT system is shown in (a). The six-plate systemconsists of two large outside shield (ground) plates and a pairof copper disks for the transmitter and receiver. The transmitdisks are smaller than the receive disks to provide tolerancefor lateral misalignment. The six-plate can be configured asa four plate system by omitting a transmit and receive diskshown by the gray highlight. The dimensions of the groundshield and the CPT disks are shown in (b). The equivalentcircuit for the four plate system with matching (compensa-tion) inductors is shown in (c). . . . . . . . . . . . . . . . . . 885.2 Simulations results for dual-band switching in a CPT system.The plots in (a) show how DC load power changes with gapdistance and the plots in (b) show how efficiency changes withgap distance. The system operates at 27.12 MHz in zone Aand switches to 13.56 MHz in zone B. Results are shown foran input DC voltage of 19 V. . . . . . . . . . . . . . . . . . . 915.3 Simulated overall efficiency and output DC power of the CPTsystem as a function of load resistance and gap distance. Re-sults are shown for a frequency of 13.56 MHz and input volt-age of 19 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925.4 Simulated overall efficiency and output DC power of the CPTsystem as a function of load resistance and gap distance. Re-sults are shown for a frequency of 27.12 MHz and input volt-age of 19 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93xviiList of Figures5.5 Simulated overall efficiency of the CPT system as a function ofload resistance and gap distance. Results are for a frequencyof 13.56 MHz and input voltage of 19 V. . . . . . . . . . . . . 945.6 Simulated output DC power of the CPT system as a func-tion of load resistance and gap distance. Results are for afrequency of 13.56 MHz and input voltage of 19 V. . . . . . . 955.7 A four-plate CPT network is connected to the class-E poweramplifier and rectifier PCB boards. . . . . . . . . . . . . . . . 965.8 The matching inductors are connected to the CPT disks throughterminal blocks that make it easy to change the matching in-ductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975.9 The stray capacitance (Ccon) of the terminal block is in par-allel with the CPT equivalent circuit capacitances CTX andCRX . The stray capacitance is approximately 5.5 pF. . . . . . 975.10 The equivalent isolated capacitance of the transmitter andreceiver are measured with the VNA. The capacitance is la-belled at 13.56 MHz and 27.12 MHz. . . . . . . . . . . . . . . 995.11 Measurements of resonant isolated transmit (a) and receive(b) plates. Measurements are shown for both 13.56 MHz and27.12 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995.12 (a) The experimental setup; (b) the corresponding drain andgate voltage waveforms of the inverter and rectifier are mea-sured at 27.12 MHz with 3.2 cm gap distance. . . . . . . . . . 101xviiiList of Figures5.13 Experimental measurements of output DC load power andoverall efficiency of the CPT system as a function of DC loadresistance. The gap distance is 3.2 cm and the inverter inputvoltage is 22 V. Measurements for 27.12 MHz are shown in(a) and for 13.56 MHz in (b). The CPT system has higheroutput power and efficiency at 27.12 MHz. . . . . . . . . . . . 1025.14 Experimental output DC load power and overall DC-to-DCpower efficiency as a function of gap distance in the CPTsystem. Measurements are shown at 27.12 MHz with 40 Ωload and the inverter DC drain voltage is 22 V. . . . . . . . . 1035.15 Output load power versus overall efficiency of the CPT systemat 27.12 MHz for a 3.2 cm gap distance. . . . . . . . . . . . . 104xixAcknowledgementsI would like to wholeheartedly express my gratitude to my supervisor, Dr.Thomas Johnson for his invaluable advice, continuous support, and patience.His immense knowledge and plentiful experience have encouraged me in bothacademic and daily life.I would also like to thank Dr. Mohammad Hossein Zarifi, Dr. Lo¨ıcMarkley, and Dr. Alyse Hawley for their technical support on my study.Many thanks to all the members in the UBCO RF and Microwave Technol-ogy Laboratory for their kind support during my time in the UBC Okanagancampus. These two years would not have been enjoyable without your helpand friendship.I would like to send gratitude from the bottom of my heart to my parents,for always encouraging me and trusting me. Words fall short of the thanksthat I would try to express to you. It is your love and endless care thatmade me the person I am today.Lastly but most importantly, to my husband. Without your tremen-dous understanding and encouragement in the past few years, it would beimpossible for me to complete this journey.xxAcronymsCCM Continuous Current Mode.CPT Capacitive Power Transfer.DCM Discontinuous Current Mode.EMI Electromagnetic Interference.FET Field Effect Transistor.GaN Gallium Nitride.IC Integrated Circuit.IPT Inductive Power Transfer.ISM Industrial, Scientific, and Medical.KCL Kirchhoff’s Current Law.KVL Kirchhoff’s Voltage Law.LDMOS Laterally-Diffused Metal-Oxide Semiconductor.LEDs Light-Emitting Diodes.xxiAcronymsMOSFET Metal-Oxide Semiconductor Field-Effect Transistor.PCB Printed Circuit Board.PWM Pulse Width Modulation.RF Radio Frequency.SEPIC Single-Ended Primary-Inductor Converter.SMD surface-mount devices.TIM Thermal Interface Material.UBCO The University of British Columbia Okanagan Campus.VNA Vector Network Analyzer.WPT Wireless Power Transfer.ZCS Zero Current Switching.ZVS Zero Voltage Switching.xxiiChapter 1IntroductionInterest in Wireless Power Transfer (WPT) systems has motivated signifi-cant research in recent years. WPT is perceived as a game-changing tech-nology by many engineers. Applications of WPT systems include wearableelectronic devices [3], biomedical devices [4], electric vehicles [5], IntegratedCircuit (IC) [6], sensors [7], and Light-Emitting Diodes (LEDs) [8]. Despitesignificant progress in developing WPT technology, there are many designchallenges that still need to be investigated. Some of these challenges are:• Safety: The electromagnetic emission might be harmful for humans[9].• Security: WPT systems can be vulnerable to cyber attacks [10].• Efficiency: The efficiency of WPT systems depends on several param-eters such as gap distance, power levels, and the implementation topol-ogy of the circuits used for generating and rectifying power. Thesefactors have limited the application of WPT to small gap distancesunder constrained spatial conditions [9].• Gap distance: Increasing the spatial bandwidth (range of gap dis-tances that a WPT system can efficiently operate over) is desired [9].11.1. History of Wireless Power Transfer Systems• Load variation: WPT systems efficiency can be sensitive to loadvariations [9].• Control to deliver regulated power with maximum efficiency:An adaptive control mechanism is required to compensate for spa-tial variation and control load power while simultaneously maximizingsystem efficiency [11].• Material properties of the transmission medium: Most studiesinvestigate WPT systems only for air gaps. There needs to be moreresearch focused on transmission through other materials between thetransmitter and receiver [9].The above-mentioned challenges and the research gaps motivate furtherstudy of capacitive wireless power transfer systems for large gap distances.In the remainder of this chapter, a brief history of WPT is given and dif-ferent categories classes of WPT are discussed and compared. Next, recentliterature that has focused on converter designs for capacitive WPT is re-viewed. The chapter concludes with a section outlining the research goalsand objectives of this work.1.1 History of Wireless Power Transfer SystemsNicola Tesla is known as the pioneer of power transfer without using wires.In 1884 he designed the first wireless power system based on capacitive cou-pling [12]. Later, in 1904, Tesla was the first to the successful demonstrationof a far-field wireless power system [13]. However, the lack of applications21.1. History of Wireless Power Transfer Systemsand the low efficiency of power transfer resulted in stagnation of the tech-nology. There were several studies to improve and commercialize Tesla’sinitial WPT system until 2006. However, no giant steps were taken. In2006, a group of researchers at the Massachusetts Institute of Technology[14] developed resonance coupling for WPT that led to a breakthrough inWPT technology and a resurgence of WPT research [15].In general, a WPT system consists of a power source, a transmitter, acoupling network, a receiver, and a load. The transmitter is often referredto as the inverter, a term derived from power electronics which refers to acircuit that converts DC to AC (RF). An inverter in principle can also beimplemented with an oscillator (DC to RF conversion) followed by a poweramplifier. The receiver is often referred to as a rectifier, since the functionof the receiver is to convert RF to DC. Overall, the WPT system can bedescribed as a system that converts a DC source to a DC load througha coupling medium. The distance between the transmitter and receiver iscalled the separation gap distance which is is denoted by g in this thesis.The term ‘separation gap distance’ is shortened to the phrase ‘gap distance’.A diagram of a general WPT system is shown in Figure 1.1a.31.1. History of Wireless Power Transfer SystemsTransmitter ReceiverCoupling Field Load(a)Electric FieldsGap DistanceTransmitterDC LoadPower Amplifier(DC to RF)Rectifier(RF to DC)ReceiverCouplingDC(b)Figure 1.1: In a near field WPT system (a), a transmitter and receiverare linked by a coupling (non-radiating) field that may be electric and/ormagnetic. In a CPT system (b), the transmitter and receiver are coupledby an electric field.WPT systems are categorized into two groups based on the wavelength(λ) of the energy transferring electromagnetic wave. If λ > g, it is catego-rized as near-field WPT, and if the gap distance is larger than a few λ, itis categorized as far-field WPT. Far-field WPT systems generate radiatingfield that propagates through a medium. Depending on the type of energycarrying wave, far field WPT systems are broadly classified in three maincategories: optical, microwave, and acoustic. Near-field WPT systems aredesigned to work with reactive field coupling that is ideally non-radiating.Depending on the coupling field, near field WPT can be divided into threesub-categories. If a magnetic field is used for the coupling, it is called In-41.1. History of Wireless Power Transfer Systemsductive Power Transfer (IPT) and if electric field is used for coupling, it iscalled Capacitive Power Transfer (CPT) [11] [16]. Hybrid power transfer(HPT) uses both magnetic and electric fields. The scope of the research inthis thesis relates to CPT and an example of a CPT system is shown inFigure 1.1. A summary of the WPT categorization is shown in Figure 1.2.Wireless Power Transfer (WPT)Near-FeildFar-FieldAcousticOptical MicrowaveInductive Power Transfer (IPT)Capacitive Power Transfer (CPT)Radiating FieldsReactive Fields (non-radiating)Hybrid Power Transfer (HPT)Figure 1.2: Categorization of wireless power transfer (WPT) systems.In comparison to traditional power transfer systems with galvanic con-nection, WPT has several advantages that come from eliminating connectorsand wired connections [16–18]. These include:• Enhancing the user friendliness of the products.• Increasing the reliability and lifespan of devices by improving batterylifetime or eliminating batteries all together.• Reducing the size of products by reducing the required battery sizeand/or eliminating connectors.• Improving the safety of products specially for exposure to flammable51.1. History of Wireless Power Transfer Systemschemicals or gases.• Improving the mobility of devices.On the other hand, disadvantages of WPT include the following [9, 16,19, 20]:• WPT sytems are restricted to low power levels and small gap distances.• The power transfer efficiency is much lower than galvanic connections.• Electromagnetic Interference (EMI) emission is high and there are con-cerns about human safety.• WPT systems have higher cost as they have not been as commercial-ized as galvanic connected systems.The power transfer level, operating frequency, system efficiency, andspatial bandwidth are the main criteria that can be considered for WPTsystem comparisons [9]. Since the focus of this thesis is on near-field WPTsystems, a comparison of the pros and cons of CPT and IPT systems aresummarized in Table 1.1. Comparisons with more details are presented in[16, 21, 22]. Reviewing the literature, it is clear that much less research hasbeen done on CPT compared to IPT and few studies have been dedicatedto CPT [9, 20, 21].61.1. History of Wireless Power Transfer SystemsCoupling Advantages DisadvantagesIPT• More mature technology• Robust• Significant publicationsavailable• High power transfercapability• Larger gap distances• Ferrite for EMIshielding• Presence of eddycurrents• Efficiency decreasesfor larger coils• High cost• Large footprintCPT• Eddy current reduction• Power transfer capabilitythrough metals• Simple structure ofcoupling• Lower cost of coupling• Higher lifespan andreliability• Smaller coupling footprint• Easier to implement in ICs• Lower temperature• Simple structure formultiple receivers• Lower power density incoupling• Safety concerns withthe exposure to largeelectric fields• Less research literatureis availableTable 1.1: Brief comparison of IPT and CPT systems.In the next section, a literature summary is presented on the designof converters for CPT systems, and after the summary, the goals of thisresearch are defined.71.2. Review of Previous Literature on Capacitive Power Transfer Converters1.2 Review of Previous Literature on CapacitivePower Transfer ConvertersPower converters are a significant part of WPT systems since they affectthe overall cost, efficiency, and performance of the system. One of the maindesign steps in WPT system design is to determine the configuration andcharacteristics of the power converters. This step is also a very challengingone as the switching semiconductor devices used in the converters often op-erates at close to its limits. Semiconductor technology, modeling techniquesfor the components of the converters, available measurement equipment,thermal management, and IC packaging are some of the parameters thathave an effect on the converter design, optimization, and operation [23].The design of the inverter and rectifier circuits for CPT systems can be sub-divided into three main circuit categories: bridge converters, single activeswitch DC-DC converters, and resonant RF converters [16, 24].1.2.1 Full-Bridge ConvertersAdvantages of the full-bridge converter topology are a simple and robustcircuit, easy to design and tune circuit parameters, and low voltage stress onsemiconductor devices. An example of a full-bridge converter used in CPTsystem is shown in Figure 1.3. Disadvantages of full-bridge converters arethat they are bulky and expensive due to having more semiconductor devicescompared to the other two categories of CPT converters. The switchingfrequency is limited and the switching loss is high if additional circuitry isnot added for soft switching capability. By the same token, the efficiency of81.2. Review of Previous Literature on Capacitive Power Transfer Convertersthe full-bridge converter is lower than the other topologies.Co RLVin+VO-TransmitterCReceiverFigure 1.3: An example of full-bridge inverter and rectifier used in CPTsystem.Based on the switch drain capacitance, a methodology has been pre-sented in [25] to maximize the efficiency for a given coupling capacitance.To verify the presented methodology, the authors have built a full-bridgeinverter for the transmitter side and a diode bridge rectifier for the receiverside. Tests in [25] have been carried out for a 0.13 mm separation gap dis-tance. It is shown that in order to boost the efficiency from 50% to 90%, thecoupling capacitance must be doubled. In addition, the effect of inductorquality factor on the required minimum coupling capacitance is analyzed.The output power level in CPT systems was increased in [26, 27] byadding a single pulse switching active capacitor to the conventional full-bridge inverter at 10 kHz. This increases the Continuous Current Mode(CCM) range of operation thereby increasing the power transfer capabilityof the system. However, a single pulse switching active capacitor adds morecomplexity to the circuit structure and control. Moreover, it makes the con-91.2. Review of Previous Literature on Capacitive Power Transfer Convertersverter circuit bulky which is a major drawback in most WPT applications.The impact of a single inductor compensation network connection pointon the CPT coupling capacitance is investigated in [28]. To verify the re-sults, a full-bridge inverter and rectifier is designed for a gap distance of0.4 mm. The results show that connecting the compensation network to theprimary side improves the CPT performance more than its connection tothe secondary side. With the optimal positioning of the tuning inductor, theauthors could transfer 0.91 W power at 71.6% efficiency. A matrix chargingpad structure with a full-bridge inverter and rectifier is presented in [29] tomake the system robust against receiver plate misalignments.Further research has been done adding LC and LCL compensation net-works to each side of the CPT [30]. Compensation networks have beeninvestigated and different structures have been compared in [31]. For exam-ple, it is shown that double sided LCL compensation networks can increasethe switching frequencies of full-bridge inverters. An inverter prototype isbuilt and tested at a switching frequency of 1 MHz and the design reachesan efficiency of 80.5% while transferring 25 W of power to the load [30].Based on fluid bearing concepts, a theory is proposed in [32] to enhancethe coupling capacitance and hence power transfer capability in rotatingCPT systems for slip ring replacement applications. The coupling plates aremounted on the stator and rotor of an electrical machine where the statoris considered as the transmitter side. To validate the theoretical discussion,a CPT system is designed with a full-bridge inverter and a rectifier. On thetransmitter side, a LC tank is used to enable soft switching in the inverter.The proposed system can reach 94% efficiency for a gap distance of 125 µm101.2. Review of Previous Literature on Capacitive Power Transfer Convertersfor transferring 100 W to the load.1.2.2 Single Active Switch ConvertersSingle active switch converters (also known as PWM DC-DC converters) arecommonly designed for boost (voltage increasing), buck (voltage decreasing)and buck-boost (either voltage increasing or decreasing) modes. The circuitsused to implement these converters typically have a LC network that canbe partitioned to incorporate a capacitively coupled gap. Essentially thecapacitor in the LC network is replaced by a physical structure that providesa gap and separates the circuit into an inverter (transmitter) and a rectifier(receiver). However, the capacitance that is required for these types of CPTsystems is usually large, because of the relatively low switching frequencies.Consequently the gap distance is usually very small in the millimetre range.In addition, the EMI produced by these converters is usually high, sinceZero Voltage Switching (ZVS) or Zero Current Switching (ZCS) techniquescannot be obtained for all load conditions. An example of a single switchconverter that has been used in CPT systems is called the Single-EndedPrimary-Inductor Converter (SEPIC). An example of the circuit is shownin Figure 1.4.111.2. Review of Previous Literature on Capacitive Power Transfer ConvertersCo RLVinL1S+VO-L2DTransmitter ReceiverFigure 1.4: Single-ended primary-inductor converter (SEPIC) is an exampleof single active switch DC-DC converters used in CPT system.A DC bias voltage may be present across the coupling capacitor thatresults in leakage currents and reduces power density. Based on the DCbias voltage criterion, Cuk, SEPIC, Zeta, and buck-boost PWM DC-DCconverters have been compared for CPT applications in [33]. The studyreports that the buck-boost converter is recommended for CPT applications.A buck-boost prototype was built for a 200 kHz switching frequency anddelivered 1034 W to a load. The CPT gap distance was less than 1 mm andthe efficiency is reported to reach 90.3%. However, the high-side transistorand inverted output voltage in the buck-boost converter makes the drivercircuit sophisticated.1.2.3 Resonant RF ConvertersIn the context of WPT systems, a module that combines an oscillator andpower amplifier, whose function is to convert DC power to RF power, iscalled an inverter [34]. The power amplifier based converters can oper-ate at high frequencies and high efficiency by taking advantage of ZVS.121.2. Review of Previous Literature on Capacitive Power Transfer ConvertersHigh frequency operation drastically reduces the footprint of power ampli-fier based topologies. However, coupling capacitance has a high impact onthese topologies which can be the main disadvantage of them. An exampleis the class-E2 amplifier and rectifier circuit shown in Figure 1.5.Co RLVin+VO-TransmitterCReceiverFigure 1.5: Class-E2 amplifier and rectifier circuit is an example of RFresonant converters used in CPT system.A current-fed resonant push-pull inverter is employed in [35] for chargingthe batteries in SoccerBots. A CPT system is used to implement the charg-ing and a full bridge diode rectifier is used on the robots. Single inductorsare used for tuning to implement a resonant power transfer system. Theswitching frequency of the inverter is 217 kHz and the overall efficiency ofthe system is 44%.As an improvement for the slip ring application, the receiver plate isdivided into several cells each having its own half-bridge diode rectifier in[36]. This improves the robustness of the CPT to angular misalignments.The results maintain load voltage changes of ±12% over a complete rotationof the shaft. The theory is tested with a class-E amplifier on the transmitter131.2. Review of Previous Literature on Capacitive Power Transfer Convertersside. Results show that 1 W could be transferred to a 100 Ω load over a gapdistance of 36 mm.Push-pull class-E converters have been implemented in CPT for robotbattery charging and energy balancing applications [37]. Push-pull class-Econverters show robust characteristics for copper foil conduction track lengthvariation in robots. Taking advantage of ZVS, the converter efficiency is78.8% at a 13.56 MHz switching frequency for a 0.2 mm gap distance.In [38], a soft-switched push-pull resonant inverter named as a class Φ2inverter is proposed for CPT applications. The proposed converter is derivedfrom a combination of class-E and class-F power amplifiers and is designedfor high voltage and high frequency operation. Experimental results haveshown that the inverter operating at 6.78 MHz can transfer more than 300 Wat 91% efficiency for gap distances less than 0.5 mm.CPT has been implemented for battery charging of electrical vehicles in[39, 40]. Split buck-boost converters and class-E2 power amplifiers with itstime reversal dual rectifier are implemented and compared for a constantair gap of 0.1 mm. The switching frequency is 530 kHz for both of thedesigns. The buck-boost converter delivered 1021 W of output power at83% efficiency, while the class-E2 amplifier architecture delivered 1040 W ofoutput power at 88% efficiency. Other literature references also recommendclass-E amplifier based designs for WPT applications [41, 42]. For example,in [42], with a proper matching network, a class-E driven CPT delivered9.5 W of load power and had an efficiency of 95.44% for an air gap of0.25 mm gap.141.2. Review of Previous Literature on Capacitive Power Transfer Converters1.2.4 Summary of Literature Review on CPT convertersThe discussions presented in Section 1.2 are summarized in Table 1.2. Thetable is sorted based on the converter topology and operating frequency.Table 1.2 shows that the maximum operating frequency of 13.56 MHz hasbeen recorded. Additionally, all the previous research has focused on design-ing the converters for a single operating frequency at constant gap distanceoperation.Ref. Gap Distance Frequency Converter[26] - 10 kHz full-bridge[27] - 10 kHz full-bridge[29] 0.5 mm 450 kHz full-bridge[28] 0.4 mm 1 MHz full-bridge[30] - 1 MHz half-bridge[32] 0.125 mm 1.5 MHz full-bridge[25] 0.13 mm 4.2 MHz full-bridge[33] <1 mm 200 kHz buck-boost[40] 0.1 mm 540 kHz buck-boost[35] 1 mm 217 kHz resonant push-pull[39] 0.1 mm 530 kHz class-E2[36] 36 mm 1 MHz class-E[42] 0.25 mm 1 MHz class-E[38] 0.5 mm 6.78 MHz class-ϕ2[37] 0.2 mm 13.56 MHz push-pull class-ETable 1.2: Previous research on CPT system converters are summarized andcompared based on the gap distance, frequency, and converter topology.151.3. Research Objectives1.3 Research ObjectivesAfter reviewing the literature, it is clear that there has been much more focuson inductive power systems compared to capacitive power transfer systems.Most papers that have published on advancing CPT technology have focusedon transferring power over small gap distances, usually in the range of a fewmillimetres. Previous work has also typically focused on optimizing powertransfer for a fixed spatial configuration of the transmitter and receiver. Theliterature review also shows that the development of high efficiency powerconverters and rectifiers has been constrained to low switching frequenciesand no published work was found for frequencies above 13.56 MHz.The primary goal of this research is to design power efficient convertersand rectifiers for a dual-band CPT system. This research goal is based onthe hypothesis that a change in the operating frequency can be used to com-pensate for changes in coupling impedance improving the spatial bandwidthof the system. Therefore, the dual band concept is expected to extend therange of gap distances that can be obtained with a CPT system.The radio frequency spectrum is regulated andWPT systems can operatein frequency bands that are allocated for Industrial, Scientific, and Medical(ISM) applications. Available ISM bands that are in the frequency range ofthis work are shown in Figure 1.6. From these frequency bands, two adjacentfrequency bands at 13.56 MHz and 27.12 MHz are selected. The 27.12 MHzfrequency band extends the work that has been published for CPT systems.161.3. Research Objectives6.78 MHz 13.56 MHz 27.12 MHz 40.68 MHz30 kHz 326 kHz14 kHz 40 kHzCenter FrequencyBandwidthFigure 1.6: ISM band spectrum; 13.56 MHz and 27.12 MHz are the operatingISM bands in the CPT system.Based on the goal of implementing a dual-band CPT system, specificresearch objectives are listed below.1. Design high efficiency class-E amplifiers for operating frequency bandsat 13.56 MHz and 27.12 MHz. Initial design specifications for theamplifiers include a peak output power of 10 W with a drain efficiencyof 85%.2. Use the theory of time-reversal duality to transform the class-E am-plifiers into synchronous class-E rectifiers.3. Build experimental prototypes of the class-E amplifiers and rectifiersto verify the designs.4. Investigate the design of an adaptive load for the rectifier using DC-DC converter concepts. The adaptive load is required to maintain anoptimum load for the rectifier as gap distance changes.5. Use simulation models of the amplifiers and rectifiers in a dual bandCPT system and demonstrate how changing frequency can extend thegap distance that power can be transferred efficiently.6. Use the experimental amplifier, and rectifier circuits with an adjustableload resistor to implement a CPT system. The experimental system171.4. Thesis Outlinewill be used to verify the hypothesis that switching operating frequen-cies can improve power transfer system efficiency for a wider range ofgap distances compared to a single frequency system.1.4 Thesis OutlineChapter 2 describes the design of power amplifiers for the CPT system.Class-E amplifiers are designed for 13.56 MHz and 27.12 MHz ISM frequencybands. The class-E circuit topology is selected to implement high efficiencydesigns that use resonant switching to minimize voltage and current overlapin the switch.In Chapter 3, synchronous class-E rectifiers are designed based on theamplifiers developed in Chapter 2. The concept of time reversal dualityis used to synthesize synchronous class-E rectifiers from class-E amplifiertemplates. A buck DC-DC converter is designed in Chapter 4. The buckconverter is capable of adjusting the output DC load to a value that isoptimum for the CPT system. In Chapter 5, the amplifiers and rectifiersare integrated into a four-plate CPT system. Simulation results are shown todemonstrate the operation of the dual-band system. The simulation resultsreveal that in the integrated CPT system the power can be transferredefficiently over a 10 cm to 20 cm range by means of switching frequencyfrom 27.12 MHz to 13.56 MHz. Experimental results are also shown for aCPT system operating at a frequency of 27.12 MHz. Lastly, conclusionsfrom the research are summarized in Chapter 6.18Chapter 2Class-E Power Amplifier2.1 IntroductionIn this chapter, the focus is on the design of the transmitter components fora dual-band CPT system. A class-E amplifier circuit topology is selected forthe transmitter. The transmitter is a class-E inverter that is composed of aclass-E amplifier and a gate drive oscillator. The oscillator is usually avail-able as a single component and, in this work, the focus is on the design of theclass-E amplifiers. Designs are made for 13.56 MHz and 27.12 MHz. Thetheory of class-E amplifier design is first reviewed. The primary challenges ofthe design are associated with implementing an experimental circuit. Sig-nificant issues include compensation for device capacitance in the switch,selecting a gate driver, careful circuit board design to minimize inductancebetween the driver and switch, selection of materials for implementing in-ductors, and thermal design considerations. The design steps are discussedand experimental results are shown for the two class-E amplifier designs.192.2. Class-E Power Amplifier Theory2.2 Class-E Power Amplifier TheoryThe class-E amplifier was developed in 1970 by Nathan Sokal and AlanSokal and presented at an IEEE symposium in 1972 [43]. The term class-Ewas introduced later by the same authors in 1975 [44],[45]. A simple circuitstructure, low Electromagnetic Interference (EMI), and high efficiency arethe key advantages of the class-E amplifier [46] and, for these reasons, it waschosen for this study.The goal of any electronic or electric system design is to reach the desiredoutput power with minimum loss (i.e., highest efficiency). The transistorsusually dissipate the highest power in RF circuits. In order to reduce thispower loss, ZVS and ZCS are effective techniques. This means that at theinstant when the transistor turns on or off, either the voltage across it shouldbe zero, or the current passing through it should be zero. Class-E poweramplifiers use these techniques to reduce the switching power losses. Thisis done with a half-period time displacement between the drain current andvoltage waveforms of the transistor. For instance, while the transistor is off,a high voltage appears across the transistor. Transitioning from the off to onstate in an ideal case, the current is kept zero until the voltage comes downto zero and then the current starts increasing. Similarly, at the switchingoff instant, the current is reduced to zero before the voltage appears acrossthe transistor. In practical circuits, a small overlap of transistor voltage andcurrent is inevitable. Additionally, the on-state voltage and off-state currentof the transistor are not exactly zero [2].Figure 2.1 shows the ideal operation of the class-E power amplifier model202.2. Class-E Power Amplifier Theoryfor both switch states. In this topology, the DC supply current flows throughthe RF choke inductor LDD and the closed switch to ground. When theswitch is open, the stored energy in the RF choke inductor continues to passthrough either the shunt capacitor CP or the output load network. Outputcurrent from the amplifier generates power in the output load resistor RL.LDDRLVDDCPLDDRLVDDCPLDDRLVDDCPFigure 2.1: A simplified class-E power amplifier circuit model is shown forboth switch states.Figure 2.2 shows a complete class-E power amplifier circuit. The class-Eamplifier consists of a load network and a transistor. The transistor operatesas an on/off switch to obtain high efficiency and it shapes the drain voltageand current waveform to minimize the switching power loss. A suitable loadnetwork design delays the rise of the transistor voltage until after the currentis reduced to zero. In addition, the switch voltage returns to zero before thecurrent begins to rise [2].212.2. Class-E Power Amplifier TheoryLDDRLCPVDDLO CO LSLoad NetworkCbEPC2037R2R1Series ResonatorOUTHOUTLINMVDDGNDINPLMG1020+5VCbCRSignal GeneratorGate DriverFigure 2.2: A signal generator (clock oscillator) feds a pulse to the LMG1020gate driver integrated with the class-E power amplifier circuit [2].The load network of the amplifier consists of a RF choke LDD, a shuntcapacitor CP , a series resonator consisting of L0 and C0, and a phase shiftinductor LS . A RF choke LDD with a high impedance at the switchingfrequency is placed in the input to prevent the RF current from flowing ina reverse direction to the DC supply. The DC supply is bypassed to groundthrough a capacitor in order provide additional attenuation to any RF signalthat passes through the choke inductor. The inductance of the RF choke(LDD) is large enough that the AC current is substantially lower than theDC current, and the inductor is selected to have a reactance that is 10 timesgreater than the output load resistance. Therefore,ωLDD = 10RL (2.1)where ω is the switching frequency (rad/s), LDD is the RF choke inductor(H), and RL is the output load resistor (Ω).The shunt capacitor CP in a class-E circuit shapes the voltage and cur-222.2. Class-E Power Amplifier Theoryrent waveform to minimize power loss. While the switch is off, the supplycurrent flows through the shunt capacitor CP and the resistive load RL.The shunt capacitor is charged during the off state. The charged capaci-tor is discharged through the on state switch resistance and causes a powerloss that reduces system efficiency. Therefore, the on state switch resistanceshould be low. The drain voltage drops to zero instantly after the switchturns on to minimize power loss. The ideal drain voltage and drain currentwaveforms are shown in Figure 2.3. In this study, the class-E amplifier isdesigned based on the Sokal’s equations [2] considering ideal capacitors andinductors. The shunt capacitor in an ideal class-E circuit is calculated bythe following equation.CP =15.447ωRL(2.2)It is worthwhile to note that the internal parasitic capacitance of the switchshould be included in the determining the final value of CP in a practicalcircuit.232.2. Class-E Power Amplifier TheoryFigure 2.3: Examples of ideal class-E power amplifier switch voltage andswitch current waveforms. The waveforms show that the voltage and currentare both zero at the switching points.According to Sokal’s derivations [2], the current in the resonant tank issinusoidal and the series resonant circuit consisting of L0 and C0 is assumedto have an infinite loaded quality (Q) factor. The infinite Q assumptionmeans higher harmonics of the switching frequency are fully attenuated andthe load current is a perfect sinusoidal current. However, in practice, the Qof the resonant circuit is finite and a value has to be selected for the design.A loaded Q of 5 is chosen from the typical range of 1.8 to 5. The values ofthe series resonant circuit elements are found from the following equations:C0 =1ωQRL(2.3)L0 =1C0 ω2(2.4)The drain voltage and drain current do not overlap in the ideal class-E242.3. Simulation Resultsamplifier. A series inductor LS adjusts the phase of the output sinusoidalvoltage and switch voltage in a way that creates the desired phase shift. Theideal class-E amplifier has zero voltage and current overlap which eliminatesthe switching power loss in semiconductor devices. The phase shift inductoris calculated using the following equation:LS =1.1525RLω(2.5)2.3 Simulation ResultsThe class-E power amplifier theory described in Section 2.2 is used to designamplifiers for frequency bands at 13.56 MHz and 27.12 MHz. A 20 W loadpower requirement is selected for the design. In order to minimize switchinglosses, a Gallium Nitride Field Effect Transistor (GaN-FET) transistor isused. GaN devices have very low switch capacitance compared to Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET). An enhancementmode GaN-FET from EPC, model 2037, meets the load power requirementand is used for the design. The vendor has a circuit model that can be usedin circuit simulations.In order to switch the GaN-FET, a driver circuit is required. The driveris a critical component in the design and affects the switching speed of theGaN device. At switching frequencies of 27.12 MHz, there are not too manydrivers available off-the-shelf. A gate driver from Texas Instruments, modelLMG1020 is selected for the design. This device can provide peak switchingcurrents up to 7 A and is rated for switching frequencies up to 60 MHz. In252.3. Simulation Resultsaddition, a small propagation delay (2.5 ns) and fast rise/fall times (400 ps)allows fast switching of the GaN transistor and reduces the overlap switchinglosses. Texas Instruments also provides a model for the driver which is usedfor circuit simulations.The gate driver and GaN-FET interface is critical. Since high gate cur-rents are generated at switching instants, it is very important to minimizeinductance in the gate drive loop. Even small inductances in the PCB layoutcan result in significant ringing on the gate waveform. If the ringing is toohigh, it can lead to overvoltage conditions that damage the GaN-FET.Two methods are used to control ringing in the gate waveform appliedto the GaN-FET. The first is an RC filter network at the input of the gatedriver that is adjusted to control the rise and fall times of the clock signal.The RC network is shown in Figure 2.2. The time constant (τ = RC) forthe RC network can be tuned to reduce ringing. The second method thatis used to control gate ringing is to include damping resistors between thedriver output terminals and the gate. The damping resistors are identifiedas R1 and R2 in Figure 2.2 . The resistors connect to the high and lowdrive transistors in the LMG1020 driver. The final values for the dampingresistors are tuned experimentally to minimize the effect of trace inductance.An example of a simulated gate waveform including these two methods forcontrolling ringing is shown in Figure 2.4. The gate waveform is scaled bya factor of twenty to have a better illustration.Component values for the class-E amplifiers are calculated for a 20 Ωload with a loaded quality factor of 5. A summary of the designs is givenin Table 2.1. These values are tuned in circuit simulations to verify the262.3. Simulation Resultsdesign and maximize output power and efficiency. Tuning component valueswas done by observing the shape of the drain voltage and drain currentwaveforms. An example is shown in Figure 2.4 where it is evident that ZeroVoltage Switching is obtained for both of the operating frequencies. Thedrain voltage and current do not reach maximum values simultaneously. Thevoltage is dropped to zero promptly after the switch is turned on. Moreover,the drain to source voltage and current of the GaN-FET should not exceedthe maximum rated values provided by the device vendor. For the EPC2037,the maximum drain voltage is 100 V and the maximum switch current is2.4 A. Figure 2.4 shows that both drain voltage and drain current are withinthe maximum ratings for the EPC2037.Operating Frequency 13.56 MHz 27.12 MHzRF Choke (µH) 2.3 1.5Shunt Capacitor (pF) 120 55Resonator Capacitor (pF) 117.4 58.7Resonator Inductor (µH) 1.17 0.58Phase shift Inductor (µH) 0.24 0.13R1 and R2 10 Ω, 5.1 Ω 10 Ω, 5.1 ΩGate Driver RC Filter 47 Ω , 60 pF 47 Ω , 35 pFRC Filter Time Constant (ns) 2.82 1.64Table 2.1: Class-E power amplifier component values that are used for circuitsimulations at 13.56 MHz and 27.12 MHz.272.3. Simulation ResultsTime (ns)50 100 150 200Voltage (V)020406080100120Current (A)0.00.51.01.52.02.53.0Drain VoltageDrain CurrentGate Voltage(a) 13.56 MHzTime (ns)20 40 60 80Voltage (V)020406080100120Current (A)0.00.51.01.52.02.53.0Drain VoltageDrain CurrentGate Voltage(b) 27.12 MHzFigure 2.4: Simulated drain voltage and drain current waveforms for class-Epower amplifiers at 27.12 MHz and 13.56 MHz. The simulated gate wave-form is scaled by a factor of twenty.Different types of power efficiency are defined in this work depending onwhat circuits or systems are evaluated. The power efficiency measure usedfor evaluating the power amplifiers is called drain efficiency in this chapter.The drain efficiency is the ratio of the RF output power over the DC drainsupply power as:282.3. Simulation ResultsηD =PoutPDC× 100 [%] (2.6)Figure 2.5 shows the simulated output power versus drain efficiency ofthe power amplifiers designed for 13.56 MHz and 27.12 MHz. There is aslight change in efficiency when the operation frequency is switched for thepower amplifier. The efficiency drops less than 1% by increasing the outputpower from 5 W to 20 W at both operating frequencies. The simulatedresults are very good and, as will be shown later, they are optimistic andneglect many practical losses that reduce efficiency. Examples include lossesin the inductors and thermal effects in the transistor.Output Power (W)5 10 15 20Efficiency (%)95.495.695.896.096.213.56 MHz 27.12 MHzFigure 2.5: Simulated results for efficiency versus power of class-E amplifiersdesigned for 13.56 MHz and 27.12 MHz frequency bands.292.4. Considerations For Practical Circuit Implementations2.4 Considerations For Practical CircuitImplementationsAlthough the designs for the class-E amplifiers are based on theoreticalprinciples, there are important limitations that come from practical circuitimplementations that limits the performance of the ideal circuit. Practicalresults can deviate from the theoretical results since, in most theoreticalstudies, there are some assumptions made for the simplicity of the analysis.This is the case for class-E converters as well. For example, in the theoreticalanalysis, it was assumed that the series resonator current was perfectly si-nusoidal and there was no power loss in the resonator components (inductorquality factor is very high) [47].This section is dedicated to mention a few of the considerations thatneed to be taken into account in the design of practical RF circuits. Theseconsiderations result in more accurate designs that explain the differencebetween simulation and practical results. In addition, considering these as-pects helps designers to make proper component selections that can reducepower loss and improve power efficiency. This section will discuss the induc-tor winding and modeling, the thermal management, and PCB trace capac-itance impacts on the overall RF system. More accuracy can be achievedby considering the proper component positioning on PCB layout, inductorcoupling effect (if there is more than one inductor on the PCB), equivalentseries resistances (ESRs), capacitance variations with temperature, and theloading impedance of measurement equipment. The capacitors are chosento have maximum temperature stability and minimum ESR. Since all the302.4. Considerations For Practical Circuit Implementationsinductors used in this study have a ferrite core, the coupling effect betweeninductors is small and negligible.2.4.1 Inductor WindingToroidal inductors wound on magnetic cores are widely used in RF appli-cations for a variety of reasons including higher inductance [48]. The wiregauge, core geometry (for instance toroidal or slug-type), and core materialare some of the parameters that affect the inductance and inductor loss [49].In the following, two types of available magnetic cores in the laboratory,powdered iron and ferrite, are evaluated to determine which core materialis most suitable to minimize inductor losses. One of the inductors used inthe circuits, a 1.4 µH inductor, is used as an example to compare the coilsand select the best core material.In the beginning, finding an approximation for the required number ofwire turns is important. Three different core materials, one powdered ironcore called T80-6 and two ferrite cores called FT87-67 and FT87-68, areused to make 1.4 µH inductors with 18 gauge wire. A suitable core sizeis chosen using an empirical inductance factor AL that is provided by thecore vendors. It is worth noting that the bigger toroids are more usefulfor higher inductances as each turn produces more inductance. In addi-tion, smaller toroids permit smaller step changes in the inductance. A goodapproximation for the number of turns (N) is given byL = N2AL. (2.7)312.4. Considerations For Practical Circuit ImplementationsTable 2.2 shows the required turns for making 1.4 µH inductors withthree different toroid cores. The outer diameter of the T80-6 is 0.8 inchesand the outer diameter of the FT87-67 and FT87-68 cores is 0.87 inches.Although these toroid diameters are almost identical, they need differentturns to make the same inductance. Consequently, the magnetic core mate-rial affects the inductance factor as well.Toroidal core Powdered iron FerriteT80-6 FT87-68 FT87-67Inductance factor (AL) 4.5 nH 7.3 nH 25 nHTurns (N) 17.5 13.5 7.5Table 2.2: The required number of turns for three toroidal cores for a 1.4 µHinductor at 13.56 MHz.Figure 2.6 shows an example of the measured impedance of a 1.4 µHinductor wound on a FT87-67 toroid. The high impedance (open circuit) atthe self resonance frequency shown in the Vector Network Analyzer (VNA)measurement indicates a shunt resonator model for the inductor. Figure 2.7shows a simple equivalent circuit model for a lossy inductor. Resonatorlosses may be due to conductor loss, dielectric loss, or radiation loss, andare represented by the equivalent series resistance Rs in the circuit model[50].322.4. Considerations For Practical Circuit ImplementationsFigure 2.6: VNA impedance measurement for a 1.4 µH inductor wound ona FT87-67 ferrite core.RSCSRLNetwork AnalyzerFigure 2.7: Equivalent circuit model for an inductor.Measuring a value for the resistance Rs is critical to define the qualityfactor and model for inductor loss. However, very small resistances in therange of one Ω or less cannot be measured accurately by a VNA. In order tohave a better comparison of small inductor losses in the Ω range, a measure-ment method to transform low impedances to more measureable impedancesis required.In this study, a small inductor L1 made of one turn on the same toroid is332.4. Considerations For Practical Circuit Implementationscoupled with the designed inductor L2 as shown in Figure 2.8. A 100 pF ex-ternal capacitor CR is added in parallel with L2 to resonate at the desired fre-quency. In this case, the secondary side should have a purely real impedance(Z2). The equivalent impedance of the transformer is measured on the pri-mary side which is defined as Z1. The measured primary impedance Z1consists of a negligible impedance of L1 and the transformed purely realsecondary impedance Z2. Therefore, the measured impedance shows theequivalent transformed resistance of R2. Equation 2.8 transforms the pri-mary impedance to the secondary impedance in a coupled inductor to findan approximation of the secondary resistance [51]. The impedance on theprimary side is Z1 and given byZ1 =(N1N2)2Z2 (2.8)where N1 and N2 are the number of turns on the primary and secondary,respectively. Based on the transformed impedance methodology we can havea comparison of the shunt resistance R2 among the different core types.R2CSRL2L1Network AnalyzerCRN1 N2MZ1Figure 2.8: Coupled inductor circuit model.342.4. Considerations For Practical Circuit ImplementationsIn general, toroidal inductors suffer from low quality factor (Q) due tothe frequency-dependent losses such as skin effects and eddy current loss insubstrate[52]. Hence, after measuring the equivalent resistance, the qualityfactor is calculated. Then, three different toroidal cores are compared basedon their quality factors. The Q of a shunt resonator is given by [50]Q =R2ωL(2.9)The measurements for all three inductors are summarized in Table 2.3.All of the coils have a self resonant frequency over 130 MHz and approx-imately 1 pF of capacitance. In this case, the quality factor is the keyparameter for our comparison. From the quality factor aspect, the FT87-67core has the highest Q at 13.56 MHz, and therefore it has the lowest loss.Consequently, this magnetic core material is selected for the power amplifierand rectifier inductors.Toroidal core Powdered iron FerriteT80-6 FT87-68 FT87-67Self resonant frequency (fSR) 130.5 MHz 133.1 MHz 136.3 MHzSelf resonant capacitance (CSR) 1.06 pF 1.02 pF 0.97 pFShunt resistor (Rs) 10.6 KΩ 14.1 KΩ 15.8 KΩQuality factor (Q) 79.3 106.5 119.4Table 2.3: Measured quality factor and the equivalent shunt resistance forthree different core materials for a 1.4 µH inductor.352.4. Considerations For Practical Circuit Implementations2.4.2 Thermal ManagementThe size of modern power semiconductor devices is shrinking to increasepower density, reduce parasitic inductances, and reduce power losses [53].However, thermal management is a crucial factor in obtaining high perfor-mance from these types of devices. Therefore, the generated heat insidethe device must be effectively dissipated to the ambient environment [54].The heat must be dissipated to ensure the maximum junction temperature(Tj,max) is not exceeded; otherwise excessive thermal dissipation may causeserious damage to the semiconductor, melt solder junctions, and over dissi-pate PCB traces.Heat can be transferred through conduction, convection, and radiationmechanisms. In this design, the primary thermal transfer mechanism isconduction heat transfer through the device, circuit board, and heat sink. Inmedium power applications, a heatsink is attached to surface-mount devices(SMD) on the circuit board. Thermal via holes in the circuit board alsoenhance heat dissipation.The component thermal characteristics, the operating ambient temper-ature, and the power dissipated in the component are the main factors todecide whether a heatsink is required or not. The thermal resistance thatmodels heat conduction is generally described asRθ,jX =Tj − TXP(2.10)where• Rθ,jX is the thermal resistance from junction to a reference location362.4. Considerations For Practical Circuit ImplementationsX (◦C/W);• Tj (◦C or K) is the device junction temperature in steady state con-ditions;• TX (◦C or K) is the temperature of the reference location (board (B),case (C), or ambient (A));• and P is the power dissipated in the device.An appropriate heatsink is chosen based on the thermal resistances ofthe device to obtain a suitable heat dissipation and avoid costly engineeringefforts. Specific values for thermal resistances are given in the datasheet foreach component. A heatsink design for the EPC2037 GaN-FET is used asan example. The heatsink requirement is determined for operation at 50◦Cof ambient temperature and assuming 3 watts of power dissipation.According to the EPC2037 datasheet, the maximum allowed junctiontemperature is 150◦C. Therefore, the largest possible temperature rise on theEPC2037 junction is ∆T = 150−50 = 100◦C. From the EPC2037 datasheet,the value for the junction to ambient thermal resistance is 100◦C/W. Thisvalue indicates that one watt of thermal dissipation will increase the junctiontemperature by 100◦C. Hence, 3 watts of power dissipation will result in a300◦C temperature rise. Based on this, we can conclude that a heatsink isrequired for EPC2037 for the aforementioned operating conditions.Figure 2.9 illustrates the attachment of the heatsink with the correspond-ing thermal resistances for a typical FET. The heatsink is attached to thebackside of the component. The contact with the component is in general372.4. Considerations For Practical Circuit Implementationsimperfect and surface roughness and a nonplanar mechanical interface canlead to small voids that reduces the thermal conduction to the heat sink. Toovercome this issue, a Thermal Interface Material (TIM) is used to improvethermal contact and provide better thermal conduction at the interface. InFigure 2.9, the ambient temperature is shown by Ta, the heatsink tempera-ture is shown by TS , the case temperature is shown by TC , and the junctiontemperature is denoted by Tj .The thermal circuit model is shown in the right side of Figure 2.9. Thecircuit consists of equivalent resistances to model the thermal conductionthrough different interfaces from the junction in a FET to ambient. Theresistance Rθ,JC models the thermal resistance from the junction to the case(package), Rθ,CS models the thermal resistance from the case to heatsink,and Rθ,SA models the thermal resistance from the heatsink to ambient ofa FET. Note that the junction to board thermal resistance (Rθ,JB) is notconsidered in this study.PCBSolderFETTIMHeatsinkTaTaTCRθSARθCSRθJCTaTjAmbientJunctionCaseTSFigure 2.9: Illustration of a heatsink attachment with corresponding thermalresistance dissipation for a typical FET device.382.4. Considerations For Practical Circuit ImplementationsIn the heatsink design for EPC2037, it is assumed that a Thermal In-terface Material 5590H-PWRMODULE with a low thermal resistivity of0.46◦C/W is used. Given that the junction temperature is 150◦C, the ambi-ent temperature is 50◦C, and the power dissipation in the EPC2037 is 3 W,the junction to ambient thermal resistance is 33◦C/W with reference toequation 2.10. Knowing that the junction to case thermal resistance Rθ,JCfor the EPC2037 is 14◦C/W and the TIM thermal resistance is approxi-mately 0.5◦C/W, a heatsink with a thermal resistance lower than 18.5◦C/Wis required to dissipate the generated heat. Finally, based on the thermalanalysis, a Wakefield-Vette 902-21-2-12-2-B-0 heatsink with a thermal re-sistance of 14.3◦C/W is selected for the design. The thermal resistance isspecified for natural ambient cooling.2.4.3 PCB Layout CapacitanceThe majority of the heat generated by the driver and transistor is dissipatedby the heatsink. Additional thermal dissipation is provided by the copperon the circuit board. Wide traces, large copper pour areas, and vias areused to improve the thermal dissipation in the design. Although the heat isdissipated using thick traces and polygons, wide traces add parasitic capaci-tance to the circuit. A two layer Printed Circuit Board with a dielectric FR4is used to implement the designs. The bottom layer ground plane is sepa-rated from the top layer traces by a dielectric layer that adds capacitanceto the circuit. Due to the fact that unwanted extra capacitance affects thefunctionality of the circuit, it should be considered in the circuit designs.The equivalent capacitance of the traces is estimated as a parallel plate392.5. Experimental Resultscapacitance that is equal toC =ϵAd(2.11)where A is the area of the plates and d is the distance between the conduc-tors. The permittivity of the substrate (ϵ) is equal to the product of therelative permittivity (ϵr) of dielectric and permittivity of free space (ϵ0):ϵ = ϵrϵ0 (2.12)The calculated capacitance of the traces should be considered in the PCBlayout since it is shunted with the other capacitors in the circuit. Consideringthe parasitic capacitance of the drain traces are paramount since this addsup to the parallel capacitor in Figure 2.2. The variance of the shunt capacitorinfluences the performance of the class-E power amplifier.2.5 Experimental ResultsAn experimental test bed was built to characterize the class-E power ampli-fiers. A block diagram of the test bed is shown in Figure 2.10 and a photoof the test bed is shown in Figure 2.11a. The class-E amplifiers require twoDC input voltages. The drain supply voltage VDD is provided by an Agi-lent E3634 variable voltage power supply, while the LMG1020 gate driverrequires a fixed 5 V supply (VDriver). An external clock signal is requiredfor the gate driver and the signal is generated by a Rigol DG 4162 functiongenerator. The function generator produces a square wave signal that has a402.5. Experimental Results4 V peak-to-peak voltage with a 2 V offset. The frequency of the clock is setto either 13.56 MHz or 27.12 MHz, depending on which amplifier is tested.The class-E amplifiers are designed for a 20 Ω RF load impedance. Sincemost RF measurement equipment is 50 Ω, an impedance matching networkis required to transform the 20 Ω impedance to 50 Ω. A high power tunablematching network consisting of a series inductor and shunt capacitor wasused to implement a low loss reactive matching network. After the outputimpedance is transformed to 50 Ω, a 40 dB attenuator is used to reducethe output power level to a range that could be measured with a AgilentE4417A power meter. The power meter has a maximum RF input level of100 mW that is significantly less that the maximum power delivered by theamplifiers which could be up to 20 W.Power AmplifierTunable Matching Network40 dB AttenuatorPower MeterDC SourceWaveform GeneratorVDDVDriverpulseFigure 2.10: Experimental test bed to verify the power class-E power am-plifiers.412.5. Experimental Resultsoscilloscopewaveform generatormulti-meterDC Power Sourcematching networkpower meter40 dB attenuatorPower Amplifier PCB(a)(b)Figure 2.11: Photos of the experimental test bench for characterizing theclass-E power amplifier (a) and an assembled class-E power amplifier (b).Each class-E amplifier was measured in the test bench shown in Fig-ure 2.11a and an example of the assembled class-E amplifier is shown inFigure 2.11b. The same circuit board is used for both frequency bands422.5. Experimental Resultsexcept the component values are different for each band.A four channel Keysight DSOX2024A is used to monitor the gate anddrain voltage waveforms in the amplifier circuit as well as the output loadvoltage. The drain voltage monitoring is done for two main purposes:• Safe region operation: The voltage should not exceed the maximumvoltage rating of EPC2037 which is 100 V.• Class-E operation: The switching transitions must occur at zero volt-age to maintain class-E operation.The measured class-E power amplifier waveforms for the drain voltage,gate voltage, and the RF load voltage are shown in Figure 2.12 for both13.56 MHz and 27.12 MHz with 22 V DC input voltage. The drain voltagewaveforms closely follow an ideal class-E voltage waveform and confirm theclass-E operating mode. As mentioned in Section 2.3, in a practical circuit,the PCB trace inductance causes ringing on the gate-source voltage. Withreference to Figure 2.2, damping resistors R1 and R2 are adjusted to mini-mize the impact of trace inductance. Figure 2.12 shows that the ringing issmall and will not damage the transistor. Also, it shows the sinusoidal RFoutput load voltage. The sinusoidal load voltage confirms that the opera-tion of the loaded Q of the output resonator is sufficient to attenuate higherharmonic frequency components that exist in the drain voltage waveform.432.5. Experimental ResultsTime (ns)0 50 100 150 200Voltage (V)-40-20020406080100120Drain Gate Output RF(a) 13.56 MHzTime (ns)0 20 40 60 80 100Voltage (V)-40-20020406080100120Drain Gate Output RF(b) 27.12 MHzFigure 2.12: Measured class-E power amplifier drain voltage, gate, and out-put voltage waveforms for amplifiers at 13.56 MHz and 27.12 MHz. Thegate voltage is scaled by a factor of sixteen.The experimental output power and the drain efficiency are recorded inFigure 2.13 for the input DC voltage changes from 1 V to 26 V at 13.56 MHzand it is varied up to 25 V at 27.12 MHz. According to the simulation re-442.5. Experimental Resultssults in Figure 2.5, the simulated drain efficiency was 95% for a maximumoutput power of 20 W. However, the experimental results show that for anoutput power range from 2 W to 9 W, the class-E amplifiers maintained highefficiency ranging from 85.5% to 82%, respectively. A comparison of the sim-ulation and experimental results shows that the measured drain efficiencyis decreased by up to 13% compared to simulation results. The simulationresults are optimistic and use ideal passive components and the circuit sim-ulation neglects parasitic inductance and capacitance associated with thePCB layout. Despite losses in the practical circuit very good efficiency isobtained at both 13.56 MHz and 27.12 MHz. The results at 27.12 MHzare particularly encouraging as less research work has reported on powerconverters for this frequency band.Output Power (W)2 4 6 8 10 12Efficiency (%)818283848586878813.56 MHz 27.12 MHzFigure 2.13: Experimental drain efficiency versus output power of the class-E amplifiers at 13.56 MHz and 27.12 MHz.452.6. Chapter Summary2.6 Chapter SummaryIn this chapter, the inverters used in the transmitter of the CPT system aredesigned, simulated, and experimentally tested. The class-E power ampli-fier topology is selected because of its high efficiency and a simple circuitthat consists of a single switching device. Although the class-E theory yieldsideally 100% efficient power conversion, there are many practical considera-tions that limit the efficiency and power of an experimental circuit. Differ-ent practical aspects were considered including inductor models, PCB traceinductance, parasitic capacitance of the power transistor, and thermal man-agement. The experimental lab prototypes have lower efficiency and outputpower than circuit simulated results. The discrepancy between measuredand simulated results is attributed to limitations in the simulation modelthat does not include inductor losses, PCB stray capacitance and thermaltemperature changes in the switching device.46Chapter 3Class-E Rectifier3.1 IntroductionThis chapter is dedicated to the receiver system design for the CPT system.Each power amplifier (inverter) needs a complementary rectifier as a receiverto form a RF DC-DC converter for a CPT system. The principle of timereversal duality is employed to design rectifiers from the resonant class-Epower amplifiers. An important aspect of the rectifier design is to implementan appropriate feedback network to generate a gate drive signal from theinput RF port of the rectifier. In this case, the drain and gate voltage shouldhave an approximately 180◦ phase difference to obtain efficient rectification.The theory of time reversal duality and the design of the feedback network tosynchronously switch the transistor will be described. Using this theory, twoclass-E rectifiers are designed for the 13.56 MHz and 27.12 MHz frequencybands.The power conversion efficiency of a RF rectifier depends on the DC loadresistance at the output of the rectifier. In general, there is an optimum loadresistance that maximizes efficiency and this may not coincide with the op-timum load that maximizes load power. Circuit simulations under differentload conditions evaluate load power and efficiency. From the simulations,473.2. Class-E Rectifier Theorythe optimum load resistance is found.In the last part of this chapter, the experimental results are presented toverify the rectifier design. The performance of the rectifier is evaluated ina back-to-back configuration where the inverter (class-E amplifier) outputis directly connected to the input port of the rectifier. The experimentalresults verify the design methodology of the class-E rectifiers.3.2 Class-E Rectifier TheoryIn power amplifier circuits, DC input power is used to generate RF outputpower. If the amplifier is 100% efficient, all the DC input power is con-verted to RF load power. A rectifier does the reverse, and converts RFinput power to DC output power in the load. In this way, an amplifier andrectifier are dual circuits in terms of power flow. The duality in power flowis theoretically derived from the concept of time reversal duality.3.2.1 Time Reversal DualityTime reversal duality is a powerful theory to synthesize a rectifier circuitfrom an inverter. An early example of time reversal duality for inverter andrectifier design was given by David C. Hamill [1]. The time domain voltageand current waveforms of the power amplifier and rectifier are associatedwith the time reversal duality concept. This means that the amplifier circuitis manipulated to design the rectifier. Based on time reversal duality, thevoltage waveform of the amplifier network v(t) becomes a voltage v(−t) inthe rectifier network. In addition, the original current waveform i(t) of the483.2. Class-E Rectifier Theoryamplifier becomes −i(−t) in the rectifier network. Therefore, the switchingdevice should have the ability to carry the current in both directions withthe same circuit design. In the inverter, the DC input power flows to theRF output load, while in the rectifier the RF input power is transferred tothe DC output load as illustrated in Figure 3.1.LDDCPRectifierLO CO LSRLDDRCPVDDLO CO LSPower AmplifierFigure 3.1: In a class-E amplifier, power flows from the DC supply to theRF load. In a class-E rectifier, power flow is reversed; power flows from theRF input source to a DC load thereby converting RF power to DC power.Table 3.1 shows the electrical quantities of a time reversed dual networkcompared to the original network. Except for current and power, the otherparameters are time reversed. The negative sign and time reversal for aver-age current and power over a cycle shows the change of direction for currentand power (in comparison to the current and power direction of the originalnetwork).493.2. Class-E Rectifier TheoryOriginal Network Time Reversed NetworkVoltage V(t) V(-t)Current I(t) -I(-t)Power P(t) -P(-t)Inductor L LCapacitor C CResistor R -RTable 3.1: A comparison of electrical parameters in the original circuit andthe equivalent circuit obtained after time reversal concepts are applied tothe original network [1].3.2.2 Synchronous RectifierThe rectifier is derived from a high efficiency class-E power amplifier by usingtime reversal dual theory. Figure 3.2 shows the circuit schematic of the syn-chronous rectifier. The feedback path generates a gate drive waveform fromfrom the input RF source port. In this way, the rectifier is synchronouslyswitched with the applied RF input signal. In order not to exceed the max-imum gate driver input voltage, the RF voltage is attenuated through aresistor Ratt after passing through the DC block capacitor CDC . Ratt witha high impedance (500 Ω) is chosen to minimize loading the 20 Ω inputRF port. A low pass filter with a Butterworth (maximally flat) frequencyresponse produces the appropriate phase shift for the rectifier and the twodiodes clip the signal amplitude to generate a switched signal that can drivethe GaN-FET.503.2. Class-E Rectifier TheoryLDDCPLO CO LSLoad NetworkEPC2037R2R1Series ResonatorOUTHOUTLINMVDDGNDINPLMG1020+5VCb RF SignalGate Driver+2VLRattLCCDCButterworth filterRdc CbFeedback LoopFigure 3.2: Synchronous class-E rectifier circuit; the feedback loop createsthe desired pulsating waveform for the gate drive oscillator from the inputRF voltage.The gate of the GaN-FET should be switched with the proper relativephase shift with regards to the drain voltage and current. There is approx-imately 180◦ phase shift between the gate and the drain voltage waveformto achieve a high power efficiency. The 2.5 ns nominal propagation delay ofthe gate driver is considered to create the appropriate phase delay. In otherwords, the filter network creates approximately 168◦ and 155◦ phase shiftat 13.56 MHz and 27.12 MHz, respectively.The Butterworth filter is designed to have the required phase shift at theoperating frequency. The values for the filter elements are given in equations(3.1), (3.2), and (3.3).513.2. Class-E Rectifier TheoryL1 =g1Rωc(3.1)C =g2Rωc(3.2)L2 =g3R2π fc(3.3)In the equations, the constants g1, g2, and g3 are the canonical element valuesfor a third order Butterworth low pass filter with termination resistances of1 Ω and a cut-off frequency of 1 rad/s. The low pass filter prototype isimpedance scaled by R = 500 Ω and frequency scaled by fc. The low passfilter is designed and simulated separately to create the required phase shiftat the operating frequency. The designed filter is connected in the feedbackloop of the rectifier and it is optimized based on the drain and gate voltagewaveforms. The optimized filter component values for the rectifier designsare shown in Table 3.2. Therefore, the low-pass filter with the gate drivercreates the 180◦ phase delay between the drain and gate voltage.Operating Frequency 13.56 MHz 27.12 MHzCut-off Frequency 12.5 MHz 26.4 MHzInductor (µH) 6.3 µH 3 µHCapacitor (pF) 51 pF 24 pFTable 3.2: Third order Butterworth filter component values for two differentfrequency bands.523.3. Simulation Results3.3 Simulation ResultsA comparison of the drain voltage and drain current waveforms in the in-verter and the rectifier are shown in Figure 3.3. Both circuits have typicalclass-E waveforms and the results are shown at 13.56 MHz and 27.12 MHz.According to the time reversal duality concept, the voltage waveforms aretime reversed, while the current waveforms are time reversed with the addi-tion of a sign change in the rectifier current waveform.533.3. Simulation ResultsTime (ns)0 50 100 150 200Darin Voltage (V)020406080100120Power Amplifier Rectifier(a)Time (ns)0 50 100 150 200Drain Current (A)-2-10123Power Amplifier Rectifier(b)Time (ns)0 20 40 60 80 100Darin Voltage (V)020406080100120Power Amplifier Rectifier(c)Time (ns)0 20 40 60 80 100Drain Current (A)-2-10123Power Amplifier Rectifier(d)Figure 3.3: The simulated drain voltage and current waveforms in the in-verter and rectifier. The waveforms confirm that the inverter and rectifierare time reversed circuit duals. The voltage waveform (a) and current wave-form (b) are for 13.56 MHz, while (c) and (d) are the voltage and currentwaveforms for 27.12 MHz.In Figure 3.4, the drain and gate voltage waveforms from circuit simula-tions show that the 180◦ phase shift is created properly in the synchronousclass-E rectifier designs. Changes to the input RF voltage do not disruptthe feedback operation. Therefore, the square pulse waveform fed to thegate driver is identical for different input RF voltages.543.3. Simulation ResultsTime (ns)0 50 100 150 200Voltage (V)020406080100120Drain 18Gate(a) 13.56 MHzTime (ns)20 40 60 80 100 120Voltage (V)020406080100120Drain 18 Gate(b) 27.12 MHzFigure 3.4: Simulated drain and gate voltage waveforms for the synchronousclass-E rectifiers: (a) 13.56 MHz; (b) 27.12 MHz.The synchronous rectifier is designed for high RF input power levelstypical of the power levels that are expected on the receive side of the CPTsystem. Since most RF test equipment does not generate sufficient RFpower, the rectifier is tested in a back-to-back configuration with the poweramplifier. The same configuration is used in the circuit simulations to have aconsistent comparison of the simulation and experimental results. Therefore,the inverter loss is also included in the measurement of the power efficiencyof the rectifier. In this thesis, the overall system efficiency is defined as theratio of the rectifier output DC power over the input DC power supplied tothe class-E power amplifier.As described in [55], the rectifier tracks the maximum power efficiencypoint by adjusting the DC load resistance for changes in RF input power.In this thesis, the optimum DC load of the rectifier is found by sweepingthe DC load resistance for a constant DC input power applied to the poweramplifier. Figure 3.5 shows the output power and efficiency of the rectifier553.3. Simulation Resultsfor changes in DC load resistance for a 19 V input DC voltage.DC Load (Ohm)20 30 40 50 60Power (W)468101214Efficiency (%)60657075808590Output Power Efficiency(a) 13.56 MHzDC Load (Ohm)20 30 40 50 60Power (W)468101214Efficiency (%)60657075808590Output Power Efficiency(b) 27.12 MHzFigure 3.5: Simulated results showing the DC load power and overall systemefficiency as a function of DC load resistance.According to Figures 3.5a and 3.5b the optimum load of 30 Ω and 40 Ω isdefined for the 13.56 MHz and 27.12 MHz rectifiers, respectively. Figure 3.6shows the the overall system efficiency versus output DC power variationwith the optimum load at the operating frequencies. It can be concludedthat the efficiency for both frequencies is almost identical. Moreover, atpower levels greater than 12 W, the efficiency is almost constant for bothoperating frequencies. A peak efficiency of approximately 88% is obtainedat an output power of 18 W.563.4. Experimental Results 2 4 6 8 10 12 14 16 18 74767880828486889092   Figure 3.6: The simulated overall system efficiency versus DC output powerof the rectifier in a back-to- back configuration. Overall system efficiencyincludes the inverter and rectifier loss.3.4 Experimental ResultsAll the discussions presented in Section 2.4 related to practical circuit con-siderations are also valid for the experimental implementation of class-Erectifiers. The low loss core material and inductor winding, thermal de-sign and the PCB layout considerations are evaluated in the rectifier circuitboard design as well. In addition, the feedback loop plays a significant rolein the rectifier to achieve a high efficiency. The phase shift of the drain andgate voltage can be controlled with the low-pass filter in Figure 3.2. Thefeedback loop design is more challenging in practical circuit boards due tothe trace capacitance in the PCB layout because the trace capacitance canchange the phase shift on the circuit board. As a way to compensate for the573.4. Experimental Resultsvariability of the trace capacitance, the fixed capacitor in the low-pass filter(C) is replaced with a trimmer capacitor on the circuit board. In this way,the capacitance in the feedback loop can be adjusted to create the requiredphase shift.The rectifier circuits require high input RF power levels. Since a highpower RF source was not available in the laboratory, the class-E inverteris used in the rectifier test as the RF input source. Therefore, the rectifiercircuit board is tested in a back-to-back configuration with the class-E in-verter as shown in Figure 3.7. A block diagram of the test system is shownin Figure 3.7 and a photo of a class-E amplifier connected to the RF inputof a class-E rectifier is shown in Figure 3.8.Power AmplifierDC SourceWaveform GeneratorRectifierIT8511A Itech DC LoadVDDVDriverpulseFigure 3.7: The block diagram of the rectifier test system.583.4. Experimental ResultsFigure 3.8: The photo of a class-E inverter (left) connected to the RF inputport of a class-E rectifier (right) in a back-to-back configuration.The experimental gate and drain voltage waveforms are shown in Fig-ure 3.9 for the synchronous rectifier at 13.56 MHz and 27.12 MHz. Fig-ure 3.9 verifies that the feedback loop of the synchronous rectifier is adjustedproperly to create the desired 180◦ phase shift between the drain and gatewaveform. The gate-source voltage is scaled by a factor of 10 for betterillustration.Time (ns)0 50 100 150 200Voltage (V)020406080 Drain-Source Scaled Gate-Source(a) 13.56 MHzTime (ns)0 20 40 60 80 100Voltage (V)020406080 Drain-Source Scaled Gate-Source(b) 27.12 MHzFigure 3.9: The drain and gate waveforms of the synchronous class-E recti-fiers are measured at 13.56 MHz and 27.12 MHz. The gate-source voltageis scaled by a factor of 10.593.4. Experimental ResultsUsing the test system shown in Figure 3.7, an IT8511A Itech DC loadis used at the output of the rectifier. The DC load resistance can be sweptto find the optimum load resistance that maximizes the overall efficiency ofthe amplifier and rectifier. Experimental results are shown in Figure 3.10.For the 13.56 MHz frequency band, the optimum load is approximately 30 Ωand for the 27.12 MHz frequency band, the optimum load is approximately40 Ω. The shape of the efficiency versus load characteristics are similar tothe results obtained from the circuit simulations shown in Figure 3.5.Output DC Load (Ohm)15 20 25 30 35 40 45Power (W)246810Efficiency (%)6065707580Output DC Power Efficiency(a) 13.56 MHzOutput DC Load (Ohm)20 30 40 50Output Power (W)246810Efficiency (%)6065707580Output DC Power Efficiency(b) 27.12 MHzFigure 3.10: Measured load power and overall efficiency of the class-E am-plifier and synchronous rectifier as a function of DC load resistance with19 V input DC voltage.The measured efficiency of the back-to-back configuration of the amplifierand rectifier versus output power is shown in Figure 3.11. The nominalefficiency of the 13.56 MHz design is approximately 80%, while the nominalefficiency is approximately 75% for the 27.12 MHz design. The efficiency ofthe 27.12 MHz is about 5% less than the 13.56 MHz.There are three major differences between the simulation and experi-603.4. Experimental Resultsmental results.• The efficiency is lower than simulation results for both 13.56 MHz and27.12 MHz because the components are ideal in the simulation andthe experimental loss is not considered in the simulation.• As the output power increases, the overall efficiency drops. Higherpower results in higher currents passing through the components. Highercurrents would generate more heat. Hence, the higher output powerwill result in higher temperature in the components that yields toefficiency reduction.• The efficiency at 27.12 MHz is lower than 13.56 MHz rectifier design.The reduced efficiency at higher switching frequencies is expected forseveral reasons. First, at 27.12 MHz, the gate switches twice as manytimes as 13.56 MHz. Power is dissipated in the driver and the switchingtransistor every time the switch state is changed. Therefore, higherswitching losses are expected at higher frequencies. Second, the drainvoltage and drain current have a small overlap period during changesin switch state. The overlap generates dissipation in the switch thatreduces efficiency. The relative duration of the overlap period is longerat higher frequencies. Therefore, overlap loss is expected to be higherat 27.12 MHz. Both switching and overlap loss are higher at 27.12 MHzcompared to 13.56 MHz and consequently lower power efficiency isexpected at 27.12 MHz compared to 13.56 MHz.613.5. Chapter SummaryOutput Power (W)2 4 6 8 10 12Efficiency (%)707274767880828413.56 MHz 27.12 MHzFigure 3.11: Overall efficiency of the back-to-back rectifier and inverterfor different output power levels is measured with 30 Ω and 40 Ω load at13.56 MHz and 27.12 MHz, respectively.3.5 Chapter SummaryThe design of the CPT receiver system was presented in this chapter. Highefficiency rectifiers are a primary component in a wireless power transferreceive system. The theory of time reversal duality has been applied to de-velop resonant synchronous rectifiers. According to this principle, class-EAC-to-DC conversion is the time reversal dual of class-E DC-to-AC conver-sion. Therefore, the rectifier circuit is the time reversed dual of the poweramplifier circuit developed in Chapter 2. The rectifier also includes a feed-back path from the input AC power to the gate drive oscillator to makea synchronous rectifier. Simulation results were presented to validate thetheoretical discussions. Finally, laboratory prototypes were built to validate623.5. Chapter Summarythe simulation results.63Chapter 4DC-DC Converter LoadCircuits4.1 IntroductionThis chapter presents a methodology for optimum load tracking of the rec-tifiers in a CPT system. DC to DC converters (DC choppers) are employedin various applications such as battery chargers [56], maximum power pointtracking [57], voltage regulation [58], LED drivers [59], energy storage sys-tems [60], and electric vehicles [61]. The main goal in these converters is tocontrol the output voltage by adjusting the duty cycle (the ratio of the timeswitch is on to the time of a period) of the transistor which commonly iscalled the switch. In other words, by controlling the input impedance, theconverter is able to control the output voltage (power). In this thesis, theaforementioned characteristic of the DC-DC converters is used as a variableDC load for the rectifier in order to extract the maximum efficiency fromthe WPT system.644.2. Converter Selection4.2 Converter SelectionA DC-DC converter is used as a variable resistive load in this study. Basedon this application of DC-DC converters, in order to determine the properconverter topology for this study, the input impedance of conventional DC-DC converters is analyzed and compared.Figure 4.1 shows the DC-DC converter as an interface device between aload resistor and an input power source. The converter is controlled by theduty cycle D. In this section, the goal is to find the input impedance of theconverter as a function of D and RLoad.RLoadDC-DC ConverterVinIin ILoadDFigure 4.1: DC-DC converter shown as an interface device between the loadand power source.According to Figure 4.1, the output voltage of the converter isVo = ILoad ×RLoad (4.1)and the input equivalent resistance of the converter is654.2. Converter SelectionRin =VinIin(4.2)The objective is to analyze a DC-DC converter and find the relationbetween Rin and RLoad. For basic DC-DC converters, the voltage gain Mis defined asM =VoVin(4.3)whereM is a function of duty cycle D. Similarly, the current gain is definedasILoadIin=1M(4.4)Solving for the output voltage in (4.3) we haveVo =M Vin (4.5)and solving for the output current in (4.4) we haveILoad =IinM(4.6)Substituting (4.5) and (4.6) in (4.1) results inM Vin =RLoadIinM(4.7)Rearranging (4.7), the effective equivalent input resistance of the DC-DCpower converter is664.2. Converter SelectionRin =VinIin=1M2RLoad (4.8)Equation 4.8 shows that the input terminals of the converter shown inFigure 4.1 acts as a variable resistance whose value depends on the loadresistance and the converter’s duty cycle which determines M . A simplifiedequivalent circuit of the DC-DC converter is shown in figure 4.2.Rin(D,RLoad)VinIin ILoadDC-DC ConverterFigure 4.2: Equivalent resistance of the DC-DC converter from the sourceside.DC-DC converters can operate either in Continuous Current Mode (CCM)or Discontinuous Current Mode (DCM). In the CCM mode, the voltage gainM depends only on the duty ratio. In the DCM mode of operation, the volt-age gain depends on the duty cycle, the inductor value (L), and the switchingfrequency (fs). The inductor value is usually a constant and does not changeduring the operation of the converter. In this study, the switching frequencyis kept constant as well. Therefore, the voltage gain in the DCM operationmode only depends on duty ratio as is the case for the CCM mode.674.2. Converter SelectionDifferent converter circuit topologies with their corresponding voltagegains are listed in Table 4.1 for CCM and DCM modes. The voltage gainis expressed in terms of duty cycle D and a constant K where K = 2LfsR .One can refer to [62] for further details of the voltage gain calculations. Aconcise and simple comparison of these converters in CCM mode with theircurrent gain is given in [63].Topology Circuit Model Voltage gainbuckC RVinDLS +VO-MCCM = DMDCM =21+√1+ 4KD2boostC RVinDLS+VO-MCCM =11−DMDCM =1+√1+ 4D2K2buck-boost C RVinLDS +VO-MCCM =D1−DMDCM =D√KTable 4.1: Basic DC-DC converter topologies with their corresponding volt-age gain both in DCM and CCM operational modes.In order to get a better idea how the input impedance of the converterschanges by varying the duty cycle, Figure 4.3 shows the input resistance ofthe DC-DC converters listed in Table 4.1 versus duty cycle. It is assumed684.2. Converter Selectionthat the converter parameters are the same for all the converters in theDCM operating mode. A 5 µH inductance, a 20 Ω output resistance, and aswitching frequency of 500 kHz are considered for this comparison. Basedon this, the coefficient K is calculated as 0.25.Depending on the application and the required load change, one can de-cide which converter is suitable to implement. Figure 4.3 shows that theboost converter has the least input impedance change among these con-verters. It is shown that both buck and buck-boost converters can covera relatively large range of input impedance. Since the output voltage ofbuck-boost converter is inverted, the control circuit of buck-boost converteris more sophisticated than the buck converter. Based on this comparison,the buck converter is chosen as the variable resistance for the wireless powersystem application. 0.2 0.3 0.4 0.5 0.6 0.7 050100150200Figure 4.3: Effective input resistance Rin comparison of boost, buck, andbuck-boost DC-DC converters operating in DCM as a function of duty cycleD. Results are shown for L = 5 µH, RLoad = 20 Ω, and fs = 500 kHz.694.3. Buck Converter Theory4.3 Buck Converter TheoryIn this section, the theory of the buck converter operating in the DCMmode is discussed briefly. For further details one can refer to [64]. TheDCM operation of the buck converter is depicted in Figure 4.4.C RVinDLS +VO-(a)C RVinDLS +VO-(b)C RVinDLS +VO-(c)Figure 4.4: DCM switching states in a buck converter: (a) Step 1 [0, DTS ],(b) Step 2 [DTs, (D +D2)Ts], and (c) Step 3 [(D +D2)Ts, Ts].704.3. Buck Converter TheoryAs shown in Figure 4.4, the DCM operation of the buck converter canbe divided into three time spans (steps):Step 1 [0, DTS ]: During this interval the switch is ON and the diodeis OFF. The inductor current starts from 0 to increase until reaching itsmaximum at DTS . This mode is shown in Figure 4.4a. Kirchhoff’s VoltageLaw (KVL) and Kirchhoff’s Current Law (KCL) in this step are:Vin − VC − Ldiindt= 0 (4.9)iL = iC + io = CdvCdt+vCR(4.10)Step 2 [DTs, (D +D2)Ts]: During this interval the switch is OFF andthe diode is ON. The inductor current starts to decrease until it reaches tozero at (D + D2)Ts. This mode is shown in Figure 4.4b. KVL and KVLequations in this step are:LdiLdt+ vC = 0 (4.11)iL = iC + io = CdvCdt+vCR(4.12)Step 3 [(D +D2)Ts, Ts]: In this interval both the switch and diode areOFF and the inductor current remains zero. This interval ends once theswitch is ON and the next cycle starts. This mode is shown in Figure 4.4c.The inductor voltage and KCL equations in this step are:714.3. Buck Converter TheoryLdiLdt= 0 (4.13)CdvCdt+vCR= 0 (4.14)Considering these three steps, the inductor current and the inductorvoltage are illustrated in Figures 4.5a and 4.5b, respectively. The averageinductor current is calculated as:iL(t)avg =1TS∫ TS0iL(t)dt =D +D22iLmax =(D +D2)(Vin − vC)2vCDTS(4.15)Based on the volt-second balance on the inductor and isolating D2 wehave:D2 =Vin − vCvCD =(2LfsDR)21 +√1 + 2LfsD2R(4.16)The boundary duty cycle below which the converter operates in the DCMmode is:Dboundary = 1− 2LfsR(4.17)In addition to 4.17, the condition that is required to operate in the DCMmode is:k =2LfsR< 1 (4.18)724.4. PWM ControllerUsing the definition of k in 4.18 means that if k > 1, the converter operatesin the CCM mode for any value of duty cycle.Further details about the converter design, including component sizing,can be found in [64]. Other methods to reduce ripple in the output voltageand inductor current can be made by adding interleaved stages which alsoimproves the reliability of the converter [65, 66].iL TS DTS (D+D2)TS (a)vL TS DTS (D+D2)TS vin-vC -vC (b)Figure 4.5: Typical inductor waveforms for the DCM buck converter oper-ation: (a) inductor current and (b) inductor voltage.4.4 PWM ControllerDifferent techniques can be implemented for the control of the switch. Themost common and well-known method is the Pulse Width Modulation (PWM)technique [67]. As discussed in previous sections, the converter output volt-age is controlled by the duty cycle. The PWM technique provides a conve-nient way to generate the proper signal with the desired duty cycle.In the PWM method, a carrier wave is compared to a modulating waveas shown in Figure 4.6. The carrier is usually a sawtooth waveform. Themodulating signal is also known as the control wave in some literature.For DC-DC converters, the modulating or control wave is a constant value734.4. PWM Controllersignal. The ratio of the modulating signal to the peak value of carrier signalwill result in a specific duty ratio. For the purpose of producing the propergate-source signal for the converter MOSFET, the sawtooth carrier andmodulating signals are fed into a comparator as shown in Figure 4.7. If thecarrier is greater than the modulating signal, then the comparator outputis low (zero), and conversely, if the carrier is greater than the modulatingsignal, the comparator output is high. It is noteworthy that the switchingfrequency is determined by the frequency of the carrier signal.VM modulating carrier D(t) TS DTS 2TS Figure 4.6: Illustration of the concept of pulse width modulation (PWM).VM D(t) comparator Figure 4.7: Circuit to generate PWM with a comparator.744.5. Experimental Results4.5 Experimental ResultsWith the intention of validating the theoretical discussions, a buck con-verter is designed and lab prototypes are built. The design parameters andcomponent part numbers are listed in Table 4.2.Parameter Part Number/ValueSwitch SSM3K361RDiode PMEG10020Inductor 5 µHCapacitor 11 pFLoad 20 Ωfs 500 kHzPWM Controller LM3477Table 4.2: Buck converter circuit parameters and components selected forthe experimental circuit.A PWM controller, a current sensor, and a buck converter power circuitare used to implement a prototype. Figure 4.8 shows a picture of the finalconverter circuit assembled on a PCB.Figure 4.8: A laboratory prototype of the buck converter including the PWMcontroller.754.5. Experimental ResultsThe LM3477 from Texas Instruments is a 500 kHz PWM controller forMOSFET based switching DC-DC converters. The LM3477 generates agate drive signal for the buck converter. The control scheme of the LM3477is based on the current mode which may cause subharmonic oscillationsin the buck converter inductor current. In order to avoid this issue, slopecompensation must be considered. The voltage at feedback pin (pin 3)must remain at 1.27 V. Hence, the resistive voltage divider consisting ofR3, R5, and R6 determines the output voltage of the converter. Based onthe fact that the output voltage affects the duty cycle, R5 is chosen as apotentiometer so we can adjust the duty cycle by changing the R5 value.The output voltage of the converter is determined by the following equation:Vo = 1.27× (1 + R3R5 +R6) (4.19)The voltage gain of the converter considering the diode forward voltagedrop VD, the drain-source voltage of the MOSFET VDS , and the voltage dropacross the input sensing resistor (connected to pin 6) VSEN is calculated byM =Vo + VDVin + VD − VDS − VSEN ≈VoVin(4.20)Based on the voltage gain determined by (4.20), the duty cycle of the buckconverter operating in DCM is obtained byD =√8LfsR((2−MM )2 − 1) =√8LfsR((2Vin+VD−2VDS−2VSEN−VoVo+VD )2 − 1) (4.21)764.5. Experimental ResultsAs seen by equation 4.21, the formulation of the other parameters such asminimum and maximum achievable duty cycle by LM3477 gets very com-plicated and is out of scope of this study.In this study, a method of measuring the input impedance of the con-verter is required for experimental verification. A current sensor is designedto monitor the input current of the converter and the input voltage is mon-itored externally using an oscilloscope. The current sensor is also addedas an incremental step to evaluate a circuit that could be integrated into afully automated adaptive load circuit where an analog-to-digital converter(ADC) could measure the voltage from the current sensor. The input volt-age is monitored using an oscilloscope and, in future work, the voltage couldbe measured with an ADC. A high-side current monitoring chip (INA138)manufactured by Texas Instruments is used for current sensing. The INA138measures a differential voltage across a current sense resistor and the volt-age gain is set by a resistor. With reference to Figure 4.9, the current senseresistor is R1 and the gain resistor is R8. The voltage at the output pin ofthe INA138 is given by:Vo−INA138 =ISR1R85kΩ(4.22)The input shunt resistor should be a very small resistor in the rangeof a few milliohms. The input sense resistor (R1) of the PWM is usedfor the current sensor resistor Rs as well. For the ease of conversion andcurrent recording, the gain is chosen such that Vo−INA138 = IS . Thus, R8 iscalculated by (4.23).774.5. Experimental ResultsR8 =5 kΩR1(4.23)A circuit diagram of the complete variable DC load circuit is shown inFigure 4.9.LM3477127456 38R2C4R5 R3R6C3 R4PWM Pulse GeneratorR1MOSFET SourceBuck ConverterOutput VoltageMOSFET DrainMOSFET GateINA1388765 4321R8R7C5VCCCurrent SensorVin From Power SupplyVo_INA138Figure 4.9: Circuit schematic of the LM3477 PWM controller and theINA138 current sensor integrated with the buck converter.In order to verify the variable load operation, first the buck converter istested individually. Therefore, the converter is fed from a Agilent E3634A200 W DC power with adjustable output voltage up to 25 V. Typical wave-forms of the buck converter are recorded by setting the E3634A to 15 V.Figure 4.10 shows the buck converter test bench.784.5. Experimental ResultsBuck Converter Power CircuitINA138LM3477Agilent E3634ADC SourceFigure 4.10: The buck converter is connected to the Agilent E3634A DCpower supply to validate the circuit. The input voltage of the buck converteris set to 15 V.Figure 4.11 shows an example of a measured gate waveform which hasa duty cycle of approximately 73%. The figure also shows the DC inputand DC output voltages. The output voltage is 11 V, the input voltage is15 V, and the voltage gain M is 0.73 which confirms the relationship withthe duty cycle. Substituting K = 0.25 and D = 0.73 in the buck converterDCM voltage gain equation given in Table 4.1, the theoretical voltage gainis calculated as 0.74.794.5. Experimental ResultsTime (microsecond)0 2 4 6 8 10Voltage (V)0102030Output DC VoltageInput DC VoltageGate VoltageFigure 4.11: Measured waveforms in the variable DC load circuit. The gatewaveform has a duty cycle of 0.73 and converts a DC input voltage of 15 Vto an output of 11 V.The duty cycle changes the input impedance of the converter with aconstant input DC voltage. Figure 4.12 demonstrates the input impedancechange as a function of duty cycle. The input resistance varies from 25 Ω to180 Ω which validates the theoretical calculations presented in Figure 4.3.The primary goal is to use the converter as a variable resistive load forthe rectifier. According to Figure 4.12, for an optimum load resistance inthe range of 25 Ω to 45 Ω, the PWM controller operates in a range whereD > 60%.804.5. Experimental ResultsDuty Cycle (%)20 30 40 50 60 70 80 90Impedance (Ohm)20406080100120140160180Input ImpedanceFigure 4.12: The measured equivalent input resistance of the buck converterversus the duty cycle ratio.As stated before, the buck converter is used as a variable load for therectifier. Therefore, the next step is to test the buck converter with a back-to-back configuration consisting of a power amplifier and rectifier system.Figure 4.13 shows the integrated test bench for the buck converter.Class-E RF Power Amplifier (Inverter)Class-E RF RectifierBuck Converter Power CircuitINA138LM3477buck converterRF DC-DC systemAgilent E3634ADC SourceRigol DG4162Waveform GeneratorFigure 4.13: The buck converter is connected to the back-to-back RF poweramplifier and rectifier (RF DC-DC) system to validate the integrated oper-ation.After testing the DC load circuit with the rectifier, it was observed that814.5. Experimental Resultseither the input under-voltage lockout or output over-voltage protectionfeature of the LM3477 PWM controller is activated for duty cycles above40%. The lockout conditions in the controller prevents the control loopfrom working and therefore the PWM controller could not generate DC loadresistances required for the optimum rectifier load. Recall that as shown inFigure 4.12 the optimal resistance range requires duty cycles above 60%.Therefore, the variable load could not meet the optimum impedance rangeof the rectifier in a back-to-back connection of the RF DC-DC system andthe buck converter.Based on the experimental results, the converter needs adjustments forthe CPT application. In order to cover the range of equivalent input resis-tance needed for the CPT application, the output load of the buck converterneeds to be reduced and the resistive voltage divider in the feedback loopof LM3477 PWM generator must be adjusted accordingly. These designchanges are recommended for future work.In summary, measurements of the converter in an isolated configurationdemonstrate that a variable DC resistance can be implemented using switch-ing DC-to-DC converters. Based on the study, the following conclusions aremade:• The control circuit of the buck converter is complicated because of thehigh-side MOSFET in the buck converter topology.• In case a smaller range of impedance variation is required in an ap-plication, the boost converter may satisfy the desired range with asimpler controller circuit than the buck circuit. The buck-boost con-824.6. Chapter Summaryverter is beneficial for high impedance range applications similar tothe buck converter. However, the control is more sophisticated thanthe boost converter.• If a large impedance range is required for an application, the SEPICconverter is recommended. This topology has a continuous input cur-rent that makes the current monitoring easier. In addition, the SEPICconverter MOSFET is a low-side switch that makes the control of theSEPIC much simpler than the buck circuit.4.6 Chapter SummaryThis chapter presented a methodology for optimum load tracking of rectifiersused in CPT systems. DC-DC converters regulate the output voltage bycontrolling the duty cycle of a switching circuit. By adjusting the duty cycle,the input impedance of converter can be changed. The controllable inputimpedance feature of DC-DC converters was used to implement a variableload that could be used as a DC load for the rectifier. The goal of havinga variable load is to maximize the power efficiency of the wireless powertransfer system. The converter was built and tested and the experimentalresults confirm theoretical calculations. However, after connecting the buckconverter in a back-to-back configuration with the rectifier, the LM3477PWM controller detected an overvoltage or undervoltage fault conditionthat prevents the operation of the converter at high duty cycles. Based onthese results and an investigation into the problem, a SEPIC DC to DCconverter is recommended for future work as the advantage of the SEPIC834.6. Chapter Summarytopology is that the current input is continuous and the circuit uses a lowside switch.84Chapter 5Capacitive Wireless PowerTransfer System5.1 IntroductionIn this chapter, the class-E power amplifiers in Chapter 2 and the class-Erectifiers in Chapter 3 are used to implement a capacitive wireless powertransfer system. The characteristics of a typical integrated CPT system fordifferent gap distances will be discussed first and the need for the dual-bandoperation will be identified. Simulation results will be presented to supportthe hypothesis that changing frequency bands can be used to improve theefficiency of the CPT system for different ranges of gap distances. The chap-ter concludes with experimental results that will be shown for 27.12 MHz tovalidate the operation of the power amplifier and rectifier designs in a CPTsystem.5.2 Capacitive WPTThere are several analytic methods for modeling capacitive coupling net-works [68–71]. Ahmadi and his colleagues at UBCO have recently provided855.2. Capacitive WPTa CPT analysis method based on filter theory [69]. The amplifiers and recti-fiers described in this thesis are part of a larger collaborative study with thesame team at UBCO RF and Microwave Technology Laboratory. The CPTcoupling network is characterized and the equivalent parameters have beenprovided by the authors of [69]. The simulation and experimental resultsare done in this work. The simulation and theoretical discussions will bebased on the filter theory provided for the CPT network.The plate shape and size, the gap distance between the plates, the op-erating frequency, and the gap dielectric material affect the coupling capac-itance impedance. The small permittivity constant ϵ0 = 8.85× 10−12 F/mfor air creates a small coupling capacitance which is one of the main limi-tations in the CPT system. Moreover, an increase in gap distance reducesthe coupling capacitance. Matching networks can be used to compensatefor the low coupling capacitance and networks can be synthesized to reachthe desired impedance at the operating frequency.A six-plate coupling structure for CPT is introduced in [72]. Usingsix plates reduces EMI issues and increases system safety and robustness.Therefore, the six-plate CPT structure is used in this study and the platearrangement is shown in Figure 5.1a. Figure 5.1b shows the plate dimen-sions and the inter-plate separation distances are given in Table 5.1. Withreference to Figure 5.1a, the large outer blue plates on each side of the net-work are the ground shield plates. Two pairs of asymmetric disks are placedbetween the ground shields. The disks are electrodes for the coupling capac-itance between the transmitter and receiver. The transmit disks are smallerthan the receive disks to provide tolerance for lateral misalignment. The gap865.2. Capacitive WPTdistance is defined as the distance between the transmit and receive disks.The six-plate CPT configuration is split into two equivalent four-platehalf circuits through the symmetric plane labeled aa′. If a balanced sourceand a load are connected to the system, a virtual ground plane appearsalong plane aa′. The simplified electrical circuit model of the half circuit isshown in Figure 5.1c. Cm is the coupling capacitor between the transmitand receive disks, and CTX and CRX are the equivalent capacitances fromthe ground shield to the transmit and receive coupling disks, respectively.The capacitance between the two outer ground shields is denoted by Cg.Additionally, LTX and LRX are used as the compensation network on eachside of the CPT link. The compensation inductors, LTX and LRX , resonatewith the equivalent capacitance of the coupling network at the operatingfrequency to provide a low impedance path for power transfer.Parameters ValuehTx 1.2 cmhRX 2.4 cml1 20 cml2 10 cmTable 5.1: Inter-plate separation distances for the six-plate CPT network.875.2. Capacitive WPTTX RXa a′Gap Distance(g)l1hTXhRXl2(a)Shield Plate61 cmDTX=10 cmDRX=20 cm83.2 cm(b)LTXCTX CRXCm LRXCgRXTX(c)Figure 5.1: A six-plate CPT system is shown in (a). The six-plate systemconsists of two large outside shield (ground) plates and a pair of copper disksfor the transmitter and receiver. The transmit disks are smaller than thereceive disks to provide tolerance for lateral misalignment. The six-platecan be configured as a four plate system by omitting a transmit and receivedisk shown by the gray highlight. The dimensions of the ground shield andthe CPT disks are shown in (b). The equivalent circuit for the four platesystem with matching (compensation) inductors is shown in (c).885.3. Simulation Results5.3 Simulation ResultsA CPT coupling network transfers RF power from an inverter at the trans-mitter side to a rectifier at the receiver side. The class-E amplifier is designedfor a 20 Ω load in Chapter 2 and the rectifier dual also has a 20 Ω inputimpedance. Therefore, for maximum power transfer, the desired input andoutput impedances for the CPT network are also 20 Ω. Therefore, the CPTcoupling network is designed for 20 Ω by the authors of [69]. The electri-cal circuit model for the CPT half circuit shown in Figure 5.1c combinedwith the circuits for the inverter and rectifier are used to simulate the in-tegrated CPT system. For the system level circuit simulations, the groundcapacitance Cg is assumed to have much lower reactance than the couplingcapacitance Cm. The assumption is valid for a full six-plate system when adifferential transmit and receive configuration is used.In the following discussion, the input power to the CPT system is theinput DC power supplied to the inverter (class-E power amplifier in thisthesis) and the output power is the power delivered to the DC load. Powerlosses in the inverter, CPT network, and rectifier affect the overall efficiency.The overall system efficiency is defined as:η =DC Load Power Delivered by RectifierDC Input Power Supplied to Inverter× 100 (5.1)Simulation results for the CPT system including the inverter, rectifierand capacitive coupling link are discussed next. The effect of the CPTgap distance on the output DC power and the overall efficiency is shownin Figure 5.2. The overall efficiency at 27.12 MHz varies from 73.5% to895.3. Simulation Results80.5% for gap distances from 10 cm to 14 cm. For the same conditions, theload power changes from 7.5 W to 6.3 W as the gap changes from 10 cmto 14 cm. For distances larger than 14 cm, the power and efficiency at27.12 MHz decreases significantly.The significant reduction in efficiency and power at 27.12 MHz for gapdistances greater than 14 cm can be mitigated by switching the operatingfrequency of the CPT link to 13.56 MHz. In this way, the CPT systemcan maintain high power and efficiency by switching to the lower frequencyband at 14 cm. At 13.56 MHz, the CPT system efficiency ranges from 75%to 85% efficiency over gap distances of 15 cm to 20 cm. The correspondingload power for the same range changes from 6.5 W to 8.8 W. According toFigure 5.2a and 5.2b, the CPT system operates at 27.12 MHz in zone A and13.56 MHz in zone B. The plots show how frequency band switching canbe used to compensate for changes in gap distance to improve power andefficiency in the CPT system.905.3. Simulation ResultsGap Distance (cm)5 10 15 20 25Output Power (W)02468101227.12 MHz 13.56 MHzA B(a)Gap Distance (cm)5 10 15 20 25Efficiency (%)02040608010027.12 MHz 13.56 MHzA B(b)Figure 5.2: Simulations results for dual-band switching in a CPT system.The plots in (a) show how DC load power changes with gap distance andthe plots in (b) show how efficiency changes with gap distance. The systemoperates at 27.12 MHz in zone A and switches to 13.56 MHz in zone B.Results are shown for an input DC voltage of 19 V.It is shown in [55] that tracking the optimum DC load resistance of therectifier is essential to maximize the power efficiency for a variable input RFpower. Therefore, load tracking is another significant factor for maintainingefficient power transfer in the CPT system. Figure 5.3a and 5.3b demon-strates the effect of load variation on overall efficiency and output power fordifferent separation gap distances at 13.56 MHz. Similarly, Figure 5.4a and5.4b shows the load variation effect on overall efficiency and output powerfor gap distance sweep at 27.12 MHz.915.3. Simulation Results(a) Overall Efficiency(b) Output DC PowerFigure 5.3: Simulated overall efficiency and output DC power of the CPTsystem as a function of load resistance and gap distance. Results are shownfor a frequency of 13.56 MHz and input voltage of 19 V.925.3. Simulation Results(a) Overall Efficiency(b) Output DC PowerFigure 5.4: Simulated overall efficiency and output DC power of the CPTsystem as a function of load resistance and gap distance. Results are shownfor a frequency of 27.12 MHz and input voltage of 19 V.The simulated power and efficiency results in Figure 5.3 and 5.4 aremagnified in Figure 5.5 and Figure 5.6 to clarify the load resistance variationeffect on the desired separation gap distances. With reference to Figure 5.5aa load resistance range of 25 Ω to 40 Ω is required to track the maximum935.3. Simulation Resultssystem efficiency at 27.12 MHz (for a gap distance range of 10 cm to 14 cm).For maximum system efficiency tracking at 13.56 MHz (for a gap distancerange of 14 cm to 20 cm) Figure 5.5b shows that the load resistance shouldvary from 28 Ω to 40 Ω. The buck converter designed in Chapter 4 was ableto cover a range of 25 Ω to 175 Ω that meets the required load for CPTapplication. The maximum overall efficiency is obtained for each separationgap distance by adjusting the output load resistance. The CPT system ismore efficient in strongly coupled networks and efficiency decreases for largergap distances because of weaker coupling in the system. Furthermore, theoutput DC power is smaller for large gap distances.20 25 30 35 40 45 50 55 60Load Resistance [ ]747678808284868890Efficiency [%]10 cm11 cm12 cm13 cm14 cm(a) 27.12 MHz20 25 30 35 40 45 50 55 60Load Resistance [ ]747678808284868890Efficiency [%]15 cm16 cm17 cm18 cm19 cm20 cm(b) 13.56 MHzFigure 5.5: Simulated overall efficiency of the CPT system as a function ofload resistance and gap distance. Results are for a frequency of 13.56 MHzand input voltage of 19 V.945.4. Experimental Results20 25 30 35 40 45 50 55 60Load Resistance [ ]345678910Output Power [W]10 cm11 cm12 cm13 cm14 cm(a) 27.12 MHz20 25 30 35 40 45 50 55 60Load Resistance [ ]2468101214Output Power [W]15 cm16 cm17 cm18 cm19 cm20 cm(b) 13.56 MHzFigure 5.6: Simulated output DC power of the CPT system as a function ofload resistance and gap distance. Results are for a frequency of 13.56 MHzand input voltage of 19 V.5.4 Experimental ResultsIn this section, an integrated CPT test bed is built and tests are carriedout to show that the designed system is capable of transferring power in alaboratory prototype. In the scope of this thesis, a few sample tests witha half circuit CPT system are measured to exhibit the power transmission.Further comprehensive test results will be published in the future.A block diagram of the half circuit CPT system with the transmitterand receiver is shown in Figure 5.7. The class E amplifier is configured asan inverter and connects to the transmit side of the CPT coupling network.On the receive side of the coupling network, a class-E rectifier is used as thereceiver. The rectifier drives a variable DC load that is implemented with ainstrument from Itech (model IT8511A). The DC load can be programmedfor a specific load resistance (constant resistance mode) or used to sweep theDC load resistance. The Rigol DG4162 is an arbitrary waveform generatorthat is used as the clock oscillator for the gate driver in the amplifier. A955.4. Experimental Resultssquare waveform is created by the waveform generator with 4 V peak topeak amplitude and 2 V DC offset at the operating frequency band.LTXClass-E RF Power Amplifier (Inverter)Class-E RF RectifierLRXIT8511A Itech Gap DistanceVDDAgilent E3634ARigol DG4162VDriverFigure 5.7: A four-plate CPT network is connected to the class-E poweramplifier and rectifier PCB boards.In order to make replacing matching inductors convenient in the CPTtest bed, a terminal block is used. The terminal block is mounted on theback side of the large aluminum shield plates as show in Figure 5.8. Theterminal block introduces additional stray capacitance into the CPT linkcircuit model. The capacitance of the terminal block connector (Ccon) isin parallel with CTX and CTR of the CPT network. The stray capacitanceof the connector is approximately 5.5 pF at 13.56 MHz and 27.12 MHz.Figure 5.9 shows the equivalent electrical circuit model of the half circuitincluding the stray capacitance from the terminal block.965.4. Experimental ResultsFigure 5.8: The matching inductors are connected to the CPT disks throughterminal blocks that make it easy to change the matching inductor.LTXCTX CRXCm LRXCcon CconTX RXCgFigure 5.9: The stray capacitance (Ccon) of the terminal block is in parallelwith the CPT equivalent circuit capacitances CTX and CRX . The straycapacitance is approximately 5.5 pF.An important step in developing the integrated CPT system is to exper-imentally verify that the compensation inductors LTX and LRX are tunedproperly. Inductor values were first obtained from electromagnetic sim-ulations of the physical CPT coupling network. Component values fromsimulations were provided by Masoud Amadi and are shown in Table 5.2.The simulations did not include the stray capacitance from the terminalblock and the experimental system had additional capacitance that intro-975.4. Experimental Resultsduces deviations between simulation and experimental results. Therefore,an experimental method to tune the inductor values was required.The first step was to measure the isolated shunt capacitance of the trans-mitter and receiver plates in the CPT network when the gap distance is verylarge (g → ∞). When the gap is very large, the coupling capacitance Cmand Cg are very small and the transmit and receive plates are essentiallyisolated. If an impedance measurement is made at the transmitter and re-ceiver ports with no matching inductors, the measurements can be used todetermine the shunt capacitances Ccon+CTX and Ccon+CRX . The isolatedcapacitances are measured with a Vector Network Analyzer (VNA) for theoperating frequency bands and the results are shown in Figure 5.10.The next step in the experimental work was to build and tune the com-pensation inductors LTX and LRX . Similar to the measurement of isolatedplate capacitances, the inductors were tuned for the condition where theplates are far apart such that the coupling capacitances are negligible. Un-der this condition, the inductors create a series resonant circuit with theplate and connector capacitances. The inductors were tuned to a resonantfrequency that is shown in Table 5.2. The corresponding VNAmeasurementsare shown in Figure 5.11 where the series resonant frequency is annotatedon the Smith charts. The measurements confirm a series resonance becausethe resistance is very low.985.4. Experimental Results(a) Transmitter (b) ReceiverFigure 5.10: The equivalent isolated capacitance of the transmitter and re-ceiver are measured with the VNA. The capacitance is labelled at 13.56 MHzand 27.12 MHz.(a) Transmitter(b) ReceiverFigure 5.11: Measurements of resonant isolated transmit (a) and receive (b)plates. Measurements are shown for both 13.56 MHz and 27.12 MHz.995.4. Experimental ResultsOperatingFrequencySimulation ExperimentalCapacitor InductorResonanceFrequencyCapacitor InductorResonanceFrequency13.56MHzTransmitter(TX)10.4 pF 13.2 µH 13.58 MHz 16 pF 8.6 µH 13.58 MHzReceiver(RX)19.9 pF 6.8 µH 13.67 MHz 25.6 pF 5.4 µH 13.58 MHz27.12MHzTransmitter(TX)10.4 pF 3.3 µH 27.15 MHz 16.4 pF 2.6 µH 27.18 MHzReceiver(RX)19.9 pF 1.6 µH 27.60 MHz 26.7 pF 1.3 µH 27.20 MHzTable 5.2: Resonator characteristics when the plates are infinitely far apart(g →∞).The experimental test bench of the integrated CPT system is shownin Figure 5.12a. The test bench was used to step through a number ofexperiments to verify the operation of the system.The first step is to verify the switching waveforms in the class-E inverterand rectifier. The waveforms depend on the impedance of the CPT link andthe dc load resistance at the output of the rectifier. Since the goal of thesystem is to maximize the efficiency of transmitting power, it is importantthat the inverter and rectifier operate in an efficient class-E mode. Fig-ure 5.12b shows the class-E mode drain and gate voltage waveforms for a3.2 cm gap distance at 27.12 MHz. The waveforms confirm class-E switch-ing operation and provides an indirect verification of the port impedancesat the transmitter and receiver terminals of the CPT link.1005.4. Experimental Results(a)(b)Figure 5.12: (a) The experimental setup; (b) the corresponding drainand gate voltage waveforms of the inverter and rectifier are measured at27.12 MHz with 3.2 cm gap distance.The second experimental test was made to vary the load resistance andmeasure changes in the output DC power and efficiency for a gap distanceof 3.2 cm. In Figure 5.13, the load resistance sweep can track the maximumefficiency in the CPT system. It can be seen that the maximum efficiency1015.4. Experimental Resultsfor the 27.12 MHz system at 3.2 cm is achieved for a 50 Ω load resistance.As expected from the simulation results, the 13.56 MHz band should havelower power and efficiency for small gap distances. At 3.2 cm, the 13.56 MHzband has lower efficiency and power compared to the 27.12 MHz band.Output DC Load Resistance (Ohm)20 30 40 50 60 70 80Power (W)012345Efficiency (%)30405060Output DC PowerOverall Efficiency(a) 27.12 MHzOutput DC Load Resistance (Ohm)20 30 40 50 60 70 80Power (W)012345Efficiency (%)30405060Output DC PowerOverall Effciency(b) 13.56 MHzFigure 5.13: Experimental measurements of output DC load power andoverall efficiency of the CPT system as a function of DC load resistance. Thegap distance is 3.2 cm and the inverter input voltage is 22 V. Measurementsfor 27.12 MHz are shown in (a) and for 13.56 MHz in (b). The CPT systemhas higher output power and efficiency at 27.12 MHz.For the purpose of finding the optimum gap distance, the load needs tobe swept at each gap distance and then one can find the maximum possiblepower and efficiency of the system. In order to show power can be trans-ferred efficiently over a variable gap distance, gap sweep tests are done for27.12 MHz with a 22 V DC input voltage and a 40 Ω load resistance. Thegap distance is swept from 1.2 cm to 10.2 cm and the results are shown inFigure 5.14. The measurements show that the load power peaks at 4.4 Wat a gap distance of 2.4 cm. The corresponding overall efficiency from DCinput to DC output is approximately 53%. Since the CPT is weakly cou-1025.4. Experimental Resultspled in larger gap distances, the power and efficiency are dropped as the gapdistance is increased.Separation Gap Distance (cm)2 4 6 8 10DC Output Power (W)1234Efficiency (%)2530354045505560Power EfficiencyFigure 5.14: Experimental output DC load power and overall DC-to-DCpower efficiency as a function of gap distance in the CPT system. Measure-ments are shown at 27.12 MHz with 40 Ω load and the inverter DC drainvoltage is 22 V.For further characterizing the CPT, the input voltage of the inverteris swept to change the output power. The test is done for 27.12 MHz at3.2 cm gap distance for a 40 Ω load resistance and the results are shownin Figure 5.15. The results show that the efficiency of the system is robustfor a 11.5 dB load power range that ranges from 0.3 W to 4.3 W. Over thisrange the overall system efficiency is relatively constant ranging from 52%to 56%.1035.5. Chapter SummaryOutput DC Power (W)1 2 3 4DC Efficiency (%)4042444648505254565827.12 MHzFigure 5.15: Output load power versus overall efficiency of the CPT systemat 27.12 MHz for a 3.2 cm gap distance.5.5 Chapter SummaryIn this chapter, the class-E power amplifier and rectifier systems were inte-grated with the capacitive coupling network to implement a CPT system.Experimental results indicate that the designed class-E inverter and rectifiersystem can transfer power in a CPT system. The coupling capacitance ofthe CPT disks depends on the gap distance. For the purpose of having aconstant impedance for a limited gap range, the converters were designedfor two different operating frequencies (13.56 MHz and 27.12 MHz). Simula-tion results show that by switching the operating frequency we can maintainefficient power transfer for gap distances ranging from 10 cm to 20 cm. Sim-ulation results indicate that 27.12 MHz is suitable for smaller gap distances(10 cm to 14 cm) and for larger gaps (15 cm to 20 cm) we need to switchto the 13.56 MHz frequency band. The simulation results confirm that a1045.5. Chapter Summarydual-band CPT system can be used to compensate the impedance changesover wide gap distances.An experimental test bed was built to evaluate the the inverter and rec-tifier designs in a CPT system. Within the scope of this thesis, preliminaryresults are shown to demonstrate complete end-to-end power transfer acrossa variable air gap that ranges from 1.2 cm to 10.2 cm. For this range of gapdistance the 27.12 MHz frequency band was more efficient than 13.56 MHzwhich follows the trend shown by simulation results. Since the CPT sys-tem testing is part of a larger research collaboration, future test results areexpected to demonstrate power transfer over gaps up to 20 cm using the13.56 MHz frequency band.105Chapter 6Conclusion and Future WorkThe work in this thesis has focused on the design of class-E inverters andsynchronous rectifiers for a dual-band capacitively coupled wireless powertransfer system. The frequency bands are ISM bands that are allocated toindustrial, scientific and medical applications including wireless power. Inthese frequency bands, CPT can be implemented to transfer power over gapsin the range of a few centimetres to tens of centimetres.The gap distance in CPT systems has a huge impact in the couplingimpedance and system efficiency. The literature review in Chapter 1 showsthat previous research has focused on power transfer for a constant (fixed)gap distance that is usually very small in the range of a few millimetres.Moreover, the literature describes CPT systems that typically operate at afixed frequencies up to 13.56 MHz.The dual-band operation is intended to give another degree of freedomin the design of CPT to compensate for spatial changes in the CPT link.Spatial changes create impedance changes in the CPT link that can reducethe efficiency and power that is transferred to the load. Another variablethat can be used to compensate for spatial impedance changes is an adaptiveDC load that can be adjusted to maximize efficiency.106Chapter 6. Conclusion and Future WorkBased on the concepts of using frequency and DC load resistance tocompensate for spatial impedance changes, there is a need to design thesystem components that can support these features where these componentscan be integrated into a complete system. The objectives in this researchwere to focus on the design of the dual-band inverters and rectifiers, and todesign an adaptive DC load circuit.The target power range for the inverter and rectifier designs is 20 W. Ahigh efficiency class-E circuit topology was selected for the designs. An un-packaged GaN-FET from EPC (model 2037) was selected as for the switchin the class-E circuits. GaN devices have lower switch capacitance thanMOSFET devices and therefore a higher peak efficiency is expected. Theunpackaged device also eliminates package inductance that can reduce theefficiency and power delivered the device. The disadvantage of workingwith an unpackaged device was the need to consider the thermal designmore carefully to ensure the device would operate at a stable temperature.Practical considerations that are important to implement efficient circuitswere also considered. Important factors include the Printed Circuit Board(PCB) layout design, the selection of core materials for inductors, and ther-mal dissipation.The design, analysis and experimental results for the class-E power am-plifiers and class-E synchronous rectifiers are described in Chapter 2 andChapter 3. Circuit simulations were done to verify the designs and val-idate the theory. Laboratory prototypes where then built and tested for13.56 MHz and 27.12 MHz operating frequencies. The simulated class-Epower amplifiers have a maximum output power of 20 W with 95% drain effi-107Chapter 6. Conclusion and Future Workciency. In the experimental verification, for an output power range from 2 Wto 9 W, the class-E amplifiers maintained high efficiency ranging from 85.5%to 82%, respectively. The synchronous rectifier was tested in a back-to-backconfiguration with the power amplifier. The simulation results showed amaximum DC-to-DC efficiency of 88% at 18 W output power. Accordingto the experimental results, for an output power of 8 W, the measured ef-ficiency at 13.56 MHz was 78% and the measured efficiency at 27.12 MHzwas 74%.In Chapter 4, the design of an adaptive load for the rectifier is described.The adaptive load is implemented using a single switch PWM DC-DC con-verter operating in the buck circuit configuration. It is shown that the inputequivalent resistance of these converters can vary by changing the duty cy-cle of the converter. An experimental prototype of the DC load circuit wasdesigned and built. The load circuit was first characterized in an isolatedconfiguration with a DC power supply as the input source. The measuredinput resistance varies from 170 Ω to 25 Ω. A second experiment was madeto verify the DC load when it was connected to a synchronous rectifier. Therectifier requires approximately 30 Ω to 50 Ω DC load variation to trackthe maximum power. Unfortunately, when the rectifier was connected tothe load, issues were found with the PWM controller of the buck converterwhere operation was restricted low resistances. The limitations of the con-troller were investigated and recommendations on how to improve the designare described in the following section on future work.In Chapter 5, the amplifier and rectifier circuits are integrated with afour plate CPT link to implement a full system including an air gap. A108Chapter 6. Conclusion and Future Worksimulation study was first done to verify the dual-band concept as a wayof compensating for changes in gap distance. The DC load on the rectifieris also adjusted to maximize the efficiency of the CPT system for changesin gap distance. The simulation results validate the theory of achievinghigh power and high efficiency for a large gap distance range by changingthe operation frequency. For a spatial bandwidth of 10 cm to 20 cm, thesimulation results show that in order to keep the system efficiency withinthe range of 75% to 85%, the operating frequency needs to be switched from27.12 MHz to 13.56 MHz at a distance of 14 cm. In other words, for gapdistances smaller than 14 cm, 27.12 MHz has higher power and efficiencythan 13.56 MHz, while for gap distances larger than 14 cm up to 20 cm, the13.56 MHz system has better power and efficiency.Chapter 5 also includes preliminary experimental results for an exper-imental four plate CPT system. The system was tested at a frequency of27.12 MHz with the class-E amplifier and rectifier. Measurements for a fixedgap of 3.2 cm showed that 4 W of load power could be delivered at an over-all system efficiency of 53%. The efficiency includes losses in the amplifier,CPT link, and rectifier. Experiments were also conducted for a variablegap distance of 1 cm to 8 cm over which the overall system efficiency var-ied from 38% to 55%. These preliminary results are very encouraging andshow merits to the proposed system concept. The utilization of high effi-ciency class-E amplifiers and rectifiers at 27.12 MHz in a CPT system isnew work and these results will be included in a future publication. Futurework will focus on a complete experimental verification of the system overboth frequency bands.109Chapter 6. Conclusion and Future WorkFuture WorkBased on the theory, analysis and experimental work described in this thesis,there are several areas that are recommended for future work.• GaN versus LDMOS devices: GaN-FETs were used in the class-Eamplifier and rectifier designs. The GaN-FETs were unpackaged andselected to minimize package inductance. The unpackaged devices arealso lower cost relative to packaged devices. On the other hand, assem-bling the circuits with the GaN die, and the implications of designingan appropriate heat sink, were challenging. It would be interestingto compare the performance of GaN designs with other low cost RFdevices such as LDMOS that are available in a plastic package with aheat sink pad. The assembly and thermal design might be much easierwith LDMOS.• Variable load: In Chapter 4 a single-switch DC-DC buck converterwas designed for a variable resistive load for maximizing rectifier effi-ciency. In the future, it is recommended to develop a SEPIC converterwith an adaptive controller for this application. SEPIC convertershave the advantage of continuous input current and a simpler con-troller structure compared to buck and buck-boost converters. TheSEPIC topology may also resolve integration issues that were foundwhen the DC load was connected to the rectifier. The adaptive con-troller can automatically detect the change in gap distance or platealignments and can adjust the load accordingly to extract maximumefficiency from the CPT system.110Chapter 6. Conclusion and Future Work• CPT system tests for 13.56 MHz: In this study, measurementsare presented for a 27.12 MHz CPT system using the class-E poweramplifiers and rectifiers that were built. Testing a CPT at 13.56 MHzfor different gap distances and comparing this result with 27.12 MHzoperation needs to be completed to fully validate the dual-band CPTsystem concept.• Differential CPT: The experiments carried out in Chapter 5 weredone with a four plate CPT system that is derived from a six platestructure. The system was evaluated in a single-ended configurationthat is equivalent to a half circuit in a differential six plate system. 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Thesis/Dissertation
eng
Electrical Engineering
Vancouver : University of British Columbia Library
Attribution-NonCommercial-NoDerivatives 4.0 International
Graduate
Johnson, Thomas
Design and implementation of class-E power amplifiers and rectifiers for a dual-band capacitive wireless power transfer system
Text