Applied Science, Faculty of
Engineering, School of (Okanagan)
DSpace
UBCO
Eyvazizadeh Khosroshahi, Alireza
Master of Science - MSc
University of British Columbia
Growing demand for clean electricity has increased the importance and need of interface devices in power systems. High Voltage Direct Current (HVDC) systems seem to be a promising solution for future power systems. Hybrid topologies combine continuous AC side current, reactive power control, lower harmonics, smaller footprint, ability to supply weak AC grids, and black-start capability advantages of voltage source converters with low conduction loss advantage of line commutated converters. Hence, among different HVDC technologies, hybrid converters that combine thyristor based current source converters with multi-level modular converters (MMC) are predicted to prevail over other topologies. However, in practical systems the number of submodules in MMC-type converters is high. Therefore, the admittance matrix for these systems becomes very large and the detailed switching-based models are computationally inefficient to represent these systems in electromagnetic transient (EMT) type simulation environments. Average value modeling is a good solution for decreasing the complexity and increasing the computational efficiency of the detailed models. However, none of the previous research has focused on hybrid topologies with combined thyristors and insulated gate bipolar transistors (IGBTs) for converter valves. This thesis is filling the gap and develops detailed equivalent model (DEM), switching function based model (SFM), average chain-link model (ACM), and standard average value model (SAVM) for a thyristor-based hybrid three-level converter (TH3LC). During normal operation of TH3LC, the converter needs to block a few submodules in the commutation chain-link and therefore none of the previous models in the literature has implemented this feature for this converter. In this thesis, firstly different models are developed and formulated for TH3LC. Then, all the models are simulated and validated in MATLAB® Simulink environment. The results show that based on the study type and required accuracy, proper model should be chosen among DEM, SFM, ACM, and SAVM.
Average Value Modeling of a Thyristor-Based Hybrid Three-Level Power Converter for High Voltage Direct Current (HVDC) Transmission by Alireza Eyvazizadeh Khosroshahi B.Sc., Islamic Azad University, 2016 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in THE COLLEGE OF GRADUATE STUDIES (Electrical Engineering) THE UNIVERSITY OF BRITISH COLUMBIA (Okanagan) May 2021 © Alireza Eyvazizadeh Khosroshahi, 2021 ii The following individuals certify that they have read, and recommend to the College of Graduate Studies for acceptance, a thesis/dissertation entitled: Average Value Modeling of a Thyristor-Based Hybrid Three-Level Power Converter for High Voltage Direct Current (HVDC) Transmission submitted by Alireza Eyvazizadeh Khosroshahi in partial fulfillment of the requirements of the degree of Master of Applied Science in Electrical Engineering . Dr. Liwei Wang - Faculty of Applied Science Supervisor Dr. Wilson Eberle - Faculty of Applied Science Supervisory Committee Member Dr. Morad Abdelaziz - Faculty of Applied Science Supervisory Committee Member Dr. Sina Kheirkhah - Faculty of Applied Science University Examiner iii Abstract Growing demand for clean electricity has increased the importance and need of interface devices in power systems. High Voltage Direct Current (HVDC) systems seem to be a promising solution for future power systems. Hybrid topologies combine continuous AC side current, reactive power control, lower harmonics, smaller footprint, ability to supply weak AC grids, and black-start capability advantages of voltage source converters with low conduction loss advantage of line commutated converters. Hence, among different HVDC technologies, hybrid converters that combine thyristor based current source converters with multi-level modular converters (MMC) are predicted to prevail over other topologies. However, in practical systems the number of submodules in MMC-type converters is high. Therefore, the admittance matrix for these systems becomes very large and the detailed switching-based models are computationally inefficient to represent these systems in electromagnetic transient (EMT) type simulation environments. Average value modeling is a good solution for decreasing the complexity and increasing the computational efficiency of the detailed models. However, none of the previous research has focused on hybrid topologies with combined thyristors and insulated gate bipolar transistors (IGBTs) for converter valves. This thesis is filling the gap and develops detailed equivalent model (DEM), switching function based model (SFM), average chain-link model (ACM), and standard average value model (SAVM) for a thyristor-based hybrid three-level converter (TH3LC). During normal operation of TH3LC, the converter needs to block a few submodules in the commutation chain-link and therefore none of the previous models in the literature has implemented this feature for this converter. In this thesis, firstly different models are developed and formulated for TH3LC. Then, all the models are simulated and validated in MATLAB® Simulink environment. The results iv show that based on the study type and required accuracy, proper model should be chosen among DEM, SFM, ACM, and SAVM. v Lay Summary The world population is increasing every day and this results in more demand for energy consumption, especially electrical energy consumption that plays an important role in our future. With the growing demand for electrical e+nergy, renewable energy resources are the main focus in power system engineering. However, the renewable sources usually do not have the proper form and voltage level to be connected to the power system directly. Consequently, interface devices such as power converters are implemented more and more in power systems. A typical power converter that most of people use in their everyday life is their cellphone battery charger. A phone battery charger converts the plug voltage to a suitable type that can charge the battery. An iPhone charger typically delivers 5 Watts to the battery. In this charger, only one switch (transistor) is used to make the conversion happen. In the power system level, a typical High Voltage Direct Current (HVDC) converter consists of 1,200 switches that delivers power in a few hundreds of Mega watt scale. Simulation and modeling of these converters is very important for the design stage. In this thesis, a new high power hybrid multilevel converter is modeled and simulated. Depending on the level of complexity and accuracy needed, four different models will be developed. Finally, the proposed models will be compared and their application will be discussed. vi Preface This research is supervised by Dr. Liwei Wang, an assistant professor in School of Engineering at the University of British Columbia. All the research work is conducted in School of Engineering. This thesis contains research work that is to be published in the future. Alireza Eyvazizadeh Khosroshahi is the principal contributer to this thesis which developes models for TH3LC. Mr. Levi Bieber provided the TH3LC structure, and Mr. Jintao Han assisted with checking the models and formulation. Dr. Liwei Wang managed the team and provided the concept and instructions both for converter topology and modeling aspects. vii Table of Contents Abstract ....................................................................................................................................................... iii Lay Summary .............................................................................................................................................. v Preface ......................................................................................................................................................... vi Table of Contents ...................................................................................................................................... vii List of Tables .............................................................................................................................................. ix List of Figures .............................................................................................................................................. x Acknowledgements ................................................................................................................................... xii Chapter 1: Introduction ............................................................................................................................. 1 Chapter 2: Literature Review .................................................................................................................... 5 2.1 Introduction ............................................................................................................................... 5 2.2 VSC-HVDC Topologies ............................................................................................................ 6 2.2.1 Two-Level Converter .......................................................................................................... 7 2.2.2 Conventional Multilevel Converters ................................................................................... 8 2.2.2.1 Diode Clamped Converters ........................................................................................ 8 2.2.2.2 Flying Capacitor Converters .................................................................................... 10 2.2.2.3 T-type converters ..................................................................................................... 12 2.2.3 Modular Multilevel Converter (MMC) Topologies .......................................................... 13 2.2.3.1 Submodules .............................................................................................................. 13 2.2.3.2 General Topology of Modular Multilevel Converters ............................................. 16 2.2.3.3 Advantages and disadvantages of MMC .................................................................. 18 2.2.4 Hybrid Topologies ............................................................................................................ 18 2.3 Modeling ................................................................................................................................. 19 2.3.1 Detailed Model (DM) ....................................................................................................... 19 2.3.2 Detailed Equivalent Model (DEM) ................................................................................... 20 2.3.3 Average Value Model (AVM) .......................................................................................... 20 viii 2.4 Conclusion ............................................................................................................................... 21 Chapter 3: Control and Average Value Modeling of TH3LC .............................................................. 22 3.1 TH3LC operation principals .................................................................................................... 22 3.1.1 Converter Control Scheme ................................................................................................ 31 3.1.2 Energy Balancing of AC chain-link .................................................................................. 32 3.1.3 Energy Balancing of commutation chain-link .................................................................. 32 3.1.4 Modulation of commutation and AC chain-links ............................................................. 33 3.1.5 Submodule capacitor voltage balancing of commutation and AC chainlinks .................. 34 3.1.6 Real and Reactive Power Control ..................................................................................... 35 3.2 TH3LC Modeling .................................................................................................................... 36 3.2.1 Detailed Model ................................................................................................................. 36 3.1.1 Detailed Equivalent Model (DEM) ................................................................................... 37 3.2.3 Switching Function based Model (SFM) .......................................................................... 41 3.2.4 Average Chain-link Model (ACM) ................................................................................... 42 3.2.5 Standard Average Value Model (SAVM) ......................................................................... 43 Chapter 4: Simulation Results ................................................................................................................. 46 4.1 DEM Validation ...................................................................................................................... 46 4.2 Average Value Models (AVMs) ............................................................................................. 52 4.3 Conclusion and Comparison ................................................................................................... 58 Chapter 5: Conclusion .............................................................................................................................. 60 Bibliography .............................................................................................................................................. 62 ix List of Tables Table 2.1: Switching states of the 3-level FC converter when the load current is directed out of the AC terminal ....................................................................................................................................................... 11 Table 2.2: Double clamped cell switching states ........................................................................................ 14 Table 3.1: Voltage ratings of TH3LC components ..................................................................................... 24 Table 4.1: Semiconductor parameters of the simulated TH3LC ................................................................. 47 Table 4.2: Model parameters of the simulated TH3LC .............................................................................. 47 Table 4.3: Numerical errors for different average value models ................................................................ 54 Table 4.4: Simulation execution times for DM, DEM, SFM, ACM, and SAVM of TH3LC ..................... 58 x List of Figures Figure 2.1: Schematics of a three-phase two-level converter ....................................................................... 7 Figure 2.2: One phase leg of diode clamp topologies [25]: (a) three-level (NPC); (b) four-level ................ 9 Figure 2.3: A single phase leg of three-level flying capacitor converter [29] ............................................ 11 Figure 2.4: T-type topoligies: (a) four-level NNPC [30]; (b) five-level extension [31] ............................. 12 Figure 2.5: half bridge submodule: (a) circuit schematic; (b) typical output voltage ................................. 14 Figure 2.6: full bridge submodule: (a) circuit schematic; (b) typical output voltage .................................. 15 Figure 2.7: Double clamped submodule: (a) circuit schematic; (b) typical output voltage ........................ 15 Figure 2.8: Modular multilevel converter (MMC) topology ...................................................................... 17 Figure 3.1: Power Circuit Schematic of Thyristor-based Hybrid 3-Level Converter ................................. 23 Figure 3.2: TH3LC director switches and CCL typical waveforms ........................................................... 26 Figure 3.3: Typical waveforms of three-level converter stage and ACCL at maximum modulation index28 Figure 3.4: Third-order harmonic injection control schematic ................................................................... 30 Figure 3.5: High-level control scheme of TH3LC ...................................................................................... 31 Figure 3.6: SM switching and energy balancing control of AC Chain-link ............................................... 32 Figure 3.7: Commutation chain-link energy balancing control scheme ..................................................... 33 Figure 3.9: Switching signal generation: (a) Director switches and CCL; (b) AC chain-link .................... 35 Figure 3.10: TH3LC active and reactive power controller scheme ............................................................ 36 Figure 3.10: (a) chain-link of full bridge submodules; (b) equivalent circuit of full bridge submodule .... 38 Figure 3.12: Submodule capacitor charging during blocking states ........................................................... 40 Figure 3.13: Standard Average Value Model (SAVM) of TH3LC............................................................. 44 Figure 4.1: General schematics of the simulated system ............................................................................ 48 Figure 4.2: DM and DEM comparison for output AC terminal voltage for phase a of TH3LC ................. 48 Figure 4.3: DM and DEM comparison for output AC terminal current for phase a of TH3LC ................. 49 Figure 4.4: DM and DEM comparison for AC chain-link voltage for phase a of TH3LC ......................... 50 Figure 4.5: DM and DEM comparison for commutation chain-link voltage for phase a of TH3LC .......... 51 xi Figure 4.6: DM and DEM comparison for DC side current of TH3LC ...................................................... 52 Figure 4.7: DEM, SFM, ACM, and SAVM comparison for AC terminal output voltage of TH3LC ........ 53 Figure 4.8: DEM, SFM, ACM, and SAVM comparison for AC terminal output current of TH3LC ......... 54 Figure 4.9: DEM, SFM, and ACM comparison for AC chainlink voltage of TH3LC ............................... 55 Figure 4.10: DEM, SFM, and ACM comparison for commutation chainlink voltage of TH3LC .............. 56 Figure 4.11: DEM, SFM, ACM, and SAVM comparison for DCside current of TH3LC .......................... 57 Figure 4.12: The trade-off between accuracy and computational efficiency .............................................. 57 Figure 4.13:Simulation execution time for different models: (a) 62 SMs/phase; (b) 186 SMs/phase ........ 59 xii Acknowledgements I would like to begin by thanking my wife Hoda for her love and constant support, for all the late nights and early mornings, and for keeping me sane over the past few months. Thank you for being my muse, editor, proofreader, and sounding board. But most of all, thank you for being my best friend. I owe you everything. I must say a special thank you to my supervisor, Dr. Liwei Wang. It is an often used cliché, but in this case it is no overstatement to say that without the consistent guidance, tutelage, support, unparalleled knowledge, and encouragement of my supervisor, this thesis would never have existed. Thank you also to Jintao Han and Levi Bieber for their help with simulations and case studies. To my family, particularly my parents, thank you for your love, support, and unwavering belief in me. Without you, I would not be the person I am today. Finally, I wish to thank all the people whose assistance was a milestone in the completion of this project. I would like to recognize the invaluable assistance that you all provided during my study. 1 Chapter 1: Introduction Electricity has become a crucial part of modern societies and economies, supporting a broad range of services. Automation, modernization, and industrialization have led to increasing demand for electric power generation [1][2]. According to International Energy Agency (IEA) report, the share of electricity in total final energy consumption of the world was 20% by October 2020 and it is estimated that by 2040 it will be the main energy source [3]. There will be a 50% increase in electricity demand by 2040 according to IEA World Energy Outlook report [4]. On the other hand, growing environmental concerns raise the need for sustainable energy resources, and in turn has shifted the focus of power system experts on extracting energy from renewable resources [5][6][7]. However, most of the renewable energy resources require power electronic converters as interface devices in order to be interconnected with power grids. Therefore, the fact that power electronic converters will play a key role in future power systems for the transmission, generation, and distribution is an undeniable point. Some of the main motives that have attracted the attention of power system engineers toward power electronics applications can be listed as [8]:  Fast pace of development in semiconductor technologies for power switches  Development in control strategies and algorithms  Stability reinforcement of electric power utility, especially with the operations close to the limit  Employing renewable energy resources as a measure to reduce CO2 emission  Integration of storage systems  Enabling distributed generation  Enabling maximum power point tracking Converting between direct current (DC) and alternating current (AC) was mostly done by current source converters (CSC) until 1970s. The mercury arc switches were the first generation of the switches utilized in CSC power converters. Later, thyristors were introduced and replaced the mercury arc valves. The main disadvantage of thyristors was the lack of controllable turn-off ability. The invention of semiconductor 2 based power switches with turn-off capability was a major breakthrough in power converter topologies since it resulted in the wide applications of voltage source converters (VSC). Demands for using renewable energy sources, energy savings and higher efficiency, ability to control active and reactive power independently, and increasing automation are perfectly met by VSCs [9]. Two-level VSC is still the most widely used topology in low voltage applications. However, the maximum voltage and current of semiconductor switches are limited. In addition, connecting the switches in series and parallel to enable high voltage and current values results in very complicated and costly converters. Therefore, multi-level converter structures were introduced to address these issues. Still the number of levels was limited by the complexity of converter control system that made multi-level topologies suitable for medium voltage levels. In order to make use of power converters feasible in high voltage levels, submodules were used to replace single switches and modular multilevel converters (MMC) were introduced. These converters will be discussed with more details in Chapter 2. High Voltage Direct Current (HVDC) systems based on power electronics converters have recently gained more importance as interface devices. HVDC systems are predicted to be the backbone of future power systems. There are three main reasons for implementation of HVDC systems in power grids:  Long distance power transmission: A challenge with the use of renewable energy resources is that in the most cases the best available resources are concentrated far away from the power system infrastructure or the residential and industrial areas. This is also the case for some cheap non-renewable sources as well. As a result, in most cases long distance transmission is required. Often high voltage direct current (HVDC) transmission is the only and most cost-effective solution for long distance transmissions.  Increasing the line capacity: Increase in demand and integration of renewable energy resources have raised the need for an increase in the capacity of power lines. A transition from traditional AC 3 overhead line transmission to VSC based HVDC at the same voltage level increases the transmission capacity by three times [9].  Interface devices for renewable power conversion: For instance, the output electricity of a wind turbine has a variable frequency or variable voltage. In this case the power converter interfaces the wind turbine unit with the constant frequency and constant voltage power grid. There are several reasons that makes developing average value models essential for power system studies:  Since HVDC systems operate in high voltage ratings, their converter topology employs large number of switches to create enough levels to achieve high voltages. For a typical MMC-HVDC converter, 1200 insulated gate bipolar transistors (IGBTs) are used in order to create around 200 levels [10]. The high number of components used in HVDC converters makes the simulation of these systems very time consuming.  At the converter design stage, tuning controllers can be very challenging and time consuming. Designers can start from the simplest model that requires only high-level controllers and continue designing and adding more controllers to their models. This is also very helpful for debugging the controller parameters.  Converter manufacturers normally do not disclose their detailed design information (specially the controller design and parameters) to their customers, i.e., power utility companies. On the other hand, the power utility companies may need to simulate the converter dynamics and investigate its impact to AC system at system level. For the system level studies, the average value models can be utilized since they do not require to implement the low level controllers of the converter. Hybrid multilevel converter topologies based on MMC structures are promising for the next generation HVDC systems that combine the advantages of CSCs and VSCs. Although different studies have been targeted for modeling of MMC HVDC systems, none of them have considered thyristor based hybrid topologies. This thesis is dedicated to provide an average value model for a thyristor based three-level 4 converter (TH3LC). TH3LC operation principals are different than the conventional MMCs. The models provided for MMCs are not valid for TH3LC. In Chapter 2, a brief literature review is presented for power converters used in HVDC systems, both from converter topology and converter modeling aspects. Chapter 3 first introduces the operation principals of TH3LC and then studies different modeling methods on the converter. The results of this study are presented in Chapter 4. The results will validate the accuracy and efficiency of the models presented in Chapter 3. Finally, a conclusion and future work is provided in Chapter 5. 5 Chapter 2: Literature Review 2.1 Introduction With the recent developments and practical installations of new High Voltage Direct Current (HVDC) transmission stations, there has been a shift in focus of power system engineers towards HVDC systems. The power converters used in HVDC systems are categorized into Line Commutated Converters (LCC) and Voltage Source Converters (VSC). Thyristors are the basic switching devices in LCC HVDCs. Since thyristors are semi-controlled switches, the commutation process relies on the line voltage of the AC side in these converters. This is the reason they are named line commutated [11]. Since the DC current in LCCs flows through a large inductor and does not change direction, it is approximately remains constant. As a result, LCC acts as a current source at the AC side. Consequently, LCC is also called Current Source Converter (CSC). The first thyristor-based HVDC was installed and commissioned in 1972 by General Electric (Eel River Crossing, New Brunswick, Canada) [12]. The advantages of LCC systems over VSC are lower costs, strong short-circuit protection capability, lower dv/dt, lower loss, and direct output current controllability [13]. The main LCC topologies are 6-pulse, 12-pulse, capacitor commutated, and reinjection converters. Controlling of grid frequency, connecting wind farms, and improving grid stability in presence of large disturbances are other applications of LCC HVDC systems in addition to DC power transmission [14][15]. However, LCC systems have some limitations and technical shortcomings such as [16]:  Reactive power control  Non-sinusoidal AC side current  Higher total harmonic distortion (THD)  Large output filter requirement  Susceptible to commutation failures On the other hand, IGBTs are the basic switching devices for VSC HVDC. Using IGBT, a fully controlled semiconductor switch, allows VSCs to switch on or off without depending on AC side voltage in addition to higher frequency switching ability. Consequently, VSCs have better controllability and black-start ability 6 [17]. The first VSC HVDC project in the world was commissioned in March 1997 by ABB (Hellsjön - Grängesberg project in Sweden, 3 MW, 10 km distance, ±10 kV) [18][19]. Since 1997, many VSC based HVDC projects have been installed worldwide [20]. The main advantages of VSC HVDC systems over CSC HVDC are continuous AC side current, lower risk of harmonic resonance, ability to switch in higher frequencies, reactive power control, no requirement for external voltage source in order to commutate the switches, lower harmonics, smaller converter station footprint, ability to supply weak AC grids, and black-start capability [13], [21]. According to [22], the installed power rating for LCC based HVDC systems has increased to 12 GW MW at ± 1,100 kV for transmission. The ratings for VSC-based HVDC systems currently have reached to 3,000 MW at ± 525 kV for transmission. New research is in progress to develop semiconductor devices and power converter structures in order to increase these ratings. In spite of the fact that VSC HVDC is promising technology for future systems, LCC is the dominant technology in the operational HVDC systems by 2020 [23]. In a nutshell, HVDC systems are predicted to be the backbone of future interconnected AC-DC power systems. However, due to implementation of large number of switches in HVDC converters, their modeling becomes an important issue for power engineers. Consequently, efficient and fast modeling of HVDC converters has a significant importance. This thesis is dedicated to study modeling of a hybrid VSC HVDC system. In this chapter, a brief review of HVDC systems is to be presented regarding two aspects: VSC power converter topologies and their modeling. 2.2 VSC-HVDC Topologies The development of power semiconductor devices results in fully controlled switches capable of self-turn off. This leads to forced commutation feature, improved harmonic, and independent operation from AC side for the converters. The DC side voltage is kept approximately constant and independent from AC side current in a VSC. This is achieved by utilizing DC capacitor as energy storage device. The DC side voltage 7 remains constant for a small portion of fundamental AC voltage cycle. In this section, firstly the traditional VSC topologies are introduced with a focus on transitioning to MMC. Then hybrid topologies will be introduced. Currently, hybrid topologies are the most trending and promising technology for VSC HVDC systems. 2.2.1 Two-Level Converter Two-level converters are considered as the basis of VSC HVDC technology. For low voltage applications, they are still the preferred topology. They are used in broad range of applications such as electric appliances, motor drives, electric vehicles, and interface devices for low voltage grid connection. Later in Section 2.2.3 we will see that a single-phase half-bridge two-level converter is the basic building block of MMCs as well. Consequently, a brief description and analysis of two-level converter is presented in this section. Figure 2.1: Schematics of a three-phase two-level converter Figure 2.1 shows the power circuit of a three-phase two-level converter. According to [24], two-level converter falls into the category of monolithic or non-modular converters. For a fraction of fundamental cycle, the DC side voltage is maintained constant independent from AC side by utilizing DC pole capacitors. Each phase leg contains two switches (S1m and S2m where m belongs to {a, b, c}) connected in series and the AC terminal is the midpoint of the series connected switches. Each switch has bidirectional current conduction capability and can block the DC side voltage in one direction. The AC side inductor keeps the AC current constant between the switch commutations. The two switches in each leg (S1m and S2m) operate S1aS2aVdc/2Vdc/2S1bS2bS1cS2c8 complementary; in other words only one switch will conduct at a time and the other will be off. In case both S1m and S2m are turned on, the DC side will be short-circuited which may damage the semiconductor devices. Depending on which switch is conducting, the AC side voltage of the phase will change. If S1m is conducting, then Vm will be equal to +𝑉𝑑𝑐/2; otherwise (S1m off and S2m operating) 𝑉𝑚 = − 𝑉𝑑𝑐/2. In case the current is drawn from the AC side terminal, in order to create a positive 𝑉𝑑𝑐/2 voltage level at AC side, the transistor will be conducting in the upper switch. Otherwise, the diode in the lower switch will be conducting to create a −𝑉𝑑𝑐/2 voltage. Then we can define the switching state of a phase leg as follows: 𝑠𝑚 = {+1 𝑖𝑓 𝑆1𝑚 𝑖𝑠 𝑜𝑛−1 𝑖𝑓 𝑆2𝑚 𝑖𝑠 𝑜𝑛 (2.1) where 𝑚 ∈ {𝑎, 𝑏, 𝑐}. As a result, the AC side phase voltage can be defined as: 𝑉𝑚 = 𝑠𝑚𝑉𝑑𝑐2 (2.2) 2.2.2 Conventional Multilevel Converters Basic and conventional multilevel converters will be introduced in this section. These converters were proposed before the modular multilevel converter topologies. The three-level version of each topology will be discussed. However, it can be easily extended to higher number of levels by series connection of semiconductor switching cells. As mentioned before for VSCs, they all have a DC link shared by all the converter phases. This DC link contains a capacitor or a series connection of capacitors usually. The DC link voltage is also called pole-to-pole DC side voltage. 2.2.2.1 Diode Clamped Converters Figure 2.2 (a) shows one phase leg of the three-level converter schematic of the first diode clamp converter proposed in 1981 [25]. It uses two capacitors for handling pole-to-pole-DC link voltage. Using the two capacitors also gives the converter the ability to have additional levels. For a higher number of levels, more 9 number of series connected capacitors should be used for handling pole-to-pole DC voltage. A 4-level extension is shown in figure 2.2 (b). As illustrated in figure 2.2, in addition to DC link capacitors, the number of clamping diodes is increased as the number of levels increases. Moreover, the number of nodes and interconnections will rise up by adding new levels which has a significant impact on mechanical design complexity of the converter. (a) (b) Figure 2.2: One phase leg of diode clamp topologies [25]: (a) three-level (NPC); (b) four-level In this section only the operation of three-level topology will be discussed briefly. The diodes 𝐷5 and 𝐷6 are called clamping diodes providing additional paths for the current so that the ac terminal can be temporarily connected to these dc levels during operation. Consequently, making possible to create S1S2D5D6S3S4Vdc/2Vdc/2+-+-S2S3D9D10S4S5Vdc/3Vdc/3S1S6D7D8Vdc/3+-+-+-10 additional ac voltage levels. As shown in Figure 2.2 (a), the clamping diodes also provide a path from DC link midpoint (neural potential) to AC terminal. Therefore, the converter is also referred as Neutral Point Clamped (NPC) converter. There are three possible switching states for NPC converter. In order to create a +𝑉𝑑𝑐/2 level, both upper switches (S1 and S2) are turned on, and for a −𝑉𝑑𝑐/2 both lower switches (S3 and S4) should be gated on. To create a zero level, both inner switches (S2 and S3) are turned on and outer switches (S1 and S4) are turned off. It is noted that with balanced DC link capacitors, the maximum blocked voltage by any of the switches is Vdc/2. Therefore, compared to two-level converter discussed in Section 2.2.1, in case given a set of switches and diodes with the same rating, NPC can handle twice the power of a two-level converter. The inner switches (S2 and S3) will be kept on transitioning between ±Vdc/2 and 0 levels. As a result, at high modulation index with approximately pure active power flow the distribution of semiconductor losses is uneven in NPC. This is a disadvantage for HVDC application. Active Neutral Point Clamped (ANPC) converter has been introduced in [26] to mitigate this problem. ANPC structure is very similar to NPC except that the clamping diodes are replaced by switches with anti-parallel diodes. This replacement results in more freedom in control. The zero-level can be implemented in different ways which in turn allows more even distribution of losses among semiconductor devices. The Cross-Sound Cable [27] and the Murray link [28] are the two HVDC projects that used ANPC. 2.2.2.2 Flying Capacitor Converters The first flying capacitor (FC) converter was introduced in 1992 [29]. Figure 2.3 shows the schematic of a phase leg of three-level topology proposed in [29]. Similar to other multi-level topologies, additional voltage levels are provided by using capacitors. These capacitors are called flying capacitors since they are not connected to a common DC link. 11 Figure 2.3: A single phase leg of three-level flying capacitor converter [29] Table 2.1: Switching states of the 3-level FC converter when the load current is directed out of the AC terminal S1 S2 S3 S4 Flying capacitor + Vdc/2 1 1 0 0 no change - Vdc/2 0 0 1 1 no change 0 1 0 1 0 charging 0 0 1 0 1 discharging Considering a load current directing out of the AC terminal, there are four possible switching states for a three-level flying capacitor converter. In order to create a +𝑉𝑑𝑐/2 level, both upper switches (S1 and S2) are turned on and the remaining switches (S3 and S4) are gated off. For a −𝑉𝑑𝑐/2 level, both lower switches (S3 and S4) are turned on while upper switches (S1 and S2) are turned off. Note that positive and negative levels are complementary. For providing a zero voltage level there are two different possibilities. One method is to turn on S1 and S3 while turning off S2 and S4. In this case, the flying capacitor will be charged. The other S1S2S3S4Vdc/2Vdc/2Vdc/2+-+-+-12 method is to turn on S2 and S4 and turn off the remaining switches (S1 and S3). In this case, the capacitor will be discharged. Table 2.1 shows the possible switching states and capacitor charging state for the three-level flying capacitor converter when the load current is flowing out of the converter AC terminal. The redundant switching states for zero-voltage level are very important for flying capacitor voltage balancing control. 2.2.2.3 T-type converters For further improvement of the flying capacitor converter, the inner capacitor can be split into two capacitors of 𝑉𝑑𝑐/3 and the midpoint of the two inner capacitors can be connected to the AC terminal [30]. This structure is called nested neural point converter (NNPC) four-level T-type. The schematics of this converter is shown in Figure 2.4 (a) and its five-level extension [31] is shown in Figure 2.4 (b). In Figure 2.4, it is illustrated that to achieve the five-level extension, basically the midpoint of DC link is connected to the midpoint of flying capacitors. Natural voltage balancing of flying capacitors, modularity, and scalability are the most important advantages of T-type topologies that makes these converters suitable for HVDC applications. In addition, T-type structures have a simpler mechanical design compared to NPC-derived converters. (a) (b) Figure 2.4: T-type topoligies: (a) four-level NNPC [30]; (b) five-level extension [31] S1S2S3S4Vdc/2Vdc/2Vdc/3Vdc/3S5S6+-+-+-+-S1S2S3S4Vdc/2Vdc/2Vdc/4Vdc/4S6S5S8S7+-+-+-+-13 2.2.3 Modular Multilevel Converter (MMC) Topologies All the converters discussed in Section 2.2.2 share a common disadvantage which is the limited voltage level extension by connection of semiconductors in series. The complex power circuit and controllers are the result of increasing voltage levels in the conventional multilevel converters. This raises the need for modular structures that are capable of extending voltage levels without increasing the complexity of circuit and controllers. In other words, the voltage levels will be increased simply by adding more submodules. These converters are called modular multilevel converters (MMCs). In this section, first different types of submodules will be introduced and their connection to obtain high voltage levels will be discussed. Then different MMC topologies will be discussed briefly. Finally, advantages and disadvantages of MMCs will be covered. 2.2.3.1 Submodules Submodules, also named cells, are the basic component for building the MMCs. The simplest and the most basic submodule type is the half-bride cell. In fact half-bridge submodule is a two-level one-phase VSC. The output voltage of the submodule can be defined as 𝑉𝑜 = 𝑠𝑉𝐶 where 𝑠 is the switching state of the submodule and 𝑉𝐶 is the voltage of the DC capacitor. There are two possible switching states: i) bypass state (𝑠 = 0): the lower switch 𝑆2 is turned on and the upper switch 𝑆1is turned off in this state. The output voltage is 0 in this case; ii) insert state (𝑠 = 1): the upper switch 𝑆1 is turned on and the lower switch 𝑆2 is turned off in this state. The cell output voltage is 𝑉𝐶 in this state. If both switches are tuned off, then it is called blocking state. Blocking state is not considered as a switching state and it is not used during normal operation of converters [32]. In the blocking mode, the diodes may conduct and the voltage of the submodule will depend on the direction of submodule current. Depending on current direction, the output voltage is equal to the cell capacitor voltage 𝑉𝐶 or 0 in this case. The half-bridge submodule schematic and its typical output voltage based on its possible states are shown in Figure 2.5. Half-bridge submodule is the most commonly used cell and it has the lowest losses compared to the other variants. 14 (a) (b) Figure 2.5: half bridge submodule: (a) circuit schematic; (b) typical output voltage As shown in Figure 2.5 (b), the cell capacitor voltage can be inserted only with the positive polarity in half-bridge submodules. In order to be able to insert the cell capacitor in either polarity, full-bridge submodules were proposed. Figure 2.6 shows the schematic of the full-bridge submodule and its typical output voltage. The possible switching states are: i) bypass state (𝑠 = 0): this state can be obtained by turning on either both upper switches (𝑆1 = 𝑆3 = 1) or both lower switches (𝑆2 = 𝑆4 = 1). The output voltage is 0 in this case; ii) positive insert state (𝑠 = 1): the switches 𝑆1 and 𝑆4 are turned on and the switches 𝑆2 and 𝑆3 are turned off. The cell output voltage will be +𝑉𝐶 for this state; iii) negative insert state (𝑠 = −1): the switches 𝑆2 and 𝑆3 are turned on and the switches 𝑆1 and 𝑆4 are turned off. This is complementary to positive insert state. The cell output voltage will be −𝑉𝐶 for this state. Same as the half-bridge submodule, the blocking state is achieved by turning all the switches off. Then the full-bridge submodule will operate as a diode bridge and the cell output voltage will depend on current direction. Table 2.2: Double clamped cell switching states state 𝑺𝟏 𝑺𝟐 𝑺𝟑 𝑺𝟒 𝑺𝟓 𝑽𝑺𝑴 1 1 0 0 1 1 2𝑉𝐶 2 0 1 0 1 1 𝑉𝐶 3 1 0 1 0 1 𝑉𝐶 4 0 1 1 0 1 0 5 0 0 0 0 0 −𝑉𝐶 S1S2Vc+-Vc15 Comparing Figures 2.5 and 2.6, it can be seen that the number of switches are doubled in order to create a negative DC voltage level. Double Clamped submodules were proposed in order to lower the number of switches to generate a specific voltage level in addition to keeping the negative voltage insertion capability. The double clamped submodule schematics and its typical output voltage is shown in Figure 2.7 which is composed of two half-bridge cells. The output voltage of the cell can be 2𝑉𝐶, 𝑉𝐶, 0, and −𝑉𝐶. The corresponding switching states are summarized in the Table 2.2. More details on different submodule types and their comparison can be found in [24], [33]. (a) (b) Figure 2.6: full bridge submodule: (a) circuit schematic; (b) typical output voltage (a) (b) Figure 2.7: Double clamped submodule: (a) circuit schematic; (b) typical output voltage S3S4S1S2Vc+-Vc-VcS1S2VcS3S4VcD7D6S5VSM+-+-2VcVc0-Vc16 In a nutshell, if the cell capacitor voltages are controlled properly and kept sufficiently balanced, each submodule can play the role of a controllable voltage source. The half-bridge cell can provide a unipolar output voltage. The full-bridge and double clamped variants have bipolar output voltages and are able to generate a negative output voltage level. The different submodules types discussed above can be connected in series to form submodule strings or chainlinks. Obviously the number of levels will be increased at the AC terminal as the number of submodules in a chainlink increases. For example, considering N submodules in a chainlink, the number of output levels will be 𝑁 + 1 and 2𝑁 + 1 for half-bridge and full-bridge types, respectively. 2.2.3.2 General Topology of Modular Multilevel Converters In 2002, Prof. Marquardt made a breakthrough to the high power electronics industry by proposing half-bridge MMC [34]. It puts chain-links or submodule strings together to form a converter which is modular and easily scalable. Figure 2.8 shows the structure of a MMC which is similar to three-phase two-level converter described in section 2.2.1. Comparing Figures 2.8 and 2.1, it can be illustrated that switches are replaced by chainlinks for the MMC which causes a significant difference in the converter mode of operation. Each phase leg in an MMC contains two arms. The arm inductors are necessary to limit the circulate current in the converter arms and prevent parallel connection of chainlinks since chainlinks act as voltage sources. SMs in Figure 2.8 can have different types as discussed in the previous section. If 𝑉𝐷𝐶 denotes the pole-to-pole DC voltage, the summation of upper and lower arm voltages in each leg should be kept equal to 𝑉𝐷𝐶 and the small voltage difference between them are applied to arm inductors. For a MMC with half-bridge SMs, each arm is designed for a rated voltage of 𝑉𝐷𝐶 and the AC terminal voltage can vary between −𝑉𝐷𝐶/2 to +𝑉𝐷𝐶/2. The operation principals of MMCs are discussed with details in [9]. 17 Figure 2.8: Modular multilevel converter (MMC) topology SMSMSMSMSMSM SMSMSMSMSMSMSMSMSM SMSMSM+DC Terminal-PhaseLegPhaseArmChain-link18 2.2.3.3 Advantages and disadvantages of MMC Currently, MMCs are the-state-of-art converter technology in HVDC systems. The most important advantages of MMCs are [35][36][37]: • Modular and scalable topology enables MMCs for creating any desired voltage level. • Implementing high number of submodules reduces rating of power semiconductor devices as well as capacitors, reduces stress on semiconductors and switching loss. • MMCs are almost filter-free reducing costs and increasing efficiency significantly. According to [38], for a converter station, 10% of total loss and 9% of cost are in regard to AC side filters. In addition to above-mentioned advantages, MMC are VSC-based and inherit VSC advantages too. The main disadvantage of MMC-HVDC compared to LCC-HVDC is its higher loss and lower efficiency. 2.2.4 Hybrid Topologies As discussed in previous sections, VSC-MMC topologies have lots of advantages over LCC converters. Moreover, in HVDC applications, DC-side short circuit fault protection is very important. Half-bridge MMC cannot suppress DC side short circuit fault because the half-bridge cell lacks the negative voltage insertion capability. Therefore additional circuitry is need. On the other hand, for other submodule types such as full-bridge submodules, negative cell voltage insertion capability results in high cost and lower efficiency for the converter. This limits the use of MMCs to some specific applications [34]. Therefore, hybrid topologies that employ thyristors in VSCs are proposed [39][40][41]. These converters utilize full-bridge submodule strings (chainlinks) in order to generate trapezoidal waveforms for thyristor commutations. However, in the converters proposed in [39][40][41] the commutation chain-links are in the load current path for zero voltage level. As a result, they suffer high conduction loss during the operations at zero voltage levels. Moreover, these converters require AC side filtering and according to [38], passive filtering is costly and lowers the total converter efficiency. In order to solve these problems, a Thyristor-19 based Hybrid 3-Level Converter (TH3LC) was proposed in [42]. This converter is considered very promising for the future HVDC systems. Modeling of this topology is the main focus of this research. The converter structure and operation details will be discussed in detail in Chapter 3. 2.3 Modeling It is expected that MMC based HVDC systems will become one of the most important parts of power systems in the near future [43]. Simulation studies of MMC-based systems are crucial for the purpose of converter, and controller design, reliability analysis, and converter protection in power systems. Electro-magnetic transient (EMT) type solvers are utilized for simulation of MMCs. However, there is not a suitable model for all types of studies. Therefore, different models are needed for different study goals. In this section, different models will be introduced briefly. Details about these modeling techniques will be discussed in the next chapter. 2.3.1 Detailed Model (DM) In this type of model, the submodule semiconductor devices and capacitors are built in with as much details as possible using EMT type graphical simulation interfaces. In this model users have access to every component current and voltage information. Detailed models are the most accurate for converter operations. The detailed models solve the circuit responses by building up the nodal admittance matrix and calculating the nodal voltage equations for every switching state. As a result, for converters with large number of submodules and nodes, the detailed models are very inefficient from the computational aspect. For MMC-HVDC systems, the converter usually consists of a large number of levels and submodules. For example, for the Trans Bay Cable Project the converter consists of 200 submodules for each arm, therefore the output voltage has 201 levels, and the total converter consists of 1200 submodules. Half-bridge submodules are used in this converter. Consequently, 2400 IGBTs with anti-parallel diodes and 1200 capacitors should be connected and modeled in the simulation software. The resulting admittance matrix 20 for this converter becomes considerably large. These numbers are typical for practical HVDC systems. Subsequently, detailed models are inefficient and sometimes computationally prohibitive for most studies [10]. 2.3.2 Detailed Equivalent Model (DEM) To address the problem of computational inefficiency of detailed models, detailed equivalent models (DEM) were proposed in [10]. DEMs are based on Thevenin equivalent circuits. This reduces the number of nodes in a converter arm drastically. Lower number of nodes results in decrease in admittance matrix size and therefore computational burden of the model. DEMs are able to represent individual submodule switching behaviours with a reasonable accuracy [44]. The disadvantage of DEM in comparison to DM is that the information about individual semiconductor component nonlinear characteristic and switching behaviours is not accessible in DEM [45]. The disadvantage of DEM compared to average value models (AVMs) is that all the converter controllers are needed for DEM and the simulation time and computational burden still increases with the number of levels, i.e., the number of submodules [46]. 2.3.3 Average Value Model (AVM) AVMs are proposed in order to increase simulation speed, decrease computational burden, and simplify the model at the cost of decreased model accuracy. Switching function based (SFB) AVMs assume that the individual submodule capacitors are balanced. Therefore the submodule voltage balancing controllers are eliminated in this model and the model is developed using the number of submodules required to be inserted in each arm. In addition, the equivalent arm capacitor is employed instead of individual submodule capacitors. AVMs based on control signals utilize outer controller signal for DC side voltage and inner loop current controller signal to model the dynamic behaviour of the converter. The AVMs proposed in [47][48] model the converter dynamics for normal operation conditions while the blocking mode (fault operation condition) is not considered. To address this issue, [49][50] consider the blocking mode of operation for MMC HVDCs. However, [47][48][49][50] are proposed only for half-bridge submodule types. Moreover, 21 these models neglect the switching loss of semiconductor devices. The AVMs proposed in [51] and [52] represent MMCs based on full-bridge and mixed-bridge submodules, respectively. 2.4 Conclusion It is an undeniable fact that HVDC systems will play a key role in the future power systems. HVDC systems based on MMC are able to handle any voltage with desired number of levels that enables filter-free systems. Since filters are expensive and lossy, filter-free MMC HVDC systems are efficient and economical. The emerging hybrid converter technology combines the low conduction loss of thyristors with VSC advantages of MMCs. However, the modeling of MMC with large number of levels becomes a challenge for power engineers. Therefore, different types of models are developed for various studies depending on the required degree of accuracy. The focus of this thesis is on numercical efficient modeling of hybrid converter for HVDC systems. 22 Chapter 3: Control and Average Value Modeling of TH3LC This chapter is dedicated to theoretical basics of the hybrid converter and the proposed numerically efficient models. As discussed in Chapter 2, hybrid thyristor based converters are very promising topologies and foreseen to be the future technology for HVDC systems. Therefore, the thyristor-based hybrid three-level converter (TH3LC) is chosen for our studies. Then, this chapter is divided into two parts: firstly the TH3LC topology and operation principals are explained; secondly, different models will be developed for the numerical efficient simulation of TH3LC. 3.1 TH3LC operation principals Figure 3.1 shows the three-phase circuit schematic of TH3LC. For each phase, the heart of the converter is composed of three director switches (upper, lower, middle) and two chain-links (commutation and AC) of full-bridge submodules. Each director switch consists of anti-parallel phase controlled thyristors connected in series. Table 3.1 shows the voltage ratings of converter components. Based on the voltage level required to be blocked, the upper and lower director switches should be rated to the pole-to-pole DC voltage (𝑉𝐷𝐶), and the middle director switch is rated to half DC link voltage plus a thyristor commutation voltage (𝑉𝐷𝐶2+𝑉𝑐𝑜𝑚). The voltage rating of commutation chain-link (CCL) is the same as middle director switch and the AC chain-link (ACCL) should be rated to one-fourth of the pole-to-pole DC voltage because third-order harmonic injected to ACCL. Both of the chain-links (ACCL and CCL) are composed of full-bridge submodules connected in series. The maximum submodule capacitor voltage of the full-bridge submodules is determined based on the blocking voltages of each IGBT. 23 Figure 3.1: Power Circuit Schematic of Thyristor-based Hybrid 3-Level Converter Vc+-Ta,u,pTa,u,nTa,l,pTa,l,nTa,m,nTa,m,p2CDCLCom,aVc+-Vc+-Vc+-Vc+-Vc+-LAC,aVc+-Tb,u,pTb,u,nTb,l,pTb,l,nTb,m,nTb,m,pLCom,bVc+-Vc+-Vc+-Vc+-Vc+-LAC,bVc+-Tc,u,pTc,u,nTc,l,pTc,l,nTc,m,nTc,m,pLCom,cVc+-Vc+-Vc+-Vc+-Vc+-LAC,c2CDCPhase a commutation chainlink (CCL)Phase b commutation chainlink (CCL)Phase c commutation chainlink (CCL)Phase a AC chainlink (ACCL)Phase b AC chainlink (ACCL)Phase c AC chainlink (ACCL)Modified active force-commutated (MAFC) thyristor-bridge24 Table 3.1: Voltage ratings of TH3LC components notation component voltage rating 𝑇𝑗,𝑢,𝑝 positive thyristor of upper director valve 𝑉𝐷𝐶 𝑇𝑗,𝑢,𝑛 negative thyristor of upper director valve 𝑉𝐷𝐶 𝑇𝑗,𝑙,𝑝 positive thyristor of lower director valve 𝑉𝐷𝐶 𝑇𝑗,𝑙,𝑛 negative thyristor of lower director valve 𝑉𝐷𝐶 𝑇𝑗,𝑚,𝑝 positive thyristor of middle director valve 𝑉𝐷𝐶/2 + 𝑉𝑐𝑜𝑚 𝑇𝑗,𝑚,𝑛 negative thyristor of middle director valve 𝑉𝐷𝐶/2 + 𝑉𝑐𝑜𝑚 𝐶𝐶𝐿 commutation chain-link 𝑉𝐷𝐶/2 + 𝑉𝑐𝑜𝑚 𝐴𝐶𝐶𝐿 AC chain-link 𝑉𝐷𝐶/4 𝐶𝐷𝐶 DC link pole capacitor 𝑉𝐷𝐶/2 In order to commutate the thyristors of the director switches, a staircase-shape trapezoidal voltage is produced at the 3-level converter AC terminal (𝑣𝑗,𝑇3𝐿𝐶) by changing the number of inserted submodules in the CCL as the case in [39][40][41]. The CCL voltage should vary between 𝑉𝐷𝐶2+ 𝑉𝑐𝑜𝑚 and −𝑉𝐷𝐶2− 𝑉𝑐𝑜𝑚 values. Therefore, the number of inserted submodules for CCL (𝑁𝑖𝑛𝑠,𝐶𝐶𝐿) is a bipolar integer variable that 𝑁𝑖𝑛𝑠,𝐶𝐶𝐿 ∈ [−𝑁𝐷𝐶 − 𝑁𝑐𝑜𝑚, +𝑁𝐷𝐶 + 𝑁𝑐𝑜𝑚] where 𝑁𝐷𝐶 and 𝑁𝑐𝑜𝑚 are the number of submodules required to create 𝑉𝐷𝐶2 and 𝑉𝑐𝑜𝑚 voltages, respectively. Once the three-level voltage 𝑣𝑗,𝑇3𝐿𝐶 is generated, ACCL is utilized to eliminate the harmonics for sinusoidal voltage output. 25 Proper modulation techniques are required to produce staircase three-level trapezoidal voltage (𝑣𝑗,𝑇3𝐿𝐶). The voltages and currents for generating the three-level voltage are shown theoretically in Figure 3.2 assuming that the converter is operating with a unity power factor. In addition, it is assumed that the converter is in steady state mode. The commutation of current from one of the thyristors to the other one can be illustrated in four steps. Step 1 [𝒕𝟏, 𝒕𝟐]: At the beginning of this interval, the number of inserted submodules in commutation chain-link will be varied in order to generate a negative commutation voltage (−𝑉𝑐𝑜𝑚) across the desired commutating thyristor. The thyristor current direction determines the produced voltage. In other words, the number of inserted submodules in commutation chain-link requires to be 𝑁𝐷𝐶 ± 𝑁𝑐𝑜𝑚, −𝑁𝐷𝐶 ± 𝑁𝑐𝑜𝑚, or ±𝑁𝑐𝑜𝑚 for current commutation away from upper, lower, and middle thyristors, respectively. Consequently, the rate of change in commutation chain-link current will depend on commutation voltage 𝑉𝑐𝑜𝑚 and chain-link inductance 𝐿𝑐𝑜𝑚; i.e., 𝑑𝑖𝑐𝑜𝑚𝑑𝑡=𝑉𝑐𝑜𝑚𝐿𝑐𝑜𝑚. The thyristor current direction is flipped at the end of this interval. The length of this interval is equal to the commutation time (𝑡2 − 𝑡1 = 𝑇𝑐𝑜𝑚). During this time, the back EMF across the commutation inductance will be equivalent to the commutation voltage. Step 2 [𝒕𝟐, 𝒕𝟑]: The length of this interval is equal to the thyristor turn off time (𝑡3 − 𝑡2 = 𝑇𝑞) which starts after flipping the thyristor current direction. In order to prevent the thyristor from re-entering the conduction state during this interval the negative commutation voltages remains across the thyristor. The three-level trapezoidal voltage will be ideal except during the thyristor turn off time where ±𝑉𝑐𝑜𝑚 is superimposed to it. Step 3 [𝒕𝟑, 𝒕𝟒]: During this interval, the thyristors are in off state and able to block voltages across them. 26 Figure 3.2: TH3LC director switches and CCL typical waveforms vDCvDC/20vDCvDC/2t1t2t3t4t5t1t2t3t4t5t1t2t3t4t5t1t2t3t4t50π/2 3π/2π 2π0v A,CCL (θ) v TA,u (θ) i A,CCL (θ) i A (θ) v TA,m (θ) i TA,u(θ) i TA,m(θ) v TA,l (θ) i TA,l(θ) vDC/2iA0-iAiA0-iAiA0-iAiA0-iAiA0-iA-vDC/20v A,3LC (θ) vDC/2-vDC/20vDC/2-vDC/2027 Step 4 [𝒕𝟒, 𝒕𝟓]: During this interval, a constant voltage slope is produced by changing the number of inserted submodules in commutation chain-link. The voltage slope is restricted by the thyristor critical commutation voltage rise rate (𝑑𝑣/𝑑𝑡𝑐𝑟𝑖𝑡). At the end of this interval, a virtual zero voltage is produced across the next conducting thyristor that results in zero-voltage switching. As shown in Figure 3.2, the commutation chain-link only operates in the previously described four steps to commutate current away from thyristors. Otherwise, the chain-link will be in the blocked mode. Consequently, the load current is mainly supplied by thyristor based director switches. Therefore, the converter conduction loss will be lower because thyristors have smaller on-state resistance compared to IGBTs. The commutation chain-link can take over the role of midpoint director switch when being bypassed. However, this will result in higher conduction loss, especially for small modulation indices. The thyristor characteristics determines the commutation voltage (𝑉𝑐𝑜𝑚), commutation chain-link inductance (𝐿𝑐𝑜𝑚) and the capacitance for each submodule of the chain-link. Since 𝑑𝑖𝑐𝑜𝑚𝑑𝑡=𝑉𝑐𝑜𝑚𝐿𝑐𝑜𝑚 and we must have 𝑑𝑖𝑐𝑜𝑚𝑑𝑡𝑐𝑟𝑖𝑡≥𝑉𝑐𝑜𝑚𝐿𝑐𝑜𝑚, then 𝑉𝑐𝑜𝑚𝐿𝑐𝑜𝑚 is design specific and depends on the chosen thyristors. The values of 𝑉𝐶𝑜𝑚 and 𝐿𝑐𝑜𝑚 can be reduced by choosing a large submodule capacitor value because large capacitance reduces the impact of voltage ripples on 𝑉𝐶𝑜𝑚 and 𝐿𝑐𝑜𝑚 ratio. However, the footprint of the converter will increase by choosing a larger capacitance. Pole-to-pole short-circuit faults in the DC side can be ridden through by TH3LC which is a very important characteristic and desired for power system applications. DC side capacitor surge currents or DC side voltage drop is utilized for the detection of the DC side pole-to-pole short-circuit. The three-level trapezoidal voltage that contains four superimposed ±𝑉𝑐𝑜𝑚 in each cycle is produced by the power stage of the converter. The ±𝑉𝑐𝑜𝑚 is superimposed only during a short period of 𝑇𝑞 each time. Since 𝑇𝑞 is very small compared to the fundamental cycle, the four superimposed commutation voltages will 28 affect the fundamental three-level trapezoidal voltage slightly. In this study for the sake of simplicity their influence is neglected. Figure 3.3: Typical waveforms of three-level converter stage and ACCL at maximum modulation index Figure 3.3 (a) illustrates the ideal three-level trapezoidal voltage 𝑣𝑗,𝑇3𝐿𝐶∗ (𝑣𝑗,𝑇3𝐿𝐶 without commutation voltages). In this figure for transiting between 0 to 𝑣𝐷𝐶/2, an angle of 𝜖 radians is needed, i.e. 𝜖 represents the slope duration. The midpoint of the trapezoidal ramp is denoted by 𝛼. Using the Fourier expansion, the three-level ideal trapezoidal voltage for phase A is written as: 𝑣𝐴,𝑇3𝐿𝐶∗ (𝜃) =2𝑣𝐷𝐶𝜋∑sin(𝑛(2𝛼+𝜖)2)−sin(𝑛(2𝛼−𝜖)2)𝑛2𝜖sin(𝑛𝜃)𝑛=1,3,5,… (3.1) In case 𝜖 → 0, the three-level trapezoidal voltage waveform will change to a square waveform controlled by 𝛼. Based on thyristor characteristic limitations (𝑑𝑣𝑑𝑡𝑐𝑟𝑖𝑡≥𝑑𝑣𝑗,𝑇3𝐿𝐶∗𝑑𝑡), 𝜖 is selected with a safety margin for practical applications. According to (3.1), the fundamental component of the ideal three-level trapezoidal voltage can be written as: ϵπ/2 3π/2πωt (rad)2π0vDC/4vDC/2-vDC/4-vDC/22π-απ-αϵϵπ+αϵαvDC/4-vDC/4v*T3LC - v1hsin(θ) - v3hsin(3θ)v*T3LCv1hsin(θ) v3hsin(3θ)v*T3LC - v1hsin(θ)29 𝑣1ℎ(𝜃) =4𝑣𝐷𝐶 cos(𝛼) sin(𝜖2) sin(𝜃)𝜋𝜖 (3.2) Equation 3.2 shows that the magnitude of the output AC terminal voltage of TH3LC can be controlled by the switching angle 𝛼. As a result, the angle 𝛼 can be obtained by fundamental component of the ideal three-level trapezoidal voltage in case of constant 𝜖 as 𝛼 = cos−1 (𝜋𝜖𝑉1ℎ4𝑣𝐷𝐶 sin(𝜖2)) (3.3) Then, the voltage of AC chain-link can be written as 𝑣𝐴,𝐴𝐶𝐶𝐿∗ (𝜃) = 𝑣𝐴,𝑇3𝐿𝐶∗ (𝜃) − 𝑉1ℎ sin(𝜃) (3.4) The maximum voltage of AC chain-link (𝑣𝑗,𝐴𝐶𝐶𝐿∗ (𝜃)) plays the most important role in determination of TH3LC semiconductor losses. Hence, in order to decrease the voltage rating of the AC chain-link third-order harmonic is injected to this voltage. The AC chain-link voltage with third-order harmonic injection for phase A is expressed as 𝑉𝐴,𝐴𝐶𝐶𝐿(𝜃) = 𝑣𝐴,𝑇3𝐿𝐶∗ (𝜃) − 𝑉1ℎ sin(𝜃) − 𝑉3ℎ sin(3𝜃) (3.5) For thyristors capable of tolerating high 𝑑𝑣/𝑑𝑡 with fast switching,very small values close to zero can be considered for 𝜖. In this study, 𝜖 is assumed to be zero. Considering 𝑉𝐴,𝐴𝐶𝐶𝐿(𝛼) = −𝑣𝐷𝐶/4 and 𝜖 = 0, 𝑉3ℎ can be obtained from (3.5) as 𝑉3ℎ =𝑣𝐷𝐶−4𝑉1ℎ sin(𝛼)4sin (3𝛼) (3.6) Equation (3.6) indicates that the AC chain-link voltage is restricted by 𝑣𝐷𝑐/4. This can be illustrated in Figure 3.3. 30 Figure 3.4: Third-order harmonic injection control schematic Analysing equation (3.6), one can understand that at 0 and 𝜋/3 for 𝛼 angle, the third-order harmonic voltage cannot be defined. The modulation indices corresponding to these two angles are ?̂?1ℎ = 4/𝜋 and ?̂?1ℎ =2/𝜋, respectively. Substituting 𝜃 = 𝜋/2 in (3.5), the maximum modulation index is derived as ?̂?1ℎ = 1.26 for this converter using the third-order harmonic injection. For modulation indices between 1.26 and 4/𝜋, there is not any third-order harmonic voltage that can restrict the AC chain-link voltage by 𝑣𝐷𝐶/4. As a result, TH3LC can have a modulation index between 0 and 1.26. The ideal three-level trapezoidal voltage slope that is a finite value can be employed for third harmonic injection at ?̂?1ℎ = 2/𝜋. The control scheme of third harmonic generation is depicted in figure 3.4. Non-zero values for 𝜖 will result in extra degree of freedom in comparison to considering a zero value for it. Higher 𝜖 values may result in higher reduction of the maximum AC chain-link voltage. However, formulating 𝑉3ℎsin (3𝜃) for the ideal three-level trapezoidal voltage with non-zero values of 𝜖 analytically is very challenging for different values of modulation indices. Consequently, numerical methods are used in [42] for finding the modulation index range for non zero 𝜖 values. According to [42], 𝜖 needs to be restricted in [0,0.5] since for values higher than 0.5 the modulation index cannot reach 1.26. The results given in [42] shows that by increasing the 𝜖 values up to 0.5, the maximum AC chain-link voltage can be bounded by as low as 0.16𝑉𝐷𝐶. However, larger values for 𝜖 leads to conduction of commutation chain-link for a larger period. This in turn requires larger submodule capacitors for commutation chain-link and the conduction losses will be increased as well. Eq. (3.6)v1hv3hsinωtδ++vabc,3*331 The necessary and sufficient condition for a converter to be able to block a pole-to-pole fault at the DC side is that the converter should be able to provide a total reverse blocking voltage in each phase larger than 50% of the AC side line-to-line voltage. In other words 𝑣𝑏𝑙𝑜𝑐𝑘𝑖𝑛𝑔 ≥12?̂?𝑚𝑎𝑥𝑣𝐷𝐶2√3, where 𝑣𝑏𝑙𝑜𝑐𝑘𝑖𝑛𝑔 is the total reversed blocking voltage. For TH3LC, 𝑣𝑏𝑙𝑜𝑐𝑘𝑖𝑛𝑔 is equal to the sum of maximum voltages of the two chain-links. Ignoring the commutation voltage, we already discussed that the maximum voltage for commutation and AC chain-links are 𝑣𝑑𝑐/2 and 𝑣𝑑𝑐/4, respectively. Since the maximum modulation index is 1.26, then TH3LC is capable to block the short circuit current in case of pole-to-pole DC side faults. 3.1.1 Converter Control Scheme The overall control scheme of the TH3LC is shown in Figure 3.5. Different controllers cooperate in order to generate the switching states of director switches and both chain-links. To generate the switching states, energy balance, converter stability, voltage balancing of different capacitors, and following power reference values must be considered, as shown in Figure 3.6. Figure 3.5: High-level control scheme of TH3LC TH3LC+--+-VDCPCCvdq ωtidqvABC,CCLvABC,ACCLvABC,3LCSDSSCCLDC cable+v1v2SACCL32 Figure 3.6: SM switching and energy balancing control of AC Chain-link 3.1.2 Energy Balancing of AC chain-link During the operation of TH3LC, the following will lead to deviations in the fundamental voltage of AC chain-link:  Chain-link semiconductor losses  Approximation of the required AC chain-link voltage with an staircase waveform  Voltage ripples of each submodule capacitor of AC chain-link  Superimposing ±𝑉𝑐𝑜𝑚 for thyristor commutation purpose Each cycle, fundamental load current passes through the AC chain-link that results in slight stored energy changes in the chain-link. There will be a drift in the rated voltage values of average submodule voltage caused by deviations of total energy of the AC chain-link. Hence, for the energy imbalance compensation, a small fundamental voltage component needs to be injected by a PI controller. 3.1.3 Energy Balancing of commutation chain-link Although for very short time intervals, the load current passes through the commutation chain-link for commutation of the director switch thyristors as shown in Figure 3.2. In other words, the commutation chain-link energy is supplied to or absorbed from the load that causes slight deviations in the total stored energy of the chain-link. This energy deviation can be compensated by exchanging energy with pole v*abcΔv1/v1hΔvabc+PIvDC/4-vABC,ACCLiΣ33 capacitors at the DC side. Same as the AC chain-link, the energy imbalance in commutation chain-link can be interpreted as voltage deviation. If the total stored energy is unbalanced in commutation chain-link, then the sum of 𝑁𝐷𝐶 submodule voltages would not be equal to 𝑣𝐷𝐶/2 anymore. This voltage difference can take the required charging current from DC pole capacitors for balancing the commutation chain-link. The balancing process is done when the three-level converter is in either the high or the low voltage level, in other words, when the load current is fed by the upper or lower director switches, respectively. Consequently, during the energy balancing process for commutation chain-link, the number of inserted submodules are either +𝑁𝐷𝐶 or −𝑁𝐷𝐶, respectively. Based on the fact that the required charging currents need to boost the average commutation chain-link voltage to 𝑣𝐷𝐶/2 + 𝑣𝑐𝑜𝑚, a charging time 𝜃𝑗,𝑐ℎ𝑎𝑟𝑔𝑒 is decided by the PI controller as illustrated in Figure 3.7. In order to prohibit excess charging of submodules of the commutation chain-link, 𝑁𝑐𝑜𝑚 submodules are blocked after the required charging time passes. Figure 3.7: Commutation chain-link energy balancing control scheme 3.1.4 Modulation of commutation and AC chain-links Different pulse width modulation (PWM) techniques are proposed for MMC in order to obtain the number of inserted submodules in a chain-link based on quantization of equation (3.5). Level-shifted PWM is recommended for small number of submodules since this method is able to mimic the chain-link or converter output voltage accurately at the point of common coupling. The switching losses will increase when increasing the carrier waveform frequency in this method. Moreover, level-shifted PWM becomes complicated with higher number of submodules. To address these issues with level-shifted PWM, nearest vABC,CCLiΣ PIvDC/2+vcomθabc,charge+-34 level control (NLC) is proposed which is a more efficient modulation technique for converters with high number of submodules. In this study, firstly level-shifted PWM is used for models with low number of submodules. After increasing the number of submodules over 20 in each chain-link, we switch to nearest level control as our PWM technique. 3.1.5 Submodule capacitor voltage balancing of commutation and AC chainlinks In order to stabilize the average voltage in each submodule capacitor and limit the ripple within a desired range (usually a few percent of the nominal voltage), voltage balancing controllers are required. Voltage balancing controllers generate the switching signals for individual submodules in each chain-link based on the required number of submodules to be inserted. In other words, the PWM method determines how many submodules to be inserted in a chain-link. Then, this is given as input data to the voltage balancing controller to determine which submodules should be inserted in the next step in order to keep the voltage ripple within the desired range. The direction of chain-link current decides whether the submodule capacitors are charged or discharged in the next step. In addition, all the submodule voltages are measured and given as an input to the voltage balancing controller. The controller sorts the submodule voltages, for example from the highest submodule capacitor voltage to the lowest one. Finally, the controller generates the submodule switching pulses (submodule states) based on the current direction, submodule voltages, and number of submodules required to be inserted. There are different algorithms for sorting of submodule capacitor voltages that can be full sorting or partial sorting. In partial sorting, the previous state of the submodule is also considered for determining the future submodule state. This study uses a partial sorting method for the voltage balancing controllers. From the control hierarchy, the submodule capacitor voltage balancing controllers are the controllers that generate the switching states for chain-link submodules. Figure 3.8 shows the control scheme of switching state generation of TH3LC. in this figure, 𝜔, 𝜃, ΔvDC, and 𝑣𝑎𝑏𝑐,3 represent the angular frequency of the power grid, initial phase angle of each phase, the voltage difference between 35 the DC pole capacitors, and the third-order harmonic voltage injection, respectively. As illustrated in Figure 3.8, the output of different controllers are given as inputs for voltage balancing and switching state generation. (a) (b) Figure 3.8: Switching signal generation: (a) Director switches and CCL; (b) AC chain-link 3.1.6 Real and Reactive Power Control In this study, PI controllers are used for the active and reactive power control (PQ control) of the TH3LC converter. Similar to conventional two-level or multi-level power electronic converters, the AC terminal voltage and current of TH3LC are transformed to dq-reference frame using [𝑓𝑑(𝑡)𝑓𝑞(𝑡)] =23[cos (𝜖(𝑡)) cos (𝜖(𝑡) − 2𝜋/3) cos (𝜖(𝑡) − 4𝜋/3)sin (𝜖(𝑡)) sin (𝜖(𝑡) − 2𝜋/3) sin (𝜖(𝑡) − 4𝜋/3)] [𝑓𝑎(𝑡)𝑓𝑏(𝑡)𝑓𝑐(𝑡)] (3.7) The reference values for active and reactive powers are given to the controllers and are compared with the measured values. Then the error signals are given to the PI controllers to stabilize the power in the desired reference value with a small tolerance. Finally, the values are converted back to abc frame. Figure 3.9 shows the PQ controller scheme for TH3LC. ϵ,α CCL and DC-link capacitor balancingSDSSCCLωtvDCθabcΔvDCv*abcvABC,3LCv*abc,3NLC and SM voltage balancing++--ΔvabcSACCLvABC,ACCL36 Figure 3.9: TH3LC active and reactive power controller scheme 3.2 TH3LC Modeling Hybrid multilevel converters based on thyristors are the promising technology for the future HVDC systems. They combine the advantages of low conduction loss of thyristors with the independent active and reactive power controllability of voltage source converters. In practical applications, because of the limited current and voltage ratings of IGBTs, the number of submodules will be large (sometimes as high as 120 submodules per phase) for high voltage applications. This results in computational inefficiency for detailed models. Therefore, numerically efficient models need to be developed for TH3LC with different levels of accuracy for various applications. For example, during the design process, for developing the active and reactive power controllers, the switching details of the individual submodules are not necessary to be represented. Hence, an average value model would be a better option since it is much faster than the detailed model. In this section, different models with their advantages, disadvantages, and possible applications will be discussed for TH3LC. 3.2.1 Detailed Model Detailed models are the most accurate models for power electronics converters and are referred as traditional library-component-based detailed models in some literature. All the converter components such as thyristors, IGBTs, diodes, and capacitors are represented in details using an electro-magnetic transient Pref id iq vd_ref vd - + - - + + + Qref iq vq vq_ref id - + - - + + + Pmeasured PI PI Qmeasured PI PI 37 (EMT) type simulation software. In this study, MATLAB Simulink is utilized for implementing and comparison of all the models. For detailed models, the nodal admittance matrix needs to be built up in order to solve the system equations. However, the admittance matrix changes in every switching state and needs to be rebuilt and solved. With higher number of submodules, the size of the admittance matrix becomes too large which leads to very slow simulation of MMCs. Therefore, the simplified and computationally efficient models needs to be developed for MMC and hybrid multilevel converter systems. 3.1.1 Detailed Equivalent Model (DEM) To address the issue with large number of nodes, based on the Thevenin equivalent circuit of the converter chain-links, detailed equivalent models (DEMs) are proposed [53][54][55]. As a result, the total number of nodes and therefore the size of admittance matrix reduces drastically which in turn results in faster simulation speed. Compared to traditional detailed models, the DEMs are much faster while being able to accurately simulate the converter dynamics. All the controllers are required for building the DEMs and the computational burden and simulation time increases by increasing the number of submodules. Hence the simulation efficiency reduces by an increase in the number of submodules. DEMs are capable of representing individual submodule switching operations. The equivalent chain-link module is developed based on [51]. All the possible operations consisting bypass, positive insert, negative insert, and blocking mode can be simulated by the proposed DEM in this section. Figure 3.10 shows a typical chain-link of full bridge submodules with its Thevenin equivalent circuit. The equivalent circuit consists of two controlled voltage sources including the 𝑉𝑑𝑏𝑙𝑘 for normal operation mode, 𝑉𝑏𝑙𝑘 for blocking operation mode, and four diodes that form a diode bridge. Comparing to the traditional detailed model, Figure 3.10 shows that the submodule capacitor and switches are not modeled explicitly in DEM. The circuit schematics shown in Figure 3.10 is also used as the base model for all other equivalent models (SFM, ACM, and SAVM) where the calculation approach of controlled voltage source values will differ in these models. 38 Figure 3.10: (a) chain-link of full bridge submodules; (b) equivalent circuit of full bridge submodule As discussed in Chapter 2, neglecting the switching and conduction losses in a submodule, the submodule output voltage based on its switching state is determined by 𝑣𝑆𝑀𝑖 (𝑡) = 𝑠𝑖𝑣𝐶𝑖 (𝑡) (3.8) where 𝑣𝑆𝑀𝑖 (𝑡) is the ith submodule output voltage, 𝑠𝑖 is the ith submodule switching state, and 𝑣𝐶𝑖 (𝑡) is the ith submodule capacitor voltage. The switching state is referred as switching function or modulation index of the submodule in some literature and can take the values of -1, 0, and +1 corresponding to negative insertion, bypass, and positive insertion. The differential equation of the submodule capacitor voltage is discretized in order to obtain the ith full bridge submodule voltage. In this study, Forward Euler method is used for the discretization of the ith submodule capacitor voltage. Using the Forward Euler method 𝑦𝑖+1 =𝑦𝑖 + 𝑓(𝑡𝑖 , 𝑦𝑖)ℎ, where (𝑡𝑖, 𝑦𝑖) is a differential equation and ℎ is the step size,the discretized ith submodule capacitor is calculated as 𝑣𝑐𝑖(𝑡 + Δ𝑡) = 𝑣𝐶𝑖 (𝑡) +1𝐶𝑆𝑀𝑖𝑗Δ𝑡𝑠𝑖 (3.9) where 𝐶𝑆𝑀 is the capacitance of each full bridge submodule, 𝑣𝐶𝑖 (𝑡) is the voltage of ith submodule in the previous time step, 𝑖𝑗 is the current of jth chainlink which is passing through the submodule capacitors, and Δ𝑡 is the time step of the simulation. VdblkFull-bridgesubmoduleFull-bridgesubmoduleFull-bridgesubmodule+VCL-Vblk(a) (b)39 For Forward Euler’s method, we use only up to the first order of the Taylor series in (3.9), which leads to truncation or discritization error in this equation. The true truncation error is 𝐸𝑡 =𝑓′(𝑡𝑖,𝑦𝑖)2!ℎ2 + ⋯ +𝑂(ℎ𝑛+1) that for small ℎ values can be approximated as 𝐸𝑎 =𝑓′(𝑡𝑖,𝑦𝑖)2!ℎ2 = 𝑂(ℎ2). For the equation (3.9) the truncation error would be approximated as 12𝐶𝑆𝑀𝑖𝑗Δ𝑡2. Since the operation of commutation and AC chainlinks are different, firstly we derive the DEM equations for AC chainlink and then apply the required changes and derive the equations for commutation chainlink. For the AC chainlink, in case of operating in normal conditions (de-blocking mode), the total chainlink voltage is equal to the sum of submodule capacitor voltages in the chainlink. Therefore, substituting 𝑣𝑐𝑖(𝑡 + Δ𝑡) in 𝑣𝑆𝑀𝑖 (𝑡), we have 𝑉𝑑𝑏𝑙𝑘,𝐴𝐶𝐶𝐿𝐷𝐸𝑀 = ∑ 𝑠𝑖𝑣𝑐𝑖(𝑡 + Δ𝑡)𝑁𝐴𝐶𝐶𝐿𝑖=1 (3.10) 𝑉𝑏𝑙𝑘,𝐴𝐶𝐶𝐿𝐷𝐸𝑀 = 0 (3.11) where 𝑁𝐴𝐶𝐶𝐿 is the number of full bridge submodules in the AC chainlink. In case of blocking mode operation, all the four semiconductor switches in each full bridge submodule is turned off and each submodule acts as a diode bridge. Consequently, the whole chainlink plays the role of a diode bridge and the capacitor voltages will be charged regardless of the direction of AC side currents, as shown in Figure 3.11. Then, the discretized capacitor voltage of the ith submodule in the chainlink is rewritten as 𝑣𝑐𝑖(𝑡 + Δ𝑡) = 𝑣𝐶𝑖 (𝑡) +1𝐶𝑆𝑀|𝑖𝑗|Δ𝑡𝑠𝑖 (3.12) Hence, during the fault operation or blocking mode operation of AC chainlink, the controlled voltage sources are calculated as 40 Figure 3.11: Submodule capacitor charging during blocking states 𝑉𝑑𝑏𝑙𝑘,𝐴𝐶𝐶𝐿𝐷𝐸𝑀 = 0 (3.13) 𝑉𝑏𝑙𝑘,𝐴𝐶𝐶𝐿𝐷𝐸𝑀 = ∑ 𝑣𝑐𝑖(𝑡 + Δ𝑡)𝑁𝐴𝐶𝐶𝐿𝑖=1 (3.14) Defining 𝑏 as the converter operation state that has a logical value (0 or 1) where 𝑏 = 1 or ?̅? = 0 indicates normal operation and 𝑏 = 0 or ?̅? = 1 indicates the fault blocking operation, the controlled voltage source values for AC chainlink can be generalized as 𝑉𝑑𝑏𝑙𝑘,𝐴𝐶𝐶𝐿𝐷𝐸𝑀 = 𝑏 ∑ 𝑠𝑖 (𝑣𝐶𝑖 (𝑡) +1𝐶𝑆𝑀,𝐴𝐶𝐶𝐿𝑖𝐴𝐶𝐶𝐿Δ𝑡𝑠𝑖)𝑁𝐴𝐶𝐶𝐿𝑖=1 (3.15) 𝑉𝑏𝑙𝑘,𝐴𝐶𝐶𝐿𝐷𝐸𝑀 = ?̅? ∑ (𝑣𝐶𝑖 (𝑡) +1𝐶𝑆𝑀,𝐴𝐶𝐶𝐿|𝑖𝐴𝐶𝐶𝐿|Δ𝑡𝑠𝑖) 𝑁𝐴𝐶𝐶𝐿𝑖=1 (3.16) As mentioned in Section 3.1.3, in order to prohibit excess charging of submodules of the commutation chainlink, 𝑁𝑐𝑜𝑚 submodules are blocked after the required charging time passes. Hence, during normal operation of the converter, both 𝑉𝑑𝑏𝑙𝑘 and 𝑉𝑏𝑙𝑘 may have non-zero values. Therefore, in order to emulate the commutation chainlink dynamics during nomrla operation of the TH3LC the controlled voltage sources are calculated as 𝑉𝑑𝑏𝑙𝑘,𝐶𝐶𝐿𝐷𝐸𝑀 = ∑ 𝑠𝑖𝑣𝑐𝑖(𝑡 + Δ𝑡)𝑁𝑖𝑛𝑠,𝐶𝐶𝐿𝑖=1 (3.17) 𝑉𝑏𝑙𝑘,𝐶𝐶𝐿𝐷𝐸𝑀 = ∑ 𝑣𝑐𝑖(𝑡 + Δ𝑡)𝑁𝑏𝑙𝑘,𝐶𝐶𝐿𝑖=1 (3.18) +-41 where 𝑁𝑖𝑛𝑠,𝐶𝐶𝐿 is the number of inserted submodules in the commutation chainlink that can be any integer between 0 and 𝑁𝐷𝐶 + 𝑁𝐶𝑜𝑚 and 𝑁𝑏𝑙𝑘,𝐶𝐶𝐿 is the number of required submodules to be blocked in order to prevent excess charging. 𝑁𝑏𝑙𝑘,𝐶𝐶𝐿 belongs to the [0, 𝑁𝐶𝑜𝑚] interval. In case of any fault occurrence, all the submodules in the commutation chainlink are blocked same as the AC chainlink. Then the controlled voltage sources during the blocking of the whole commutation chainlink can be written as 𝑉𝑑𝑏𝑙𝑘,𝐶𝐶𝐿𝐷𝐸𝑀 = 0 (3.19) 𝑉𝑏𝑙𝑘,𝐶𝐶𝐿𝐷𝐸𝑀 = ∑ 𝑣𝑐𝑖(𝑡 + Δ𝑡)𝑁𝐷𝐶+𝑁𝐶𝑜𝑚𝑖=1 (3.20) A generalized version based on TH3LC operation state can be expressed as: 𝑉𝑑𝑏𝑙𝑘,𝐶𝐶𝐿𝐷𝐸𝑀 = 𝑏 ∑ 𝑠𝑖 (𝑣𝐶𝑖 (𝑡) +1𝐶𝑆𝑀,𝐶𝐶𝐿𝑖𝐶𝐶𝐿Δ𝑡𝑠𝑖)𝑁𝑖𝑛𝑠,𝐶𝐶𝐿𝑖=1 (3.21) 𝑉𝑏𝑙𝑘,𝐶𝐶𝐿𝐷𝐸𝑀 = 𝑏 ∑ (𝑣𝐶𝑖 (𝑡) +1𝐶𝑆𝑀,𝐶𝐶𝐿|𝑖𝐶𝐶𝐿|Δ𝑡𝑠𝑖)𝑁𝑏𝑙𝑘,𝐶𝐶𝐿𝑖=1 + ?̅? ∑ (𝑣𝐶𝑖 (𝑡) +1𝐶𝑆𝑀,𝐶𝐶𝐿|𝑖𝐶𝐶𝐿|Δ𝑡𝑠𝑖)𝑁𝐷𝐶+𝑁𝐶𝑜𝑚𝑖=1 (3.22) 3.2.3 Switching Function based Model (SFM) The switching function based model of the TH3LC is derived in this section. The approach is the same as the DEM except that the submodule capacitors are assumed to be balanced in SFM. Then, all the submodule capacitors in the chainlink have equal voltages and their individual voltage deviations are neglected. Hence, a voltage balancing controller is not required for SFM and the equivalent capacitance for the chainlink is considered for further simplification. The equivalent chainlink capacitance is calculated as 𝐶𝑒𝑞 =1∑1𝐶𝑆𝑀𝑁𝑖=1=𝐶𝑆𝑀𝑁 (3.23) In addition, a normal operation chainlink switching state 𝑠𝑛 ∈ [−1,1] is defined as 42 𝑠𝑛 =𝑁𝑖𝑛𝑠𝑁=number of submodules required to be insertertedtotal number of submodules in the chainlink (3.24) Similar to the case in DEM, the voltage of the equivalent AC chainlink capacitor is written as 𝑣𝑐,𝐴𝐶𝐶𝐿𝑒𝑞 (𝑡 + Δ𝑡) = 𝑣𝑐,𝐴𝐶𝐶𝐿𝑒𝑞 (𝑡) + 𝑖𝑗Δ𝑡𝑠𝑛𝐶𝑒𝑞,𝐴𝐶𝐶𝐿 (3.25) where the value of 𝑣𝑐𝑒𝑞(𝑡) is calculated in the previous step. The controlled voltage source values for the AC chainlink during normal operation are calculated as 𝑉𝑑𝑏𝑙𝑘,𝐴𝐶𝐶𝐿𝑆𝐹𝑀 = 𝑏𝑠𝑛 (𝑣𝑐𝑒𝑞(𝑡) + 𝑖𝐴𝐶𝐶𝐿Δ𝑡𝑠𝑛𝐶𝑒𝑞,𝐴𝐶𝐶𝐿) (3.26) 𝑉𝑏𝑙𝑘,𝐴𝐶𝐶𝐿𝑆𝐹𝑀 = ?̅? (𝑣𝑐𝑒𝑞(𝑡) + |𝑖𝐴𝐶𝐶𝐿|Δ𝑡1𝐶𝑒𝑞,𝐴𝐶𝐶𝐿) (3.27) Individual switching indices are eliminated because one equivalent capacitor is used for each chainlink. For the commutation chainlink, in addition to the normal operation chainlink switching state, blocking operation switching state is defined as 𝑠𝑏 =𝑁𝑏𝑙𝑘𝑁=number of submodules required to be blockedtotal number of submodules in the chainlink (3.28) Then, the controlled voltage sources for commutation chainlink can be generally expressed as 𝑉𝑑𝑏𝑙𝑘,𝐶𝐶𝐿𝑆𝐹𝑀 = 𝑏𝑠𝑛 (𝑣𝑐𝑒𝑞(𝑡) + 𝑖𝐴𝐶𝐶𝐿Δ𝑡𝑠𝑛𝐶𝑒𝑞,𝐶𝐶𝐿) (3.29) 𝑉𝑏𝑙𝑘,𝐶𝐶𝐿𝑆𝐹𝑀 = 𝑏 (𝑣𝑐𝑒𝑞(𝑡) + |𝑖𝐶𝐶𝐿|Δ𝑡𝑠𝑏𝐶𝑒𝑞,𝐶𝐶𝐿) + ?̅? (𝑣𝑐𝑒𝑞(𝑡) + |𝑖𝐶𝐶𝐿|Δ𝑡1𝐶𝑒𝑞,𝐶𝐶𝐿) (3.30) 3.2.4 Average Chain-link Model (ACM) In order to further reduce the simulation complexity, average chainlink model of TH3LC is derived in this section. The complexity reduction is obtained by assuming constant voltages during de-blocking operation 43 mode for submodule capacitors. Therefore, the dynamics of submodule capacitor voltage is neglected. This results in elimination of chainlinks energy balancing controllers and modulation of chainlinks. The required chainlink output voltage is achieved from the director switch modulation and DC pole capacitor voltage balancing control loops and directly used in calculation of chainlink average voltage. 𝑉𝑑𝑏𝑙𝑘,𝐴𝐶𝐶𝐿𝐴𝐶𝑀 (𝜃) = 𝑏(𝑣𝑇3𝐿𝐶∗ (𝜃) − 𝑉1ℎ sin(𝜃) − 𝑉3ℎ sin(3𝜃)) (3.31) 𝑉𝑏𝑙𝑘,𝐴𝐶𝐶𝐿𝐴𝐶𝑀 = ?̅? (𝑣𝑐𝑒𝑞(𝑡) + |𝑖𝐴𝐶𝐶𝐿|Δ𝑡1𝐶𝑒𝑞,𝐴𝐶𝐶𝐿) (3.32) 𝑉𝑑𝑏𝑙𝑘,𝐶𝐶𝐿𝐴𝐶𝑀 (𝑡) = 𝑏𝑠𝑛𝑣𝑑𝑐 (3.33) 𝑉𝑏𝑙𝑘,𝐶𝐶𝐿𝐴𝐶𝑀 (𝑡) = 𝑏 (𝑠𝑏𝑣𝑑𝑐2) + ?̅? (𝑣𝑑𝑐2+ 𝑣𝑐𝑜𝑚) (3.34) 3.2.5 Standard Average Value Model (SAVM) Standard average value model was proposed in [47] for the traditional MMCs. All the lower level controllers are eliminated and the model calculates the controlled voltage source values based on the high-level converter active and reactive power and d-q current controllers. Since the commutation chainlink is part of the director switch control in TH3LC, the commutation chainlink will not be represented in SAVM and its dynamics are ignored. However, the AC chainlink will still be represented in SAVM. SAVM has the highest simulation efficiency and speed for high-level system studies by sacrificing the simulation accuracy. The converter DC and AC sides are decoupled in SAVM as shown in figure 3.12. Therefore, a controlled DC current source is used along with the DC pole capacitors in order to model the TH3LC dynamics on the DC side. During a DC pole-to-pole fault occurrence, the controlled DC current source is turned off in order to mimic the fault operation of the TH3LC. Consequently, the DC side controlled current source is calculated by 44 Figure 3.12: Standard Average Value Model (SAVM) of TH3LC 𝐼𝑑𝑐 = 𝑏∑ (𝑣1ℎ,𝑗𝑖𝑗)𝑗=𝑎,𝑏,𝑐𝑣𝑑𝑐 (3.35) The controlled voltage source of the AC side in de-blocking mode is calculated based on the PQ controller output signals including the third harmonic injection as 𝑉𝑑𝑏𝑙𝑘𝑆𝐴𝑉𝑀 = 𝑏(𝑉1ℎ sin(𝜃) + 𝑉3ℎ sin(3𝜃)) (3.36) In order to be able to represent the TH3LC DC fault blocking in case of a DC pole-to-pole fault, the commutation chainlink blocking voltage is added to the AC side chainlink voltage. The controlled voltage source in blocking mode is calculated by 𝑉𝑏𝑙𝑘𝑆𝐴𝑉𝑀 = ?̅? (𝑣𝑑𝑐4+𝑣𝑑𝑐2+ 𝑣𝑐𝑜𝑚) (3.37) In order to achieve a better accuracy during the blocking state, one can also use the same equation of the controlled voltage source as in SFM expressed by 𝑉𝑏𝑙𝑘𝑆𝐴𝑉𝑀 = ?̅? [(𝑣𝑐,𝐶𝐶𝐿𝑒𝑞 (𝑡) + |𝑖|Δ𝑡1𝐶𝑒𝑞,𝐶𝐶𝐿) + (𝑣𝑐,𝐴𝐶𝐶𝐿𝑒𝑞 (𝑡) + |𝑖|Δ𝑡1𝐶𝑒𝑞,𝐴𝐶𝐶𝐿)] (3.38) Vdblk,AVblk,AVdblk,BVblk,BVdblk,CVblk,CAC SideIdcDC SideAC Grid45 where 𝑣𝑐,𝐶𝐶𝐿𝑒𝑞 and 𝑣𝑐,𝐴𝐶𝐶𝐿𝑒𝑞 are initialized to 𝑣𝑑𝑐2+ 𝑣𝐶𝑜𝑚 and 𝑣𝑑𝑐4 at the time of fault occurrence. 46 Chapter 4: Simulation Results The TH3LC is simulated in MATLAB Simulink environment in order to validate the modeling methods proposed in Chapter 3. All of the simulations are carried out on a Dell Latitude 5480 laptop with Intel® Core™ i5-7440HQ 2.8 GHz CPU. First, a detailed model is built for TH3LC and compared to DEM model with lower number of submodules. Then, the DEM model is used as a base model to compare the accuracy of the other models with larger number of submodules. 4.1 DEM Validation Similar to [42], a 1096 MVA TH3LC is simulated for this study. The pole-to-pole DC voltage is 600 kV, the commutation voltage is 15 kV, the converter output is connected to the 440 kV AC grid with a delta-wye transformer. A 100 km DC cable is used between the DC source and DC pole-to-pole capacitors of the TH3LC. The schematics of the simulated system is shown in Figure 4.1 that consists of DC source, DC cable, TH3LC, transformer, and AC grid. As the DC source voltage is 600 kV, the commutation and AC chainlinks require to be rated for 315 kV and 150 kV, respectively. In this section, it is assumed that each submodule voltage in both of the chainlinks is 7.5 kV. Therefore, the number of submodules is 42 and 20 for commutation and AC chainlinks (62 submodules per phase), respectively. In other words, the total number of submodules will be 186. MATLAB Simulink Simpscape toolbox is used to carry out the simulations. The DM and DEM are simulated for normal and DC fault operations. The converter is simulated for 1 second. At the beginning of the simulation, the active and reactive power reference values are set to 900 MW and 200 MVAR, respectively. At t=0.2 second, a DC fault occurs and the DC source voltage is stepped to 0 V for 150 ms. Both of the chainlinks are put into blocking state. The DC source voltage is recovered to 600 kV gradually by a ramp function. At t=0.5 second (150 ms after fault clearance), the active and reactive power reference values are changed back to their nominal values. The TH3LC starts operating in normal condition again. The simulation time step is 50 micro seconds. 47 The details of the simulated TH3LC is given in Tables 4.1 and 4.2. Table 4.1: Semiconductor parameters of the simulated TH3LC Device IGBT Thyristor part number T1800GB45A 5STP27N8500 Vref 2.5 kV 4.7 kV Iref 1.8 kA 1.8 kA Eon 11 J / Eoff 11 J 4 J @5 A/µs, 0.25 kV Erec 2.8 J / vT0 1.82 V 1.09 V rT 1.21 mΩ 0.42 mΩ vD0 2.27 V / rD 1.07 mΩ / Table 4.2: Model parameters of the simulated TH3LC DC-side voltage 600 V VAC,grid 440 kV SM voltage in AC chainlink 7.5 kV SM voltage in commutation chainlink 7.5 kV Number of SMs in AC chainlink 20 Number of SM in commutation chainlink 42 SM capacitance in AC chainlink 3.2 mF SM capacitance in commutation chainlink 3.2 mF Trapezoidal slope duration 0.1 radian Commutation inductance 6 mH DC pole-to-pole capacitance 250 µF Transformer leakage impedance 0.001+0.18j pu Transformer winding ratio 350 kV/400 kV AC inductance 23 mH DC inductance 50 mH 48 Figure 4.1: General schematics of the simulated system (a) (b) Figure 4.2: DM and DEM comparison for output AC terminal voltage for phase a of TH3LC TH3LC+--+-VDCDC c able+v1v249 The TH3LC results are shown in Figures 4.2 - 4.6. All the figures have two subfigures (a) and (b) that show the converter operation during 1 second period (normal and fault operation) and zoomed-in 3 cycles (for better comparison) in steady state normal operation after the DC fault is cleared. Figure 4.2 shows the output phase voltage for phase a of the TH3LC at the converter terminal that is connected to the transformer. The output phase voltage has a peak around 600 kV at 60 Hz and it is shown that the proposed DEM can model the TH3LC dynamics with an acceptable accuracy both in normal and fault operation. (a) (b) Figure 4.3: DM and DEM comparison for output AC terminal current for phase a of TH3LC 50 (a) (b) Figure 4.4: DM and DEM comparison for AC chain-link voltage for phase a of TH3LC The converter output current for phase a is shown in Figure 4.3. The peak value of the current reaches about 2 kA in steady state. It is shown that the converter is able to block the current during a DC fault and DEM can mimic DM output current both in normal and blocked operations. The AC chainlink voltage is shown in Figure 4.4. During the blocking period, the chainlink voltage is a little higher than 𝑉𝑑𝑐/4 since the current in any direction charges the capacitors. This figure illustrates that the proposed DEM is able to simulate the AC chainlink voltage of TH3LC with an acceptable accuracy. The commutation chainlink voltage is shown is figure 4.5. It illustrates that the proposed DEM can mimic the DM for commutation chainlink voltage accurately. 51 (a) (b) Figure 4.5: DM and DEM comparison for commutation chain-link voltage for phase a of TH3LC Figure 4.6 shows the DC side current. It is shown in Figure 4.6 that DEM is also able to accurately model TH3LC dynamics during fault and normal operation for DC side as well. Detailed models are the most accurate modeling technique for power converters. However, for large number of submodules DMs are not computationally efficient and even in some cases DMs are computationally prohibitive. The results in Figures 4.2 to 4.6 shows that the proposed DEM can model the TH3LC dynamics accurately for normal and fault operation scenarios. However, the computation time for DEM increases as the number of submodules increase. All the converter controllers are needed for DEM. Furthermore, some system level studies may not need the detailed switching information of the converter. As a result, simpler 52 and more computationally efficient models are required to be developed for TH3LC. In the next section, SFM, ACM, and SAVM will be compared to DEM for a TH3LC with higher number of submodules. (a) (b) Figure 4.6: DM and DEM comparison for DC side current of TH3LC 4.2 Average Value Models (AVMs) According to the design details of the simulated TH3LC given in Tables 4.1 and 4.2, the selected T1800GB45A IGBTs (considering a safety margin) can tolerate a voltage of 2.5 kV. Therefore, in this section 2.5 kV is chosen as each submodule voltage for both commutation and AC chain-links. Hence, 126 submodules for the commutation chain-link (𝑉𝑑𝑐/2 + 𝑉𝑐𝑜𝑚) and 60 submodules for the AC chain-link (𝑉𝐷𝐶/4) that is a total of 186 submodules per phase is chosen for the simulation of TH3LC in this section. 53 The submodule capacitance is adjusted accordingly to maintain same total chain-link capacitance as previous section. Figure 4.7 shows the output terminal voltage of the TH3LC for phase a. It can be illustrated that DEM and SFM can represent the detailed switching transients while ACM and SAVM models can accurately model the low frequency transient of the converter. The AC phase output current of TH3LC for phase a is depicted in Figure 4.8. Since the current waveform is much smoother than output voltage, the difference in different models is not significant. (a) (b) Figure 4.7: DEM, SFM, ACM, and SAVM comparison for AC terminal output voltage of TH3LC 54 (a) (b) Figure 4.8: DEM, SFM, ACM, and SAVM comparison for AC terminal output current of TH3LC The AC chainlink voltage of the TH3LC is shown in Figure 4.9. SAVM is not capable of representing the AC chainlink voltage. We can see that for the peak values, ACM is not as accurate as SFM to model the AC chainlink voltage due to considering constant capacitor voltages in ACM. Table 4.3: Numerical errors for different average value models Parameters SFM ACM SAVM Phase a voltage 0.0240 0.0260 0.0321 Phase a current 0.0179 0.0182 0.0196 55 (a) (b) Figure 4.9: DEM, SFM, and ACM comparison for AC chainlink voltage of TH3LC In order to compare the accuracy of different average value mdels, percentage error is calculated considering DEM as the reference model. The numerical error is calculated using 2-norm as 𝐸𝑟𝑟𝑜𝑟 =√∑ (𝑦𝐷𝐸𝑀 − 𝑦𝐴𝑉𝑀)2𝑛𝑖=1√∑ 𝑦𝐷𝐸𝑀2𝑛𝑖=1 Figure 4.10 illustrates the commutation chainlink voltage of the TH3LC. Similar to the AC chainlink voltage, it cannot be represented by SAVM. However, all the other models can generate the voltage waveform of the commutation chainlink with good accuracy. 56 (a) (b) Figure 4.10: DEM, SFM, and ACM comparison for commutation chainlink voltage of TH3LC Figure 4.11 shows the DC side current for TH3LC. We can see that ACM and SAVM produce similar simulation results as DEM. From the simulation results of converter normal and DC fault operations, we can observe that SAVM and ACM are suitable for system level studies when the modeling of detailed switching events are not required. 57 (a) (b) Figure 4.11: DEM, SFM, ACM, and SAVM comparison for DCside current of TH3LC Figure 4.12: The trade-off between accuracy and computational efficiency Complexity 58 4.3 Conclusion and Comparison As discussed in previous chapters, based on the nature of study we can choose a proper model for modeling the TH3LC. There is a trade-off between accuracy and computational efficiency (model complexity). Figure 4.12 shows this trade-off among different models. For a step size of 50 𝜇𝑠 and total simulation time of 1 second, the simulation execution time for different models with different number of submodules are listed in Table 4.3. Figures 4.13(a) and 4.13(b) show the computation time of different models for 62 and 186 submodules per phase, respectively. The results show that the simulation time for all the models except the SAVM increases as the number of submodules increase. Comparing the results for different models with 62 submodules per phase, we can see a drastic decrease in computational time. The reason lies in the fact that DEM decreases the number of nodes in the simulation drastrically. However, all the controllers are required for DEM simulation and the number of equations to be calculated is directly proportional to the number of sbmodules per phase. For the SFM, ACM, and SAVM the controller complexity affects the simulation speed. Looking at the last column of Table 4.4, it is noted that the computation time of the SAVM is constant for any number of submodules. Therefore, SAVM simulation speed is independent of the number of submodules. Table 4.4: Simulation execution times for DM, DEM, SFM, ACM, and SAVM of TH3LC SMs per Phase DM DEM SFM ACM SAVM (42+20) = 62 301.47 s 10.24 s 4.36 s 3.85 s 2.38 s (84+40) = 124 - 13.10 s 5.97 s 4.82 s 2.38 s (126+60) = 186 - 20.22 s 6.43 s 5.95 s 2.39 s 59 (a) (b) Figure 4.13:Simulation execution time for different models: (a) 62 SMs/phase; (b) 186 SMs/phase 050100150200250300350DM DEM SFM ACM SAVMTimes [s]ModelsSimulation time for 62 SMs / Phase0510152025DEM SFM ACM SAVMTime [s]ModelsSimulation time for 186 SMs / Phase60 Chapter 5: Conclusion Chapter 1 explained the motivation of this thesis. It is predicted that HVDC systems will be the backbone of future integrated AC-DC power grids. Hybrid converter based topologies will have the potential to be the next-generation converter technology for the HVDC systems. However, in real world applications, the number of submodules used in hybrid multilevel converter topologies are high that makes the conventional detailed switching models of these systems computationally prohibitive. Therefore, a need is raised for developing proper modeling techniques for electromagnetic transient type simulation. Chapter 2 reviewed the literature both from converter topology and modeling aspects. Hybrid multilevel converter topologies are the most promising technologies for HVDC systems. Average value modeling is an important solution for accelerated EMT type simulation of HVDC converters. Different average value models have been proposed for conventional MMC converters. However, reviewing the published literature in this regard, there is no model developed for thyristor-based hybrid multilevel converters. As a result, TH3LC is chosen for this study to develop proper modeling techniques in order to fill this research gap. In Chapter 3, operation principals of TH3LC are discussed and detailed equivalent model as well as different average value models (switching function based, average chain-link, and standard AVM models) are proposed for TH3LC. DEM is based on the Thevenin equivalent circuit of the chainlinks. DEM is very accurate and can represent detailed switching transients of the converter. SFM is based on the assumption that submodule capacitor voltages are balanced and there is no need for voltage balancing controller. ACM further simplifies the modeling assuming a constant capacitor voltage for submodules of the chainlinks. This leads to elimination of energy balancing controllers in addition to the voltage balancing controllers. Finally, in SAVM, the DC and AC sides are separated and higher level controller signals are used to calculate the converter behavior. Finally, simulation results are used in Chapter 4 to validate the theoretical discussion of Chapter 3. It is shown in the case studies that, based on the required level of accuracy, computational efficiency, and 61 computation time, proper models can be chosen among DEM, SFM, ACM, and SAVM for detailed converter studies or power system level studies. It is also shown that for all the models except SAVM computation time increases as the number of submodules increases in the converter. For SAVM, the computation time is independent of the number of submodules in the chainlinks of the converter. For any number of submodules, SAVM has the lowest simulation execution time among the other models. Based on the analysis and discussion given in this thesis, the further research can be carried out in the following aspects:  developing and proposing new converter topologies with higher converter efficiency and less complexity  improving and optimizing the control techniques for hybrid converter topologies  developing comprehensive combined detailed and average value models that can be switched among different simulation models on the simulation run by the users 62 Bibliography [1] N. V. Kurdkandi, A. E. Khosroshahi, and S. H. Hosseini, “A switched-capacitor DC-DC converter with voltage regulation for photovoltaic applications,” 2016, doi: 10.1109/ELECO.2015.7394509. [2] H. Dadashzadeh, A. E. Khosroshahi, and S. H. Hosseini, “A digital predictive controller for a SEPIC-based battery charger in photovoltaic power systems,” 2017, doi: 10.1109/EMCT.2017.8090371. [3] IEA, “Power Systems in Transition,” Paris, 2020. [4] IEA, “World Energy Outlook 2019,” 2019. [Online]. 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Thesis/Dissertation
eng
Electrical Engineering
Vancouver : University of British Columbia Library
Attribution-NonCommercial-NoDerivatives 4.0 International
Graduate
Wang, Liwei
Average value modeling of a thyristor-based hybrid three-level power converter for high voltage direct current (HVDC) transmission
Text