Applied Science, Faculty of
Engineering, School of (Okanagan)
DSpace
UBCO
Meng, Xuekun
Doctor of Philosophy - PhD
University of British Columbia
High Voltage Direct Current (HVDC) technology has been widely used in providing interconnection between the remote renewable power plants and the existing power grid infrastructures. The latest development of Modular Multi-level Converter (MMC) in Voltage Source Converter (VSC) family can independently control active and reactive power and provide stability enhancement in weak AC grids. Additionally, harmonic filters are unnecessary in the implementation of MMC as it provides nearly perfect sinusoidal shape waveforms with a sufficient number of levels and switches. In recent years, various projects are developed based on the MMC-HVDC, and it proves its potential in becoming the backbone of the long-distance power transmission in the near future. However, the massive number of power switches in MMC-HVDC also brings notable challenges in digital simulation. Especially for simulating an interconnected system that involves both the MMC-HVDC system and large-scaled AC networks, a large number of switching operations and massive input/output data transfer will introduce a tremendous computational burden. Developing a numerically efficient model for MMC-HVDC interfacing with large-scale AC grids is essential for experimental testing and real-time simulations. This thesis addresses several aspects of the numerically efficient modeling of MMC-HVDC and its integration with a large-scale AC grid. First, a simplified model of MMC is proposed with improved simulation efficiency while preserving accuracy for various transients. The proposed model offers the flexibility in converter operation modes to accommodate the MMC with different submodule topologies and its relevant detailed controls. Next, we extend the concept of the simplified model of MMC into a unified framework to incorporate different levels of simplification into a general circuit structure. The proposed model is validated against state-of-the-art models to demonstrate its significantly improved simulation accuracy. Finally, the simplified MMC model is incorporated into hybrid transient stability and electromagnetic transient simulation for simulating the large-scale AC grid interconnected with MMC-HVDC links. The case studies demonstrate the superior numerical efficiency of the proposed approaches and their advantage in capturing the system-level details. It is envisioned that the proposed modeling approaches can be implemented by various power system transient simulation tools to streamline the HVDC converter design process.
Numerically Efficient Models of Modular Multilevel Converters for High Voltage Direct Current Transmission System and AC-DC Super Grid by Xuekun Meng B.A.Sc., The University of British Columbia, 2015 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY in THE COLLEGE OF GRADUATE STUDIES (Electrical Engineering) THE UNIVERSITY OF BRITISH COLUMBIA (Okanagan) November 2020 © Xuekun Meng, 2020 ii The following individuals certify that they have read, and recommend to the College of Graduate Studies for acceptance, a thesis/dissertation entitled: Numerically Efficient Models of Modular Multilevel Converters for High Voltage Direct Current Transmission System and AC-DC Super Grid submitted by Xuekun Meng in partial fulfillment of the requirements of the degree of Doctor of Philosophy Dr. Liwei Wang, School of Engineering, University of British Columbia Supervisor Dr. Morad Abdelaziz, School of Engineering, University of British Columbia Supervisory Committee Member Dr. Wilson Eberle, School of Engineering, University of British Columbia Supervisory Committee Member Dr. Rudolf Seethaler, School of Engineering, University of British Columbia University Examiner Dr. Venkata Dinavahi, Faculty of Engineering, University of Alberta External Examiner iii Abstract High Voltage Direct Current (HVDC) technology has been widely used in providing interconnection between the remote renewable power plants and the existing power grid infrastructures. The latest development of Modular Multi-level Converter (MMC) in Voltage Source Converter (VSC) family can independently control active and reactive power and provide stability enhancement in weak AC grids. Additionally, harmonic filters are unnecessary in the implementation of MMC as it provides nearly perfect sinusoidal shape waveforms with a sufficient number of levels and switches. In recent years, various projects are developed based on the MMC-HVDC, and it proves its potential in becoming the backbone of the long-distance power transmission in the near future. However, the massive number of power switches in MMC-HVDC also brings notable challenges in digital simulation. Especially for simulating an interconnected system that involves both the MMC-HVDC system and large-scaled AC networks, a large number of switching operations and massive input/output data transfer will introduce a tremendous computational burden. Furthermore, the interconnected AC and MMC-HVDC systems bring new challenges for the real-time simulation of such systems for instrument testing. Developing a numerically efficient model for MMC-HVDC interfacing with large-scale AC grids is essential for experimental testing and real-time simulations. This thesis addresses several aspects of the numerically efficient modeling of MMC-HVDC and its integration with a large-scale AC grid. First, a simplified model of MMC is proposed with improved simulation efficiency while preserving accuracy for various transients. The proposed model offers the flexibility in converter operation modes to accommodate the MMC with different submodule topologies and its relevant detailed controls. Next, we extend the concept of the simplified model of MMC into a unified framework to incorporate different levels of simplification into a general circuit structure. The proposed model is validated against state-of-the-art models to demonstrate its significantly improved simulation accuracy. Finally, the simplified MMC model is incorporated into hybrid transient stability and electromagnetic transient simulation for simulating the large-scale AC grid interconnected with MMC-HVDC links. The case studies demonstrate the superior numerical efficiency of the proposed approaches and their advantage in capturing the system-level details. It is envisioned that the proposed modeling approaches can be implemented by various power system transient simulation tools to streamline the HVDC converter design process. iv Lay Summary New infrastructures and controllers for the utilities require accurate numerical modeling and extensive simulation testing before practical field deployment. The components must be modeled and tested in the digital simulation to verify the response of the component against different fault scenarios. Interconnecting the existing AC grid with the offshore renewable energy power plants through MMC-HVDC is gaining its popularity in the next generation power system. However, the massive switching devices and components of the MMC-HVDC make the simulation very challenging due to the heavy computational cost, which slows down the model developing process, especially for real-time simulation studies and hardware-in-the-loop testing. The ultimate goal of this thesis is to develop numerically efficient models for the interconnected AC and MMC-HVDC systems. This is achieved by the proposed simplified model of MMC and advance hybrid simulation techniques. The results have demonstrated the efficiency and accuracy of the proposed modeling approaches, which will enable the next generation simulation tools for accelerated HVDC converter simulation and design.v Preface Most of the chapters presented in this thesis have been or will be published in scientific journals or conference publications. I have derived the formulas, developed simulation models, performed case studies, analyzed results, and prepared the first draft. My supervisor has provided guidance on my research works and revised my publications. Other co-authors have assisted me to prepare simulation models and experimental results. The chapters presented in this thesis are based on the research works conducted throughout my doctorate program as listed below. Chapter 1 and Chapter 2 present the basic introduction and background of my research topics. Chapter 3: • Xuekun Meng, Jintao Han, Levi Bieber, Liwei Wang, Wei Li, and Jean Belanger, "A Universal-Blocking-Module-Based Average Value Model of Modular Multilevel Converters with Different Types of Submodules", published in IEEE Transactions on Energy Conversion, vol. 35, no. 1, Mar. 2020. • Xuekun Meng, Jintao Han, Liwei Wang, Wei Li, and Jean Belanger, "A Unified Arm Module-Based Average Value Model for Modular Multilevel Converter", published in IEEE Access, vol. 8, no. 1, Dec. 2020. • Xuekun Meng, Jintao Han, Joel Pfannschmidt, Liwei Wang, Wei Li, and Jean Belanger, "An Enhanced Average Value Model of Modular Multilevel Converter for Accurate Representation of Converter Blocking Operation", published in IEEE Power Engineering Society General Meeting 2019, paper ID: 19PESGM2632. Chapter 4: • Xuekun Meng, Jintao Han, Joel Pfannschmidt, Liwei Wang, Wei Li, Fei Zhang, and Jean Belanger, "Combining Detailed Equivalent Model with Switching-Function-Based Average Value Model for Fast and Accurate Simulation of MMCs", published in IEEE Transactions on Energy Conversion, vol. 35, no. 1, Mar. 2020. Chapter 5: • Xuekun Meng, Liwei Wang, "Interfacing an EMT-type modular multilevel converter HVDC model in transient stability simulation", published in IET Generation, Transmission & Distribution, vol. 11, no. 12, May 2017. • Xuekun Meng, Liwei Wang, "Parallel-Rate Hybrid TSP and EMT Simulation of AC-MMC-vi HVDC System using AC Thevenin Equivalent Circuits", to be submitted to IEEE Power Engineering Society General Meeting 2021. vii Table of Contents Abstract ................................................................................................................................... iii Lay Summary .......................................................................................................................... iv Preface .......................................................................................................................................v Table of Contents ................................................................................................................... vii List of Tables ........................................................................................................................... xi List of Figures......................................................................................................................... xii Acknowledgements .................................................................................................................. xv Dedication ...............................................................................................................................xvi 1 Introduction .......................................................................................................................1 1.1 Motivation ....................................................................................................................1 1.2 Literature Review..........................................................................................................2 1.2.1 Modular Multi-level Converter Detailed Equivalent Model ....................................2 1.2.2 Modular Multi-level Converter Average Value Model ...........................................3 1.2.2.1 Controlled-signal-based Average Value Model ...............................................3 1.2.2.2 Switching-function-based Average Value Model ............................................4 1.2.3 Hybrid Simulation Interfacing Techniques .............................................................5 1.3 Research Objectives and Anticipated Impact .................................................................7 2 Modular Multilevel Converter Topologies ........................................................................9 2.1 MMC Submodule Operations ........................................................................................9 2.2 MMC Modulation Techniques .................................................................................... 11 2.3 MMC Capacitor Voltage Balancing and Circulating Current Control .......................... 13 2.4 Detailed swithing-based Equivalent MMC Modeling .................................................. 14 3 Controlled-signal-based Average Value Model of MMC ............................................... 17 3.1 Previous Average Value Models of Modular Multilevel Converter.............................. 17 3.1.1 Standard Average Value Model............................................................................ 18 3.1.2 Improved Average Value Model .......................................................................... 21 3.1.3 Modified Average Value Model ........................................................................... 22 3.2 Generalized Average Value Model .............................................................................. 23 3.2.1 Proposed AVM for the HB MMC ........................................................................ 25 viii 3.2.1.1 Converter De-blocking Mode ........................................................................ 26 3.2.1.2 Converter Energizing Mode .......................................................................... 26 3.2.1.3 Converter DC Pole-to-Pole Fault Blocking Mode.......................................... 27 3.2.2 Proposed AVM for the FB MMC ......................................................................... 28 3.2.2.1 Converter Energizing Mode .......................................................................... 28 3.2.2.2 Converter DC Pole-to-pole Fault Blocking Mode .......................................... 29 3.2.3 Proposed AVM for the MB MMC ........................................................................ 29 3.2.4 Including Conduction and Switching Losses in the Proposed AVM ..................... 31 3.2.4.1 Conduction Loss due to On-State Resistance................................................. 32 3.2.4.2 Conduction Loss due to Saturation Voltage ................................................... 33 3.2.4.3 Switching Loss ............................................................................................. 33 3.2.5 Simulation Studies ............................................................................................... 34 3.2.5.1 Simulation Results of HB MMC ................................................................... 34 3.2.5.2 Simulation Results of FB and MB MMCs ..................................................... 41 3.2.6 Experimental Verification of the Proposed AVM ................................................. 44 3.2.7 Simulation Efficiency .......................................................................................... 47 3.2.8 Modeling Accuracy of Converter Losses .............................................................. 48 3.3 Unified Arm Module Based Average Value Model ..................................................... 50 3.3.1 De-Blocking Mode Model with Virtual DC Equivalent Capacitor ........................ 51 3.3.2 Blocking Mode Model ......................................................................................... 53 3.3.2.1 HBSM-MMC Blocking Model ...................................................................... 53 3.3.2.2 FBSM-MMC Blocking Model ...................................................................... 54 3.3.2.3 CDSM-MMC Blocking Model ...................................................................... 55 3.3.2.4 MBSM-MMC Blocking Model ..................................................................... 56 3.3.3 Complete NAVM Formulation and its Equivalent Circuit .................................... 56 3.3.4 Simulation Studies ............................................................................................... 58 3.3.4.1 HBSM-MMC Energizing .............................................................................. 59 3.3.4.2 HBSM-MMC Active Power Transfer ............................................................ 61 3.3.4.3 HBSM-MMC DC Pole-to-pole Fault............................................................. 62 3.3.4.4 FBSM- and CDSM-MMC DC Pole-to-pole Faults ........................................ 63 3.3.4.5 MBSM-MMC Energizing and DC Pole-to-pole Fault ................................... 66 3.3.5 Simulation Speed Performance ............................................................................ 69 ix 4 Switching-function-based Average Value Model of MMC ............................................. 71 4.1 Detailed Equivalent Model .......................................................................................... 71 4.2 Switching-function-based Average Value Model......................................................... 73 4.3 Generalized Detailed Equivalent Model ...................................................................... 75 4.4 Generalized Switching-function-based Average Value Model ..................................... 78 4.4.1 GSFB-AVM for HBSM-MMC ............................................................................ 79 4.4.2 GSFB-AVM for MMCs with Different SMs ........................................................ 80 4.4.3 Simulation results ................................................................................................ 82 4.4.3.1 Simulation Results of GSFB-AVM for HBSM-MMC ................................... 82 4.4.3.2 Simulation Results of GSFB-AVM for CDSM-MMC ................................... 83 4.5 Combined Model ........................................................................................................ 86 4.5.1 Simulation Results of Combined Model ............................................................... 88 4.5.1.1 Converter Energizing .................................................................................... 88 4.5.1.2 Converter Power Transfer ............................................................................. 90 4.5.1.3 DC-side Pole-to-pole Fault Ride-through ...................................................... 91 4.6 Loss estimation ........................................................................................................... 93 4.6.1 Semiconductor Loss Modeling Results ................................................................. 94 4.7 Modeling a large-scale DC grid in CIGRE .................................................................. 95 4.7.1 DC-side Pole-to-pole Fault ................................................................................... 96 4.7.2 Speed Performance for 1-second Simulation ........................................................ 98 4.8 Real-time simulation ................................................................................................. 100 5 Hybrid Transient Stability and Electromagnetic Transient Simulation ...................... 103 5.1 Modeling Large-scale AC/DC Grid Using Hybrid Simulation Technique .................. 104 5.1.1 Modeling of TS and EMT Subsystems ............................................................... 105 5.1.2 TSP Subsystem Equivalent in EMTP ................................................................. 106 5.1.3 EMTP Subsystem Equivalent in TSP ................................................................. 107 5.1.4 Interfacing Bus Location .................................................................................... 108 5.1.5 Interfacing Protocol ........................................................................................... 108 5.1.6 Case Studies....................................................................................................... 111 5.2 Applying AVM Concept to Establish Parallel Simulation.......................................... 116 5.2.1 The Proposed EMT Subsystem Equivalent and Parallel Interfacing .................... 119 5.2.2 Simulation Results ............................................................................................. 121 x 6 Concluding Chapter ....................................................................................................... 126 6.1 Summary .................................................................................................................. 126 6.2 Future Work .............................................................................................................. 129 Bibliography .......................................................................................................................... 130 Appendices ............................................................................................................................ 136 Appendix A: Experimental Setup and Two-terminal MMC-HVDC System ......................... 136 Appendix B: CIGRE B4-57 MMC-HVDC Grid................................................................... 137 Appendix C: New England 39 Bus Interfacing with Two-terminal MMC-HVDC ................ 138 xi List of Tables Table 1.1 Properties of the State-of-the-art and Proposed Models of MMC .................................7 Table 3.1 Simulation Speeds of Different Models...................................................................... 47 Table 3.2 Comparison of HB MMC Losses Calculated at Different power factors. .................... 49 Table 3.3 Comparison of HB MMC Switching Losses. ............................................................. 49 Table 3.4 Execution Times of the Proposed NAVM vs. DEM and Other AVMS for One-Terminal System ...................................................................................................................................... 69 Table 3.5 Execution Times of the Proposed NAVM vs. DEM and Other AVMS for CIGRE MMC-HVDC Grid............................................................................................................................... 70 Table 4.1 Semiconductor Voltage Drops in GSFB-AVM. ......................................................... 81 Table 4.2 Semiconductor Data................................................................................................... 95 Table 4.3 Semiconductor Losses of MMCs with Different SMs. ............................................... 95 Table 4.4 Execution Times of The Proposed GSFB-AVM vs. DEM .......................................... 98 Table 4.5 CPU Execution Times of Two-Terminal Monopole System. .................................... 101 Table 4.6 CPU Execution Times of Four-Terminal Bipolar System ......................................... 101 Table 5.1 Parameters of the MMC HVDC System. .................................................................. 111 xii List of Figures Figure 2.1 MMC circuit diagram. .............................................................................................. 10 Figure 2.2 Detailed half-bridge SM of an MMC. ....................................................................... 11 Figure 2.3 Level-shifted modulation of an MMC with N=10 SMs per arm. ............................... 12 Figure 2.4 MMC per-phase equivalent circuit model in EMTP .................................................. 15 Figure 3.1 SAVM circuit diagram. ........................................................................................... 19 Figure 3.2 IAVM circuit diagram. ............................................................................................ 22 Figure 3.3 MAVM-AIBM circuit diagram. ............................................................................... 22 Figure 3.4 MAVM-HBM circuit diagram. ................................................................................ 23 Figure 3.5 Proposed Generalized Controlled Signal based Average Value Model. ..................... 25 Figure 3.6 Four charging stages of the MB MMC...................................................................... 30 Figure 3.7 Two-terminal MMC HVDC system. ......................................................................... 34 Figure 3.8 HB MMC energizing. ............................................................................................... 35 Figure 3.9 HB MMC active power transfer. ............................................................................... 37 Figure 3.10 HB MMC three-phase-to-ground fault. ................................................................... 38 Figure 3.11 HB MMC single-phase-to-ground fault. ................................................................. 39 Figure 3.12 DC currents of HB MMC DC pole-pole fault. ........................................................ 40 Figure 3.13 FB MMC energizing............................................................................................... 41 Figure 3.14 MB MMC energizing. ............................................................................................ 42 Figure 3.15 DC currents of DC pole-to-pole fault. ..................................................................... 44 Figure 3.16 Experimental MMC setup (the cabinet houses the MMC hardware). ....................... 45 Figure 3.17 Comparison of experimental and simulated waveforms. ......................................... 46 Figure 3.18 Proposed NAVM in de-blocking mode. .................................................................. 51 Figure 3.19 HBSM in blocking mode. ....................................................................................... 53 Figure 3.20 FBSM in blocking mode. ........................................................................................ 54 Figure 3.21 CDSM in blocking mode. ....................................................................................... 56 Figure 3.22 Proposed complete NAVM in de-blocking and blocking modes. ............................ 57 Figure 3.23 CIGRE two-terminal MMC HVDC system............................................................. 59 xiii Figure 3.24 HBSM-MMC energizing. ....................................................................................... 60 Figure 3.25 HBSM-MMC active power transfer. ....................................................................... 61 Figure 3.26 HBSM-MMC DC fault blocking. ........................................................................... 63 Figure 3.27 FBSM-MMC DC fault blocking. ............................................................................ 65 Figure 3.28 CDSM-MMC DC fault blocking............................................................................ 66 Figure 3.29 MBSM-MMC energizing. ...................................................................................... 67 Figure 3.30 MBSM-MMC DC fault blocking. ........................................................................... 68 Figure 4.1 DEM arm equivalent circuits. ................................................................................... 72 Figure 4.2 SFB-AVM arm equivalent circuits. .......................................................................... 74 Figure 4.3 MMC configuration. ................................................................................................. 75 Figure 4.4 HBSM output voltages based on arm current directions and SM operation modes. ... 76 Figure 4.5 One MMC arm. ........................................................................................................ 77 Figure 4.6 Two-terminal MMC HVDC system .......................................................................... 82 Figure 4.7 HBSM-MMC energizing. ......................................................................................... 83 Figure 4.8 CDSM-MMC energizing. ......................................................................................... 84 Figure 4.9 CDSM-MMC de-blocking. ....................................................................................... 85 Figure 4.10 CDSM-MMC DC pole-to-pole fault. ...................................................................... 86 Figure 4.11 CM circuit configuration. ....................................................................................... 87 Figure 4.12 MBSM-MMC energizing, Phase-A upper arm. ....................................................... 89 Figure 4.13 MBSM-MMC de-blocking, Phase-A upper arm. ..................................................... 90 Figure 4.14 MBSM-MMC DC fault ride-through, Phase-A upper arm....................................... 92 Figure 4.15 Converter Cb-B1 upper FBSM-MMC. .................................................................... 96 Figure 4.16 Converter active powers injected into AC grid. Results presented using the DEM (line) and the GSFB-AVM (dash). ...................................................................................................... 97 Figure 4.17 Converter Cm-B2 FBSM-MMC. ............................................................................ 97 Figure 4.18 Simulation execution times for CIGRE B4-57 test system. ..................................... 99 Figure 4.19 Four-terminal MMC HVDC system. ..................................................................... 100 Figure 5.1 MMC per-phase equivalent circuit model in EMTP. ............................................... 106 Figure 5.2 Interfacing protocol of the TSP and EMTP simulators. ........................................... 109 Figure 5.3 10-generator 39-bus AC system integrating the MMC-based HVDC system........... 110 Figure 5.4 MMC-based HVDC system configuration. ............................................................. 111 xiv Figure 5.5 TS Interface with MMC HVDC model in PSCAD/EMTDC. .................................. 112 Figure 5.6 The RMS values of the interface bus voltage. ......................................................... 113 Figure 5.7 The phase-A interfacing current flowing into the primary side of the sending end transformer.............................................................................................................................. 113 Figure 5.8 The voltage waveforms of the Phase-A upper and lower arms in the sending end converter. ................................................................................................................................ 114 Figure 5.9 The current waveforms of the Phase-A upper arm in the sending end converter. ..... 114 Figure 5.10 The Phase-A output converter voltages at the secondary side of the sending end transformer with the 3rd order harmonic filtered out................................................................ 115 Figure 5.11 The submodule capacitor voltages in the Phase-A upper arm of the sending end converter. ................................................................................................................................ 115 Figure 5.12 Traditional hybrid simulation interfacing equivalent circuits. ................................ 118 Figure 5.13 Traditional hybrid simulation interfacing protocols. .............................................. 119 Figure 5.14 Equivalent circuit of the proposed parallel-rated interfacing method. .................... 120 Figure 5.15 The proposed parallel-rated interfacing protocol. .................................................. 121 Figure 5.16 Instantaneous waveforms from interfacing terminal located at bus-16................... 122 Figure 5.17 Instantaneous power injected from the AC system to the MMC at interfacing terminal located at bus-16. .................................................................................................................... 122 Figure 5.18 RMS voltage waveforms from interfacing terminals. ............................................ 124 Figure 5.19 RMS voltage waveforms at generator buses. ......................................................... 124 xv Acknowledgements My first and foremost sincere gratitude is expressed to my advisor Dr. Liwei Wang for the continuous support of my Ph.D. study and research, and for his patience, motivation, enthusiasm, and immense knowledge. It is a great privilege for me to be his doctoral student. I would also like to thank Dr. Wei Li from OPAL-RT Technologies for his support and valuable suggestions given to me in developing simulation models. Also, I would like to pay my special regards to Mr. Jintao Han for his invaluable support on my work, and for the sleepless nights we are working together before deadlines. Particular thanks are owed to my parents and wife, who have supported me throughout my years of education, both morally and financially. xvi Dedication To my parents 1 1 Introduction 1.1 Motivation Modern power system is experiencing an unprecedented challenge in its system structure. The supply chain in the traditional power system, which includes the combination of generation, transmission, and load, requires significant advancement to meet the increasing global energy consumption. The U.S. Energy Information Administration predicts that the world energy consumption will grow by nearly 50% between 2018 and 2050 [1]. With the urgent need in energy demand, the electrical utilities also seek for developments on its infrastructure. Traditional fossil fuel power plants offer the most economical competitive solution in generating power bult also lead to massive greenhouse gas, which contributes as a major undesirable factor to global warming. Large scale Distributed Energy Resources (DERs) and renewable energies are proposed to reduce greenhouse gas emissions while increasing the power generation capacity and lower the stress in the power system. The renewable energy power plants, including wind farm and solar power plants, are becoming more attractive compared to the traditional fossil fuel power plants due to mature renewable energy integration technologies and abundant natural resources in offshore area and remote communities. Besides, the DERs, including electric car charging and PV rooftop technologies, control the load and generation on small community-scale. Thus, it can effectively complement the traditional generations for improved efficiency and reliability. Together, the interconnection of the offshore renewable power plants to the existing power grid infrastructure is forming the trend of the new power system structure. However, the advancements heavily rely on long-distance power transmission, which is the key to provide external support to the DER and to interconnect the existing infrastructures with the off-shore renewables. Recent research works have focused on the development of the Voltage Source Converter High Voltage Direct Current (VSC-HVDC) long-distance power transmission. Compared to traditional thyristor-based Line Communicated Converter (LCC), the Insulated-Gate Bipolar Transistors (IGBTs) based VSC offers significant advantages, including independent control of active and reactive power, reduced converter footprint, and compensation to weak AC grid [2]–[7]. Especially for the latest development of Modular Multilevel Converter (MMC) [8]–[10] in the VSC family, harmonic filters are unnecessary for the implementation of MMC as it provides near perfect 2 sinusoidal shape waveforms with a sufficient number of levels and switches. In recent years, various projects [11]–[13] were commissioned based on the MMC-HVDC. It has further proved its potential in becoming the backbone of the long-distance power transmission in the near future [14]. However, the massive number of power switches in MMC-HVDC also brings notable challenges in digital simulation. The fast and simultaneous switching behavior of the converter can be modeled in the Electromagnetic transient (EMT) program to capture the device level transition. Each component including switches and submodules is represented in detail in the EMT program. Each switching operation would make a change in the impedance value of the switch, which requires a re-triangularization in the network conductance matrix. This approach, the so-called Detailed Model (DM), provides the most accurate representation of the MMC’s behavior but also required significant computational resources for a complete dynamic simulation study [15]. Especially for an interconnected system that involves both the MMC-HVDC system and large-scaled AC networks, a large number of switching operations and massive input/output data transfer will introduce a tremendous computational burden to the EMT-type solver. Furthermore, the interconnected AC and MMC-HVDC systems bring new challenges for the real-time simulation of such systems for rapid control prototy ing. Therefore, developing numerically efficient models for MMC-HVDC interfaced with large-scale AC grids is essential for experimental testing and real-time simulations before the system commission. 1.2 Literature Review 1.2.1 Modular Multi-level Converter Detailed Equivalent Model Instead of explicitly modeling of each IGBT inside the submodules, the Detailed Equivalent Models (DEM) presented in [16]–[19] utilized the Thevenin equivalent circuits along with a variable resistance to represent the switching behavior of the submodules. In [16], submodules within the same converter arm are discretized and bundled-up to form an equivalent circuit based on the controlled voltage source and variable resistance, which relies on the discretized capacitance equations and the status of the IGBTs. The methods reduce the size of the admittance matrix thus simplify the calculation for the solution at each time instant. The nodal method was presented in [17] that decouples the calculation of the arm submodules using Norton equivalent circuits and realizes the model in the real-time simulation. Instead of providing the equivalent method for a 3 particular scenario based on MMC with half-bridge submodules, the equivalent circuit is expanded in [18] to cover MMC with full-bridge submodule topology, and ideal switches are added in [19] to enhance the model with blocking mode representation. In [20], [21], the direct relationship between the arm currents and the insertion of the submodule capacitors is explored. It concluded that the submodule operation status, which controlled by the IGBTs, can be simply represented using a 1 or 0 status index. This method further improves the simulation efficiency, where the calculation of the variable resistance is no longer needed, and the size of the admittance matrix is reduced. All the detailed characteristic from the switching device is preserved, but meanwhile, the computational burden caused by the individual submodule remains intensive as the number of submodules increases. 1.2.2 Modular Multi-level Converter Average Value Model To further improve the simulation efficiency of MMC, a certain degree of simplification to the converter model must be applied. The smooth and clean waveforms produced from MMC rely on the modularity of the converter, i.e., the number of submodule capacitors. A submodule capacitor is inserted or bypassed to add or decrease a level in the voltage waveform. Nevertheless, the charging or discharging of the submodule capacitors constitutes the dynamics of the DC side voltage. Thus, the response of the converter is heavily dependent on the dynamics of the submodule capacitors, and the simplification on the submodule capacitor modeling and the internal lower level control details are the keys to developing the Average Value Models (AVMs) of MMC. 1.2.2.1 Controlled-signal-based Average Value Model Controlled-signal-based AVM represents MMC using a pair of decoupled AC and DC equivalent circuits, where the AC equivalent circuit highly correlates to the modulation signals produced from the controller; and the DC equivalent circuit emulates the overall dynamics of the submodule capacitors. The concept of controlled-signal-based AVM of MMCs was first proposed by [22] based on the averaging principle in the 2-level VSC. The model simulates the external behavior of MMC using the most essential circuit elements, but the model is not adequate to represent DC side fault due to lack of the blocking mode representation. The AVM is improved in [23] by implementing the ideal switches to transform the equivalent circuit in emulating the free-wheeling behavior from the didoes. However, the re-direction approach of the converter DC current causes numerical oscillation in handling the arm inductor 4 current at the converter DC-side fault. The AVMs proposed in [24] utilized blocking modules to improve the accuracy of the AVMs for converter blocking states. The blocking modules establish electrical connections between the AC-side and the DC-side equivalent circuit, and it is composed of diodes and ideal switches. During de-blocking mode, the blocking module separates the AC-side and DC-side equivalent circuit. When blocking mode is applied, the blocking module is inserted to represent the converter’s free-wheeling diode behaviors. The AVMs proposed in [24] realized the converter blocking capability based on [22], [25]. But, the complicated circuit structure may be difficult for straightforward implementation in a commercial software package. The concept of controlled-signal-based average value model, in general, offers the most numerically efficient solution to simulate the external behavior of the MMC; but meanwhile, the detailed converter insights, e.g., converter arm dynamics are neglect. 1.2.2.2 Switching-function-based Average Value Model The switching-function-based AVM proposed in [26], [27] introduced arm simplification approaches for averaging the capacitor dynamics within an arm. An arm equivalent circuit, which is composed of controlled voltage source and diodes, is used to represent the arm behavior during blocking and de-blocking modes. The existence of the arm structure preserves the circulating current thus provides a better representation of the MMC, although the impact of the individual submodules capacitors is neglected. The model proposed in [26] uses a bidirectional equivalent circuit to represents the arm dynamics for the different current paths. The dynamics of the capacitors are established by the controlled voltage sources and capacitor voltage integration calculation, where the arm currents and the capacitor currents are used as inputs. During de-blocking mode, the arm currents from both directions will be adopted; whereas during blocking mode, only the capacitor current will be used in the calculation. The equivalent circuit with bidirectional diodes can easily distinguish the current flowing into the capacitor and the current bypassed from the capacitor. The model is suitable for half-bridge, but not designed for full-bridge submodules. The model proposed in [27] presents a similar idea but adopts the AC-side current instead of the arm current. The approach in [27] requires an estimated arm current for the calculation of the capacitor voltages. The blocking mode is established by the equivalent circuit with the ideal switches. 5 1.2.3 Hybrid Simulation Interfacing Techniques Although the aforementioned models simplify the calculation of the MMC, the pure electromagnetic transient environment may not be suitable for a large-size AC/DC system. The EMT program takes advantage of the discretization of the differential equations of network elements and performs simulation in the instantaneous value data-type. On the other hand, the conventional Transient Stability (TS) program models the system by a set of differential and algebraic equations in the phasor domain. The use of the hybrid simulation establishes the connection between these two distinct simulation programs and simulates the whole system in two levels of modeling details. The EMT simulator considers the Detailed System (DS), which generally contains the electronic devices and requires a smaller time step. The electromechanical behavior of the remainder system is included in the External System (ES) and is modeled in the TS simulator. Various interfacing techniques are proposed in the previous literature [28]–[36] to built-up the connection between the DS and ES, and each contributed to the improved performance of the simulation. The fundamental difference between the TS program and the EMT program is the type of data each proceeds with. The TS program relies on the fundamental frequency based positive sequence phasor-type data, while the EMT program processes the three-phase instantaneous-value-type data. Therefore, the ES and the DS are simulated on different timescales. The interfacing protocol of the ES and DS would be the major challenge in establishing hybrid simulation. A conventional approach is to use a fundamental frequency based Thevenin/Norton equivalent to represent the dynamics of the ES in the DS. For single port interfacing, the value for the Thevenin/Norton equivalent impedance is evaluated by one per unit current injection at the interfacing terminal. The reference [37] has also addressed the equivalent calculation with Gaussian elimination in case of the multi-terminal interfacing. Noting the admittance equivalent represents the network passive characteristic of the ES, which includes the transmission line, transformer, and generator ground inductance. During the simulation, the equivalent admittance will only be updated when there are any changes occurred in the ES network. The reference [30] demonstrated that the fundamental frequency-based equivalent is not adequate in representing the ES when wide-range frequency components present. Further development was accomplished in [38] and provided several solutions to solve this issue. One is to extend the DS system to include 6 a portion of the ES system, thus lower the harmonic and unbalance effect at the interfacing terminals. However, this would increase the complexity of the hybrid simulation since more interfacing terminals may be introduced as the interfacing boundary moves toward the ES. Another approach is to represent the passive network characteristic of ES with the Frequency-Dependent Network Equivalent (FDNE). The frequency response at interfacing terminals was first fitted with a rational function and then implemented in the form of parallel RLC passive components. Various papers [32], [33], [39] have contributed to demonstrate the accuracy of the FDNE in the hybrid simulation. However, the wide-range frequency data is not easy to be obtained which limits the application of the method. Most tests system data provided in IEEE (etc.) contains only the fundamental frequency based positive sequence data, whereas the negative and zero sequence and multi-section transmission line parameters are not considered. The representation of the DS in the ES can be modeled in the form of constant power load, constant impedance load or Norton/Thevenin equivalent [31]. There is no significant difference in the performance among different implementations. However, they all are based on the voltage and current waveforms accessed from the interfacing boundary. Moreover, the fast instantaneous value based dynamics of the detailed system has to be converted to a phasor based solution via fundamental frequency based fast Fourier transform or least-squares curve fitting techniques to establish the representation. Information exchange between the DS and the ES is achieved by interfacing protocol at the common time steps of TS and EMT solutions. A common approach for sequential protocol is to execute one program followed by another. The EMT program simulates one step or more steps ahead of the TS program by assuming the quasi-state of the external system. It should be evident that the sequential protocol requires at least one program to be idle in each execution thus lower the simulation speed. The reference [40] contributed to the parallel interfacing protocol for which the information from the EMT program can be exchanged in a smaller time step, depending on the execution time of the TS program in solving one iteration. 7 1.3 Research Objectives and Anticipated Impact The functionality of the average value model discussed in section 1.2.1 and 1.2.2 are summarized in Table 1.1. It is recalled that for modeling the blocking mode of MMC using AVMs, modifications of the de-blocking-mode equivalent circuit structure are commonly required to transition the current operation mode using the ideal switches. The feasibility of implementing the ‘circulating current’ and ‘energy balancing’ controllers into the model are also added into the comparison. Results that include the impacts from these controllers are more accurate, compared with the reference solution. Some AVMs also explored the possibility to cover MMC with different submodule types but also presented some limitations on the generality of the circuit structure. The objectives of the thesis are discussed as the following based on the listed criteria. Table 1.1 Properties of the State-of-the-art and Proposed Models of MMC Models Model Type Simulation Efficiency Equivalent Type Blocking Mode Different Submodule Types Circulating Current Control Energy Balancing Control [15] DM Low None ✓ ✓ ✓ ✓ [16]–[18] DEM Medium Submodules ✓ ✓ [19], [20] DEM Medium Submodule ✓ ✓ ✓ [21] DEM Medium Submodule ✓ ✓ ✓ ✓ [22] AVM Very High External [23], [24] AVM Very High External ✓ Proposed GAVM in Section 3.2 AVM Very High External ✓ ✓ Proposed NAVM in Section 3.3 AVM Very High External/Arm ✓ ✓ [26] SFB-AVM High Arm ✓ ✓ [27] SFB-AVM High Arm ✓ ✓ Proposed GSFB-AVM in Section 4.4 SFB-AVM High Arm ✓ ✓ ✓ Proposed CM in Section 4.5 Combined DEM & SFB-AVM Medium/ High Submodules/ Arm ✓ ✓ ✓ ✓ 8 Objective 1: Summarize the fundamentals of the state-of-the-art average value modeling approaches. Pinpoint the differences and limitations through the simulation studies and discuss the possible improvements. Objective 2: Develop a generalized controlled-signal-based average value model that can represent the dynamics of MMC with different submodule types. The developed model should be also capable of simulating the MMC blocking mode while preserving accurate representation of de-blocking mode. Objective 3: Develop a generalized switching-function-based average value model. The MMC with different submodule types can be easily implemented in this model, without significant modification of the circuit structure. Objective 4: Extend Objective 3 to develop a combined DEM and SFB-AVM. The unified framework allows the user to switch from one model type to another during the dynamic simulation. Objective 5: Incorporate the hybrid simulation techniques with the AVM approach for efficient modeling of large-scale AC/DC grid. The ultimate goal of this thesis is to develop an efficient and accurate model for the integrated AC/DC system, which is achieved by the improved average value models and the hybrid simulation techniques. A combined DEM and SFB-AVM framework is proposed to give the users the flexibility to decide which MMC model to employ for the desired study, where the DEM provides the most accurate solution and SFB-AVM offers faster simulation speed. This thesis also presents a test system based on a large-scale AC/DC grid using the combined DEM and SFB-AVM framework. The hybrid simulation offers the most feasible solution in balancing the efficiency and the accuracy of the AC/DC system with thousand of AC buses and switching devices. The slow dynamic of the AC grid can be modeled in TS dominated subsystem, whereas the fast transient from the converter can be modeled in EMT dominated subsystem. Together, the use of the combined model and the hybrid simulation brings the most efficient and accurate solution for the interconnected AC grid and MMC-HVDC system. 9 2 Modular Multilevel Converter Topologies The challenge arises with the growing applications of HVDC systems in the electric power systems. HVDC system enables the interconnection of the AC/DC power system through the VSC, more specifically the MMC, and also provides interconnection among asynchronous networks. Recent research works have proposed the employment of the HVDC grid in long-distance power transmission, especially for the off-shore renewable power plants. The first MMC-HVDC project, Trans Bay Cable, was introduced in North America. It integrates the remote source of renewable energy with the power grid in San Francisco through an 85 km transmission line [12]. By 2018, more than ten projects have been commissioned using MMC-HVDC [41]. It is foreseen that the MMC-HVDC will become the backbone of long-distance power transmission systems in the near future for large-scale renewable energy integration [14]. 2.1 MMC Submodule Operations The three-phase circuit topology of an MMC is shown in Figure 2.1 (a). In each phase of an MMC, there are two converter arms, i.e. upper arm and lower arm, composed of a large number of identical Submodules (SM) as the basic building blocks of an MMC. Depending on converter functionality requirements and applications, there are different types of SMs, for instance, half-bridge [8], full-bridge [2], [42], [43], or clamped double-cell submodules [44], [45] as shown in Figure 2.1 (b)-(d). A combination of mixed half-and full-bridge submodules is also proposed in [46], [47]. The number of submodules in each arm is determined by the total converter DC-side voltage and the SM DC-link voltage. An air-core inductor 𝐿𝑎𝑟𝑚 is used in each converter arm to limit the circulating harmonic current generated in the converter arms due to SM capacitor voltage ripples. The arm inductor is also used to limit short-circuit current flowing in the converter arms when the converter DC-side fault occurs. 10 Figure 2.1 MMC circuit diagram. (a) Three-phase MMC circuit; (b) Half-bridge submodule; (c) Full-bridge submodule; (d) Clamped double-cell submodule. The detailed circuit diagram of the half-bridge SM is given in Figure 2.2. There are three operating modes for each half-bridge SM, i.e., the inserting mode, the bypassing mode, and the blocking mode. For the inserting mode, the upper IGBT switch T1 is turned on, and the lower IGBT switch T2 is off. Thus, the SM capacitor 𝐶𝑆𝑀 is inserted in the converter arm. For the bypassing mode, the upper IGBT switch T1 is turned off while the lower IGBT switch is on. Therefore, the SM capacitor is bypassed from the converter arm. The blocking mode of the half-bridge SM occurs during the converter faulty condition in which the IGBT switches T1 and T2 are blocked. A short-circuit current flows through the freewheeling diodes D1 or D2 depending on the direction of the short-circuit current. 11 Figure 2.2 Detailed half-bridge SM of an MMC. Some MMC-HVDC manufacturers, for example, SIMENS and ALSTOM/GE use industrial module IGBTs which have limited surge current capability for the freewheeling diode D2. Therefore, a parallel press-pack thyristor K is used to conduct a large portion of the short-circuit current to protect the diode D2 as shown in Figure 2.2. A high-speed mechanical switch S is used to bypass the SM when a permanent failure of the SM occurs so that the MMC can still operate until the next scheduled maintenance. 2.2 MMC Modulation Techniques The modulation of an MMC aims at generating reference AC voltage output by the appropriate switching control [48]. It is assumed that an arbitrary phase of the converter reference AC output voltages is expressed as 𝑒𝑟𝑒𝑓 = 𝑣𝑝𝑘sin (𝜔𝑒𝑡 + 𝜃𝑣) (2.1) where 𝑣𝑝𝑘 is the peak reference voltage; 𝜔𝑒 is the electrical frequency of the converter voltage; 𝜃𝑣 is the initial phase angle of the converter voltage. The insertion indices of the upper and lower arm voltages are formulated as 𝑛𝑢 =1 − 𝑚 𝑠𝑖𝑛(𝜔𝑒𝑡 + 𝜃𝑣)2 (2.2) 𝑛𝑙 =1 + 𝑚 𝑠𝑖𝑛(𝜔𝑒𝑡 + 𝜃𝑣)2 (2.3) 12 where the modulation index 𝑚 = 𝑣𝑝𝑘𝑣𝑑𝑐2⁄ . The insertion indices 𝑛𝑢 and 𝑛𝑙 ensure the common-mode voltage of the upper and lower arms equals to the converter DC-side voltage 𝑣𝑑𝑐 while the differential mode voltage of the upper and lower arms produces the converter reference AC output. Figure 2.3 Level-shifted modulation of an MMC with N=10 SMs per arm. (a) carrier and modulation waves; (b) 𝑛𝑢 inserted in the upper arm. Different types of modulation techniques have been proposed for the modulation of MMC converter arm voltages, including phase-shifted and level-shifted carrier-based modulations [49], [50], space-vector modulation [8], nearest level control modulations [51]. Without loss of generality, the research uses the level-shifted carrier-based modulation approach. It is assumed that there are N numbers of identical SMs cascaded in one converter arm where N is decided by 13 the ratio of the converter DC-side voltage 𝑣𝑑𝑐 to the SM DC-link voltage 𝑣𝑝𝑘 . The level-shifted modulation uses N triangular carrier signals. Each carrier wave has an amplitude of 1 2𝑁⁄ with their averages shifted by 1 𝑁⁄ from each other. In Figure 2.3 (a), an example of level-shifted modulation with 𝑁 = 10 is illustrated with the upper modulation index 𝑛𝑢 . The resulting modulated waveform for 𝑛𝑢 is shown in Figure 2.3 (b). 2.3 MMC Capacitor Voltage Balancing and Circulating Current Control The SM capacitors in each converter arm are charged and discharged by the corresponding arm current which results in capacitor voltage ripples. Thus, the SM capacitor voltage should be regulated so that the average of SM capacitor voltages maintain constant for a stable MMC operation. Therefore, SM capacitor voltage balancing control [8], [49]–[51] is required for an MMC. In the capacitor balancing control, the SM capacitor voltages and the corresponding converter arm current are measured. Given the number of SMs to be inserted in a converter arm, 𝑛𝑢 and 𝑛𝑙, from the MMC modulation, the choice of the SM capacitors to be inserted is decided by the capacitor voltage balancing control. Depending on the arm current flow direction, the capacitor voltages are sorted in ascending or descending order. When the arm currents flow from the positive to the negative DC poles as shown in Figure 2.1, the SMs with the lowest voltages will be inserted first so that the arm currents will charge the inserted SM capacitors. When the arm currents flow from the negative to the positive DC poles, the SMs with the highest voltages will be inserted first which causes the arm currents to discharge the inserted SM capacitors. Thus, the SM capacitor is charged and discharged in one electrical cycle to maintain its storage energy and the average DC-link voltage constant. The SM capacitor voltage ripples produce the circulating currents which contain the second-order harmonic component flowing in the converter arms. This second-order circulating current should be suppressed in order to reduce the converter arm current rating and the SM capacitor voltage ripples. Several methods have been proposed for the circulating current control including the second-order harmonic filter [52], the circulating current suppression controller [51], and the arm-energy-estimation-based open-loop control [53]. The open-loop control method which modulates the converter upper and lower arm reference voltages as [53] 14 𝑣𝑢𝑟𝑒𝑓=𝑣𝑑𝑐2− 𝑒𝑟𝑒𝑓 − 𝑢𝑑𝑖𝑓𝑓𝑟𝑒𝑓 (2.4) 𝑣𝑙𝑟𝑒𝑓=𝑣𝑑𝑐2+ 𝑒𝑟𝑒𝑓 − 𝑢𝑑𝑖𝑓𝑓𝑟𝑒𝑓 (2.5) where 𝑣𝑑𝑐 is the converter DC-side voltage; 𝑒𝑟𝑒𝑓is the converter AC output voltage; and 𝑢𝑑𝑖𝑓𝑓𝑟𝑒𝑓 is the voltage drop across the arm impedance. The voltage 𝑢𝑑𝑖𝑓𝑓𝑟𝑒𝑓 is regulated to be a constant/DC voltage which drives the second-order harmonic circulating current in the arm to zero. Thus, the modulation indices of the upper and lower arms can be represented as [53] 𝑛𝑢 =𝑣𝑢𝑟𝑒𝑓𝑣𝑐𝑎𝑝,𝑢Σ (2.6) 𝑛𝑙 =𝑣𝑢𝑟𝑒𝑓𝑣𝑐𝑎𝑝,𝑙Σ (2.7) where 𝑣𝑢𝑟𝑒𝑓 and 𝑣𝑙𝑟𝑒𝑓 are the modulated converter arm reference voltages; 𝑣𝑐𝑎𝑝,𝑢Σ and 𝑣𝑐𝑎𝑝,𝑙Σ are the total capacitor voltages in the upper and lower arm, respectively. 𝑣𝑐𝑎𝑝,𝑢Σ and 𝑣𝑐𝑎𝑝,𝑙Σ are estimated from the capacitor energy stored in the arms. 2.4 Detailed swithing-based Equivalent MMC Modeling The Detailed switching-based Equivalent Model (DEM) is essential for the design and simulation of converter modulation and controls. There have been several different types of models proposed in EMTP [16]–[21]. In order to implement an MMC model for EMTP-type solutions, the circuit components in the SMs are discretized using numerical integration rules, for example, Trapezoidal Rule [16]. This section provides a general overview of the DEM. The result comparisons of the DEM [21] to the prior-art and proposed average value models are illustrated in section 4.3. Figure 2.4 illustrates the per-phase equivalent circuit model of an MMC. The two IGBT switches in a SM can be represented by two equivalent resistors with a large value for the OFF state and a small value for the ON state. A SM capacitor can be discretized into the Thevenin equivalent circuit, for example, 𝑅𝑒𝑞1 and 𝐸𝑒𝑞1 for SM1’s capacitor. Due to the modular structure of an MMC, the discretized equivalent circuits of the SMs can be combined into a Thevenin equivalent circuit for each converter arm as shown in Figure 2.4. This 15 circuit reduction technique greatly improves the MMC simulation efficiency by eliminating the redundant internal electrical nodes [16]. The converter arm Thevenin equivalent can be readily formulated given the IGBT gating signals. However, the MMC blocking state is not represented by the converter arm Thevenin equivalent circuit. When the MMC converter is blocked, the insertion or bypass of a SM capacitor depends on the freewheeling diode conduction state of the SM which is determined by the arm current direction. Therefore, the zero crossings of the converter arm currents are required to determine the conduction states of the freewheeling diodes in the SMs. Figure 2.4 MMC per-phase equivalent circuit model in EMTP For the converter arm equivalent circuit model shown in Figure 2.4, one equivalent IGBT switch (𝑇u and 𝐷u) and diode switch (𝐷l) are used in combination with the converter arm Thevenin equivalent circuit. During normal operation, the IGBT switch (𝑇u and 𝐷u) is in constant ON state 16 so that the converter arm Thevenin equivalent circuit is inserted into the MMC circuit. When the MMC is in blocked state, the IGBT switch 𝑇u is turned off. The natural commutation of the arm current in the diode 𝐷u or 𝐷l will insert or bypass the converter arm Thevenin equivalent circuit in the MMC. This blocking-state modeling approach avoids the zero current detection of the arm currents, thus reducing the modeling complexity of an MMC. 17 3 Controlled-signal-based Average Value Model of MMC This chapter presents the controlled-signal-based AVMs of MMC. It is recalled in Section 1.2.2.1 that the controlled-signal-based AVMs are developed based on the external behavior of the MMC, and it can provide satisfactory simulation accuracy for power system-level studies. We begin by reviewing the state-of-the-art controlled-signal-based AVMs of MMC. The state-of-the-art AVMs can accurately model the steady-state or slow transient behaviors, but they are insufficient to represent MMC during large disturbance or has complicated circuit structures for the implementation in commercial EMT software packages. An arm current initialization method1 is also proposed to improve the accuracy of the AVM for DC fault transients. Later, we propose a new Generalized Average Value Model2 (GAVM) of MMC, where the model can be switched to different modes to mimic the behavior of MMC with different submodule types. Then, a New Average Value Model3 (NAVM) based on the unified circuit is introduced, where this model can provide the simplest circuit structure and detailed representation of the MMC during large disturbances. The accuracy and speed advantages over other AVMs are highlighted. 3.1 Previous Average Value Models of Modular Multilevel Converter Due to the fast and simultaneous switching characteristics of MMC, simulating the dynamics of MMC in EMT-type programs for the fast and accurate solution is challenging. Especially for the MMC with a large number of submodules, modeling the individual behaviors of each IGBT and diode can cause heavy computational load and slow down the overall simulation speed. An AVM that can provide a fast and accurate solution is required to improve the simulation speed and shorten the design and testing process. 1 Xuekun Meng, Jintao Han, Levi Bieber, Liwei Wang, Wei Li, and Jean Belanger, "A Universal-Blocking-Module-Based Average Value Model of Modular Multilevel Converters with Different Types of Submodules", published in IEEE Transactions on Energy Conversion, vol. 35, no. 1, Mar. 2020. 2 Xuekun Meng, Jintao Han, Liwei Wang, Wei Li, and Jean Belanger, "A Unified Arm Module-Based Average Value Model for Modular Multilevel Converter", published in IEEE Access, vol. 8, no. 1, Dec. 2020. 3 Xuekun Meng, Jintao Han, Joel Pfannschmidt, Liwei Wang, Wei Li, and Jean Belanger, "An Enhanced Average Value Model of Modular Multilevel Converter for Accurate Representation of Converter Blocking Operation", published in IEEE Power Engineering Society General Meeting 2019, paper ID: 19PESGM2632. 18 3.1.1 Standard Average Value Model The concept of the controlled-signal-based AVM of MMC is first proposed in [15] in 2013. The model is developed based on the AVM of two-level converter and power balancing theorem. The dynamic of MMC can be described by 0 = −𝑣𝑑𝑐2+ 𝑣𝑢𝑗 + 𝐿𝑎𝑟𝑚𝑑𝑖𝑢𝑗𝑑𝑡+ 𝐿𝑎𝑟𝑚𝑑𝑖𝑙𝑗𝑑𝑡+ 𝑣𝑙𝑗 −𝑣𝑑𝑐2 (3.1) −𝑣𝑑𝑐2+ 𝑣𝑢𝑗 + 𝐿𝑎𝑟𝑚𝑑𝑖𝑢𝑗𝑑𝑡+ 𝑣𝑗 = 0 (3.2) 𝑣𝑑𝑐2− 𝑣𝑙𝑗 − 𝐿𝑎𝑟𝑚𝑑𝑖𝑙𝑗𝑑𝑡+ 𝑣𝑗 = 0 (3.3) where the 𝑣𝑢,𝑗 , 𝑣𝑙𝑗, and 𝑖𝑢,𝑗 , 𝑖𝑙𝑗 are the voltages and currents passing through the upper and lower arms 𝑢 and 𝑙 in phase 𝑗 = 𝑎, 𝑏, 𝑐. Summing up (3.2) and (3.3) gives the relationship between arm voltage and AC-side voltage −𝑣𝑢𝑗 + 𝑣𝑙𝑗2+𝐿𝑎𝑟𝑚2(−𝑑𝑖𝑢𝑗𝑑𝑡+𝑑𝑖𝑖𝑗𝑑𝑡) = 𝑣𝑗 (3.4) Simplifying the upper and lower arms gives a Thevenin equivalent circuit representation of the MMC AC-side dynamic. It is noted that the arm current contains the AC, DC and circulating components, which can be express as 𝑖𝑢𝑗 =𝑖𝑗2+𝑖𝑑𝑐3+ 𝑖𝑧𝑗 (3.5) 𝑖𝑙𝑗 = −𝑖𝑗2+𝑖𝑑𝑐3+ 𝑖𝑧𝑗 (3.6) where 𝑖𝑧 is the current circulating between phases. Assuming the energies are perfectly balanced over the arms, the circulating current will be eliminated, that is 𝑖𝑧 ≈ 0. Subtracting (3.6) from (3.5) gives the relation between arm currents and AC phase current 𝑖𝑢𝑗 − 𝑖𝑙𝑗 = 𝑖𝑗 (3.7) The reference voltage, which is the product from the inner-loop controller, can be expressed based on the function of DC voltage and modulation index as 19 𝑒𝑟𝑒𝑓𝑗 =−𝑣𝑢𝑗 + 𝑣𝑙𝑗2= 𝑚𝑗𝑣𝑑𝑐2 (3.8) Substitute (3.7) and (3.8) into (3.4) gives the direct relation between the common voltage and AC-side voltage 𝑒𝑟𝑒𝑓𝑗 −𝐿𝑎𝑟𝑚2(𝑑𝑖𝑗𝑑𝑡) = 𝑣𝑗 (3.9) It is noted that the derivative of DC components is eliminated from the equation. Substitute (3.9) into (3.2) and (3.3) gives the upper and lower arm voltage representation 𝑣𝑢𝑗 =𝑣𝑑𝑐2− 𝑒𝑟𝑒𝑓𝑗 (3.10) 𝑣𝑙𝑗 =𝑣𝑑𝑐2+ 𝑒𝑟𝑒𝑓𝑗 (3.11) Hence, the abovementioned relationship can be visualized as in Figure 3.1a, where the voltage source inputs are calculated as in (3.10) and (3.11). Figure 3.1 SAVM circuit diagram. (a) AC equivalent circuit; (b) DC equivalent circuit. Based on the power balancing relationship, the power transmitted from the AC-side is approximately equal to the power received from the DC-side plus power loss, which is given as 20 𝑃𝑎𝑐 = 𝑃𝑑𝑐 − 𝑃𝑙𝑜𝑠𝑠 (3.12) Expand the AC-side power based on the common voltage and phase current ∑ 𝑒𝑟𝑒𝑓𝑗𝑖𝑗𝑗=𝑎,𝑏,𝑐= 𝑣𝑑𝑐𝑖𝑑𝑐 − 𝑃𝑙𝑜𝑠𝑠 (3.13) ∑ 𝑒𝑟𝑒𝑓𝑗𝑖𝑗𝑗=𝑎,𝑏,𝑐𝑣𝑑𝑐= 𝑖𝑑𝑐 −𝑃𝑙𝑜𝑠𝑠𝑣𝑑𝑐 (3.14) Plugging in (3.8), we can obtain 12∑ 𝑚𝑗𝑖𝑗𝑗=𝑎,𝑏,𝑐= 𝑖𝑑𝑐 −𝑃𝑙𝑜𝑠𝑠𝑣𝑑𝑐 (3.15) In [15], [22], the total converter loss is estimated to be 1% of the converter power rating. The total power loss is represented using an approximated resistance in the model. For the current source in Figure 3.1, the current source input is calculated as 𝑖𝑐𝑡𝑟𝑙 = −12∑ 𝑚𝑗𝑖𝑗𝑗=𝑎,𝑏,𝑐 (3.16) 𝐸𝑀𝑀𝐶 = 6 (12𝐶𝑆𝑀 ∑(𝑣𝐶𝑖)2𝑁𝑘=1) =12𝐶𝑑𝑐𝑣𝑑𝑐2 (3.17) Assume capacitor voltages are all equal due to the perfect balancing, the DC-side equivalent capacitance can be estimated based on (3.18)-(3.22). 𝐸𝑀𝑀𝐶 = 6 (12𝐶𝑆𝑀𝑁𝑣𝐶2) (3.18) 𝑣𝑑𝑐 = 𝑁𝑣𝐶 (3.19) 𝐸𝑀𝑀𝐶 = 6 (12𝐶𝑆𝑀𝑣𝑑𝑐2𝑁) (3.20) 𝐸𝑀𝑀𝐶 =12(6𝐶𝑆𝑀𝑁) 𝑣𝑑𝑐2 (3.21) 𝐶𝑑𝑐 =6𝐶𝑆𝑀𝑁 (3.22) 21 Switches S are closed in normal operation. During DC-side pole-to-pole fault, the controlled voltage and current sources are set to zero. The switches S are opened to emulate the blocking operation of the MMC. The model can represent the converter dynamics in the de-blocking mode. However, the model is not accurate for the converter blocking mode operations due to the lack of converter diode conduction mode representation. This model is defined as Standard AVM (SAVM) in the following sections to facilitate further discussion. The AVM proposed in [15] identifies the AC-side circuit with basic equivalent arm structure along with the voltage source to represent the switching on and off submodules. In [22], the arms are further simplified according to each phase, based on the AC-component with the DC voltage neglected. The AC-controlled voltage source can solely rely on the control signal and the measured DC voltage source as expressed in (3.8). There is no significant difference from the model proposed in [15] rather than a simplification in the circuit to the Thevenin equivalent circuit. However, a notable challenge arose to the comprehensiveness of the AVMs in [15], [22]. It is noted that the circuit structure of the isolated AC-and DC-equivalent circuit cannot accurately model the DC side fault. The fault current from the AC side is not able to flow to the fault location in the DC side. In addition, the AVMs in [15], [22] is not able to present the free-wheeling diode behavior due to lack of converter arm representation. 3.1.2 Improved Average Value Model Other researchers have made extensive efforts in improving the SAVM for an accurate representation of the converter blocking mode operations. An Improved AVM (IAVM) was proposed in [23], as presented in Figure 3.2, to achieve better modeling accuracy of the MMC in blocking mode. The model uses ideal switches and diodes to represent the de-blocking and blocking behaviors of the MMC. In de-blocking mode, S2 is opened while S1, S3, and S4 are closed. The AC-DC equivalent circuits are isolated from each other and have a similar operation to that of the SAVM in [15]. In blocking mode, S2 is closed while S1 and S3 are opened. S4 is based on an independent control and opens when DC pole-to-pole fault applies. The use of the diodes in the IAVM enables the converter blocking mode representation while S2 establishes the electrical connection between the AC and DC equivalent circuits for the fault currents to flow from the AC- to DC-side. The model assumes that the capacitors are completely bypassed when converter is blocked, and the blocking behaviour of the MMC can be represented by a six-bridge 22 diode. This assumption is valid for MMC with HBSM but not for MMC with other submodule types. However, it should also be noted that the arm inductor 𝐿𝑎𝑟𝑚 in Figure 3.2 are not initialized by the DC fault current at the moment of converter blocking (i.e., at S2 turn-on moment), which causes numerical oscillation in the simulated converter arm and DC currents. Figure 3.2 IAVM circuit diagram. 3.1.3 Modified Average Value Model The so-called Modified Average Value Model with Arm Impedance Blocking Module (MAVM-AIBM) was proposed in [24], which uses a six-pulse diode bridge to represent the converter blocking mode. The model is developed based on the SAVM proposed in [22] and with the so-called Blocking Module (BM) to facilitate the connection between the AC-and DC-side equivalent circuits during blocking mode. Figure 3.3 MAVM-AIBM circuit diagram. In de-blocking mode, the switches S are closed, which keeps the diode bridge blocked and isolates the AC- and DC-side Thevenin equivalent circuits. When the convert is blocked during the DC 23 pole-to-pole fault, the switches S are opened to produce the appropriate fault current path from AC to DC side. However, the arm inductors 𝐿𝑎𝑟𝑚 inside AIBM in Figure 3.3 are not initialized by the DC fault current at the moment of converter blocking (i.e., at S turn-off moment). This causes numerical oscillation in the simulated converter arm and DC currents, similar to the IAVM. The so-called Modified Average Value Model with Hybrid Blocking Module (MAVM-HBM) was also proposed in [24] as an alternative solution to overcome the arm inductor current initialization problem in the MAVM-AIBM. As shown in Figure 3.4, the MAVM-HBM assumes the DC fault current is produced from the discharging of the DC equivalent capacitor 𝐶𝑑𝑐 before the converter is blocked (i.e., the switches S are closed). Therefore, the DC fault current flows through the arm inductors 𝐿𝑎𝑟𝑚 before converter blocking. After the converter is blocked, the switches S are opened to allow the AC-side short-circuit currents to flow to the DC-side. Since the arm inductors 𝐿𝑎𝑟𝑚 are initialized by the DC fault current, the MAVM-HBM can accurately represent the converter blocking behavior under the DC fault without any numerical oscillation. However, the MAVM-HBM has a complicated circuit structure with eight ideal switches and six diodes to enable the transitions between blocking and de-blocking operations. Also, the abovementioned AVMs are designed only for the simulation of the HBSM-MMC and cannot be applied for the MMCs with other SM types, such as the FBSM, the CDSM, and the MBSM. Figure 3.4 MAVM-HBM circuit diagram. 3.2 Generalized Average Value Model The proposed GAVM for the MMCs with different types of SMs (i.e., HB, FB, and MB) is introduced in this section. The developed GAVM is formulated based on the concept of Universal 24 Blocking Module (UBM) which improves the accuracy and applicability of the previous AVMs during converter energizing and DC pole-to-pole fault blocking. The proposed GAVM of MMCs is illustrated in Figure 3.5. The main features of the proposed GAVM are summarized in the following: 1) The proposed GAVM uses Blocked Arm Module (BAM), i.e., diode-based FB structure in each arm of the UBM. The switching state of T (T1 or T2) in the BAM configures the HB, FB or MB MMCs. 2) The controlled voltage source Varm,j in the BAM is defined based on the operating modes of the converter, i.e., blocking vs. de-blocking modes. In blocking mode, Varm,j represents the charging dynamics of the arm capacitors. In de-blocking mode, Varm,j is set to be vdc so that the UBM is inactive due to the reverse biased diodes in the BAMs. 3) The controlled voltage source Vcap at the DC side represents the voltage of the MMC’s DC equivalent capacitance Cdc. The differential equation of Cdc is discretized to obtain the equivalent capacitor output voltage at each time step. A controlled voltage source is used instead of equivalent capacitor Cdc to conveniently assign initial capacitor voltage during converter energizing operation. 4) The controlled current sources Iinit are used to represent the initial arm inductor currents due to the SM capacitor discharging during DC pole-to-pole fault. Compared to the HB MAVM-AIBM in [24], the added controlled current sources Iinit improve the modeling accuracy of the proposed AVM for the DC pole-to-pole fault. 5) The conduction loss due to on-state resistance of the IGBTs/diodes is represented as the AC and DC-side resistances. The conduction losses due to the saturation voltage of the semiconductors and the switching loss are modeled by a controlled current source signal Iloss as shown in Figure 3.5. Iloss depends on the DC current 𝑖𝑑𝑐 , the peak AC modulation index, and the power factor of the MMC. 25 Figure 3.5 Proposed Generalized Controlled Signal based Average Value Model. (a) Overall structure; (b) UBM; (c) HB BAM; (d) FB BAM; (e) MB BAM. 3.2.1 Proposed AVM for the HB MMC The proposed GAVM for HB MMC is realized by turning on switch T in each BAM to form a constant ON-state switch during the entire operation of the HB MMC. Diode D3 in the opposite position will remain in OFF state due to the positive arm voltages Varm,j. Three operating modes of the HB MMC will be represented by the proposed AVM as described in the following. 26 3.2.1.1 Converter De-blocking Mode When the HB MMC operates in de-blocking mode, the converter high-level controls (e.g. P-Q or Vdc-Q) are activated. Switches S are closed to connect the AC and DC equivalent circuits while switch S1 is opened in Figure 3.5 (a). The three-phase AC-side Thevenin equivalent circuit and the DC-side equivalent circuit are used to represent the converter dynamic behavior [24]. The values of the controlled sources Vcj and Icon are calculated based on (3.8) and (3.16) which are the same as the MAVM-AIBM in [24]. The DC-side controlled voltage source Vcap represents the voltage of MMC’s DC equivalent capacitance Cdc. It is calculated based on the following discretized capacitor voltage equation: 𝑉𝑐𝑎𝑝(𝑡) = 𝑉𝑐𝑎𝑝(𝑡 − ∆𝑡) +∆𝑡𝐶𝑑𝑐𝑖𝑐𝑎𝑝(𝑡 − ∆𝑡) (3.23) where ∆𝑡 is the simulation time step. In converter de-blocking mode, the UBM should be isolated from the three-phase AC-side Thevenin equivalent circuit and the DC-side equivalent circuit. Therefore, the six controlled voltage sources, Varm,j, are assigned the rated value of the converter DC-side voltage Vdc as 𝑉𝑎𝑟𝑚,𝑗 = 𝑉𝑑𝑐,𝑟𝑎𝑡𝑒𝑑 (3.24) The diodes in the BAMs are all reverse blocked which isolates the UBM from the AC grid. 3.2.1.2 Converter Energizing Mode In this subsection, the proposed AVM is used to represent the energizing operation of the HB MMC. It assumes that the HB MMC is energized from the AC side with zero SM capacitor voltages and zero initial arm inductor currents Iinit. The controlled voltage sources Varm,j are used to represent the equivalent charging voltages of the SM capacitors in the corresponding arms. Therefore, the values of Varm,j are calculated by 𝑉𝑎𝑟𝑚,𝑗(𝑡) = 𝑉𝑎𝑟𝑚,𝑗(𝑡 − ∆𝑡) +𝑁∆𝑡𝐶𝑆𝑀𝑖𝑎𝑟𝑚,𝑗(𝑡 − ∆𝑡) (3.25) The switch T in Figure 3.5 (c) is closed to form HB diode circuit. The two diodes D1 and D2 in Figure 3.5 (c) provide the current flow paths for the uncontrollable charging. Since the converter is blocked, the DC-side 𝑉𝑐𝑎𝑝, 𝐼𝑙𝑜𝑠𝑠 and 𝐼𝑐𝑜𝑛 are set to zero. The DC-side switch S is opened to 27 disconnect the DC equivalent voltage source 𝑉𝑐𝑎𝑝. Switch S1 is closed to bypass the DC-side arm equivalent impedance. At the end of the uncontrollable charging process, the converter arm equivalent voltage Varm,j will reach the peak line-to-line voltage of the AC source. The converter can de-block its IGBTs and enable Vdc control. This charging stage is also known as controllable charging [54]. Thus, switch S is closed while switch S1 is open. The UBM in Figure 3.5 (b) is de-activated by assigning 𝑉𝑎𝑟𝑚,𝑗 to be the rated DC-side voltage 𝑉𝑑𝑐,𝑟𝑎𝑡𝑒𝑑 . The DC equivalent voltage source 𝑉𝑐𝑎𝑝 is assigned its initial value using the DC voltage at the end of the uncontrollable charging process. Thereafter, Vcap is updated using (3.23). The converter DC voltage will be regulated to the rated voltage by applying the reference DC voltage to the converter Vdc control. The MAVM-AIBM introduced in Section 3.1.3 is applied for the controllable charging process. It is noted that the use of the full-bridge diode circuit and the controlled voltage source Varm,j in Figure 3.5 (c) slightly increases the complexity of the proposed AVM compared to the MAVM-AIBM and MAVM-HBM. However, the controlled voltage sources Varm,j enable accurate modeling of converter energizing transients for the HB, FB, and MB MMCs while the MAVM-AIBM and MAVM-HBM can only be used for the HB MMC. Therefore, the slightly increased complexity of the proposed AVM may be justified by the increased functionality and modeling accuracy. The latter subsections will elaborate on this point in more detail. 3.2.1.3 Converter DC Pole-to-Pole Fault Blocking Mode In the DC pole-to-pole fault scenario, the HB SM capacitors of the MMC will be discharged to the DC fault location. The converter discharging process is modeled in the proposed AVM using the DC-side equivalent capacitor voltage 𝑉𝑐𝑎𝑝 as shown in Figure 3.5 (a). After the converter is blocked, the DC controlled current source is set to zero. The DC-side equivalent voltage source Vcap is disconnected by opening switch S. The DC-side equivalent impedance is bypassed by switch S1. At the moment of S1 closing, the instantaneous DC fault current flowing through the DC-side impedance is used for the controlled current sources Iinit to initialize the UBM’s arm inductors, i.e., 𝐼𝑖𝑛𝑖𝑡 = 𝑖𝑑𝑐(𝑡𝑏𝑙𝑘)/3 (3.26) where 𝑡𝑏𝑙𝑘 is converter blocking time instant. 28 The converter equivalent arm voltages Varm,j are assigned the value of the DC-side equivalent voltage 𝑉𝑐𝑎𝑝 at the moment of opening switches S. For the HB MMC, since the SM capacitors are bypassed during DC pole-to-pole fault blocking, the converter total SM capacitor voltage in each arm is constant. In the proposed AVM, the equivalent arm voltage Varm,j in each arm is correspondingly bypassed by the lower position diode D2 in Figure 3.5 (c) which is consistent with the physical phenomena occurring in the converter. 3.2.2 Proposed AVM for the FB MMC The proposed AVM of the FB MMC is represented in Figure 3.5 (d) by turning off the controllable switch T in Figure 3.5 (d) to form an FB diode circuit for each arm of the UBM. The proposed AVM represents the converter de-blocking mode similar to the HB MMC. Therefore, this subsection focuses more on the blocking mode modeling of the FB MMC using the proposed AVM. 3.2.2.1 Converter Energizing Mode Typically, there are three sequential charging stages for the FB MMC, i.e. (I) FB-mode uncontrollable charging stage; (II) HB-mode uncontrollable charging; (III) controllable charging. According to [54], the use of the three charging stages can effectively limit the inrush charging current. The proposed AVM in Figure 3.5 can accurately represent the three charging stages as described in the following. At the beginning of the converter charging process, the switching of the IGBTs is blocked while the diodes of the FB MMC provide the current conduction path. This corresponds to the FB-mode uncontrollable charging stage. During this charging stage, the SMs in both upper and lower arms of each phase are charged simultaneously. Due to the symmetry of the upper and lower arms of the FB MMC, the upper and lower arm voltages are 180° out of phase, leading to zero DC-side voltage. To represent this FB-mode uncontrollable charging stage, switches S and T in Figure 3.5 (a) and (d) are opened. The converter arm equivalent voltage source Varm,j in Figure 3.5 (d) is used to represent the total arm capacitor voltage in each arm of the FB MMC and is calculated according to (3.25). After the MMC arm voltages reach to the half of the peak AC line to line voltage, the FB-mode uncontrollable charging stage is completed. The next charging stage, i.e., HB-mode uncontrollable charging is activated. Each FB SM in the MMC has one IGBT that must be turned on to operate in HB mode. The SM capacitors are charged by the AC power grid until the converter arm voltages 29 reach the peak value of the line-to-line AC voltage. The UBM can represent this charging stage by turning on switch T in Figure 3.5 (d) and calculating the arm equivalent voltage source Varm,j according to (3.25). In the third stage, i.e., controllable charging, the MMC can de-block its IGBTs and enable its Vdc control to regulate the DC-side voltage to the rated value. The proposed AVM represents the controllable charging stage of FB MMC similar to the HB MMC and is not repeated here. 3.2.2.2 Converter DC Pole-to-pole Fault Blocking Mode The proposed AVM can represent the DC pole-to-pole fault scenario of the FB MMC using the UBM. Before converter blocking, the DC-side equivalent capacitor voltage 𝑉𝑐𝑎𝑝 is discharged through the closed switch S and the DC impedance as shown in Figure 3.5 (a). When the converter is blocked, the DC-side equivalent capacitor voltage 𝑉𝑐𝑎𝑝 is disconnected by opening switch S. The value of the DC-side equivalent voltage 𝑉𝑐𝑎𝑝 is then transferred to the converter equivalent arm voltages Varm,j in the UBM as the initial value of the total capacitor voltage in each arm. The controlled voltage sources Varm,j are used to represent the equivalent voltages of the SM capacitors in the corresponding arms. Therefore, the values of Varm,j are calculated by (3.25). The controlled voltage sources Varm,j are therefore inserted through the FB diode circuit in the short-circuit current paths to block the DC-side short-circuit current. At the moment of converter blocking, the DC-side converter arm equivalent impedance is bypassed by switch S1 since the converter arm inductors have been represented in the UBM. The instantaneous DC fault current flowing through the DC-side arm equivalent impedance is then used for the controlled current sources Iinit to initialize the arm inductors in the UBM as shown in Figure 3.5 (b). Therefore, the DC pole-to-pole fault-blocking of the FB MMC is accurately represented by the proposed AVM. 3.2.3 Proposed AVM for the MB MMC The proposed AVM of the MB MMC is shown in Figure 3.5 (a), (b), and (e). Two cascaded diode-based FB circuits are used to represent each converter arm of the MB MMC in blocking mode. Two controllable switches T1 and T2 in Figure 3.5 (e) are opened or closed to emulate the HB or FB SMs of the MB MMC. The proposed AVM can represent converter de-blocking mode and DC 30 pole-to-pole fault blocking mode like those of the HB and FB MMCs. Thus, this subsection focuses on the energizing operation. The energizing process of MB MMC has typically four charging stages, i.e., (I) uncontrollable HB and FB SMs charging; (II) FB SM bypass stage; (III) All-SMs-in-HB-mode charging; and (IV) controllable charging [54]. The four charging stages are illustrated in Figure 3.6. Figure 3.6 Four charging stages of the MB MMC. The proposed AVM can represent each charging stage accurately as described below. First, the converter SM capacitors are energized through the diodes which correspond to the uncontrollable charging. The HB SM capacitors are charged only when the arm currents are positive while the FB SM capacitors are charged by both positive and negative arm currents. Therefore, the steady-state voltages of the FB SM capacitors are greater than those of the HB SMs [54] as shown in Figure 3.6. The proposed AVM represents the first charging stage by turning off switches S and the DC-side controlled current source in Figure 3.5 (a). The controllable current sources Iinit in Figure 3.5 (b) are initialized to zero since the converter charging is from zero initial arm currents. The controlled voltage sources Varm,j,FB and Varm,j,HB, are calculated by (3.25) which represent the equivalent charging voltages of the FB and HB SM capacitors in the corresponding arms. In the second charging stage, the FB SMs are bypassed so that the HB SM capacitors are charged to the same voltage as the FB SM capacitors. This charging operation can eliminate the voltage difference between the FB and HB SMs and reduce the subsequent charging transients [54]. The proposed AVM represents this charging stage by setting Varm,j,FB to zero in Figure 3.5 (e) to emulate 31 the bypassed FB SMs. The Varm,j,FB values are restored to the uncontrollable steady-state voltage level when HB SM capacitors are charged to the same voltage. In the third charging stage, the FB SMs of the MB MMC are operated in HB mode so that the SM capacitors of the FB and HB SMs are equally charged to 𝑉𝑐,𝐹𝐵𝑖,𝑢𝑐 = 𝑉𝑐,𝐻𝐵𝑖,𝑢𝑐 =𝑉𝑙𝑙𝑁𝐹𝐵 + 𝑁𝐻𝐵 (3.27) where 𝑁𝐻𝐵 and 𝑁𝐹𝐵 are the numbers of SMs of the HB and FB in an arm, respectively. 𝑉𝑙𝑙 is the peak AC-side line-to-line voltage. The proposed AVM represents this charging stage by turning on the switch T2 in Figure 3.5 (e) to change the equivalent FB diode circuit into HB. The last charging stage, i.e., controllable charging, uses the converter Vdc control to regulate the DC-side voltage to the rated value. The proposed AVM represents the controllable charging stage similar to those of the HB or FB MMC. 3.2.4 Including Conduction and Switching Losses in the Proposed AVM The semiconductor conduction and switching losses are modeled in the proposed AVM. Under the MMC circulating current suppression control, the converter phase-A upper arm current can be represented as 𝑖𝑢𝑎 =𝑖𝑎2±𝑖𝑑𝑐3 (3.28) where 𝑖𝑑𝑐 is assumed to be positive. The converter phase-A current is expressed as 𝑖𝑎 = 𝐼𝑎 cos(𝜔𝑡) = √2𝐼𝑎,𝑅𝑀𝑆 cos(𝜃) (3.29) where 𝐼𝑎 and 𝐼𝑎,𝑅𝑀𝑆 are the peak and RMS values of the AC current. The zero-crossing phase angles of the converter arm current 𝑖𝑢𝑎 can be calculated from (3.28) and (3.29) as 𝜃1,2 = ± acos (23𝑖𝑑𝑐𝐼𝑎) ∓ 𝜋 and 𝜃1,2 = ∓acos (23𝑖𝑑𝑐𝐼𝑎) (3.30) In (3.30), two sets of solutions for 𝜃1,2 correspond to the two different arm currents 𝑖𝑢𝑎 in (3.28). The average absolute value of the arm current can be calculated from (3.28)–(3.30) as 32 |𝐼?̅?𝑎| =12𝜋(∫ |𝑖𝑢𝑎|2𝜋+𝜃1𝜃1𝑑𝜃)=1𝜋[√𝐼𝑎2 −49𝑖𝑑𝑐2 +𝑖𝑑𝑐3(𝜋 − 2 acos (23𝑖𝑑𝑐𝐼?̂?))] (3.31) According to the power balance, the phase-A current peak value can be represented using the DC current 𝑖𝑑𝑐 as 𝐼𝑎 = 𝑖𝑑𝑐43?̂?|cos (𝜑)| (3.32) where ?̂? is the peak value of the AC modulation index;cos(𝜑) is the power factor. Substitute (3.32) into (3.31), the average of the absolute value of the arm current can be expressed as |𝐼?̅?𝑎| =𝑘3𝜋𝑖𝑑𝑐 (3.33) where the coefficient k is defined as 𝑘 = 2√4?̂?2𝑐𝑜𝑠2𝜑− 1 + 𝜋 − 2 acos (12?̂?|cos (𝜑)|) (3.34) 3.2.4.1 Conduction Loss due to On-State Resistance It is assumed that the on-state resistance 𝑅𝑜𝑛 is the same for the IGBT and diode to simplify the conduction loss formulation. The converter arm resistance 𝑅𝑎𝑟𝑚 can be expressed as 𝑅𝑎𝑟𝑚 = 𝑁𝜌𝑅𝑜𝑛 + 𝑁(1 − 𝜌)2𝑅𝑜𝑛 = 𝑁𝑅𝑜𝑛(2 − 𝜌) (3.35) where 𝜌 is the percentage of the HB SMs out of the total SMs in one converter arm. Thus, 1 − 𝜌 is the percentage of the FB SMs. N is the total number of SMs in one arm. The conduction losses due to the on-state resistances of IGBTs and diodes are formulated as [24] 𝑃𝑙𝑜𝑠𝑠,𝑅 =62𝜋∫ 𝑖𝑢𝑎22𝜋0𝑅𝑎𝑟𝑚𝑑𝜃 = (23𝑅𝑎𝑟𝑚) 𝑖𝑑𝑐2 + 3 (𝑅𝑎𝑟𝑚2) 𝐼𝑎,𝑅𝑀𝑆2 (3.36) The AC- and DC-side resistances 12𝑅𝑎𝑟𝑚 and 23𝑅𝑎𝑟𝑚 are included in the equivalent circuit of Figure 3.5. 33 3.2.4.2 Conduction Loss due to Saturation Voltage Assuming the same saturation voltage 𝑉𝑜 of an IGBT and diode module, the converter arm saturation voltage 𝑉0,𝑎𝑟𝑚 can be expressed as 𝑉0,𝑎𝑟𝑚 = 𝑁𝜌𝑉0 + 𝑁(1 − 𝜌)2𝑉0 = 𝑁𝑉0(2 − 𝜌) (3.37) The conduction loss due to saturation voltage can be calculated as 𝑃𝑙𝑜𝑠𝑠,𝑉 =6𝑉0,𝑎𝑟𝑚2𝜋(∫ |𝑖𝑢𝑎|2𝜋+𝜃1𝜃1𝑑𝜃) = 6𝑉0,𝑎𝑟𝑚|𝐼?̅?𝑎| (3.38) Substitute (3.31) and (3.37) into (3.38), 𝑃𝑙𝑜𝑠𝑠,𝑉 is represented as 𝑃𝑙𝑜𝑠𝑠,𝑉 =2𝑘𝑁𝑉0(2 − 𝜌)𝜋𝑖𝑑𝑐 (3.39) The number of SMs per arm, 𝑁 is given by 𝑁 =𝑉𝑑𝑐𝑉𝑆𝑀 (3.40) where 𝑉𝑆𝑀 and 𝑉𝑑𝑐 are the rated SM voltage and the DC-side voltage. Substitute (18) into (17), 𝑃𝑙𝑜𝑠𝑠,𝑉 is expressed as 𝑃𝑙𝑜𝑠𝑠,𝑉 =2𝑘𝑉0(2 − 𝜌)𝜋𝑉𝑆𝑀𝑉𝑑𝑐𝑖𝑑𝑐 (3.41) 3.2.4.3 Switching Loss The switching loss can be analytically estimated as [9] 𝑃𝑙𝑜𝑠𝑠,𝑠𝑤 = 6𝑁𝑓𝑃(𝐸on + 𝐸off + 𝐸rec)𝑉𝑆𝑀𝑉𝑟𝑒𝑓𝐼𝑟𝑒𝑓|𝐼?̅?𝑎| (3.42) where 𝐸on, 𝐸off, and 𝐸rec are the IGBT turn-on, turn-off, and the diode reverse recovery energies from datasheet; 𝑉𝑟𝑒𝑓 and 𝐼𝑟𝑒𝑓 are the reference voltage and current for the switching energies; 𝑓𝑃 is the switching frequency per SM. Substituting (3.33) and (3.40) into (3.42), the switching loss is expressed as 𝑃𝑙𝑜𝑠𝑠,𝑠𝑤 =2𝑘𝑓𝑃(𝐸on + 𝐸off + 𝐸rec)𝜋𝑉𝑟𝑒𝑓𝐼𝑟𝑒𝑓𝑉𝑑𝑐𝑖𝑑𝑐 (3.43) 34 Based on (3.41) and (3.43), the conduction loss due to saturation voltage and the switching loss can be combined and represented using a controlled current source signal 𝐼𝑙𝑜𝑠𝑠 in the DC-side of the proposed AVM as 𝐼𝑙𝑜𝑠𝑠 =2𝑘𝜋(𝑉0(2 − 𝜌)𝑉𝑆𝑀+𝑓𝑃(𝐸on + 𝐸off + 𝐸rec)𝑉𝑟𝑒𝑓𝐼𝑟𝑒𝑓) 𝑖𝑑𝑐 (3.44) 3.2.5 Simulation Studies The proposed AVM and the DEM are implemented in MATLAB/Simulink 2014b. A two-terminal MMC HVDC system with 40 SMs in each converter arm is used to benchmark the simulation accuracy and efficiency of various converter models. The MMC system and its parameters [55] are illustrated in Figure 3.7 and Appendix A. The MMC-1 and MMC-2 employ P-Q and Vdc-Q controls, respectively. The detailed low-level controls such as the converter modulation, SM capacitor voltage balancing, and the arm circulating current suppression controls are implemented in the DEM. Figure 3.7 Two-terminal MMC HVDC system. 3.2.5.1 Simulation Results of HB MMC The proposed AVM is verified under three operating modes as discussed in Section 3.2.1. In addition to the DEM, the proposed AVM is also compared to the MAVM-AIBM and MAVM-HBM [24] to illustrate the simulation accuracy. a. Converter Energizing The black start-up of the MMC-1 in Figure 3.7 is studied. The SM capacitors have zero initial voltages. The AC breaker is closed at 0.05 s to energize the converter from the AC side. A charging resistor of 100 Ω is used at the AC side to limit the inrush current for the uncontrollable charging 35 stage. From 0.2 s, the AC charging resistor is bypassed. The converter is de-blocked to enable DC voltage control which regulates the DC voltage to the rated value. The DC voltages and phase-A currents produced by the DEM, the proposed AVM, the MAVM-AIBM, and the MAVM-HBM are shown in Figure 3.8. It is observed in Figure 3.8 that the DEM and the proposed AVM predict identical uncontrollable charging transients for the DC voltage and AC current from 0.05 s to 0.2 s while the MAVM-AIBM and the MAVM-HBM generate small errors of the uncontrollable charging transients compared to the DEM. The improvement of the simulation accuracy by the proposed AVM is due to the use of HB-BAM in Figure 3.5 (c) instead of the lumped DC capacitors in the MAVM-AIBM and the MAVM-HBM in Figure 3.3 and Figure 3.4. Figure 3.8 HB MMC energizing. (a) DC voltage; (b) Phase-A current When the converter is de-blocked after 0.2 s, the proposed AVM, the MAVM-AIBM, and the MAVM-HBM produce identical DC-side voltages as shown in Figure 3.8 (a) which are the average values of the DC-side voltage obtained by the DEM. The AC phase currents predicted by the 36 proposed AVM, the MAVM-AIBM, and the MAVM-HBM are identical after 0.2 s and are very close to the DEM. The identical simulation results of the proposed AVM, the MAVM-AIBM, and the MAVM-HBM after 0.2 s are because the proposed AVM uses the same de-blocked model as the MAVM-AIBM, and the MAVM-HBM as discussed in Section 3.1.3). b. Converter Operations in De-blocked Mode MMC-1 and MMC-2 initially operate in a steady-state. At 0.7 s, the P reference of the MMC-1 is stepped from zero to 1GW. The converter transients due to the change of the P reference are illustrated in Figure 3.9 which shows the accuracy of the proposed AVM compared to the DEM. Since the proposed AVM uses the same de-blocked model as the MAVM-AIBM and the MAVM-HBM, the simulation results of the MAVM-AIBM and the MAVM-HBM are not included in the research. The phase-A upper arm individual SM capacitor voltages and the six-arm average capacitor voltage by the DEM, as well as the DC-side equivalent capacitor voltage by the proposed AVM, are shown in Figure 3.9 (c). The phase-A upper arm currents produced by the DEM and the proposed AVM are illustrated in Figure 3.9 (d). The arm current predicted by the AVM is calculated from the AC and DC currents using (3.28) since the AVMs do not represent converter arm circuits in de-blocking mode. It is seen in Figure 3.9 that the proposed AVM produces accurate low-frequency responses compared to the DEM. A three-phase-to-ground fault is applied on the converter transformer primary side at 1 s and is cleared after 220 ms. Figure 3.10 illustrates the simulation results by the DEM and the proposed AVM. It is observed from Figure 3.10 that the proposed AVM predicts accurate transients that match those of the DEM. The minor difference in the predicted DC currents by the DEM and the proposed AVM is mainly because the proposed AVM does not represent any SM capacitor voltage ripple. 37 Figure 3.9 HB MMC active power transfer. (a) Active power; (b) DC current; (c) Phase-A upper arm individual SM capacitor voltages by the DEM, average six-arm capacitor voltage by the DEM, and the DC-side equivalent capacitor voltage by the proposed AVM; (d) Phase- A upper arm currents. 38 Figure 3.10 HB MMC three-phase-to-ground fault. (a) Active power; (b) Phase-A current; (c) DC voltage; (d) DC current. 39 Figure 3.11 HB MMC single-phase-to-ground fault. (a) Active power; (b) Phase-A current; (c) DC voltage; (d) DC current. 40 To further verify the proposed AVM for the unbalanced operating condition, a single-phase-to-ground fault is applied on Phase A of the converter transformer primary side at 1 s and is cleared after 220 ms. The simulation results by the DEM and the proposed AVM are shown in Figure 3.11 which demonstrates the accuracy of the proposed AVM compared to the DEM. It is noted that the proposed AVM produces slightly less accurate results for the DC-side voltage in Figure 3.11 (c) during the single-phase fault due to the lack of individual SM capacitor voltage ripple representation. c. DC-side Pole-to-pole Fault A DC-side pole-to-pole fault is applied at 1 s in the middle of the transmission line. The MMCs are blocked at 1.2 ms after the fault occurs. The AC breakers are opened at 1.04 s. The DC-side currents of MMC-1 predicted by the DEM, the proposed AVM, the MAVM-AIBM, and the MAVM-HBM are shown in Figure 3.12. It is observed in Figure 3.12 that the proposed AVM and the MAVM-HBM produce accurate results, almost identical to that of the DEM. The MAVM-AIBM predicts less accurate DC current response when the converter is blocked. Figure 3.12 DC currents of HB MMC DC pole-pole fault. The reason that the proposed AVM and the MAVM-HBM produce almost identical results is because their arm currents in the BMs are initialized using the initial DC fault current when the converter is blocked. The MAVM-AIBM does not account for the initial DC-fault currents in the arm inductors of the BM. Therefore, the arm currents in the BM of the MAVM-AIBM are forced 41 to change instantly from zero to the fault current level at the converter blocking instant which causes some numerical oscillation as shown in Figure 3.12. 3.2.5.2 Simulation Results of FB and MB MMCs The proposed AVM for the FB and MB MMCs are verified in the subsection for the converter blocking mode operations, i.e., converter energizing and DC pole-to-pole fault. d. Converter Energizing The DC voltage and the AC current of the FB MMC during the energizing process are shown in Figure 3.13. As described in Section 3.2.2, the FB MMC experiences three charging stages. The uncontrollable diode charging stage first starts from 0.05 s to 0.1 s. Since both the lower and upper arms of the FB MMC are energized together, the lower and upper arm voltages are 180° out of phase, leading to zero 𝑉𝑑𝑐. Figure 3.13 FB MMC energizing. (a) DC voltage; (b) Phase-A current. 42 Figure 3.14 MB MMC energizing. (a) DC voltage; (b) Phase-A current; (c) HB-and FB-arm total capacitor voltages by DEM; (d) HB-and FB-arm total capacitor voltages by the proposed AVM. 43 From 0.1 s to 0.2 s, the FB SMs operate in HB mode which results in increased SM voltages with reduced inrush current before the start of the controllable charging stage. At 0.2 s, the Vdc control is enabled to regulate the DC voltage to the rated value. It is observed from Figure 3.13 that the proposed AVM predicts accurate charging transient compared to the DEM. The charging process of the MB MMC is shown in Figure 3.14 in which the MB MMC experiences four charging stages as discussed in Section 3.2.3. The uncontrollable diode charging stage first starts from 0.05 s to 0.1 s. From 0.1 s to 0.128 s, FB SMs are bypassed while the HB SMs are charged until the HB SMs reach the same capacitor voltages as those of the FB SMs. The third charging stage starts from 0.128 s to 0.2 s when the FB SMs are operated as HB SMs so that the capacitor voltages of all the SMs are increasing equally until the start of the controllable charging stage at 0.2 s. The Vdc control is enabled at 0.2 s to regulate the DC voltage to the rated value. To better illustrate the charging process of the MB MMC, the HB- and FB-arm total capacitor voltages by the DEM and the proposed AVM are illustrated in Figure 3.14 (c) and (d). It is noted in Figure 3.14 (d) that the HB- and FB-arm total capacitor voltages are obtained from the controlled voltage sources 𝑉𝑎𝑟𝑚,𝑗 in the UBM and 𝑉𝑐𝑎𝑝 in the DC side of the proposed AVM in Figure 3.5, respectively. It is observed from Figure 3.14 that the proposed AVM predicts accurate charging transient compared to the DEM. e. DC-side Pole-to-pole Fault The DC-side pole-to-pole fault is simulated for the FB and MB MMCs using the proposed AVM and the DEM. To illustrate the improved modeling accuracy of the proposed AVM due to the use of the initial arm inductor currents, (𝐼𝑖𝑛𝑖𝑡 in Figure 3.5), two proposed AVMs with initial current (AVM-WI) and without initial current (AVM-WOI), i.e., 𝐼𝑖𝑛𝑖𝑡 = 0 , are implemented and compared with the DEM. Assuming the DC pole-to-pole fault occurs at 1 s and the MMCs are blocked at 1.0025 s, the DC-side currents of FB and MB MMCs predicted by the DEM, the AVM-WI, and the AVM-WOI are shown in Figure 3.15. It is observed in Figure 3.15 that the proposed AVM-WI produces accurate results compared to the DEM. The proposed AVM-WOI predicts less accurate DC current response due to the zero initial currents of the arm inductors in the UBM. 44 Figure 3.15 DC currents of DC pole-to-pole fault. (a) FB MMC; (b) MB MMC. 3.2.6 Experimental Verification of the Proposed AVM Although the DEM is generally accepted as a highly accurate representation of the MMCs and is used to get the reference solutions, the DEM and the proposed AVM are confirmed by the experimental results to illustrate the high fidelity of the MMC models to represent the actual scaled-down physical system. An MMC test bench (OP1210) from OPAL-RT Technologies, shown in Figure 3.16, is used in the experiment. There are 10 SMs in each converter arm, resulting in 60 SMs for the three-phase converter. The MMC requires 400 V at its DC link, which is supplied by 10 kW Chroma 62100H DC power supply. The AC terminals of the MMC test bench are connected to the 208V three-phase AC power grid. The parameters of the MMC test bench are listed in Appendix A. 45 Figure 3.16 Experimental MMC setup (the cabinet houses the MMC hardware). 46 Figure 3.17 Comparison of experimental and simulated waveforms. (a) Phase-A AC current; (b) Phase-A upper arm current; (c) one SM capacitor voltage; (d) Phase-A upper arm voltage. 47 The MMC test bench digital control platform is based on XILINX KINTEX7 FPGA in an OP4510, a real-time power electronic simulator, and a controller developed by OPAL-RT Technologies. A customized controller can be implemented using RT-XSG Blockset in MATLAB/Simulink, which compiles and loads the Simulink controller model into the KINTEX7 FPGA. The sampling rate of the SM capacitor voltage and arm current measurements is 20 𝜇𝑠. The 12-bit 500 ksps serial sampling ADCs are used for the SM voltage and converter arm current measurements. The MMC test bench initially operates in the steady-state sending real power of 1311 W from the DC power supply to the AC grid. At 2.1 s, the real power reference is stepped up to 2622 W, doubling the previous steady-state value. Figure 3.17 illustrates the converter phase-A currents, the phase-An upper arm currents, an SM capacitor voltage, and phase-A upper arm voltage measured by the hardware and simulated by the DEM and/or the proposed AVM. It is observed in Figure 3.17 that the DEM and the proposed AVM have predicted very accurate results compared to the hardware measurements. 3.2.7 Simulation Efficiency The simulation efficiency is compared for the proposed AVM, the MAVM-AIBM, the MAVM-HBM [24] as well as the DEM. A 1.2-s simulation study for the two-terminal MMC HVDC system is executed on a PC with 2.8 GHz Intel Core i5-7440HQ with 8 GB RAM under Microsoft Windows 10 operating system and the time step of 20 𝜇𝑠. The simulation times for various models are summarized in Table 3.1. It is seen in the Table that all the AVMs give comparable simulation efficiency and about ten times faster than the DEM. Table 3.1 Simulation Speeds of Different Models Model Simulation Time DEM of HB/FB/MB-MMC 164.9 seconds MAVM-AIBM of HB-MMC 14.4 seconds MAVM-HBM of HB-MMC 15.2 seconds Proposed AVM of HB/FB/MB-MMC 16.5 seconds 48 3.2.8 Modeling Accuracy of Converter Losses The converter loss modeling of the proposed AVM is verified using the HB MMC under inverter and rectifier modes with different power factors assuming constant apparent power of 1 GVA. The semiconductor data for the loss calculation are summarized in Appendix A. In Table 3.2, the average SM switching frequency is 150 Hz which is commonly used in the HVDC application. The DEM is used to obtain the arm instantaneous switching currents and voltages from which 𝑃𝑙𝑜𝑠𝑠,𝑅 , 𝑃𝑙𝑜𝑠𝑠,𝑉, and 𝑃𝑙𝑜𝑠𝑠,𝑆𝑊 are calculated as the reference. The analytical loss calculation method introduced in section 3.2.4 is implemented in the proposed AVM. The calculated converter losses are compared in Table 3.2 and Table 3.3. It is observed in Table 3.2 that the converter losses slightly reduce when the power factors decrease. This is due to the reduced real power transfer, given the constant apparent power in the operations. It is also observed in Table 3.2 that the analytical loss calculation method used in the proposed AVM produces accurate loss estimation compared to the EMT simulation-based (detailed waveform-based) loss calculation method. The maximum relative error of 9% by the analytical loss calculation method occurs for the switching loss estimation in the rectifier mode with the unity power factor. Table 3.3 compares the switching losses calculated by the DEM using detailed simulation and by the proposed AVM using the analytical method. It is shown in Table 3.3 that the increase of the SM average switching frequency from 150 Hz to 250 Hz will increase the switching losses linearly. The proposed analytical switching loss calculation method can provide an accurate estimation of the semiconductor switching losses for the average SM switching frequency of 150 Hz or higher. The semiconductor switching loss calculation methods [4], [5], [9], [56]–[59] of the MMCs or generic high-power converters have been an active research area. There are mainly two types of calculation methods available in the literature, i.e., detailed simulation-based methods [4], [5], [59] and analytical loss calculation methods [9], [56]–[58]. The detailed simulation-based methods use EMT-type simulation tools to produce the instantaneous semiconductor currents and voltages before and after switching transients. These voltage and currents are used to calculate the switching energies (i.e., IGBT turn-on or turn off, diode reverse recovery energies) per pulse based on the switching energies measured at the rated voltages and currents using double-pulse test and the piecewise linear characteristics of switching energies vs. switching currents and voltages [60]. 49 Table 3.2 Comparison of HB MMC Losses Calculated at Different power factors. Model DEM MAVMs Proposed AVM DEM MAVMs Proposed AVM cos(𝜑)= ±1 Operating Mode Inverter cos(𝜑) = 1 𝑖𝑑𝑐 = 1560𝐴 𝐼𝑎,𝑅𝑀𝑆 = 1762𝐴 𝑚 = 0.837 Rectifier cos(𝜑) = −1 𝑖𝑑𝑐 = 1560𝐴 𝐼𝑎,𝑅𝑀𝑆 = 1793𝐴 𝑚 = 0.821 𝑃𝑙𝑜𝑠𝑠,𝑅 1.71 MW 1.63 MW 1.63 MW 1.61 MW 1.68 MW 1.68 MW 𝑃𝑙𝑜𝑠𝑠,𝑉 2.26 MW N/A 2.42 MW 2.62 MW N/A 2.46 MW 𝑃𝑙𝑜𝑠𝑠,𝑆𝑊 2.61 MW N/A 2.40 MW 2.67 MW N/A 2.43 MW cos(𝜑)= ±0.9 Operating Mode Inverter cos(𝜑) = 0.9 𝑖𝑑𝑐 = 1430𝐴 𝐼𝑎,𝑅𝑀𝑆 = 1610𝐴 𝑚 = 0.930 Rectifier cos(𝜑) = −0.9 𝑖𝑑𝑐 = 1430𝐴 𝐼𝑎,𝑅𝑀𝑆 = 1630𝐴 𝑚 =0.920 𝑃𝑙𝑜𝑠𝑠,𝑅 1.41 MW 1.37 MW 1.37 MW 1.31 MW 1.39 MW 1.39 MW 𝑃𝑙𝑜𝑠𝑠,𝑉 2.06 MW N/A 2.22 MW 2.38 MW N/A 2.24 MW 𝑃𝑙𝑜𝑠𝑠,𝑆𝑊 2.27 MW N/A 2.19 MW 2.37 MW N/A 2.21 MW cos(𝜑)= ±0.8 Operating Mode Inverter cos(𝜑) = 0.8 𝑖𝑑𝑐 = 1270𝐴 𝐼𝑎,𝑅𝑀𝑆 = 1560𝐴 𝑚 = 0.959 Rectifier cos(𝜑) = −0.8 𝑖𝑑𝑐 = 1270𝐴 𝐼𝑎,𝑅𝑀𝑆 = 1580𝐴 𝑚 =0.947 𝑃𝑙𝑜𝑠𝑠,𝑅 1.28 MW 1.23 MW 1.23 MW 1.20 MW 1.25 MW 1.25 MW 𝑃𝑙𝑜𝑠𝑠,𝑉 1.98 MW N/A 2.12 MW 2.27 MW N/A 2.15 MW 𝑃𝑙𝑜𝑠𝑠,𝑆𝑊 2.22 MW N/A 2.10 MW 2.25 MW N/A 2.12 MW Table 3.3 Comparison of HB MMC Switching Losses. Converter Parameter Semiconductor Parameter Detailed Method Analytical Method Power Rating 1059 MVA Ron,IGBT Ron,diode 1.21 m  m 1.14 m DC-link Voltage 640 kV Vo,IGBT Vo,diode 1.82 V 2.27 V 2.05 V SM Capacitance 1 mF Eon,IGBT Eoff,IGBT 11 J 10.5 J 11 J 10.5J Arm Inductance 50 mH Erec,diode 2.8 J 2.8 J SM Voltage 16kV Vref 2.8kV 2.8kV NSM 40 Iref 1.8kA 1.8kA Alternatively, these switching currents and voltages can be used as the inputs to semiconductor switching models [4], [5], [57] to generate the filled-in switching waveforms [59] for the calculation of the instantaneous switching energies per switching instance. The semiconductor switching models are characterized using a double-pulse test (i.e., inductive switching loss test [5]). The accurate semiconductor loss modeling is often used for the converter cooling design (e.g. to predict IGBT junction temperature ripples). For power system studies, the datasheet values of the switching energies are used instead of the measured instantaneous switching energies [9], [56]–[58] to simplify the switching loss calculation. In the manuscript, the DEM calculates the switching losses based on the detailed SM switching currents and the SM DC-link voltages as well as the datasheet piecewise-linear switching characteristics of the switching energies vs. switching currents and voltages. 50 The analytical switching loss calculation methods are reported in [9], [56]–[58] for the MMCs, which is valid for carrier-based (level- or phase-shifted) modulation method or nearest level modulation. It is also applicable to MOSFETs and IGBTs, given their piecewise linear switching characteristics. According to [9], [56]–[58], the analytical switching loss calculation method provides accurate loss estimation (The relative error is within 10% [56]) given the following assumptions: (1) the SM capacitor voltages are all equal with the voltage ripples ignored; (2) the converter arm 2nd order harmonic current is suppressed so that only DC and fundamental frequency AC components are present in the arm currents; (3) the switching events are uniformly distributed over the fundamental frequency cycle; (4) the average switching frequency of all SMs is used and all SMs incur the same amount of average switching loss. In the research, it is verified that the analytical switching loss calculation method produces accurate estimation with the maximum relative error of 9% compared to those calculated using the detailed simulated-based method by the DEM. This research proposes an AVM for the MMCs with different types of SMs. The model uses the UBM to accurately represent the converter in blocking mode operations. The proposed UBM is based on diode-FB circuit structure and can be reconfigured to model the blocking states of the HB, FB, and MB MMCs. The semiconductor loss model, which can accurately calculate the conduction and switching losses, is included in the proposed AVM. The proposed AVM has a simple model structure and can be implemented in EMT-type simulators using standard library components. The configurations of the proposed AVM for converter energization and DC-side pole-to-pole fault are investigated. The proposed AVM is verified in the de-blocking and blocking mode studies of the two-terminal MMC HVDC system. The simulation results correspond with the detailed switching-based model. The proposed AVM provides good simulation efficiency, accuracy, and straightforward model implementation which are desirable for the EMT-type simulation of integrated AC and multi-terminal DC grids. 3.3 Unified Arm Module Based Average Value Model The previous AVMs use a decoupled AC-DC equivalent circuit in their model formulations to represent converter de-blocking operations. The AC and DC equivalent circuits accurately simulate the external behaviors of the MMC, seen from the converter AC- and DC sides. However, 51 decoupled AC-DC equivalent circuits cannot model the converter blocking operations, which necessitates the use of blocking modules and diode bridges to connect the AC and DC sides. The previous AVMs use equivalent circuits to model the de-blocking and blocking operations separately and to transition between the two modes, which increases modeling complexity. A new average value model (NAVM) is proposed to handle the MMC de-blocking and blocking operations with the original MMC AC-DC coupled circuit configuration. In addition, the MMCs with various SMs can be represented conveniently in the proposed NAVM using the so-called universal arm module (UAM). Figure 3.18 Proposed NAVM in de-blocking mode. (a) MMC equivalent circuit; (b) Virtual DC equivalent capacitor. 3.3.1 De-Blocking Mode Model with Virtual DC Equivalent Capacitor The proposed NAVM in de-blocking mode is illustrated in Figure 3.18, in which a virtual DC equivalent capacitor is introduced to represent the converter DC dynamics. 52 Using the converter arm currents, the AC and DC currents can be calculated as 𝑖𝑎𝑐𝑗 = 𝑖𝑢𝑗 − 𝑖𝑙𝑗 (3.45) 𝑖𝑑𝑐𝑗 = (𝑖𝑢𝑗 + 𝑖𝑙𝑗) /2 − 𝑖𝑧𝑗 (3.46) where 𝑖𝑢𝑗 and 𝑖𝑙𝑗 are the upper and lower arm currents in phase j, and 𝑖𝑧 is the circulating current. When the circulation current suppression control (CCSC) is implemented in the MMC, the circulating current is suppressed to zero, leading to zero 𝑖𝑧. The AC and DC components of the modulation signals of the converter arm voltages can be express as in (3.47) and (3.48). 𝑚𝑎𝑐𝑗 = (−𝑚𝑢𝑗 + 𝑚𝑙𝑗 )/2 (3.47) 𝑚𝑑𝑐𝑗 = (𝑚𝑢𝑗 + 𝑚𝑙𝑗)/2 (3.48) The virtual DC equivalent capacitor dynamic in Figure 3.18 (b) is modeled based on the AVM circuit presented in Figure 3.18 (b), which can be calculated based on the AC- and DC-equivalent current sources, 𝑖𝑐𝑡𝑟𝑙,𝑎𝑐 and 𝑖𝑐𝑡𝑟𝑙,𝑑𝑐 respectively. Using (3.45)-(3.48), the two controlled current source inputs in Figure 3.18 (b) are calculated as 𝑖𝑐𝑡𝑟𝑙,𝑎𝑐 = −12∑ 𝑚𝑎𝑐𝑗𝑖𝑎𝑐𝑗𝑗=𝑎,𝑏,𝑐 (3.49) 𝑖𝑐𝑡𝑟𝑙,𝑑𝑐 = ∑ 𝑚𝑑𝑐𝑗𝑖𝑑𝑐𝑗𝑗=𝑎,𝑏,𝑐 (3.50) It is noted that (3.50) equals to 𝑖𝑑𝑐 when the arm circuiting currents are suppressed. With the virtual DC capacitor voltage 𝑣𝐶𝑑𝑐, the controlled voltage source inputs in the six converter arms can be represented as 𝑣𝑢𝑗 = 𝑚𝑢𝑗𝑣𝐶𝑑𝑐2 (3.51) 𝑣𝑙𝑗 = 𝑚𝑙𝑗𝑣𝐶𝑑𝑐2 (3.52) where 𝑣𝑢𝑗 and 𝑣𝑙𝑗 are the upper and lower arm voltages in phase j. It is noted that (3.51) and (3.52) are similar to (3.10) and (3.11), but they are based on the DC equivalent capacitor voltage instead of the measured DC voltage. Moreover, such modeling approach includes the DC voltage dynamics in the AVM and avoids the decoupled AC-DC equivalent circuit used in the previous AVMs. 53 3.3.2 Blocking Mode Model In blocking mode, the proposed NAVM models the converter arm dynamics with the controlled voltage sources in each arm. The individual SM capacitor voltage equations are discretized to represent the dynamics of the SM capacitors. The calculation of the arm controlled voltage source inputs in the blocking mode is derived based on the SM types of the MMC as following. 3.3.2.1 HBSM-MMC Blocking Model For the HBSM-MMC, the individual SM capacitors are charged only in the positive direction of the arm current 𝑖𝐷1, as shown in Figure 3.19 (a). Otherwise, the SM capacitor is bypassed. Figure 3.19 (b) demonstrates that the SM output voltage is based on the SM capacitor voltage 𝑣𝐶𝑠𝑚𝑖 and the current direction. Similarly, the dynamics of the SM capacitors reply to the arm current directions. Figure 3.19 HBSM in blocking mode. (a) HBSM circuit diagram; (b) Equivalent circuit based on arm current directions. According to Figure 3.19 (a), the SM capacitor voltage can be discretized using a numerical integration rule, for example, the Forward Euler method, as 𝑣𝐶𝑠𝑚𝑖 (𝑡 + 𝛥𝑡) = 𝑣𝐶𝑠𝑚𝑖 (𝑡) +𝛥𝑡𝐶𝑠𝑚𝑖𝐷1(𝑡) (3.53) where 𝑣𝐶𝑠𝑚𝑖 is the individual SM capacitor voltage for ith SM in an arm; Δt is the simulation time step. It is shown in Figure 3.19 (b) that an SM is represented by the SM capacitor voltage in the positive current path and is shorted in the negative current direction. Therefore, the summation of the SM capacitor voltages in an arm produces the arm output voltages for positive and negative current paths as 54 𝑣𝑠𝑝 = ∑ 𝑣𝐶𝑠𝑚𝑖 (𝑡)𝑁𝑖=1 (3.54) 𝑣𝑠𝑛 = 0 (3.55) The DC equivalent capacitor voltage and individual SM capacitor voltages can be derived from each other to enable the transitions between the de-blocking and blocking mode modeling. From the de-blocking mode to the blocking mode transition, the ith SM capacitor voltages is derived as 𝑣𝐶𝑠𝑚𝑖 (𝑡) = 𝑣𝐶𝑑𝑐(𝑡)/𝑁 (3.56) For blocking mode to de-blocking mode transition, the arm and DC equivalent capacitor voltages are expressed as 𝑣𝐶𝑎𝑟𝑚(𝑡) = ∑ 𝑣𝐶𝑠𝑚𝑖 (𝑡)𝑁𝑖=1 (3.57) 𝑣𝐶𝑑𝑐(𝑡) =16∑ 𝑣𝐶𝑎𝑟𝑚𝑘 (𝑡)6𝑘=1 (3.58) where 𝑣𝐶𝑎𝑟𝑚𝑘 is the summation of the arm capacitor voltage in the kth arm. This modeling approach offers a smooth transition between the de-blocking and blocking modes and is also implemented for the MMCs with other SM types. 3.3.2.2 FBSM-MMC Blocking Model For the FBSM-MMC, the SM capacitor in the FBSM provides a voltage that opposes the arm current flowing in both positive and negative current directions, as shown in Figure 3.20 (a). Thus, the FBSM capacitor is charged for both arm current directions in blocking mode. Figure 3.20 FBSM in blocking mode. (a) FBSM circuit diagram; (b) Equivalent circuit based on arm current directions. 55 According to Figure 3.20 (a), the ith FBSM capacitor voltage is discretized as 𝑣𝐶𝑠𝑚𝑖 (𝑡 + 𝛥𝑡) = 𝑣𝐶𝑠𝑚𝑖 (𝑡) +𝛥𝑡𝐶𝑠𝑚(𝑖𝐷1(𝑡) + 𝑖𝐷2(𝑡)) (3.59) Summing up the FBSM voltages across the arm produces the total output voltages for the arm in the positive and negative arm current directions as 𝑣𝑠𝑝 = ∑ 𝑣𝐶𝑠𝑚𝑖 (𝑡)𝑁𝑖=1 (3.60) 𝑣𝑠𝑛 = − ∑ 𝑣𝐶𝑠𝑚𝑖 (𝑡)𝑁𝑖=1 (3.61) 3.3.2.3 CDSM-MMC Blocking Model The SM capacitors of the CDSM-MMC are charged differently along with the positive and negative arm current directions. When the arm current is positive, the two SM capacitors in a CDSM are connected in series. When the arm current is negative, the two SM capacitors are connected in parallel, as shown in Figure 3.21 (a). However, the dynamics of two capacitor voltages in each CDSM are identical during the transient, each CDSM capacitor voltage is calculated as 𝑣𝐶𝑠𝑚𝑖 (𝑡 + 𝛥𝑡) = 𝑣𝐶𝑠𝑚𝑖 (𝑡) +𝛥𝑡𝐶𝑠𝑚(𝑖𝐷1(𝑡) +𝑖𝐷2(𝑡)2) (3.62) Figure 3.21 (b) demonstrates the equivalent output voltages of a CDSM based on the current directions. By summing up the CDSMs’ output voltages in each arm, the arm output voltages in positive and negative arm current directions are expressed as 𝑣𝑠𝑝 = ∑ 2𝑣𝐶𝑠𝑚𝑖 (𝑡)𝑁𝑖=1 (3.63) 𝑣𝑠𝑛 = − ∑ 𝑣𝐶𝑠𝑚𝑖 (𝑡)𝑁𝑖=1 (3.64) where the factor 2 indicates that both of the two SM capacitors are inserted and -1 represents that the two SM capacitors in a CDSM are parallel-connected in the negative current path. 56 Figure 3.21 CDSM in blocking mode. (a) CDSM circuit diagram; (b) Equivalent circuit based on arm current directions. 3.3.2.4 MBSM-MMC Blocking Model The HB and FB SMs of the MBSM-MMC exhibit different blocking behaviors. When the MBSM-MMC is blocked, the capacitors in the FBSMs charged faster than those of the HBSMs. Therefore, the capacitor voltages of the FBSMs and the HBSMs in (3.53) and (3.59) can be used in the calculation of the arm voltages of the MBSM-MMC. Assuming there are k number of HBSMs, and 𝑁 − 𝑘 number of FBSMs, the arm output voltages in the positive and negative arm current directions are calculated as 𝑣𝑠𝑝 = ∑ 𝑣𝐶ℎ𝑏𝑠𝑚𝑖 (𝑡)𝑘𝑖=1+ ∑ 𝑣𝐶𝑓𝑏𝑠𝑚𝑖 (𝑡)𝑁𝑖=𝑘+1 (3.65) 𝑣𝑠𝑛 = − ∑ 𝑣𝐶𝑓𝑏𝑠𝑚𝑖 (𝑡)𝑁𝑖=𝑘+1 (3.66) where 𝑣𝐶ℎ𝑏𝑠𝑚𝑖 is the ith HBSM capacitor voltage and 𝑣𝐶𝑓𝑏𝑠𝑚𝑖 is the ith FBSM capacitor voltage. 3.3.3 Complete NAVM Formulation and its Equivalent Circuit The proposed NAVM uses the UAM to represent the MMCs with various SMs in one universal circuit structure. As shown in Figure 3.22, each UAM is composed of two anti-parallel diodes with their respective series-connected controlled voltage sources [21] to represent the arm output voltages in positive and negative arm current directions. 57 Figure 3.22 Proposed complete NAVM in de-blocking and blocking modes. (a) Circuit diagram; (b) Unified arm module with controlled voltage sources calculation block. In the UAM of Figure 3.22 (b), either D1 or D2 conducts at any time instant. By using the two anti-parallel diodes, the UAM can automatically identify the arm current directions and impose the corresponding arm voltage along the current paths. The arm current can be calculated based on the diodes D1 and D2 currents as 𝑖𝑎𝑟𝑚 = 𝑖𝐷1 − 𝑖𝐷2 (3.67) a b U MU MU MU MU MU M . . 0 . . . 0 . . . MBSM . . 0 . . . . . C et or 58 where 𝑖𝐷1 is the current flowing through the diode D1 in the positive arm current path; and 𝑖𝐷2is the current flowing through diode D2 in the negative arm current path. The controlled voltage source inputs are derived according to the calculation block shown in Figure 3.22 (b). In de-blocking mode, both the controlled voltage sources of the UAM, i.e., 𝑣𝑠𝑝 and 𝑣𝑠𝑛 , use identical input voltage signal. Using phase-A upper arm voltage as an example, the voltage source inputs can be calculated as 𝑣𝑠𝑝 = 𝑣𝑠𝑛 = 𝑣𝑢𝑎 = 𝑚𝑢𝑎𝑣𝐶𝑑𝑐2 (3.68) Using the virtual DC equivalent capacitor circuit in Figure 3.18 (b), the virtual DC equivalent capacitor voltage can be discretized as 𝑣𝐶𝑑𝑐(𝑡 + 𝛥𝑡) = 𝑣𝐶𝑑𝑐(𝑡) +𝛥𝑡𝐶𝑑𝑐(𝑖𝑐𝑡𝑟𝑙,𝑎𝑐(𝑡) + 𝑖𝑐𝑡𝑟𝑙,𝑑𝑐(𝑡)) (3.69) It is noted that the virtual DC equivalent capacitor can be implemented in the form of the discretized equation (3.69) instead of the actual DC equivalent capacitor circuit in the NAVM. Different from the previous AVMs, the proposed NAVM has a unified circuit structure and avoid the extensive use of ideal switches, which simplifies its model implementation in various online and off-line EMT-type simulators. 3.3.4 Simulation Studies The proposed new average value modeling method is evaluated using a two-terminal MMC HVDC system from the CIGRE B4-57 MMC-HVDC Grid test system [61], as shown in Figure 3.23. Each MMC station includes 300 SMs (50 SMs per arm) and is regulated using higher- and lower-level controls. The higher-level controls include inner-loop current controls and outer-loop P-Q or Vdc-Q controls. It is noted that MMC-1 is under Vdc-Q control while MMC-2 is under P-Q control. 59 Figure 3.23 CIGRE two-terminal MMC HVDC system. The lower-level controllers include CCSC [51], nearest level control (NLC), and voltage-balancing control (VBC) [62]. The detailed parameters of the two-terminal MMC HVDC system can be found in [61]. The lower-level controls are implemented in the DEM to generate reference solutions while they are not required for the AVMs due to the assumption of balanced/equal SM capacitor voltages and no switching representation required in the AVMs. The proposed NAVM is validated against the state-of-the-art AVMs and the DEM under different operating scenarios. Due to the space limitation, only the waveforms from MMC-1 are presented in this section. 3.3.4.1 HBSM-MMC Energizing This subsection presents the AC-side energizing transients of the HBSM-MMC predicted by different AVMs. The MMC is initially blocked and isolated from the DC side. The SM capacitors are charged from the AC-side grid via the free-wheeling diodes of the SMs until the summation of the SM capacitor voltages in each arm reaches to the AC-side line-to-line voltage. 100Ω charging resistor is pre-inserted in the AC side to avoid inrush current. The charging resistor is bypassed when the IGBTs of the converter are de-blocked at 0.2s for Vdc control. The active DC voltage regulation continues until the DC voltage reaches its rated value. Figure 3.24 demonstrates the MMC energizing transients predicted using different modeling methods. The proposed NAVM uses equivalent arm capacitors in blocking mode and then the DC-side equivalent capacitor in de-blocking mode. As observed in Figure 3.24 (a), the proposed NAVM produces identical results to the DEM in blocking mode. The converter energizing behavior is accurately modeled by the NAVM using the discretized equivalent arm capacitor equations and the UAMs. Minor inaccuracy observed in the waveforms of other AVMs since the energizing process simulated with the six-pulse diode model approximation. It is also noted that the MAVM-HBM has a relatively complicated charging procedure. The switches S in the MAVM-HBM of Figure 3.4 are opened in blocking mode. Thus, the DC-side equivalent capacitor 𝐶𝑑𝑐 is 60 connected only at Phase-C, as shown in Figure 3.4. The charging currents in Phases-A and -B flow through two arm impedances in Figure 3.4 to reach to the DC-side equivalent capacitor 𝐶𝑑𝑐 , which produces slightly inaccurate charging transients as shown in the zoomed-in portion of Figure 3.24 (a). When the converter is de-blocked at 0.2s, the simulation results produced by the proposed NAVM are very similar to the other AVMs since all the AVMs use DC-side equivalent capacitor equivalent capacitor 𝐶𝑑𝑐 in de-blocking mode. A small difference can be observed in Figure 3.24 between the DEM and the AVMs after 0.2s since the DEM implements the lower level controls such as the VBC and the CCSC. The small difference disappears soon after the converter enters a steady state. Figure 3.24 HBSM-MMC energizing. (a) DC voltage; (b) Phase-A current. 61 3.3.4.2 HBSM-MMC Active Power Transfer In this subsection, the active power transfer operation is used to verify the proposed NAVM. Assuming the active power reference of MMC-2 increases from 0 to −400MW at 1s. Figure 3.25 illustrates the simulated DC currents, active powers, and converter arm currents by various models. As shown in Figure 3.25 (a) and (b), different modeling methods have produced almost identical transient responses of the DC currents and active powers. The converter arm currents produced by the proposed NAVM and the DEM are compared in Figure 3.25 (c). Figure 3.25 HBSM-MMC active power transfer. (a) DC current; (b) Active power injected into AC-side; (c) Phase-A upper arm current. 62 It is observed in Figure 3.25 (c) that the proposed NAVM predicts almost identical transient response of the arm current to that of the DEM, due to the use of the coupled AC-DC circuit and the virtual DC equivalent capacitor representation. For the IAVM, MAVM-AIBM, and MAVM-HBM, the arm currents are not simulated since the arm equivalent circuits are not represented in their decoupled AC-DC equivalent circuits. Therefore, the arm currents predicted by the IAVM, MAVM-AIBM, and MAVM-HBM are not included in Figure 3.25 (c). 3.3.4.3 HBSM-MMC DC Pole-to-pole Fault This subsection validates the proposed NAVM under DC-side pole-to-pole fault scenario for the HBSM-MMC. A DC pole-to-pole fault is applied in the middle of the DC cable at 2s. The IGBTs of the SMs are blocked in 4ms after the DC fault occurs. The AC breaker trips off the AC grid at 2.055s. The DC fault transients predicted by various models are shown in Figure 3.26. It is observed in Figure 3.26 that, for the HBSM-MMC, the DC fault current rises quickly from 2s due to the discharging of SM capacitors. After the converter is blocked, the short-circuit currents are contributed from AC grid through the freewheeling diodes of the HBSMs. After the AC-grid is disconnected by the AC circuit breaker, the DC fault current gradually decreases through the resistance of the MMCs and the DC cables. As observed in Figure 3.26 (a) and (b), the simulated DC and AC currents using the AVMs are very similar to the reference waveform produced by the DEM. The simulated DC currents and arm currents using the IAVM and the MAVM-AIBM show some numerical oscillations at the converter blocking instant in the zoomed-in figures of Figure 3.26 (a) and (c) while the MAVM-HBM and NAVM are free of numerical oscillations. The numerical oscillations of the IAVM and the MAVM-AIBM are due to the fact that the arm inductances 𝐿𝑎𝑟𝑚 in Figure 3.2 and Figure 3.3 are not initialized by the DC fault current at the moment of converter blocking. The MAVM-HBM, on the other hand, avoids the numerical oscillations of the DC current since the arm inductances 𝐿𝑎𝑟𝑚 in Figure 3.4 are inserted in the DC fault current path before and after the converter blocking moment. However, the MAVM-HBM has a more complicated circuit structure compared to the NAVM. In addition, the MAVM-HBM and the other state-of-the-art AVMs cannot produce the accurate arm current before the converter blocking, as shown in Figure 3.27 (c). The proposed 63 NAVM can produce accurate DC and arm currents due to the proposed UAM structure in Figure 3.19. Figure 3.26 HBSM-MMC DC fault blocking. (a) DC current; (b) Phase-A current; (c) Phase-A upper arm current. 3.3.4.4 FBSM- and CDSM-MMC DC Pole-to-pole Faults The state-of-the-art AVMs of the MMC are designed for the HBSM-MMC only and thus cannot be applied to the FBSM- and CDSM-MMCs. In this subsection, the proposed NAVM is validated for the FBSM- and CDSM-MMCs in the DC pole-to-pole fault scenario. Figure 3.27 and Figure 64 3.28 demonstrate the converter DC pole-to-pole fault responses for FBSM- and CDSM-MMCs, respectively. It is assumed that the IGBTs of the SMs are blocked in 4ms after the DC fault occurs at 2s. For the FBSM-MMC, the SM capacitors are always charged in converter blocking mode regardless of the directions of the arm currents, resulting in counter-reacting voltages to the AC-grid to suppress the DC fault current. Similar to the FBSM-MMC, the CDSM-MMC also has DC fault blocking capability. The CDSM capacitors can be connected in series or parallel connections, depending on the directions of the arm currents. After the CDSM-MMC is blocked, the fault currents in the converter arms flow through the diodes of the CDSMs, leading to reverse voltages to the AC-grid to suppress the DC fault current. As shown in Figure 3.27 and Figure 3.28, the proposed NAVM produces accurate simulation results, compared to those of the DEM. These DC pole-to-pole fault studies verify the proposed UAM circuit in Figure 3.19 for the de-blocking and blocking mode operations of the FBSM- and CDSM-MMCs. The equivalent voltage sources 𝑣𝑠𝑝 and 𝑣𝑠𝑛 in Figure 3.19 ensure accurate arm voltage representations in de-blocking and blocking modes. It is noted that some minor differences in the waveforms can be observed in the zoomed-in portions of Figure 3.27 and Figure 3.28. These small differences are due to the assumption that the SM capacitor voltages are perfectly balanced and the six-arm voltages are identical at the blocking instant in the NAVM. 65 Figure 3.27 FBSM-MMC DC fault blocking. (a) Phase-A upper arm current; (b) DC current; (c) Phase-A current. 66 Figure 3.28 CDSM-MMC DC fault blocking. (a) Phase-A upper arm current; (b) DC current; (c) Phase-A current. 3.3.4.5 MBSM-MMC Energizing and DC Pole-to-pole Fault The development of an AVM for the MBSM-MMC is more challenging than the HBSM- or FBSM-MMC in representing the converter blocking mode operations. The capacitors of the HBSMs and the FBSMs are charged differently in blocking mode, depending on the arm current directions as given in (3.65) and (3.66). This section validates the proposed NAVM for the MBSM-MMC using AC energizing and DC pole-to-pole fault studies. It is assumed that the MBSM-MMC 67 has 50% of the HBSMs and 50% of the FBSMs in one converter arm. In addition, soft-charging controllers [54], [63] are used to reduce the inrush AC currents and to facilitate the voltage balancing between the HBSMs and the FBSMs. Figure 3.29 MBSM-MMC energizing. (a) DC voltage; (b) Phase-A AC current. The MBSM-MMC is energized from the AC grid with zero initial SM capacitor voltages. The converter is blocked at the beginning of the energizing process. The HBSMs and FBSMs exhibit different charging responses based on their SM topologies. The capacitor voltages of the FBSMs are charged higher than those of the HBSMs. In addition, the output voltages of the FBSMs in the upper and lower arms are equal but have reverse polarities, leading to a relatively low DC voltage from 0 to 0.1s, as shown in Figure 3.29 (a). At 0.1s, the FBSMs are bypassed from the converter arms. The capacitors of the HBSMs are charged up from the AC grid until they reach to the same voltage level as the FBSMs. Thereafter, the FBSMs are inserted back to the converter arms in the form of HBSMs until the SM capacitor voltages in each arm reach to the AC-side line-to-line voltage at 0.2s. Then, the converter is de-blocked, which allows the converter Vdc controller to 68 gradually regulate the DC voltage to the referenced value. As shown in Figure 3.29, the proposed NAVM has produced accurate energizing responses compared to the reference solutions by the DEM. The detailed transient response of the DC voltage, when the FBSMs are bypassed at 0.12s, are accurately captured, as shown in the zoomed-in portion of Figure 3.29 (a). Small differences in the waveforms in Figure 3.29 can be observed at 0.2s at the beginning of the de-blocking operation, which is due to the use of the equivalent DC capacitor 𝐶𝑑𝑐 of the NAVM in Figure 3.22 (b) to represent the arm capacitor dynamics. Figure 3.30 MBSM-MMC DC fault blocking. (a) Phase-A upper arm current; (b) DC current; (c) Phase-A current. 69 A DC pole-to-pole fault is used to validate the effectiveness of the proposed NAVM for the MBSM-MMC. It is noted that the FBSMs of the MBSM-MMC can suppress the DC fault current when the converter is blocked since the FBSMs are used in the MBSM-MMC. The predicted arm, DC, and AC currents are shown in Figure 3.30. It is observed in Figure 3.30 that the predicted responses by the NAVM match well the reference solutions obtained by the DEM before and after the DC pole-to-pole fault. 3.3.5 Simulation Speed Performance This subsection evaluates the simulation speed performance of the proposed NAVM, the DEM, and the state-of-the-art AVMs using a one-terminal MMC system and the full CIGRE B4-57 MMC-HVDC grid [61]. The one-terminal system can provide precise simulation efficiency comparison of various converter models since passive components such as transmission lines and cables are not involved in the simulation. The full CIGRE B4-57 MMC-HVDC grid case study verifies the advantage of the AVMs over the DEM for a large-scale AC-DC grid. The full CIGRE B4-57 MMC-HVDC grid is composed of 6 monopole MMC stations and 5 bipole MMC stations. The schematic diagram of the MMC-HVDC grid is shown in Appendix B. The test is implemented in Matlab/Simulink 2014b and OPAL-RT ARTEMIS v7.3.6 using 50 μ time step. The simulation study is performed using 2.8 GHz Intel Core i5-7440HQ CPU and 8 GB RAM under Windows 10 operating system. Table 3.4 and Table 3.5 list the execution times for 1 s simulation of the one-terminal system and the full 11-terminal CIGRE MMC-HVDC grid. Table 3.4 Execution Times of the Proposed NAVM vs. DEM and Other AVMS for One-Terminal System Number of SMs per Arm Execution Time (s) DEM NAVM IAVM AIBM HBM 10 13.51 8.10 8.95 7.30 7.50 50 18.04 8.08 7.96 8.18 7.49 100 21.79 7.80 7.66 7.46 7.47 200 36.29 8.20 7.84 7.37 7.60 70 Table 3.5 Execution Times of the Proposed NAVM vs. DEM and Other AVMS for CIGRE MMC-HVDC Grid Number of SMs per Arm Execution Time (s) DEM NAVM IAVM AIBM HBM 10 174.9 112.9 111.8 108.9 107.1 50 181.7 111.2 110.4 105.9 106.7 100 238.4 114.7 112.2 106.6 106.9 200 373.0 112.9 113.3 106.3 111.5 It is observed in Table 3.4 and Table 3.5 that the DEM requires the largest execution times compared to the AVMs. This is mainly because the individual SM capacitor voltages have to be solved at each time step. The lower-level controllers, such as the VBC and the SM capacitor voltage sorting algorithm, also increase the computational burden of the DEM. This point is verified by the fact that the execution times of the DEM increase with the numbers of SMs in the converter, as shown in Table 3.4 and Table 3.5. On the other hand, it is observed in Table 3.4 and Table 3.5 that the execution times of the AVMs are all similar. The NAVM and the IAVM require slightly more execution times than the MAVM-AIBM and -HBM due to the arm equivalent circuits used in the two models. However, the speed-up of the execution times offered by the AVMs over the DEM is significant for the case of 200 SMs per arm, which is typical in practical MMC HVDC applications. It is also noted that the execution times for the AVMs do not increase with the numbers of SM which is very desirable for the MMCs with a large number of SMs. 71 4 Switching-function-based Average Value Model of MMC This section presents the detailed equivalent model and the switching function based-average value model of MMC. The controlled-signal-based average value model introduced in Section 3 can represent the external behavior of MMC using the most essential circuit structure, but also lose the detailed insight of the converter (e.g. arm behavior, SM capacitor dynamic, and circulating current, etc.). The model presented in this section is intended to improve the simulation efficiency of the fully detailed model while preserving internal dynamics of the converter in the simulation. First, the previously proposed DEM and SFB-AVM are discussed. Both approaches have demonstrated the improved simulation efficiency of MMC with different degrees of details in representing individual SM capacitor dynamics. Later on, the GDEM and GSFB-AVM 4 are proposed to represent a more generalized modeling of MMC that includes switching and conduction losses, and universal representation of MMCs with different submodule types. The proposed circuit structure also enables a combination framework, where the model can switch from AVM-mode to DEM-mode during the dynamic simulation. The switching feature is highlighted to further compensate for the limitations of a single-type model. 4.1 Detailed Equivalent Model The detailed equivalent model (DEM) provides an alternative solution in simulating the behaviour of MMC, as it can reduce the number of electrical nodes in a converter arm. In [16], each SM capacitor is discretized using the implicit Trapezoidal rule and represented by a time-variant resistor connected in series with a controlled voltage source as shown in Figure 4.1 (a). When the IGBT is on, it is represented by resistance with small value. When the IGBT is off, it is represented by resistance with a large value. With resistance representation of the IGBTs and discretized capacitor voltage equations, each submodule can be represented by a Thevenin equivalent circuit. Summing up the resistances and Thevenin equivalent voltages in an arm results in a uniform representation of the arm with an equivalent resistance 𝑟𝐸𝑄 and equivalent Thevenin voltage 𝑣𝐸𝑄. The number of electrical nodes are reduced thus improves the simulation speed. However, the blocking stage operation is not addressed. The reference [22] later improves the model by 4 Xuekun Meng, Jintao Han, Joel Pfannschmidt, Liwei Wang, Wei Li, Fei Zhang, and Jean Belanger, "Combining Detailed Equivalent Model with Switching-Function-Based Average Value Model for Fast and Accurate Simulation of MMCs", published in IEEE Transactions on Energy Conversion, vol. 35, no. 1, Mar. 2020. 72 including blocking state representation. The free-wheeling diodes can be represented by the time-variant resistances but would require complicated iterative calculations on the arm current zero-crossing point to identify the direction of the current path. Figure 4.1 DEM arm equivalent circuits. (a) time-variant resistance circuit; (b) switch-diode circuit; (c) unified circuit. Later on, the DEM based on the explicit integration method is proposed in [27]. This approach utilized a direct relation between the switching status and the SM output voltage (e.g. if SM is in inserting mode, 𝑣𝑆𝑀𝑖 = 𝑣𝑐; if SM is in bypassing mode, 𝑣𝑆𝑀𝑖 = 0). The capacitance voltages are explicitly calculated using an explicit numerical integration approach, and the arms dynamic is represented by a controlled voltage source. The source inputs are assigned with the summation of the SM output voltages 𝑣𝑆𝑀∑. As shown in Figure 4.1 (b), the de-blocking and blocking mode is established by the dblk/blk command on the ideal switch. The switch is closed during normal operation, and it is opened to direct only the positive arm current flow through the voltage source during blocking mode operation. When the gate pulses are blocked, the source input is modified to be the summation of the capacitance-voltage. The circuit configuration is ideal for HBSM where other submodule topologies cannot be represented. 73 The DEM proposed in [21] further extends the concept of an explicit integration approach by utilizing a unified circuit structure in representing the arm behavior of the MMC under both blocking and de-blocking modes. As shown in Figure 4.1 (c), the diodes can precisely identify the direction of the arm current. The switching between operation modes can be easily achieved by modifying the source inputs 𝑣𝑠𝑝∑ and 𝑣𝑠𝑛∑. During de-blocking mode, the source are given with the same input based on the summation of the submodule output voltages. For blocking mode, the source inputs are based on the SM capacitor voltages seen in different current paths (e.g. for FBSM in positive arm current, 𝑣𝑠𝑝𝑖 = 𝑣𝑐𝑖 ; for FBSM in negative arm current, 𝑣𝑠𝑛𝑖 = −𝑣𝑐𝑖). The model is capable of modelling the MMC with different submodule types. This unified circuit structure will be adapted and continuously developed toward our proposed models. In general, the DEMs have provided an improvement in the simulation speed compared to DM while maintaining a high level of accuracy. However, the computational requirement increases as the number of SMs increased making it inefficient when simulating MMC with a large number of SMs. 4.2 Switching-function-based Average Value Model Switching-Function-Based Average Value Models (SFB-AVMs) consider the arm equivalent capacitance 𝐶𝑆𝑀𝑎𝑣𝑔 with the concept of switching function index 𝑠𝑛 (e.g. the number of the submodule to be inserted in an arm at each time instant). Assuming the SM capacitor voltages are perfectly balanced, the dynamics of an arm during de-blocking operation can be represented by a controlled voltage source with the input of 𝑣𝐶𝑎𝑣𝑔𝑠𝑛. The AVMs proposed in [20], [22], [26] have demonstrated a similar approach to derive the arm equivalent voltage but with different circuit structures. Moreover, this circuit structure has played a significant role in ensuring the accurate representation of arm behavior. The model proposed in [22] utilized a mode-based switching circuit structure, as shown in Figure 4.2 (a). For on-state operation, the arm is represented by a Thevenin/Norton equivalent circuit. The arm equivalent capacitance-voltage 𝑣𝐶𝑎𝑣𝑔 is first calculated based on the current 𝑖𝑎𝑟𝑚𝑠𝑛 that flows into the arm equivalent capacitance and is later used to calculate the equivalent arm voltage 𝑣𝐶𝑎𝑣𝑔𝑠𝑛. For blocking mode operation, the lower circuit is inserted to represent the free-wheeling diode 74 phenomenon. However, the switching between the circuits is relatively complicated for the implementation in conventional toolboxes. Figure 4.2 SFB-AVM arm equivalent circuits. (a) mode-based switching circuit; (b) two-state controlled voltage source circuit. The model presented in [20] has a similar structure to [27], as shown in Figure 4.2 (b) except that the source input is calculated based on the switching function and arm equivalent capacitance approach. Different than a component representation of the arm equivalent capacitance in [22], the arm equivalent capacitance voltage is derived based on the numerical integration approach. The switching between modes can be easily achieved by changing the source input and opening/closing the ideal switch. Instead of establishing the blocking/de-blocking state using ideal switches, the reference [26] has presented a straightforward two-state controlled voltage source circuit structure as shown in Figure 4.2 (b). It uses two controlled voltage sources; One is used to represents the arm voltage during the de-blocking operation, the other one is used to represents the arm equivalent capacitance-voltage during the blocking mode. Only one source will be given an input while the other source is shorted which enables a smooth transition between blocking and de-blocking modes without the use of switches. 75 The abovementioned SFB-AVMs have provided a feasible solution in simplifying the computational burden. However, the developed models are focusing on representing the MMC with the HB SM only, and they are not suitable for MMC with other SM topologies. 4.3 Generalized Detailed Equivalent Model The MMC circuit topology is shown in Figure 2.1, which is redrawn in Figure 4.3. One converter arm or a half phase consists of N number of SMs connected in series. An SM is a two-terminal power electronic building block including storage capacitors and semiconductor switches. Figure 4.3 b − d sho s the typical SM configurations of HB, FB and CD SMs. An HBSM and an FBSM can be used simultaneously in one converter arm, known as an MBSM for the advantages of DC pole-to-pole fault blocking and reduced semiconductor losses. The output voltage of each SM depends on the semiconductor conduction states. By controlling the IGBT gating signals, an SM can operate in inserted, bypassed, or blocked mode. Figure 4.3 MMC configuration. (a) circuit diagram; (b) HBSM; (c) FBSM; (d) CDSM. 76 The on-state characteristics of the semiconductor switches (i.e., IGBTs and anti-parallel diodes) can be modeled by piece-wise linear functions [60], [64] using saturation voltages (𝑉𝑇, 𝑉𝐷) and on-state resistances (𝑅𝑇, 𝑅𝐷). Without loss of generality, an HBSM is used to illustrate the SM output voltage as shown in Figure 4.4. The SM output voltage, including the SM capacitor voltage 𝑣𝑐 and semiconductor on-state voltage drop, can be determined based on the direction of the arm current and SM operating mode as illustrated in Figure 4.4. The SM output voltage in the inserted mode is shown in Figure 4.4 (a). In this case, the upper-leg diode d1 in Figure 4.3 (b) conducts the positive arm current, whereas the upper-leg IGBT t1 in Figure 4.3 (b) conducts the negative arm current. Figure 4.4 (b) and (c) show the SM output voltages when the SM is in bypassed and blocked modes. The analysis is similar to Figure 4.4 (a) for the inserted mode and is not discussed in detail due to space limitation. Figure 4.4 HBSM output voltages based on arm current directions and SM operation modes. (a) Inserted; (b) Bypassed; (c) Blocked. An MMC arm output voltage can be derived based on the summation of the SM output voltages as 𝑣𝑎𝑟𝑚 = ∑ 𝑣𝑆𝑀𝑖𝑁𝑖=1 (4.1) where 𝑖 indicates the SM index; N is the total number of SMs in an arm; 𝑣𝑆𝑀𝑖 is the SM output voltage. An MMC arm can be modeled by a unified arm module (UAM) [21] consisting of a pair of anti-parallel diodes and two controlled voltage sources as shown in Figure 4.5. The use of the anti-parallel diodes can automatically identify the arm current directions so that the arm output 77 voltage 𝑣𝑎𝑟𝑚 can be represented using the corresponding diode currents 𝑖𝐷1 and 𝑖𝐷2 . The arm voltage is modeled by one of the two controlled voltage sources (𝑣𝑠𝑝, 𝑣𝑠𝑛) based on the positive or negative arm current. The calculations of 𝑣𝑠𝑝 and 𝑣𝑠𝑛 are performed using the SM insertion indices, the SM capacitor voltages, and the arm current. Figure 4.5 One MMC arm. (a) cascaded SMs; (b) UAM. The differential equation of an SM capacitor can be discretized using a numerical integration method. In this research work, the explicit integration method (i.e., the Forward Euler method) is applied. The SM capacitor voltage is calculated in the discrete-time domain as 𝑣𝑐𝑖 (𝑡 + Δ𝑡) = 𝑣𝑐𝑖 (𝑡) + Δ𝑡(𝑖𝐷1(𝑡) − 𝑖𝐷2(𝑡))𝑠𝑖𝐶𝑆𝑀𝑖 (4.2) where 𝑠𝑖 is the switching index (i.e., 0 or 1) of the ith SM; 𝐶𝑆𝑀𝑖 is the SM capacitance; 𝑣𝑐𝑖 (𝑡) is the SM capacitor historical voltage; Δ𝑡 is the simulation time step. In converter de-blocking mode, based on Figure 4.4 (a) and (b), the voltage sources 𝑣𝑠𝑝 and 𝑣𝑠𝑛 can be calculated as 𝑣𝑠𝑝 = ∑ (𝑠𝑖(𝑣𝑐𝑖(𝑡 + Δ𝑡)) + 𝑠𝑖(𝑉𝐷 + 𝑖𝐷1(𝑡)𝑅𝐷) + ?̅?𝑖(𝑉𝑇 + 𝑖𝐷1(𝑡)𝑅𝑇))𝑁𝑖=1 (4.3) 𝑣𝑠𝑛 = ∑ (𝑠𝑖 (𝑣𝑐𝑖 (𝑡 + Δ𝑡)) + 𝑠𝑖(−𝑉𝑇 − 𝑖𝐷2(𝑡)𝑅𝑇)𝑁𝑖=1+ ?̅?𝑖(−𝑉𝐷 − 𝑖𝐷2(𝑡)𝑅𝐷)) (4.4) 78 where ?̅?𝑖 is the negation of the switching index 𝑠𝑖. The instantaneous conduction losses due to the on-state resistances, 𝑝𝑙𝑜𝑠𝑠,𝑟 , and the saturation voltages, 𝑝𝑙𝑜𝑠𝑠,𝑣, of the IGBTs and the diodes can be calculated as 𝑝𝑙𝑜𝑠𝑠,𝑟 = ∑ 𝑠𝑖(𝑖𝐷12 𝑅𝐷 + 𝑖𝐷22 𝑅𝑇) + ?̅?𝑖(𝑖𝐷12 𝑅𝑇 + 𝑖𝐷22 𝑅𝐷)𝑁𝑖=1 (4.5) 𝑝𝑙𝑜𝑠𝑠,𝑣 = ∑ 𝑠𝑖(𝑖𝐷1𝑉𝐷 + 𝑖𝐷2𝑉𝑇) + ?̅?𝑖(𝑖𝐷1𝑉𝑇 + 𝑖𝐷2𝑉𝐷)𝑁𝑖=1 (4.6) In converter blocking mode, all the IGBTs are blocked. The SM capacitors in the HBSMs are inserted through the free-wheeling diodes when the arm current is positive as shown in Figure 4.4 (c). The SM capacitor voltage under blocking mode is calculated as 𝑣𝑐𝑖 (𝑡 + Δ𝑡) = 𝑣𝑐𝑖(𝑡) + Δ𝑡𝑖𝐷1(𝑡)1𝐶𝑆𝑀𝑖 (4.7) The voltage sources 𝑣𝑠𝑝 and 𝑣𝑠𝑛 are expressed as 𝑣𝑠𝑝 = ∑(𝑣𝑐𝑖(𝑡 + Δ𝑡) + 𝑉𝐷 + 𝑖𝐷1(𝑡)𝑅𝐷)𝑁𝑖=1 (4.8) 𝑣𝑠𝑛 = ∑(−𝑉𝐷 − 𝑖𝐷2(𝑡)𝑅𝐷)𝑁𝑖=1 (4.9) The UAM in Figure 4.5 can be used to represent the MMCs with other SM types such as FB, CD SMs which leads to the generalized DEM. The derivation of the voltage sources 𝑣𝑠𝑝 and 𝑣𝑠𝑛 for the MMCs with other SM types are very similar to that of the HBSM-MMC and are not included in this section. 4.4 Generalized Switching-function-based Average Value Model The proposed GSFB-AVM represents the dynamic behaviors of the MMCs using arm equivalent capacitors. Assuming the SM capacitances in each arm are identical, the arm equivalent capacitance can be represented as 𝐶𝑎𝑟𝑚𝑒𝑞=1∑1𝐶𝑆𝑀𝑁𝑖=1=𝐶𝑆𝑀𝑁 (4.10) 79 where 𝐶𝑆𝑀 is the SM capacitance. The switching function or insertion index of a converter arm can be represented by the number of SMs inserted over the total number of SMs in the arm, i.e., 𝑁, as 𝑠𝑛 =1𝑁∑ 𝑠𝑖𝑁𝑖=1 (4.11) The proposed GSFB-AVM is derived in this section based on the UAM circuit proposed in Figure 4.5 (b). It will be shown in the section that the proposed GSFB-AVM can represent the MMCs with different SM types. 4.4.1 GSFB-AVM for HBSM-MMC The proposed GSFB-AVM is derived for the HBSM-MMC in this subsection. Assuming the SM capacitor voltages are balanced (or equal), the summation of the SM capacitor voltages in (4.2) can be expressed as 𝑣𝑐𝑎𝑣𝑔(𝑡 + Δ𝑡) = 𝑣𝑐𝑎𝑣𝑔(𝑡) + Δ𝑡(𝑖𝐷1(𝑡) − 𝑖𝐷2(𝑡)) ∑ (𝑠𝑖𝐶𝑆𝑀)𝑁𝑖=1 (4.12) By substituting the arm equivalent capacitance and switching function index, i.e., (4.10) and (4.11), into (4.12), the average summation capacitor voltage can be expressed as 𝑣𝑐𝑎𝑣𝑔(𝑡 + Δ𝑡) = 𝑣𝑐𝑎𝑣𝑔(𝑡) + Δ𝑡(𝑖𝐷1(𝑡) − 𝑖𝐷2(𝑡))𝑠𝑛𝐶𝑎𝑟𝑚𝑒𝑞 (4.13) The voltage sources in the UAM can also be derived as 𝑣𝑠𝑝𝑎𝑣𝑔= 𝑠𝑛(𝑣𝑐𝑎𝑣𝑔(𝑡 + Δ𝑡)) + 𝑁𝑠𝑛(𝑉𝐷 + 𝑖𝐷1(𝑡)𝑅𝐷) + 𝑁(1 − 𝑠𝑛)(𝑉𝑇+ 𝑖𝐷1(𝑡)𝑅𝑇) (4.14) 𝑣𝑠𝑛𝑎𝑣𝑔= 𝑠𝑛(𝑣𝑐𝑎𝑣𝑔(𝑡 + Δ𝑡)) + 𝑁𝑠𝑛(−𝑉𝑇 − 𝑖𝐷2(𝑡)𝑅𝑇) + 𝑁(1 − 𝑠𝑛)(−𝑉𝐷− 𝑖𝐷2(𝑡)𝑅𝐷) (4.15) It is noted that only a portion of 𝑣𝑐𝑎𝑣𝑔 appears in the voltage sources (4.14) and (4.15) based on the arm insertion index 𝑠𝑛. The instantaneous conduction losses can be derived as 𝑝𝑙𝑜𝑠𝑠,𝑟𝐴𝑉𝑀 = 𝑁𝑠𝑛(𝑖𝐷12 𝑅𝐷 + 𝑖𝐷22 𝑅𝑇) + 𝑁(1 − 𝑠𝑛)(𝑖𝐷12 𝑅𝑇 + 𝑖𝐷22 𝑅𝐷) (4.16) 𝑝𝑙𝑜𝑠𝑠,𝑣𝐴𝑉𝑀 = 𝑁𝑠𝑛(𝑖𝐷1𝑉𝐷 + 𝑖𝐷2𝑉𝑇) + 𝑁(1 − 𝑠𝑛)(𝑖𝐷1𝑉𝑇 + 𝑖𝐷2𝑉𝐷) (4.17) 80 In converter blocking mode, the switching function 𝑠𝑛 is not applicable for (4.13)−(4.15). In this case, the dynamics of the arm equivalent capacitors depend on the SM topologies. The SMs with the same topologies will have identical capacitor dynamic behavior. Applying (4.10) and (4.11) to (4.7)−(4.9), the voltage sources can be derived as 𝑣𝑐𝑎𝑣𝑔(𝑡 + Δ𝑡) = 𝑣𝑐𝑎𝑣𝑔(𝑡) + Δ𝑡𝑖𝐷1(𝑡)1𝐶𝑎𝑟𝑚𝑒𝑞 (4.18) 𝑣𝑠𝑝av𝑔= 𝑣𝑐𝑎𝑣𝑔(𝑡 + Δ𝑡) + 𝑁(𝑉𝐷 + 𝑖𝐷1(𝑡)𝑅𝐷) (4.19) 𝑣𝑠𝑛𝑎𝑣𝑔= 𝑁(−𝑉𝐷 − 𝑖𝐷2(𝑡)𝑅𝐷) (4.20) It is noted in (4.18) that the arm equivalent capacitor of the HBSMs will be charged by the positive arm current and bypassed by the negative arm current. 4.4.2 GSFB-AVM for MMCs with Different SMs In this subsection, the GSFB-AVM for the MMCs with different SMs is derived under de-blocking and blocking modes. In de-blocking mode, the FBSM- and CDSM-MMCs typically operate like the HBSM-MMC [65]. In blocking mode, the operations of the FBSM- and CDSM-MMCs are different from the HBSM-MMC due to the diode positions of the FB and CD SMs. When the arm current is positive, the capacitors of the FB and CD SMs are inserted like the HBSM. When the arm current is negative, the capacitors of FB and CD SMs are inserted to opposite the increasing of fault current. It is noted that the two capacitors in a CDSM are charged by half of the arm current since the two capacitors are connected in parallel. The average summation capacitor voltages (4.13) and (4.18) can be generalized for the MMCs with different SMs as 𝑣𝑐𝑎𝑣𝑔(𝑡 + Δ𝑡) = 𝑣𝑐𝑎𝑣𝑔(𝑡) + (?̅?𝑠𝑛 + 𝑏)(𝑖𝐷1(𝑡) − 𝑚𝑖𝐷2(𝑡))Δ𝑡𝐶𝑎𝑟𝑚𝑒𝑞 (4.21) where the converter operation index 𝑏 and the SM index 𝑚 depend on blocking/de-blocking mode and SM types as {𝑏 = 0, ?̅? = 1 for de‐ blocking mode𝑏 = 1, ?̅? = 0 for blocking mode (4.22) 81 {𝑚 = 1 any SMs, in de‐ blocking mode𝑚 = 0 𝐻𝐵𝑆𝑀𝑚 = −1 𝐹𝐵𝑆𝑀𝑚 = −1/2 𝐶𝐷𝑆𝑀} in blocking mode (4.23) The converter arm equivalent output voltages for positive and negative arm currents are given as 𝑣𝑠𝑝𝑎𝑣𝑔= (?̅?𝑠𝑛 + 𝑏)𝑣𝑐𝑎𝑣𝑔+ 𝑣𝑠𝑝,𝑙𝑜𝑠𝑠 (4.24) 𝑣𝑠𝑛𝑎𝑣𝑔= (?̅?𝑠𝑛 + 𝑏𝑚)𝑣𝑐𝑎𝑣𝑔+ 𝑣𝑠𝑛,𝑙𝑜𝑠𝑠 (4.25) where the conduction-loss-related voltage drops in the positive and negative current paths are expressed as 𝑣𝑠𝑝,𝑙𝑜𝑠𝑠 = ?̅?(𝑁𝑠𝑛𝑣1 + 𝑁(1 − 𝑠𝑛)𝑣2) + 𝑏𝑁𝑣5 (4.26) 𝑣𝑠𝑛,𝑙𝑜𝑠𝑠 = ?̅?(𝑁𝑠𝑛𝑣3 + 𝑁(1 − 𝑠𝑛)𝑣4) + 𝑏𝑁𝑣6 (4.27) In (4.26) and (4.27), the semiconductor on-state voltage drops, 𝑣1, 𝑣2, 𝑣3, 𝑣4, 𝑣5, and 𝑣6 are summarized in Table I for different SM types. It is noted that, for the MBSM-MMC, the equivalent capacitor voltages in (4.21) have two separate equations based on the numbers of HB and FB SMs (𝑁𝐻𝐵 and 𝑁𝐹𝐵) in an arm to accurately account for the different capacitor dynamics in HB and FB SMs. Table 4.1 Semiconductor Voltage Drops in GSFB-AVM. HBSM-MMC FBSM-MMC CDSM-MMC 𝑣1 𝑉𝐷 + 𝑖𝐷1𝑅𝐷 2(𝑉𝐷 + 𝑖𝐷1𝑅𝐷) 12(3𝑉𝐷 + 3𝑖𝐷1𝑅𝐷) 𝑣2 𝑉𝑇 + 𝑖𝐷1𝑅𝑇 𝑉𝑇 + 𝑉𝐷 + 𝑖𝐷1(𝑅𝑇 + 𝑅𝐷) 12(2𝑉𝑇 + 𝑉𝐷 + 𝑖𝐷1(2𝑅𝑇 + 𝑅𝐷)) 𝑣3 −(𝑉𝑇 + 𝑖𝐷2𝑅𝑇) −2(𝑉𝑇 + 𝑖𝐷2𝑅𝑇) −12(3𝑉𝑇 + 3𝑖𝐷2𝑅𝑇) 𝑣4 −(𝑉𝐷 + 𝑖𝐷2𝑅𝐷) −(𝑉𝑇 + 𝑉𝐷 + 𝑖𝐷2(𝑅𝑇 + 𝑅𝐷)) −12(𝑉𝑇 + 2𝑉𝐷 + 𝑖𝐷2(𝑅𝑇+ 2𝑅𝐷)) 𝑣5 𝑉𝐷 + 𝑖𝐷1𝑅𝐷 2(𝑉𝐷 + 𝑖𝐷1𝑅𝐷) 32(𝑉𝐷 + 𝑖𝐷1𝑅𝐷) 𝑣6 −(𝑉𝐷 + 𝑖𝐷2𝑅𝐷) −2(𝑉𝐷 + 𝑖𝐷2𝑅𝐷) −32(𝑉𝐷 + 𝑖𝐷2𝑅𝐷) 82 4.4.3 Simulation results The proposed GSFB-AVM and the DEM are implemented in Matlab/Simulink 2014b and RT-LAB 11.3.6 for a two-terminal 41-level monopole MMC HVDC system [22] as shown in Figure 4.6. The system parameters are indicated in Figure 4.6, and the controller parameters are listed in the Appendix. 100 Ω charging resistor is used at the secondary side of each transformer to limit any inrush current. The simulation time step for the GSFB- VM and the EM is 0μs. The standard MMC controllers, including inner-loop current and outer-loop power controllers, and CCSC are implemented in the GSFB-AVM and the DEM. The VBC controller maintaining the voltage balancing of the SM capacitors is implemented for the DEM. Figure 4.6 Two-terminal MMC HVDC system 4.4.3.1 Simulation Results of GSFB-AVM for HBSM-MMC This subsection validates the accuracy of the proposed GSFB-AVM for the HBSM-MMC systems (MMC-1 and MMC-2 in Figure 4.6). Due to space limitation, only the transient responses of MMC-1 are included in Figure 4.7. Initially, all IGBT gates are blocked, and the converters are energized from the AC grid. The capacitors in the HBSMs are charged by the positive arm currents and are bypassed by the negative arm currents. The DC-side voltage 𝑣𝑑𝑐 gradually rises to the AC line-to-line voltage level. At 0.2s, the converters are de-blocked to regulate 𝑣𝑑𝑐 to the rated value. Then, the charging resistor is bypassed. It is observed from Figure 4.7 that the results obtained by the proposed GSFB-AVM match well with those of the DEM. It is noted that the Phase-A current 𝑖𝑎 in Figure 4.7 (b) is defined in Figure 4.3 (a) as the AC terminal current 𝑖𝑗 where 𝑗 = 𝑎, 𝑏, 𝑐. 83 Figure 4.7 HBSM-MMC energizing. (a) DC voltages; (b) Phase-A currents; (c) Phase-A upper-arm sum of the SM capacitor voltages. 4.4.3.2 Simulation Results of GSFB-AVM for CDSM-MMC In this subsection, the proposed GSFB-AVM is used to simulate the CDSM-MMC systems (MMC-1 and MMC-2 in Figure 4.6). The verification is performed for the converter operations under blocking and de-blocking modes in three cases: converter energizing, power transfer, and DC-side pole-to-pole fault. a. Converter Energizing The converter energizing transients of the CDSM-MMC simulated by the GSFB-AVM and the DEM are shown in Figure 4.8. The energizing procedure is similar to that of the HBSM-MMC, except that the capacitors in the CDSMs are initially charged in parallel or series connection depending on the arm current directions. At 0.1s, the IGBT switch t5 in the CDSM in Figure 4.3 (d) is turned on so that all CDSMs are charged in similar behavior as the HBSMs, where the SM 84 capacitors are inserted by the positive arm currents. All gate pulses are enabled and the converters are de-blocked at 0.2s. Figure 4.8 shows that the proposed GSFB-AVM can accurately represent the behavior of the CDSM-MMC compared to the DEM. Figure 4.8 CDSM-MMC energizing. (a) DC voltages; (b) Phase-A currents; (c) Phase-A upper-arm sum of the SM capacitor voltages. b. Converter Power Transfer In converter de-blocking mode, all CDSMs operate similarly to the HBSMs. The real power is regulated to 1 GW from 0.7s as shown in Figure 4.9 (a). Hence, the DC current increases from zero to the rated value (Figure 4.9 (b)) which results in higher SM capacitor voltage ripples as shown in Figure 4.9 (c). It is noted in Figure 4.9 that the proposed GSFB-AVM can accurately represent the power transfer transient for the CDSM-MMC. The relative error of the sum of the SM capacitor voltages for the proposed GSFB-AVM is less than 0.4%, compared to the DEM. 85 Figure 4.9 CDSM-MMC de-blocking. (a) Converter AC-side active powers; (b) DC currents; (c) Phase-A upper-arm sum of the SM capacitor voltages. c. DC-side Pole-to-pole Fault Following the real power transfer, a DC pole-to-pole fault is applied in the middle of the DC cable at 1s. An instant drop of the DC current at 1s can be observed in Figure 4.10 (a). The IGBT gate pulses are bloc ed at 00μs later to avoid the overcurrent damage in the IGBTs. The C SM-MMC offers DC pole-to-pole fault blocking ability compared to the HBSM-MMC. The SM capacitors of the CDSMs are inserted by the SM diodes and impose counter-reacting arm voltages to the AC voltages so that the AC fault currents are reduced to zero. As shown in Figure 4.10 (a) and (b), the DC and the arm currents are forced to zero within a short time period after the CDSM-MMC is blocked. The sum of the SM capacitor voltages stays constant after the converter is blocked as shown in Figure 4.10 (c). It is observed from Figure 4.10 that the proposed GSFB-AVM produces nearly identical responses compared to the DEM. Figure 4.10 (d) shows that the relative error of 86 the upper-arm SM total capacitor voltage of the GSFB-AVM is less than 0.3% compared to the DEM. Figure 4.10 CDSM-MMC DC pole-to-pole fault. (a) DC currents; (b) Phase-A upper-arm currents; (c) Phase-A upper-arm sum of the SM capacitor voltages; (d) Relative error of upper-arm SM total capacitor voltage of the GSFB-AVM compared to the DEM. 4.5 Combined Model In the DEM, the insertion status of an SM is determined by its switching function generated from the VBC, which sorts the SM capacitor voltages in an arm and issues SM switching signals to balance the SM capacitor voltages. In the GSFB-AVM, the SM capacitor voltages are assumed to 87 be balanced (or equal) which enables the use of the arm equivalent capacitors to speed up the dynamic simulation. Although the GSFB-AVM can accurately simulate the dynamic behaviors of an MMC, it does not model the individual SM capacitor voltage ripples. It is noted from Sections 4.3 and 4.4 that the DEM and the GSFB-AVM utilize the same arm equivalent circuit, i.e., UAM, in Figure 4.5 (b), but different calculation methods for the controlled voltage sources 𝑣𝑠𝑝 and 𝑣𝑠𝑛. Therefore, a CM of the DEM and the GSFB-AVM is proposed and is shown in Figure 4.11. In the CM, depending on the operation mode, the UAM with its controlled voltage source calculated from either the DEM or the GSFB-AVM calculation block. Figure 4.11 CM circuit configuration. (a) Arm equivalent circuit; (b) UAM; (c) Combined DEM and GSFB-AVM block. In the proposed CM framework, the DEM and the GSFB-AVM can be conveniently switched between one another during the dynamic simulation. The model switching is established by the CM calculation block in Figure 4.11 (c). When the switch T is triggered to a, the calculation block is performed by the DEM. When the switch T is triggered to b, the calculation block is carried out by the GSFB-AVM. The data transfer between the two models is achieved by updating the historical voltages of the SM capacitors as GSFB-AVM → DEM: 𝑣𝑐𝑖 (𝑡) =𝑣𝑐𝑎𝑣𝑔(𝑡)𝑁 (4.28) 88 DEM → GSFB-AVM: 𝑣𝑐𝑎𝑣𝑔(𝑡) = ∑ 𝑣𝑐𝑖𝑁𝑖=1(𝑡) (4.29) where 𝑣𝑐𝑖 is the ith SM capacitor voltage at the time instant t and 𝑣𝑐𝑎𝑣𝑔is the summation of the SM capacitor voltages in an arm. The calculations of 𝑣𝑐𝑖 and 𝑣𝑐𝑎𝑣𝑔 are given in (4.2) and (4.21) from section 4.3 and 4.4, respectively. It is noted that the VBC and the individual SM capacitor voltage calculations can be avoided when the CM is in the GSFB-AVM mode. It greatly improves the MMC simulation efficiency. When the individual SM capacitor voltage ripples and the VBC are the focus of simulation studies, the DEM mode can be activated in the CM which offers high modeling accuracy and flexibility. 4.5.1 Simulation Results of Combined Model The proposed CM of the GSFB-AVM and the DEM is evaluated using the same test system in Figure 4.6. The MBSM-MMC is used in the case study, which includes 50% HBSMs and 50% FBSMs in each converter arm. The simulation results obtained by the CM is compared to those of the DEM and the GSFB-AVM to verify its modeling accuracy. 4.5.1.1 Converter Energizing The energizing process of the MBSM-MMC is presented in Figure 4.12. The converter is initially blocked. The AC-side breaker is closed at 0.01s. The FBSMs are charged faster than the HBSMs by the AC grid in the blocking mode due to the bidirectional current charging capability of the FBSMs. The soft-charging method [54] is used to reduce the inrush currents of the MBSM-MMC before entering to the de-blocking mode. From 0.2s, the converter is de-blocked. The sorting algorithm from the VBC regulates the capacitor voltages of the HBSMs and FBSMs to the same rated value. The individual SM capacitor voltages produced by the CM are shown in Figure 4.12 (a). The CM is initially executed in the GSFB-AVM mode. Two equivalent capacitors are used in an arm to represent the HBSMs and FBSMs, respectively. At 0.2s, the CM is switched to the DEM mode, when the VBC starts operating. 89 Figure 4.12 MBSM-MMC energizing, Phase-A upper arm. (a) SM capacitor voltages of the CM; (b) SM capacitor voltages for GSFB-AVM; (c) sum of the SM capacitor voltages; (d) arm currents. Figure 4.12 (b) shows the individual SM capacitor voltages when the GSFB-AVM is used for the entire converter energizing simulation. The proposed GSFB-AVM uses two separate arm equivalent capacitors to represent the HB and FB SMs, respectively, in each arm. Therefore, the SM capacitor voltages 𝑣𝑐𝑖 in Figure 4.12 (b) diverge after the converter energizing transient dies out. However, the DEM predicts the correct response as shown in Figure 4.12 (a) since the SM capacitor VBC is implemented (as shown in Figure 4.11) in the DEM to balance the individual SM capacitor voltages of the HB and FB SMs all together. The unbalanced HB and FB SM voltages in the proposed GSFB-AVM lead to slightly inaccurate simulation results for the 90 proposed GSFB-AVM as shown in Figure 4.12 (c) and (d). It is also observed from Figure 4.12 (c) and (d) that the simulation results obtained by the CM is identical to those of the DEM. Therefore, the CM can be used to switch between the GSFB-AVM and DEM modes to achieve improved simulation efficiency. 4.5.1.2 Converter Power Transfer The CM is also verified using a power transfer study as shown in Figure 4.13. The CM simulation is first executed in the DEM mode. At 0.65s, the simulation is switched to the GSFB-AVM mode. At 0.7s, the reference of the real power is set to 1 GW. The real power transfer results in an increase in the SM capacitor voltage ripples. At 0.75s, the CM simulation is switched back to the DEM mode. Figure 4.13 MBSM-MMC de-blocking, Phase-A upper arm. (a) SM capacitor voltages in CM; (b) sum of the SM capacitor voltages; (c) arm currents. The VBC of the DEM starts regulating the capacitor voltages. The comparisons of the simulation results are shown in Figure 4.13 (b) and (c). Both the GSFB-AVM and the CM have demonstrated 91 good accuracy with less than 0.4% difference when comparing to DEM. For the CM operating in the DEM mode, the influence of the VBC on the capacitor voltages of the individual SMs can be investigated. 4.5.1.3 DC-side Pole-to-pole Fault Ride-through The MBSM-MMC has the advantage of the DC-side pole-to-pole fault blocking compared to the HBSM-MMC. The DC-side fault ride-through behavior of the MBSM-MMC is simulated by the DEM, the proposed GSFB-AVM, and the proposed CM as shown in Figure 4.14. MMC-1 is originally operated in rectifier mode with the power reference of 1GW. At 1s, a pole-to-pole fault is applied in the middle of the DC cable. Therefore, the DC current and AC power experienced an instant drop in Figure 4.14. After the fault current is detected, the converters are blocked at 1.0004s. The FBSM capacitor voltages keep increasing until the fault current is suppressed. Meanwhile, the HBSM capacitors are naturally bypassed by the fault current. It is assumed that the DC fault is cleared at 1.1s and the converters are de-blocked at 1.2s. The DC voltage is then regulated to the pre-fault rated value by the converter DC voltage control. The real power transfer is restored to the pre-fault value from 1.4s. Figure 4.14 (a) shows the individual capacitor voltages produced by the CM. The CM was originally in GSFB-AVM mode until 1.2 s, when it was switched into DEM mode. The VBC in the DEM can balance the capacitor voltages of the HB and FB SMs as shown in Figure 4.14 (a). Figure 4.14 (b) and (c) shows the individual capacitor voltages produced by the GSFB-AVM and the DEM. It is observed from Figure 4.14 a − c that hen the DC pole-to-pole fault is suppressed by the FBSMs of the MBSM-MMC, the capacitor voltages of the FBSMs and HBSMs will be notably different due to the different blocking behaviors of the FB and HB SMs. When the GSFB-AVM is used, the capacitor voltages of the FBSMs and HBSMs diverge during the post-fault recovery, as shown in Figure 4.14 (b). If the capacitor voltages of the FBSMs and HBSMs simulated by the GSFB-AVM are not treated properly at post-fault, the capacitor voltage may have the risk of further divergence upon another DC fault. On the contrary, the DEM provides the accurate simulation results of the capacitor voltages of the FBSMs and HBSMs during the post-fault recovery. Although one can manually average the equivalent SM capacitor voltages of the FBSMs and HBSMs during post-fault steady-state in Figure 4.14 (b), the timing of the averaging action is yet unknown and the transients of the FBSM and HBSM capacitor voltage balancing at 92 post-fault will be missing. Therefore, the DEM can be used to obtain the correct SM capacitor voltages of the MBSM-MMC at the post-fault steady state. The DEM can be switched to the GSFB-AVM after the capacitor voltages are balanced to achieve improved simulation efficiency for off-line simulation. Figure 4.14 MBSM-MMC DC fault ride-through, Phase-A upper arm. (a) SM capacitor voltages in CM; (b) SM capacitor voltages in GSFB-AVM; (c) SM capacitor voltages in DEM; (d) DC currents; (e) Converter active powers. 93 4.6 Loss estimation This section describes the modeling of semiconductor loss in the DEM and the proposed GSFB-AVM. The semiconductor loss is composed of the conduction loss and switching loss. The conduction loss depends on the semiconductor V-I on-state characteristic and the instantaneous current flowing through the semiconductor. A device datasheet normally specifies the on-state characteristic curves at room temperature (25°) and the worst case (125°). Depending on a manufacturer’s converter design guideline the interpolated on-state characteristic between 25° and 125° can be used for conduction loss calculation. The nonlinear on-state characteristics are usually represented by piece-wise linear characteristics to simplify the loss calculation. In this research, the slope resistance (𝑅𝑇 or 𝑅𝐷 ), the saturation voltage (𝑉𝑇 or 𝑉𝐷 ), as well as the simulated instantaneous converter arm currents by the DEM and the proposed AVM, are used for the conduction loss calculation [60], [64]. Switching transitions of the IGBTs and diodes result in switching losses. There are mainly two types of switching loss calculation methods available in the literature, i.e., detailed simulation-based methods [4], [5], [59] and analytical loss calculation methods [9], [56]–[58]. In the detailed simulation-based methods, the EMT-type simulation tools are used to generate the instantaneous semiconductor currents and voltages before and after switching transients. These voltage and currents are then used to calculate the switching energies per pulse [60]. The exact switching-loss calculation requires the count of the switching transitions and the values of switching energy per switching event. The IGBT turn-on, turn-off energies (𝐸𝑜𝑛 , 𝐸𝑜𝑓𝑓 ) and the diode reverse recovery energy (𝐸𝑟𝑒𝑐 ) can be obtained from a semiconductor datasheet. In the manuscript, the DEM calculates the switching losses based on the detailed SM switching currents, the SM DC-link voltages, and the individual SM switching events. The analytical switching loss calculation methods are reported in [9], [56]–[58] for the MMCs. The analytical loss calculation method of the MMC was originally proposed in [9]. In the analytical loss calculation method, the instantaneous switching currents and voltages are not required which simplifies the switching loss calculation. Since, the GSFB-AVM does not represent individual SMs, meaning the exact switching counts are not available in the GSFB-AVM. Therefore, the analytical switching loss calculation method [9] is used for the proposed GSFB-AVM. Assuming the switching events are 94 uniformly distributed over each fundamental frequency cycle, the switching loss for the GSFB-AVM is estimated as [9] 𝑃𝑙𝑜𝑠𝑠,𝑠𝑤 = 6𝑁𝑓𝑆𝑀(𝐸on + 𝐸off + 𝐸rec)𝑉𝑐,𝑟𝑎𝑡𝑒𝑑𝑉𝑟𝑒𝑓𝐼𝑟𝑒𝑓|𝐼?̅?𝑟𝑚| (4.30) where the 𝑉𝑟𝑒𝑓 and 𝐼𝑟𝑒𝑓 are the reference voltage and current for the switching energy; 𝑓𝑆𝑀 is the estimated switching frequency for each SM; 𝑉𝑐,𝑟𝑎𝑡𝑒𝑑 is the rated value of SM capacitor voltage; and |𝐼?̅?𝑟𝑚| is the average of the absolute value of an arm current. It is noted that the number of SMs 𝑁 = 𝑉𝑑𝑐 /𝑉𝑐,𝑟𝑎𝑡𝑒𝑑 . The switching loss can be expressed in (4.31) using the DC-side current source shown in Figure 4.11 (a). 𝐼𝑙𝑜𝑠𝑠,𝑠𝑤 = 6𝑓𝑃(𝐸on + 𝐸off + 𝐸rec)𝑉𝑟𝑒𝑓𝐼𝑟𝑒𝑓|𝐼?̅?𝑟𝑚| (4.31) 4.6.1 Semiconductor Loss Modeling Results This subsection presents the converter semiconductor loss modeling results. One converter terminal from the test system in Figure 4.6 is operated under inverter mode with a unity power factor. The converter semiconductor data are listed in Table 4.2. Since the SM capacitor voltage in the case study is 16𝑘𝑉, the semiconductor data is rescaled by 16𝑘𝑉/𝑉𝑟𝑒𝑓 to match the SM voltage in the test system. The losses for the MMCs with different SMs are shown in Table 4.3. The conduction losses 𝑃𝑙𝑜𝑠𝑠,𝑟 and 𝑃𝑙𝑜𝑠𝑠,𝑣 for both the DEM and the GSFB-AVM are derived based on the average of the instantaneous power losses presented in Sections section 4.3 and 4.4. The FBSM- and CDSM-MMCs have shown higher conduction losses compared to the HBSM-MMC. The higher conduction loss is due to the increased numbers of semiconductors used in the FBSMs and the CDSMs. The conduction loss results have shown excellent agreement between the DEM and the GSFB-AVM. The small loss value difference is observed due to the minor difference of the arm currents in the DEM and the GSFB-AVM. The switching loss, 𝑃𝑙𝑜𝑠𝑠,𝑠𝑤 , for the DEM is calculated based on the average of the total instantaneous switching losses of all the SMs. The 𝑃𝑙𝑜𝑠𝑠,𝑠𝑤 for the GSFB-AVM is derived based on the analytical approach as shown in (4.30). The average of the absolute-value arm current in 95 each cycle is measured from the simulation as |𝐼?̅?𝑎| = 883𝐴. The average SM switching frequency for the GSFB-AVM is assumed to be 𝑓𝑃 = 150𝐻𝑧, which is consistent with the average SM switching frequency of the DEM. The results in Table 4.3 have demonstrated the proposed loss modeling method can accurately represent the semiconductor losses for the MMCs with different SM types. Table 4.2 Semiconductor Data. Conduction Loss Semiconductor Parameter Switching Loss Semiconductor Parameter RT,IGBT RD,diode 1. 1 mΩ 1.0 mΩ Eon,IGBT Eoff,IGBT 11 J 10.5 J VT,IGBT VD,diode 1.82 V 2.27 V Erec,diode Vref Iref 2.8 J 2.8kV 1.8kA Table 4.3 Semiconductor Losses of MMCs with Different SMs. Converter Type GSFB-AVM DEM MMC Type HBSM FBSM CDSM HBSM FBSM CDSM Ploss,r (MW) 1.76 3.40 2.59 1.76 3.41 2.60 Ploss,v (MW) 2.30 4.99 3.63 2.29 4.98 3.63 Ploss,sw (MW) 2.45 2.45 2.45 2.47 2.47 2.47 Ploss,tot (MW) 6.51 10.84 8.67 6.52 10.86 8.70 4.7 Modeling a large-scale DC grid in CIGRE This subsection verifies the accuracy and off-line simulation speed performance for the proposed GSFB-AVM using CIGRE B4-57 DC grid test system [66], [67]. The test system interconnects the onshore AC network with offshore wind turbines through a meshed DC grid that includes three DC systems (DCS). As shown in Appendix B, DCS1 and DCS2 use symmetrical monopole MMC converters. DCS3 consists of bipolar MMC converters. There are 16 individual MMCs (6 monopole MMC converters and 5 bipolar MMC converters) in the three DC systems considering 96 one bipolar station has two MMCs. The converters in the test system operate in different control modes, including P/Vdc/droop control, Q/Vac, and island controls. The complete list of the control and system parameters can be found in [66]. Since this research focuses on MMC modeling, the AC networks and the wind turbines are modeled using equivalent voltage sources. The VBC controller, similar to [22], [66], is used in the DEM while the proposed GSFB- VM doesn’t require the VBC control. The case study is developed using Matlab/Simulink 2014b and RT-LAB 11.3.6 and is based on the FBSM-MMC with 200 SMs per arm which provides DC-side pole-to-pole fault blocking. The waveforms from a few selected converters are presented in this research. Other converters have similar behaviors to the selected converters. Figure 4.15 Converter Cb-B1 upper FBSM-MMC. (a) Phase-A upper-arm total SM capacitor voltages; (b) Phase-A arm currents; (c) DC currents. 4.7.1 DC-side Pole-to-pole Fault As shown in Figure 4.15, all converters initially operate in a steady-state. A DC pole-to-pole fault occurs at 2 s at the terminal Bb-B1, shown in Appendix B. Figure 4.15 shows the transient behavior of the converter Cb-B1, the closest converter to the fault location. When the DC fault occurs, the discharging of the SM capacitors causes the arm currents and the DC current drop dramatically. 97 The overcurrent protection is activated to block the converter at 2.00115s. The capacitors of the FBSMs are then inserted to provide counter-reacting voltage to eliminate the faulty current. The transient responses produced by the proposed GSFB-AVM demonstrate good agreement with those of the DEM. Figure 4.16 Converter active powers injected into AC grid. Results presented using the DEM (line) and the GSFB-AVM (dash). Figure 4.17 Converter Cm-B2 FBSM-MMC. (a) DC voltages; (b) Phase-A arm currents; (c) DC currents. 98 The converter Cb-B2 and other converters in DCS3 are also blocked based on their overcurrent protection controls. The influence of the DC fault is reduced for the converters located further away from the fault. The active powers of the converters Cb-B1 and Cb-B2 drop to zero as shown in Figure 4.16. The converter Cm-C1, located in DCS1, is almost not impacted by the DC fault at Bb-B1 since it is not directly connected to the other DCSs. Unlike DCS1, the converters in DCS2 are affected but remain in de-blocking mode after the DC fault occurs. The converters Cm-B2 and Cm-B3 are in PV droop control mode. As the DC voltage decreases in DCS2 due to the DC fault in Bb-B1, the converters Cm-B2 and Cm-B3 tend to gradually inject more active power into the DC grid, as presented in Figure 4.16. Figure 4.17 shows the transient behavior of the MMC Cm-B2, where the DC voltage drops and the arm and DC currents increase before the converter reaches its overcurrent limit. Additional protection actions are required to restore the normal operation of DCS2 [66], which is beyond the scope of the research. 4.7.2 Speed Performance for 1-second Simulation The off-line simulation speed performance of the DEM and the proposed GSFB-AVM is evaluated in this subsection. A 1- second simulation study of the CIGRE B4-57 DC grid test system is performed under 2.8 GHz Intel Core i5-7440HQ with 8 GB RAM under Microsoft Windows 10 operating system and the time step of 0 μs. Table 4.4 Execution Times of The Proposed GSFB-AVM vs. DEM Number of SMs per Arm Run Time (s) Cm-A1 (1 MMC) DCS 1 (2 MMCs) Full CIGRE B4-57 (16 MMCs) GSFB-AVM DEM Speedup Ratio GSFB-AVM DEM Speedup Ratio GSFB-AVM DEM Speedup Ratio 50 3.5 6.4 182.9% 7.7 12.9 167.5% 140.9 200.6 142.4% 100 3.6 9.6 266.7% 7.7 20.4 264.9% 140.3 250.0 178.2% 200 3.6 18.6 516.7% 7.8 38.5 493.6% 140.2 403.6 287.9% 400 3.5 37.7 1077.1% 7.7 76.4 992.2% 140.7 687.8 488.8% Different numbers of MMCs and SMs per arm are used in the simulation studies to represent different complexities of the test systems. The simulation execution times using the proposed 99 GSFB-AVM and the DEM are summarized in Table 4.4. The simulation execution times vs. the numbers of SMs per arm in Table 4.4 are also plotted in Figure 4.18 to demonstrate the modeling efficiencies of the proposed GSFB-AVM and the DEM. It is shown in Table 4.4 that the DEM requires longer simulation execution times as the numbers of SMs per arm increase. Figure 4.18 indicates that the simulation times are approximately proportional to the numbers of SMs per arm, i.e., the complexity of the test systems. However, the proposed GSFB-AVM uses the same amount of execution time regardless of the number of SMs per arm due to the use of arm equivalent capacitors. It is also noted that the linear relationship of the simulation execution time vs. the number of SMs per arm is only approximate due to the simulation overheads caused by the other grid components such as AC/DC transmission lines, cables, and DC-DC converters. The benefits of using the proposed GSFB-AVM over the DEM will be even pronounced for larger and more complicated DC grid test system. Figure 4.18 Simulation execution times for CIGRE B4-57 test system. (a) Cm-A1 (1 MMC); (b) DCS 1 (2 MMCs); (c) Full CIGRE B4-57 (16 MMCs). EM GS B VM EM GS B VM EM GS B VM100 4.8 Real-time simulation In this subsection, both the DEM and the proposed GSFB-AVM are implemented in OPAL-RT OP5700 real-time simulator using RT-LAB version 11.3.6 to verify their computational performances in the real-time simulation environment. The two-terminal monopole system, shown in Figure 4.6, and a four-terminal bipolar system from CIGRE working group B4-72, shown in Figure 4.19, are used to demonstrate the improved computational performance of the proposed GSFB-AVM over the DEM. The system and control parameters of the four-terminal bipolar system can be found in [68], [69]. The test systems are divided into individual converter terminals and their controllers and are dispatched to different CPU cores to achieve parallel processing in real-time. our case studies are performed using the time step of μs. Real-time simulation is achieved if CPU execution time is within the specified simulation time step. Figure 4.19 Four-terminal MMC HVDC system. The CPU times measured in the two-terminal monopole system are presented in Table 4.5. The CPU time of each simulation configuration is the mean value of the CPU time for every simulation time step. Converters 1 and 2 are assigned to CPUs 1 and 2 while the controllers for both converters are assigned to CPU 3. In Table 4.5 “T” stands for converter terminal; “C TLR” stands for the controllers of the converters. Two case studies are established based on the DEM and the GSFB-AVM, respectively. Both the DEM and the GSFB-AVM have achieved real-time simulation. But the GSFB-AVM has demonstrated a simulation speedup factor of 24.45𝜇𝑠5.3𝜇𝑠= 4.6 compared to that of the DEM. The use of the proposed GSFB-AVM also leads to a faster simulation speed for the 101 controllers .1 μs in Case 1 vs. . μs in Case since the VBC inside the DEM requires significant computational resources while the GSFB-AVM avoids the VBC by assuming balanced individual SM capacitor voltages. Table 4.5 CPU Execution Times of Two-Terminal Monopole System. Case Case 1 240 SMs per station Case 2 240 SMs per station CPU Model CPU 1 T1 DEM CPU 2 T2 DEM CPU 3 T1-T2 CNTLR CPU 1 T1 AVM CPU 2 T2 AVM CPU 3 T1-T2 CNTLR CPU Time .0 μs . μs .1 μs . μs . 0μs . μs CPU Usage 71.58% 69.87% 83.19% 15.06% 15.15% 11.34% Table 4.6 CPU Execution Times of Four-Terminal Bipolar System Case Case 3 480 SMs per station Case 4 4800 SMs per station CPU Model CPU 1 T1-T3 AVM CPU 2 T4 DEM CPU 3 T1-T4 CNTLR CPU 1 T1-T3 AVM CPU 2 T4 AVM CPU 3 T1-T4 CNTLR CPU Time . μs 1. μs . μs . 0μs . μs 10. μs CPU Usage 92.11% 100% 100% 92.34% 27.25% 31.80% Table 4.6 demonstrates the CPU time and usage of the four-terminal bipolar system simulated using the GSFB-AVM and/or DEM. The converters of T1 to T3 are modeled using the GSFB-AVM and are assigned to CPU 1 in both cases. The converter in T4 is modeled using the DEM in Case 3 and the GSFB-AVM in Case 4, respectively. The controllers are simulated in CPU 3 in both cases. It is observed from Table 4.6 that the CPU times in CPUs 2 and 3 of Case 3 is larger than the given simulation time step of μs which means the CPU is overload and real-time 102 simulation is not achieved. Compared to Case 1, the number of SMs in CPU 2 is doubled due to the use of a bipolar system in Case 3 which increases simulation time in the DEM. However, the use of the GSFB-AVM achieves real-time simulation for the three converters T1-T3 simulated in CPU 1 of Case 3. The increase in CPU time of CPU 1 in Case 3, compared to that of Cases 2, is due to the increased number of the converters simulated in CPU 1 (three bipolar converters in Case 3 vs. 1 monopole converter in Case 1). In Case 4, the numbers of SMs per converter station in the converters T1 to T4 are increased from 480 to 4800 and all four converters are simulated using the GSFB-AVM. It is observed in Table 4.6 that the CPU times remain the same for CPU 1 in Cases 3 and 4. That is, the increase in SM numbers in the GSFB-AVM does not affect the CPU time since one converter arm can be represented by a lumped-parameter equivalent circuit in Figure 4.11 (b). It is also noted that the use of the GSFB-AVM for the converter T4 in CPU 2 of Case 4 has improved the simulation speed over times . μs in Case vs. 1. μs in Case hich is consistent with the results of the two-terminal test system in Cases 1 and 2. It is noted that the proposed CM is not implemented for the real-time simulation study. When the CM operates in DEM mode, the required CPU usage or computational resource of the CM will be determined by the DEM which represents the bottleneck of the CM for real-time simulation. Therefore, the CM is not intended to improve the real-time simulation performance of the MMCs. On the other hand, the CM would find its applications in the off-line simulations to achieve the fastest simulation speed with good numerical accuracy.103 5 Hybrid Transient Stability and Electromagnetic Transient Simulation A power system is an electric network combining generation, transmission, and loads. A power system consists of thousands of various types of components (e.g. generators, transformers, transmission lines, converters, etc.) that interact with each other in the power network. The dynamic modeling of the power system is required to represent these components and the interactions among the components using differential equations. This dynamic modeling approach represents the time-domain evolution of the state variables in the system to study the dynamic behavior of the power system and predicting any variable of interest in the system during steady-state and transients. The dynamic modeling of the power system can be classified into two different types depending on the study interest. The Transient Stability (TS) program is one of the most extensively used simulation tools for power grid angular stability analysis with multiple synchronous machines. A TS study [70] is widely employed to perform analysis in a large system with slow dynamic responses. It produces phasor type solutions with the assumption of the fundamental frequency modeling and millisecond time step. With the quasi-steady-state model of HVDC and Flexible Alternating Current Transmission System (FACTS) devices, Transient Stability Program (TSP) is suitable to handle thousands of differential equations in a large-scale power network. However, its phasor and fundamental frequency properties cause restrictions in modeling the fast-transient phenomenon of the HVDC and FACT devices and the harmonic characteristics of these non-linear elements. On the other hand, the Electro-Magnetic Transient (EMT) study [71] is based on three-phase instantaneous values and is commonly used for analyzing the dynamics of the non-linear elements. The fast-transient phenomenon, control, and internal fault operation properties of power electronic converters can be adequately represented by EMT program as it models fast transient in the small-time step of typically 50 s. Moreover, EMT program is very computationally demanding depends on the size of the studied system [71], [72]. 104 This section demonstrates a hybrid TS-EMT simulation based on interconnected AC-MMC-HVDC system. First, the hybrid simulation technique5 is presented, where the test system is based on the 39-bus New England AC grid and a one-terminal MMC system. The obtained results are validated by the full-EMT solution as the reference, and is shown to have a high-level of accuracy. Later, the concept of MMC-AVM is incorporated into hybrid simulation6. The idea is to adopt the AC-side circuit of the AVM to represent the EMT-subsystem dynamics inside the TS simulator. This approach enables the parallel simulation, even during a fault, thus it can provide a more efficient solution compares to conventional hybrid simulation. 5.1 Modeling Large-scale AC/DC Grid Using Hybrid Simulation Technique Hybrid simulation of TS and EMT was proposed to provide interfacing between the two distinct simulators [28]. Equivalents resulted from each simulator can exchange information through a series or parallel interaction protocol [40]. Such techniques allow the hybrid simulator to take advantage of both TSP and EMTP. Previous research works have attempted to apply the hybrid simulator and the related interfacing techniques to AC/DC power system through average VSC models [7], [35], [73]. However, the investigated converter models cannot adequately represent the detailed dynamic characteristic in the converter. The purpose of the hybrid simulation algorithm is to integrate the TS modeling of a large AC grid with the detailed EMT simulation of local subsystems. The TSP is capable of solving thousands of phasor-based differential and algebraic equations using a time step of tens of milliseconds. On the other hand, the EMTP can precisely represent the non-linear transient behaviors of power electronic converters. For example, MMC HVDC uses a detailed switching-based EMT-type converter model with a time step of several microseconds. Therefore, the hybrid simulator incorporates the advantages of both the TSP and the EMTP in terms of fast simulation speed and high modeling fidelity. 5 Xuekun Meng, Liwei Wang, "Interfacing an EMT-type modular multilevel converter HVDC model in transient stability simulation", published in IET Generation, Transmission & Distribution, vol. 11, no. 12, May 2017. 6 Xuekun Meng, Liwei Wang, "Parallel-Rate Hybrid TSP and EMT Simulation of AC-MMC-HVDC System using AC Thevenin Equivalent Circuits", to submit to IEEE Power Engineering Society General Meeting 2021. 105 5.1.1 Modeling of TS and EMT Subsystems The hybrid simulation algorithm decouples the entire power grid into TSP (or external) subsystem and the EMTP (or detailed) subsystem. Each subsystem features different transient simulation methodologies according to the objectives of the transient studies. The external AC subsystem, including a large amount of AC components such as synchronous generators, transformers, and transmission lines, accounts for the major portion of the entire AC-HVDC system. The hybrid simulation algorithm models the external AC subsystem for system-level TS solution which is based on the positive sequence, single-phase and fundamental-frequency phasor. The external AC subsystem can be represented by a set of differential equations and algebraic equations as [70] {?̇? = 𝑓(𝒙, 𝑉)𝐼(𝒙, 𝑉) = 𝒀𝑁𝑉 (5.1) with a set of known initial conditions (𝒙0, 𝑽0), where 𝒙 is the state vector of the TS subsystem, 𝑽 is the bus vector of the TS subsystem, 𝑰 is the current injection vector, and 𝒀𝑵 is the network conductance matrix. The detailed HVDC subsystem, including the converters, the transformers, the DC transmission lines or cables, are modeled in the EMTP using three-phase, instantaneous values. Therefore, the unbalance and harmonics characteristics of the system components in steady-state operations and transient disturbances are adequately represented in the EMTP subsystem. The transient behavior of the EMTP subsystem is described by the nodal equation in the discrete-time domain as 𝒀𝑽(𝑡) = 𝑰𝒉(𝑡 − ∆𝑡) (5.2) where 𝑽 is the nodal voltage vector of the EMTP subsystem; 𝑰𝒉 is the equivalent history source vector, and 𝒀 is the equivalent nodal conductance matrix. The TSP subsystem and the EMTP subsystem are based on different modeling paradigms. When the two transient simulation algorithms are interfaced, the equivalent circuits need to be established for the TSP and EMTP subsystems. The TSP represents an external AC network using fundamental frequency, positive sequence, phasor-type data, while the EMTP utilizes three-phase instantaneous 106 values to model the detailed power electronic components. Therefore, waveform-to-phasor and phasor-to-waveform data transformations are needed for the hybrid simulation algorithm. 5.1.2 TSP Subsystem Equivalent in EMTP The external TSP subsystem can be represented by a Thevenin or Norton equivalent circuit [28] in the detailed EMTP subsystem. When the detailed EMTP subsystem is connected to the TSP subsystem through a single terminal interfacing bus, the single-port Thevenin equivalent circuit can be used to represent the TSP subsystem as shown in Figure 5.1. Figure 5.1 MMC per-phase equivalent circuit model in EMTP. The voltage source and the impedance in the Thevenin equivalent circuit are updated when the two simulators exchange data at each or multiple TSP time steps. When the EMTP subsystem is simulated, the Thevenin equivalent circuit voltage amplitude and the impedance are assumed to be constant. The voltage source of the Thevenin equivalent circuit can be calculated from the open-circuit voltage at the interfacing bus [37]. Assuming the sub-transient generator model is used in the TSP, the equivalent current source of the ith generator connected to the AC network is determined by the generator state variables and the sub-transient reactance 𝑗𝑥𝑑′′ and 𝑗𝑥𝑞′′ as [74]: 𝐼𝑥 + 𝑗𝐼𝑦 = (𝐸𝑞𝑖′′ 𝑠𝑖𝑛𝛿𝑖𝑥𝑑𝑖′′ −𝐸𝑑𝑖′′ 𝑐𝑜𝑠𝛿𝑖𝑥𝑞𝑖′′ ) + 𝑗 (𝐸𝑑𝑖′′ 𝑠𝑖𝑛𝛿𝑖𝑥𝑞𝑖′′ −𝐸𝑞𝑖′′ 𝑐𝑜𝑠𝛿𝑖𝑥𝑑𝑖′′ ) (5.3) Given the network conductance matrix of the TSP, the open-circuit voltage at the interface bus can be calculated. In order to estimate the impedance of the Thevenin equivalent, the unit current at 107 the interfacing bus is injected into the AC grid. With the equivalent current sources of the generators turned off, the measured voltage at the interfacing bus gives the Thevenin equivalent impedance of the AC subsystem. It is noted that the Thevenin equivalent impedance needs to be updated only when the AC network changes its topology. The reference [30] has proposed that the fundamental frequency-based equivalent is not adequate in representing the ES if wide-range frequency components present. Further development was accomplished in [38] and provided solutions in encountering this issue. One is to extend the DS system to include a portion of the ES system thus lower the effect of disturbance source at the interfacing terminals. However, this would increase the complexity of the hybrid simulation since more interfacing terminals are introduced as the interfacing boundary moves toward the ES. Another approach is to represent the passive network characteristic of ES with the Frequency-dependent network equivalent (FDNE). The frequency response at interfacing terminals was first fitted with a rational function then implemented in the form of parallel RLC passive components or discretized parameters. Various paper [32], [33], [39] have contributed to prove the accuracy of the FDNE in the hybrid simulation; however, the wide-range frequency data is not easy to be obtained. Most tests system data provided in IEEE (etc.) contained only the fundamental frequency based positive sequence data, whereas the negative and zero sequence and multi-section transmission line parameters are not considered. 5.1.3 EMTP Subsystem Equivalent in TSP The simulation results produced by the EMTP simulation are based on three-phase instantaneous values. To interface the EMTP subsystem into the TSP, Direct Fourier Transform (DFT) analysis or least-square curve fitting method is commonly used to convert the instantaneous-value waveform to the corresponding phasor [75]. The DFT method requires the sampling period to be one or multiple cycles to calculate the voltage and current phasors correctly. During fault and fault recovering stages, the EMTP subsystem simulation may exchange data with the TSP at the sub-cycle period which limits the use of the DFT analysis. On the other hand, the least-square curve fitting method [31] is flexible on the sample length of the EMTP data. It extracts the fundamental frequency component at the interfacing bus and fits the instantaneous data into a sinusoidal curve that consists of the amplitude and phase angle as the parameters. The representation of the DS in the ES can be modeled in the form of constant power load, constant impedance load or Norton/Thevenin equivalent [31]. There is no significant difference in the performance between 108 each implementation. However, they all are based on the voltage and current waveform accessed from the interfacing boundary. 5.1.4 Interfacing Bus Location In the hybrid simulation, the electromechanical and electromagnetic transient behaviors of the TSP and EMTP subsystems are coupled through an interfacing bus. The TSP and EMTP subsystem equivalents are calculated based upon the interfacing variables at each data exchange time point. The interfacing location has to be carefully arranged to minimize the system size for the EMTP simulation but maintained sufficient details. The interfacing location can be further extended to increase the accuracy of the overall hybrid simulation [38]. However, the expansion of the detailed system will increase the complexity of the detailed system modeling and the computational load of the hybrid simulator. 5.1.5 Interfacing Protocol In the hybrid simulation algorithm, the simulation data from the TSP and the EMTP subsystems are exchanged in sequential order or parallel order. Due to the different simulation time steps, the data from TSP and EMTP can only be exchanged at the common time points, which is generally considered to be the TSP time steps. Since the TSP solves nonlinear differential-algebraic equations for the AC subsystem, the iterative solution is required for the generators and the AC network. On the other hand, the EMTP allows non-iterative solutions due to a small-time step used in the EMTP simulator. The data exchanging protocol and sequence has a direct impact on the accuracy of the overall hybrid simulation. A common approach for the sequential protocol is to execute each program followed by another. Figure 5.2 illustrates the sequential interfacing protocol between TSP and EMTP [31]. With the described equivalent representation, the interaction protocol can be summarized as follows: (1). Assuming the hybrid simulator has the TSP solution at 𝑡𝑖−1; run the TSP from 𝑡𝑖−1 to 𝑡𝑖 for one-time step to obtain the solution at 𝑡𝑖. (2). Calculate the Thevenin equivalent circuit of the AC network in the TSP; transform the Thevenin equivalent circuit from positive sequence phasor domain into three-phase time-domain circuits for the EMTP. 109 (3). Perform the EMTP simulation from 𝑡𝑖 to 𝑡𝑖+1 assuming the TSP Thevenin equivalent has constant voltage source magnitude and constant impedance. (4). Extract phasor quantities from the voltage and current at the interfacing bus; Calculate the real and reactive power injections from the EMTP to TSP. The EMTP subsystem is equivalent as a constant P, Q load in [𝑡𝑖 , 𝑡𝑖+1]. (5). Execute the TSP simulation from 𝑡𝑖 to 𝑡𝑖+1 , given the constant P, Q load as the EMTP equivalent. The abovementioned steps can be repeated until the end of the hybrid simulation. Figure 5.2 Interfacing protocol of the TSP and EMTP simulators. (a) Interfacing sequence, (b) PSCAD implementation. 110 Figure 5.2 (b) presents the implementation of the hybrid simulation algorithm in PSCAD/EMTDC. The built-in three-phase controlled voltage source and variable RL branch from the PSCAD component library are used to represent the Thevenin equivalent circuit of the AC grid. The voltage amplitude and phase angle of the controlled voltage source, as well as the values of variables R and L, are updated by the TSP at every data exchange time instant of the hybrid simulation. The TSP is initialized at the beginning of the PSCAD simulation using the AC-grid input data file, which contains the AC-grid topology and parameters. The interfacing variables are the three-phase voltages and currents at the point of the common coupling of the MMC-HVDC system. The curve fitting method is used in the phasor extractor block to obtain the real and reactive power injections (P and Q) to the AC grid for the TSP simulation. The TSP and phasor extractor blocks are implemented in PSCAD/EMTDC as user-defined models and are coded using C language. Figure 5.3 10-generator 39-bus AC system integrating the MMC-based HVDC system. 111 5.1.6 Case Studies The IEEE 10-generator 39-bus AC system is used in the case studies to verify the proposed hybrid simulation algorithm. The single-line diagram of the 10-generator 39-bus system is shown in Figure 5.3. The system parameters can be found in [76]. An MMC-based HVDC transmission system is connected to the bus 15 of the AC system as shown in Figure 5.4. There are two terminals for the MMC HVDC system connected by DC cables as shown in Figure 5.4. Without loss of generality, the receiving terminal of the HVDC system is assumed to be connected with a three-phase constant impedance load. The parameters of the MMC HVDC converter is given in Table 5.1. The commercial EMTP-type software package PSCAD/EMTDC is used to implement the hybrid simulation algorithm and the full EMTP simulation of the entire AC-DC system for benchmark comparisons. Figure 5.4 MMC-based HVDC system configuration. Table 5.1 Parameters of the MMC HVDC System. Quantity Value AC bus voltage 230 kV AC system frequency 50 Hz Transformer ratio 230/345 kV Transformer leakage reactance 0.15 pu Transformer connection Y / Δ DC-link voltage 640 kV Arm resistance 𝑅𝑎𝑟𝑚 0.8 Ohm Arm inductance 𝐿𝑎𝑟𝑚 76.4 mH SM per arm 10 SM capacitance 0.28 mF SM switching frequency 150 Hz 112 The hybrid simulation algorithm models the AC system using the TSP which is coded using C language and is implemented in PSCAD/EMTDC as a user-defined block. The generators in the TSP are represented by the reduced-order double-axis machine model [70]. The loads in the TSP of the AC system are represented by a constant impedance model. The MMC-based HVDC transmission system is represented by a detailed switching-based converter model and implemented in PSCAD/EMTDC. The TS subsystem of the AC grid is interfaced with the EMT model of the MMC HVDC using the Thevenin equivalent circuit as shown in Figure 5.5. The values of the Thevenin equivalent circuit voltage and impedance are updated at each TS simulation time step according to the interfacing protocol stated in section 5.1.5. The simulation time-step for the TSP is 20 ms while the EMTP subsystem uses a time step of 5 μs to simulate the detailed switching behavior of the MMC converter. Figure 5.5 TS Interface with MMC HVDC model in PSCAD/EMTDC. In the PSCAD/EMTDC simulation, the MMC HVDC is initially operated at the full-loading condition for which the real and reactive powers are set at 4.5 MW and -1.25 MVAR, respectively at the sending end of the HVDC system. A three-phase fault occurs at the bus 9 of the AC grid at 1.22s and disappears at 1.32s. The simulation results using the hybrid simulation algorithm and the full EMT model of the AC-DC system (the reference model) are compared in Figure 5.6−Figure 5.11. Figure 5.6 and Figure 5.7 illustrate the RMS values of the interface bus voltages and the instantaneous Phase-A currents flowing into the EMTP subsystem. It is observed from Figure 5.6 and Figure 5.7 that the hybrid simulation algorithm produces similar simulation results to the reference model in the overall transient period. The RMS voltage predicted by the hybrid simulation is slightly higher during transient recovery between 1.36s and 1.4s. The slightly different RMS voltages may arise from the different synchronous machine modeling approaches 113 used in TSP and PSCAD/EMTDC where a full-order machine model is used to represent the detailed stator transients. Figure 5.6 The RMS values of the interface bus voltage. Figure 5.7 The phase-A interfacing current flowing into the primary side of the sending end transformer. 114 Figure 5.8 The voltage waveforms of the Phase-A upper and lower arms in the sending end converter. Figure 5.9 The current waveforms of the Phase-A upper arm in the sending end converter. Figure 5.8 and Figure 5.9 illustrate the sending-end converter upper and lower arm voltages and upper arm currents of Phase-A produced by the reference model and the hybrid simulation. It is noted that the third-harmonics voltage injection is used in the converter reference voltage 𝑒𝑉𝑟𝑒𝑓 to increase its linear modulation range as is shown in Figure 5.8. It is observed in Figure 5.8 and 115 Figure 5.9 that the hybrid simulation predicts very similar responses compared to the reference model. Figure 5.10 The Phase-A output converter voltages at the secondary side of the sending end transformer with the 3rd order harmonic filtered out. Figure 5.11 The submodule capacitor voltages in the Phase-A upper arm of the sending end converter. (a). Reference model; (b). Hybrid simulation. 116 Figure 5.10 illustrates the converter output AC voltages at the secondary side of the sending-end converter transformer. The third-harmonics are filtered out from the converter output AC voltages. Figure 5.11 (a) and (b) show the SM capacitor voltage ripples in the Phase-A upper arm of the sending-end converter. It is shown in Figure 5.10 and Figure 5.11 that the simulation results produced by the hybrid simulation match the reference model using full PSCAD/EMTDC simulation. A hybrid electromechanical and electromagnetic transient simulation of the AC grid integrated with MMC-based VSC HVDC transmission is investigated in the research. A detailed switching-based EMT-type model of the MMC HVDC system is implemented to represent the dynamic behavior of the MMC converter. The external AC grid is modeled by fundamental-frequency phasor-based TSP. The EMT-type model of the MMC converter is interfaced with the TS model of the AC grid using sequential interaction protocol. The hybrid simulation algorithm calculates the Thevenin equivalent circuit of the external AC grid after each time step of the TS simulation. The Thevenin equivalent circuit is then used for the EMT simulation of the MMC HVDC system within the time step of the TS simulation. The Fourier transformation is used to extract the voltage and current phasors at the interfacing bus, i.e., the PCC of the AC grid and the MMC HVDC system. The real and reactive powers of the MMC HVDC converter are calculated as the interfacing variables for the TSP of the AC grid. The proposed hybrid simulation algorithm is implemented in PSCAD/EMTDC. The detailed switching-based MMC converter model and the TSP of the AC grid are constructed using customized models and codes. A case study of 10-generator 39-bus New England system is used to demonstrate the effectiveness of the hybrid simulation method. The simulation studies verify that the proposed hybrid algorithm improves the overall simulation efficiency compared to the full-EMT model of the AC-DC system while preserving the simulation accuracy. 5.2 Applying AVM Concept to Establish Parallel Simulation The hybrid simulation provides a fundamental framework that integrates the TS with EMT simulators. The purpose of the hybrid simulation is to incorporate the speed advantage from the TS simulator and the detailed representation from the EMT simulator. This research explicitly focused on the interfacing techniques for a test system based on a large-scale AC system 117 interconnecting with an MMC-HVDC link. The entire system is separated into two distinct subsystems based on the complexities of the modeling components. The EMT simulator dominates the portion of the system that requires detailed simulation while the remaining portion is taken care of by the TS simulator. The subsystems are represented using equivalent circuits and exchange information to another at the common time step. The AC system is composed of a large number of passive components, which include the generators, transformers, and transmission lines. The components inside of the AC system can be represented using a set of differential and algebraic equations (DAE) with fundamental frequency based positive-sequence phasor-type data. TS simulator is widely employed in simulating the large-scaled AC system, as it is capable of efficiently handle thousands of DAE under milliseconds time steps. The MMC station includes massive power electronics devices that exhibit nonlinear transient behavior. Using an EMT simulator with instantaneous type data under a microsecond time step can accurately capture the detailed switching behavior under the steady-state and the transients. The converter stations, converter transformer, and the DC cables are included in the EMT subsystem to obtain a detailed insight into the transient behavior. It is noted that the EMT subsystem could be extended to include more components from the AC grid, but this will increase the computational burden due to the additional calculation inside the EMT. The interfacing terminal is selected to be the interfacing buses that interconnect the AC system and the MMC-HVDC system to minimize the size of the EMT subsystem. Due to the data type difference between the EMT and TS solvers, an equivalent circuit is required to represent the response of the solver-dominated subsystem. As shown in Figure 5.12, a Thevenin or Norton equivalent circuit can be adopted to represent the TS subsystem inside of the EMT. The voltage source 𝑣𝑇𝑆 and impedance 𝑅𝑇𝑆 and 𝐿𝑇𝑆 is calculated based on the open-circuit theorem and the generator sub-transient reactance. The equivalent circuit is based on the phasor to waveform data type conversion in which the equivalent circuit is assumed to remain constant over the cycle. It is noted that only the voltage source inputs are updated at each TS cycle. The impedance is calculated based on the grid structure and generator reactance and changes only when major disturbance applied in the TS subsystem. 118 For representing the EMT subsystem inside the TS simulator, a window extraction method is adopted to convert the instantaneous data to phasor type data. As shown in Figure 5.12, the obtained instantaneous terminal voltage and current from EMT are converted to phasor solutions using Direct Fourier Transformer (DFT). Thus, the EMT subsystem is represented using a PQ load equivalent inside the TS simulator. The PQ load equivalent can adequately represent the EMT subsystem under steady-state. However, this approach becomes vulnerable when a severe disturbance is subjected inside the EMT subsystem. The calculation of active and reactive powers becomes inadequate for large transients (e.g. converter PCC fault, DC pole-pole fault). Figure 5.12 Traditional hybrid simulation interfacing equivalent circuits. The information has to exchange between subsystems at a common time step to timely represent the subsystem within the other simulator. The common time step is usually defined as the TS time step due to its large simulation time step. Figure 5.13 (a) shows the conventional parallel interfacing protocol, where EMT and TS simulators are executed simultaneously and exchange information for the hybrid simulation at the next time step. This approach introduces a delay to TS subsystem if disturbance occurred in the EMT subsystem. Alternatively, a sequential interfacing protocol, as presented in Figure 5.13 (b) is introduced where the EMT is first performed and transfers the information to the TS simulator for current time step execution. The approach provides a more precise representation of the EMT subsystem inside of 119 the TS simulator, as EMT includes most of the details; however, one simulator has to be idle while the other is executing, resulting in a reduced overall simulation efficiency. Figure 5.13 Traditional hybrid simulation interfacing protocols. a) Parallel interfacing protocol; b) Sequential interfacing protocol. Blue-line indicates information without disturbance. Red-line indicates the information contains disturbance. 5.2.1 The Proposed EMT Subsystem Equivalent and Parallel Interfacing The proposed method in representing the MMC-based EMT subsystem inside the TS simulator is based on the averaging theory of the MMC, where the AC current of MMC is driven by the inner EMF voltage. The inner EMF voltage can be calculated as 𝑣𝑠𝑗 =𝑣𝑙𝑗 − 𝑣𝑢𝑗2 (5.4) where 𝑣𝑢𝑗 and 𝑣𝑙𝑗 are the upper and lower arm voltages for the phase index j=a,b,c. Using the Kirchhoff’s voltage la the interfacing voltage at the converter AC-end is calculated as 120 𝑣𝑗 = 𝑣𝑠𝑗 −𝑅𝑎𝑟𝑚2𝑖𝑗 −𝐿𝑎𝑟𝑚2𝑑𝑖𝑗𝑑𝑡 (5.5) where 𝑖𝑗 is the AC phase current, 𝑅𝑎𝑟𝑚 and 𝐿𝑎𝑟𝑚 are the arm resistance and inductance. The behavior of be MMC seen from the AC-side can be represented using a Thevenin equivalent. Assuming the converter is perfectly balanced, the converter can be represented using impedance behind the EMF voltage. The impact from the transformer can also be included by adding the transformer impedance and converting 𝑣𝑗 to the transformer's primary side. Figure 5.14 Equivalent circuit of the proposed parallel-rated interfacing method. As shown in Figure 5.14, the measured EMF from the MMC is first converted to the primary-side and transformed to phasor-type data. The results are then sent to the equivalent circuit as the source input. It is noted that the impedance remains constant if no changes are presented, and only the voltage source is updated in every common cycle. When the converter is blocked due to DC pole-pole fault, the converter storage capacitors are bypassed. The short-circuit current flows through free-wheeling diodes of the converter. This research adopts the assumption that the AC-side fundamental frequency behavior of the MMC can be represented by shorting the EMF voltage inside [22]. 121 Figure 5.15 The proposed parallel-rated interfacing protocol. The purpose of the assumption is to decouple the TS and EMT subsystems during DC pole-pole fault transient. Hence, the TS simulator can run independently from EMT until the converter is re-energized. As shown in Figure 5.15, the approximation of the EMT subsystem is updated into TS simulator when the disturbance is applied. The TS simulator carries the disturbance information and calculates the solution over one TS time step. The fault in EMT-side is accurately represented in the TS simulator by the end of the TS time step. This approach allows the parallel interfacing to achieve no time delay in represents the fault inside of the EMT subsystem. 5.2.2 Simulation Results The test system is developed based on the New-England 39-bus system [76] interconnected with a two-terminal MMC-HVDC link as shown in Appendix C. The MMC-HVDC link is connected between bus 16 and bus 20 inside the AC grid and includes a total of 60 SMs in each MMC. Detailed parameters of the MMC are included in Appendix C. The test system is modeled using Matlab 2014b with OPAL-RT eMEGAsim simulator using 50us, whereas the TS subsystem is running at 20ms and is incorporated inside the model using the built-in Matlab function block. This section verifies the proposed hybrid simulation modeling method under the steady state and DC pole-to-pole fault blocking operations. A comparison is made between the results obtained from the proposed parallel-rate interfacing method, sequential interfacing method, and the full EMT simulation as the reference solution. The converters stations are initially operating in normal condition and is regulated with P=−100MW, Q=+100MVAR and Vdc=580kV. At 1.2s, a DC pole-to-pole fault occurs at the DC terminal of MMC-1. The current flows from the AC grid to the fault location and rises dramatically. 122 Converters are blocked 400s after to protect the IGBTs from over-current damage. The AC breakers are later opened at 1.24s to prevent further impact on the AC grid. Figure 5.16 Instantaneous waveforms from interfacing terminal located at bus-16. (a) Phase-A voltage; (b) Phase-A current. Figure 5.17 Instantaneous power injected from the AC system to the MMC at interfacing terminal located at bus-16. (a) Active power; (b) Reactive power. 123 Figure 5.16 presents the instantaneous voltage and current at the interfacing terminal at Bus 16 measured in the EMT subsystem. It can be observed that the voltage is dropped in amplitude while the current increases after the DC fault applied. A spike at 1.2004s indicates the blocking transient inside the converter. The proposed parallel-rate interfacing method is identical to the conventional sequential method. The results from the hybrid simulation is a little different from the reference waveform until the AC breakers are closed. The difference is due to the fact that the negative or zero sequence components in interfacing current can only simulate in full EMT simulation, whereas the hybrid simulation can only simulate a positive sequence component under fundamental frequency. Nevertheless, the results obtained using hybrid simulation is reasonably accurate to the EMT solutions. The differences in the voltage and current waveforms have a further impact on the calculation of the instantaneous powers. As shown in Figure 5.17, the waveforms match precisely well during steady-state operation. Once the DC pole-to-pole fault is applied, the active and reactive powers raise dramatically and slows down when the converter is blocked. The HVDC link is completely disconnected when the AC breaker is opened. As observed from Figure 5.17, the results from the traditional hybrid simulation and the proposed hybrid simulation are well matched. The waveforms obtained from the full EMT contains sequence components, which cannot be accurately represented in the TS simulator. However, the results obtained from the hybrid simulation still provide a reasonably accurate response to the EMT-side fault. Figure 5.18 demonstrates the RMS voltages at the interfacing terminal located at Bus-16 and Bus-20 from the TS subsystem. The RMS voltage for the full EMT reference is reproduced using the positive sequence analyzer. It is observed that the proposed parallel-rate hybrid simulation interfacing method can accurately model the DC-fault converter blocking behavior inside the EMT subsystem without compromising on the time delay. As seen in Figure 5.18, the proposed method shows better accuracy than the traditional hybrid simulation approach. The reason for that is the traditional hybrid simulation approach represents the EMT subsystem using PQ load. Under the severe circumstance, the measured active and reactive power cannot be accurately calculated using a positive sequence with the fundamental frequency. Therefore, the proposed method with Thevenin equivalent representation to the EMT subsystem can produce better accuracy. 124 Figure 5.18 RMS voltage waveforms from interfacing terminals. a) Bus-16; b) Bus-20. Figure 5.19 RMS voltage waveforms at generator buses. a) Bus-33; b) Bus-34. 125 Figure 5.19 presents the RMS voltage from the nearest generators. The results obtained from the full EMT reference show lower frequency oscillation due to the transient impact from the connected HVDC system. After the DC system is tripped, the generator is recovered to normal operation. The simulation results obtained using the proposed hybrid simulation method demonstrates satisfactory accuracy. This research analyzed the hybrid interfacing techniques for the TS-based AC system connecting to the EMT-based MMC-HVDC system. The traditional hybrid simulation with the PQ load equivalent circuit and sequential interfacing protocol can produce sufficiently accurate results for power-system-level simulation. However, the sequential interfacing protocol introduced computational resource vacancy, which requires one simulator to be idle while the other is in operation. On the other hand, the traditional parallel interfacing protocol allows parallel execution between the simulators, but the TS simulator has a time delay in responding to the EMT-side fault. This research proposed a parallel-rate method that improves the simulation accuracy and provides a more adequate representation of the EMT-side fault. The proposed method is developed based on the EMF voltage and the blocking equivalent circuit of the MMC. Once DC pole-to-pole fault is applied on the EMT-side system, TS is decoupled from the EMT system to remove the one time step delay. The proposed method is verified using a test system based on the New-England 39-bus system and a 2-terminal MMC-HVDC system. The proposed interfacing method demonstrates improved accuracy and enables the parallel interfacing between the TS and EMT simulator. 126 6 Concluding Chapter 6.1 Summary Due to the fast-growing renewable energy and long-distance power transmission technologies, developing numerically efficient models for the MMC-HVDC transmission system is very important for controller design and converter transient studies in a large-scale AC/DC system. In addition, modeling a large-scale AC/DC grid using the traditional EMT simulation tool has introduced computational challenges that need to be solved for the design and testing of the next generation power system infrastructure. On the other hand, modeling the power system with the TS program can provide the most efficient solution but lacks of detailed representation of the power electronic converters. This thesis focuses on developing the numerically efficient models for MMC-HVDC system and the interconnected AC/DC grid. This is achieved by the proposed average value models of MMC and the combined EMT and TS hybrid simulation method. Based on the comprehensive literature review, previous research works introduced various average value models of MMC. However, these models cannot represent the MMC with different submodule types. Hybrid simulation techniques were proposed to interface the AC grid and the Line Communicate Converter (LCC). But the interfacing technique between the AC grid and the MMC-HVDC system have not yet been addressed. Furthermore, the traditional sequential interfacing protocol introduces idle time to the hybrid simulation program, which slows down the overall simulation speed. This thesis proposes generalized MMC average value models and a new hybrid simulation algorithm to improve the abovementioned modeling limitations. The objectives introduced in sections 1.3 are achieved throughout this thesis as described in the following: The Objective 1, which provides an overview of the state-of-the-art average value models, is accomplished in Section 3.1 and 4.2. A comprehensive literature review of the state-of-the-art average value models is presented and concluded that the controlled-signal-based AVM and switching-function-based AVM of MMC have their drawbacks. For the state-of-the-art controlled signal-based AVM, Thevenin and Norton circuit equivalents are adopted to represent the external dynamics of the MMC. But complicated modifications on the AVM equivalent circuits are required to represent the MMC under blocking mode operation. The switching-function-based AVM simplifies the individual SM capacitor modeling using the arm equivalent capacitors while 127 preserving the converter arm dynamic behaviors. The switching-function-based AVM provides more accurate solution than the controlled-signal-based AVM and faster simulation speed than the detailed equivalent model. Since the individual SM capacitor dynamics are neglect, the switching-function-based AVM is not suitable for SM capacitor voltage balancing studies. Several observations on the limitations of the state-of-the-art AVMS of MMC are been discussed in the thesis. The Objective 2 is achieved in Section 3.2 and 3.3. In these sections, two average value models that can represent the blocking and de-blocking behaviors of the MMC with different submodule topologies are proposed. The proposed generalized AVM is developed based on the standard AVM and the concept of blocking module, but with a more generalized circuit structure to represent the transient behaviors of the blocking and de-blocking operations. The proposed unified-arm-module-based new AVM extends the concept of AVM and establishes a unified arm equivalent circuit structure for various operating modes and different submodule types. The approach provides the most straightforward circuit structure for implementation in commercial software packages and numerically efficient solution in representing the dynamics behavior of MMC. The Objectives 3 and 4 are accomplished in Section 4.3-4.5. Switching-function-based AVM improves the simulation efficiency compared to DEM, but also neglected the individual SM capacitor dynamics, which makes it not suitable to model some special operating conditions, e.g., the converter AC-side energization of the mixed half- and full-bridge SM-based MMC. Moreover, the state-of-the-art switching-function-based AVMs models can represent MMC with half-bridge SMs, but other SM types were not addressed. A more comprehensive generalized switching-function-based AVM is proposed in the thesis, where the proposed model can accurately represent the dynamic of MMC including the switching and conduction losses with different submodule types. Later on, the proposed generalized switching-function-based AVM and the DEM are extended into a combined modeling framework, where the model can be switched freely to either AVM or DEM mode during the dynamic simulation. This combined model framework offers the users much flexibility to choose the most appropriate modeling mode during the dynamic simulation. The Objective 5 is discussed in Section 5.1 and 5.2. The concept of hybrid simulation is first introduced for AC/DC grid integrated with MMC HVDC. The new interfacing techniques for TS 128 and EMT subsystems are implemented for an interconnected AC-MMC-HVDC test system. The dynamic simulation results have demonstrated that the accuracy of the proposed hybrid approach in interfacing two distinct simulation tools. Later on, a parallel interfacing method is developed based on the converter Thevenin equivalent circuit of MMC that is derived from the concept of AVM. The proposed parallel interfacing protocol can further improve the simulation efficiency while preserving simulation accuracy of the system dynamic responses during a large disturbance. In summary, the proposed modeling approaches are suitable for different applications depending on the scope of studies and aiming at the maximum simulation efficiency. For the detailed model, individual responses from submodule capacitors and IGBTs can be accurately represented, which makes it ideal for switching transient studies; however, the complicated calculation and excess computational cost limit its applications to a smaller size test system. The idea of a detailed equivalent model is to reduce the number of internal nodes of the MMC. It is suitable for voltage balancing and submodule-level failure studies, which require detailed insights into the behavior of the individual submodule capacitors. For the proposed generalized switching-function-based average value model, the dynamics from the submodule capacitors within an arm are been averaged out, in which the behavior is represented by an arm equivalent capacitor. It utilizes the switching-function and arm equivalent capacitor to represent the arm voltage in discretized equations. It is suitable for arm circulating current suppression control, arm-level failure testing studies. The proposed generalized average value mode presents the most ideal approach for power system-level study under both converter blocking and de-blocking mode. It is suitable for inner- and out-loop controller design, power system-level transient study, and converter external behavior study. However, the model is limited based on the assumption, which the energies are perfectly balanced between arms and submodules, and the internal waveforms are not accessible due to simplifications on the circuit. The hybrid simulation is the most efficient model for large-scale AC-DC grid, where the AC grid can be modeled by the TS simulator for the slow dynamic behavior study while the EMT simulator accurately represents the fast transient from the MMC-HVDC or other switching applications; however, the proposed hybrid simulation techniques are limited to positive sequence and fundamental frequency behavior in the AC grid. More advanced hybrid simulation interfacing techniques are available in recent research, where wider frequency ranged and other sequences can be considered for the TS subsystem. It is also noted that the proposed average value models can be included in the EMT subsystem to improve the simulation speed. 129 Together, this research presents a comprehensive study for the modeling approaches of the large scale AC-MMC-HVDC test system from various aspects. Different models are proposed allowing the users to perform the most efficient simulation for their scopes of the studies. 6.2 Future Work To conclude this thesis, several potential works based on the proposed research are discussed below: • Real-time Hybrid Simulation Based on Mixed CPU and FPGA Platforms Modeling a large-scale grid using the TS and EMT simulators can provide both system and device level behaviours of the test system with significant speed improvement. However, the interfacing is established in personal-computer-based environment, which its simulation speed is depended on the hardware performance. Therefore, real time application of hybrid simulation for control equipment testing is not available yet. Establishing hybrid simulation in a mixed CPU and FPGA platform provides an ideal solution for real-time applications. The TS simulator can be executed on the CPU environment, whereas the EMT simulator can be dispatched into the FPGA platform. Simulators are executed within their designated platform and exchanged data at the common time step. Exploring the interfacing sequence for the real-time hybrid simulation in the mixed CPU and FPGA platforms can be interesting and useful research direction. • Average Value Modeling of Hybrid Multilevel Converter Topologies Average value modeling provides a numerically efficient solution to the computational challenges introduced by the massive and simultaneous switching devices in the multilevel converters. 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[77] IXYS “Westcode IGBT Type T 00G E datasheet ” 01 . 136 Appendices Appendix A: Experimental Setup and Two-terminal MMC-HVDC System Experimental Setup Specifications Number of SMs per arm (N) 10 SM capacitance [mF] 5.0 Arm inductance [mH] 2.5 Arm resistance [Ω] 0.7 DC voltage (pole-to-pole) [V] 400 AC voltage (line-to-line) [V] 208 Inner current id, iq control kp = 0.33; ki = 8.33 Arm circulating current control kp = 10; ki = 150 MMC HVDC Configuration and Semiconductor Data [77] Converter Parameter Semiconductor Parameter Detailed Method Analytical Method Power Rating 1059 MVA Ron,IGBT Ron,diode 1.21 mΩ 1.07mΩ 1.14 mΩ DC-link Voltage 640 kV Vo,IGBT Vo,diode 1.82 V 2.27 V 2.05 V SM Capacitance 1 mF Eon,IGBT Eoff,IGBT 11 J 10.5 J 11 J 10.5J Arm Inductance 50 mH Erec,diode 2.8 J 2.8 J SM Voltage 16kV Vref 2.8kV 2.8kV NSM 40 Iref 1.8kA 1.8kA 137 Appendix B: CIGRE B4-57 MMC-HVDC Grid General parameters for CIGRE B4-57 MMC-HVDC Grid Test System [61]. Data1 pu E1 C2 A1, B2 C1, D1, F1 A1, B1, B3 Rated power 1 200MVA 400MVA 800MVA 800MVA 1200MVA Arm reactor 15% 116mH 58mH 29mH 29mH 19mH Converter Transformer X leakage 18% 139mH 69mH 35mH 35mH 23mH Rtfos 0.60% 1. Ω 0. Ω 0. Ω 0. Ω 0. Ω Vprim 1 145kV 145kV 380kV 145kV 380kV Vsecond 1 220kV 220kV 220kV 220kV 220kV Star point reactor Inductance - 5000H 5000H 5000H 5000H 5000H Resistance - Ω Ω Ω Ω Ω Sub-modules Number / half arm - 200 200 200 200 200 Individual capacitance - 2.5mF 5mF 10mF 10mF 15mF Ron 0.30% 5.445mΩ 2.722mΩ 1.361mΩ 1.361mΩ 0. 0 mΩ Schematic Diagram of CIGRE B4-57 MMC-HVDC Grid Test System [61]. 138 Appendix C: New England 39 Bus Interfacing with Two-terminal MMC-HVDC The schematic drawing of the test system. a). New-England 39-bus system; b) 2-terminal MMC-HVDC link. Parameters for Two-terminal MMC-HVDC [19]. Converter Parameter Transformer Parameter Power Rating 1000 MVA Power Rating 1000 MVA DC-link Voltage 580 kV Nominal Frequency 50 Hz SM Capacitance 1 uF Primary-side Voltage 345 kV Arm Inductance 48.89 mH Secondary-side Voltage 320 kV SM Voltage 58 kV Leakage Reactance 0.15 pu NSM 10 Leakage Resistance 0.0075 pu Parameters for New England 39 Bus System [76]. 139 Line data Number of bus Number of branch Slack bus Number of generator 39 46 39 10 MVA base V base Frequency 100 230 50 From bus To bus r x b 1 2 0.0035 0.0411 0.6936 1 39 0.001 0.025 0.75 2 3 0.0013 0.0151 0.2572 2 25 0.007 0.0086 0.146 3 4 0.0013 0.0213 0.2214 3 18 0.0011 0.0133 0.2138 4 5 0.0008 0.0128 0.1342 4 14 0.0008 0.0129 0.1382 5 6 0.0002 0.0026 0.434 5 8 0.0008 0.0112 0.1476 6 7 0.0006 0.0092 0.113 6 11 0.0007 0.0082 0.1388 7 8 0.0004 0.0046 0.078 8 9 0.0023 0.0363 0.3804 9 39 0.001 0.025 1.2 10 11 0.0004 0.0043 0.0728 10 13 0.0004 0.0043 0.0728 13 14 0.0009 0.0101 0.1724 14 15 0.0018 0.0217 0.366 15 16 0.0009 0.0094 0.171 16 17 0.0007 0.0089 0.1342 16 19 0.0016 0.0195 0.304 16 21 0.0006 0.0135 0.2548 16 24 0.0003 0.0059 0.068 17 18 0.0007 0.0082 0.132 17 27 0.0013 0.0173 0.3216 21 22 0.0008 0.014 0.2564 22 23 0.0006 0.0096 0.1846 23 24 0.0022 0.035 0.361 25 26 0.0032 0.0323 0.513 26 27 0.0014 0.0147 0.2396 26 28 0.0043 0.0474 0.7802 26 29 0.0057 0.0625 1.029 28 29 0.0014 0.0151 0.249 140 2 30 0 0.0181 0 6 31 0 0.025 0 10 32 0 0.02 0 11 12 0.0016 0.0435 0 12 13 0.0016 0.0435 0 19 33 0.0007 0.0142 0 19 20 0.0007 0.0138 0 20 34 0.0009 0.018 0 22 35 0 0.0143 0 23 36 0.0005 0.0272 0 25 37 0.0006 0.0232 0 29 38 0.0008 0.0156 0 Source Data index magnitude angle power.r power.i load.r load.i Node type 1 1 0 0 0 0 0 pq 2 1 0 0 0 0 0 pq 3 1 0 0 0 3.22 0.024 pq 4 1 0 0 0 5 1.84 pq 5 1 0 0 0 0 0 pq 6 1 0 0 0 0 0 pq 7 1 0 0 0 2.338 0.84 pq 8 1 0 0 0 5.22 1.76 pq 9 1 0 0 0 0 0 pq 10 1 0 0 0 0 0 pq 11 1 0 0 0 0 0 pq 12 1 0 0 0 0.075 0.88 pq 13 1 0 0 0 0 0 pq 14 1 0 0 0 0 0 pq 15 1 0 0 0 3.2 1.53 pq 16 1 0 0 0 3.294 0.323 pq 17 1 0 0 0 0 0 pq 18 1 0 0 0 1.58 0.3 pq 19 1 0 0 0 0 0 pq 20 1 0 0 0 6.8 1.03 pq 21 1 0 0 0 2.74 1.15 pq 22 1 0 0 0 0 0 pq 23 1 0 0 0 2.475 0.846 pq 24 1 0 0 0 3.086 -0.922 pq 25 1 0 0 0 2.24 0.472 pq 141 26 1 0 0 0 1.39 0.17 pq 27 1 0 0 0 2.81 0.75 pq 28 1 0 0 0 2.06 0.276 pq 29 1 0 0 0 2.833 0.269 pq 30 1.047 0 2.5 0 0 0 pv 31 0.982 0 5.63 0 0.092 0.046 pv 32 0.983 0 6.5 0 0 0 pv 33 0.997 0 6.32 0 0 0 pv 34 1.012 0 5.08 0 0 0 pv 35 1.049 0 6.5 0 0 0 pv 36 1.063 0 5.6 0 0 0 pv 37 1.027 0 5.4 0 0 0 pv 38 1.026 0 8.3 0 0 0 pv 39 1.03 0 0 0 11.04 2.5 vv Generator Data Gene type Gene index m xd2 xq2 xd1 xq1 xd xq tdd tqq td tq pv 30 84 0.02 0.02 0.031 0.031 0.1 0.069 0.04 0.04 10.2 0 pv 31 60.6 0.02 0.02 0.0647 0.0697 0.295 0.282 0.04 0.04 6.56 1.5 pv 32 71.6 0.02 0.02 0.0531 0.0531 0.2495 0.237 0.04 0.04 5.7 1.5 pv 33 59.2 0.02 0.02 0.0436 0.0436 0.262 0.258 0.04 0.04 5.69 1.5 pv 34 52 0.02 0.02 0.132 0.132 0.67 0.62 0.04 0.04 5.4 0.44 pv 35 79.6 0.02 0.02 0.05 0.05 0.254 0.241 0.04 0.04 7.3 0.4 pv 36 52.8 0.02 0.02 0.049 0.049 0.295 0.292 0.04 0.04 5.66 1.5 pv 37 48.6 0.02 0.02 0.057 0.057 0.29 0.28 0.04 0.04 6.7 0.41 pv 38 69 0.02 0.02 0.057 0.057 0.2106 0.205 0.04 0.04 4.79 1.96 vv 39 1000 0.02 0.02 0.006 0.006 0.2 0.019 0.04 0.04 7 0.7
Thesis/Dissertation
eng
Electrical Engineering
Vancouver : University of British Columbia Library
Attribution-NonCommercial-NoDerivatives 4.0 International
Graduate
Numerically efficient models of modular multilevel converters for high voltage direct current transmission system and AC-DC super grid
Text