Applied Science, Faculty of
Electrical and Computer Engineering, Department of
DSpace
UBCV
Chiu, Hsi Nien
Master of Applied Science - MASc
University of British Columbia
Novel advancements in silicon dangling bond (SiDB) fabrication has led to logical circuitry at the atomic scale, with crucial building blocks including binary wires and logic gates experimentally demonstrated on the SiDB platform. However, complex SiDB circuitry will require clocking control for signal propagation and timing. This work proposes the use of control and clocking electrodes commonly presented in quantum-dot cellular automata (QCA) implementations for the SiDB platform and introduces PoisSolver, a simulation engine used to obtain clocking potentials in a SiDB system with complementary metal-oxide semiconductor (CMOS) metal layers. PoisSolver is built into the SiQAD computer aided design (CAD) tool, aiding circuit design by visualising electric potentials and providing potential solutions to other built-in SiQAD simulation engines. Utilising PoisSolver’s output and the electrode design in SiQAD, geometry agnostic methods are employed to estimate power characteristics for QCA’s columnar, wave, and USE clocking schemes. Parasitic power densities of these clocking schemes are estimated to be on the order of 10-100μW cm⁻² at 1GHz and 77K. The potentially low power dissipation of SiDBs is extremely attractive for low power applications. As a result, a novel CMOS-to-SiDB flash analog-to-digital converter (ADC) proof-of-concept is designed using PoisSolver and SiQAD as a case study. A 2-bit implementation of the flash ADC is estimated to perform on par with thermal-noise limited CMOS ADCs in the worst case, and approximately four orders of magnitude better in the best case, depending on the elasticity of SiDB relaxations.
Simulation and Analysis of Clocking and Control forField-Coupled Quantum-Dot NanostructuresbyHsi Nien ChiuB. Applied Science, The University of British Columbia, 2017A THESIS SUBMITTED IN PARTIAL FULFILLMENTOF THE REQUIREMENTS FOR THE DEGREE OFMaster of Applied ScienceinTHE FACULTY OF GRADUATE AND POSTDOCTORALSTUDIES(Electrical and Computer Engineering)The University of British Columbia(Vancouver)April 2020c© Hsi Nien Chiu, 2020The following individuals certify that they have read, and recommend to the Fac-ulty of Graduate and Postdoctoral Studies for acceptance, the thesis entitled:Simulation and Analysis of Clocking and Control for Field-CoupledQuantum-Dot Nanostructuressubmitted by Hsi Nien Chiu in partial fulfillment of the requirements for the de-gree of Master of Applied Science in Electrical and Computer Engineering.Examining Committee:Konrad Walus, Electrical and Computer EngineeringSupervisorJoe Salfi, Electrical and Computer EngineeringSupervisory Committee MemberiiAbstractNovel advancements in silicon dangling bond (SiDB) fabrication has led to log-ical circuitry at the atomic scale, with crucial building blocks including binarywires and logic gates experimentally demonstrated on the SiDB platform. How-ever, complex SiDB circuitry will require clocking control for signal propagationand timing. This work proposes the use of control and clocking electrodes com-monly presented in quantum-dot cellular automata (QCA) implementations forthe SiDB platform and introduces PoisSolver, a simulation engine used to obtainclocking potentials in a SiDB system with complementary metal-oxide semicon-ductor (CMOS) metal layers. PoisSolver is built into the SiQAD computer aideddesign (CAD) tool, aiding circuit design by visualising electric potentials and pro-viding potential solutions to other built-in SiQAD simulation engines. UtilisingPoisSolver’s output and the electrode design in SiQAD, geometry agnostic meth-ods are employed to estimate power characteristics for QCA’s columnar, wave,and USE clocking schemes. Parasitic power densities of these clocking schemesare estimated to be on the order of 10-100 µWcm−2 at 1 GHz and 77 K.The potentially low power dissipation of SiDBs is extremely attractive for lowpower applications. As a result, a novel CMOS-to-SiDB flash analog-to-digitalconverter (ADC) proof-of-concept is designed using PoisSolver and SiQAD as acase study. A 2-bit implementation of the flash ADC is estimated to perform onpar with thermal-noise limited CMOS ADCs in the worst case, and approximatelyfour orders of magnitude better in the best case, depending on the elasticity ofSiDB relaxations.iiiLay SummaryRecent advancements have led to the pinnacle of circuit minimisation: the fabrica-tion of individual atomic scale silicon dangling bond (SiDB) quantum dots. Essen-tial computational building blocks have been demonstrated with this technology,with more complex designs requiring additional control. One approach to imple-ment this control utilises metal structures placed close to SiDB circuits. Voltageson these structures produce electric fields which in turn manipulate quantum dots.This work introduces PoisSolver, a tool enabling the investigation of controlfields generated by metal structures on the SiDB system. Results from PoisSolverare used to estimate power consumption and other bottlenecks for devices basedon SiDB technology. PoisSolver is also employed to design a novel device withconsiderable impact in neural network applications. This novel device exhibitsseveral orders of magnitude improvement over conventional designs, and is justone example of where a clocked SiDB device can bring substantial improvements.ivPrefaceThis thesis is an original work by Hsi Nien Chiu. The SiQAD computer aided de-sign (CAD) tool first mentioned in Section 3.3.1 is a collaborative project betweenthe members of Walus Lab, including Hsi Nien Chiu, Samuel S. H. Ng, and JacobRetallick, supervised by Dr. Konrad Walus. Details are published with the Instituteof Electrical and Electronics Engineers Transactions on Nanotechnology [SamuelS. H. Ng, Jacob Retallick, Hsi Nien Chiu, Robert Lupoiu, Lucian Livadaru, TaleanaHuff, Mohammad Rashidi, Wyatt Vine, Thomas Dienel, Robert A. Wolkow, andKonrad Walus. SiQAD: A Design and Simulation Tool for Atomic Silicon Quan-tum Dot Circuits. IEEE TNANO doi:10.1109/TNANO.2020.2966162]. KonradWalus is the principal investigator. Samuel S. H. Ng is responsible for the SimAn-neal simulation engine, the logical gate suites, and the analysis in the publication.Jacob Retallick is responsible for the HoppingDynamics simulation engine andmodelling of electron hoppig behaviour. Within SiQAD, Hsi Nien Chiu is respon-sible for the electrode design feature and electric potential simulation. KonradWalus, Samuel S. H. Ng, Jacob Retallick, Hsi Nien Chiu, and Robert Lupoiu con-tributed to the SiQAD interface and simulation engines as part of the Walus Lab.Robert A. Wolkow, Lucian Livadaru, Taleana Huff, Mohammad Rashidi, WyattVine, and Thomas Dienel provided measurement data and experimental analysisas part of Dr. Wolkow’s lab.Parts of Chapter 4 and Chapter 5 were accepted to IEEE NANO2020 [HsiNien Chiu, Samuel S. H. Ng, Jacob Retallick, Konrad Walus. PoisSolver: a Toolfor Modelling Silicon Dangling Bond Clocking Networks. arXiv:2002.10541], buthave yet to be presented. Konrad Walus is the principal investigator. The finiteelement method (FEM) potential solver PoisSolver was developed by Hsi NienvChiu, with guidance from Jacob Retallick on the derivation of the variational form.SimAnneal is the work of Samuel S. H. Ng.The ripple carry adder design in Chapter 5 is the work of Samuel S. H. NgChapter 6 overviews the design of an analog-to-digital converter (ADC), stemmingfrom discussions between Dr. Robert A. Wolkow of Quantum Silicon Inc. and themembers of Walus Laboratory. At the time of writing a manuscript based on thework presented in Chapter 6 is in progress. All figures are original except whenindicated otherwise.viContentsAbstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiiLay Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ivPreface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vContents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiList of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiList of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiiGlossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xivAcknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Background and Motivation . . . . . . . . . . . . . . . . . . . . 11.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Electric Field-modulated Field-Coupled Nanocomputing Structures 32.1 Silicon Dangling Bonds . . . . . . . . . . . . . . . . . . . . . . . 32.1.1 Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . 42.1.2 Electron Population and Device Operation . . . . . . . . . 52.2 Quantum Cellular Automata . . . . . . . . . . . . . . . . . . . . 72.2.1 Operating Principle . . . . . . . . . . . . . . . . . . . . . 7vii2.2.2 Analogies Between Molecular QCA and SiDBs . . . . . . 92.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Clocking Field-Coupled Nanocomputing Structures . . . . . . . . . 103.1 Multiple Phase Clocking . . . . . . . . . . . . . . . . . . . . . . 103.2 Clock Zones and Applications . . . . . . . . . . . . . . . . . . . 123.2.1 Information Transfer . . . . . . . . . . . . . . . . . . . . 123.2.2 Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.2.3 Packeting and Pipelining . . . . . . . . . . . . . . . . . . 133.3 Clocking Silicon Dangling Bonds Using Electrodes . . . . . . . . 133.3.1 Electrode Design in SiQAD . . . . . . . . . . . . . . . . 153.4 Clocking Floorplans as a Design Rule . . . . . . . . . . . . . . . 163.4.1 One Dimensional Columnar . . . . . . . . . . . . . . . . 173.4.2 Two Dimensional Wave . . . . . . . . . . . . . . . . . . 173.4.3 Universal, Scalable, Efficient . . . . . . . . . . . . . . . . 173.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 PoisSolver: a Finite Element Poisson’s Equation Solver . . . . . . . 204.1 Physical Model in a Three Dimensional Potential Solver . . . . . 204.1.1 Poisson’s Equation . . . . . . . . . . . . . . . . . . . . . 214.1.2 Boundary Conditions . . . . . . . . . . . . . . . . . . . . 244.1.3 Variational Form . . . . . . . . . . . . . . . . . . . . . . 244.2 Finite Element Solver Implementation . . . . . . . . . . . . . . . 254.2.1 Mesh Generation . . . . . . . . . . . . . . . . . . . . . . 254.2.2 Material Parameters, Boundary Conditions, and Nuances . 254.2.3 Numerical Solver Parameters . . . . . . . . . . . . . . . . 274.3 Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274.3.1 COMSOL Comparison . . . . . . . . . . . . . . . . . . . 274.4 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294.4.1 Physical Models . . . . . . . . . . . . . . . . . . . . . . 294.4.2 Clocking Scheme Potentials . . . . . . . . . . . . . . . . 324.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34viii5 Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 355.1 Clocking Network Power Draw . . . . . . . . . . . . . . . . . . . 355.1.1 Capacitance Estimation . . . . . . . . . . . . . . . . . . . 365.1.2 Resistance Estimation . . . . . . . . . . . . . . . . . . . 375.1.3 Power Dissipation of Four Phase Clocking Schemes . . . 395.2 Comparison to Other Power Costs . . . . . . . . . . . . . . . . . 445.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 PoisSolver Application: Analog-to-Digital Converter Design . . . . 496.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496.2 Analog-to-Digital Converter Design . . . . . . . . . . . . . . . . 506.2.1 Comparator Array . . . . . . . . . . . . . . . . . . . . . 506.2.2 Error Correction . . . . . . . . . . . . . . . . . . . . . . 546.2.3 Binary Encoding . . . . . . . . . . . . . . . . . . . . . . 566.2.4 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 566.2.5 Area Scaling . . . . . . . . . . . . . . . . . . . . . . . . 566.3 Power Comparison to Other Analog-to-Digital Converters . . . . 586.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637.2.1 Inclusion of Inductance in Power Estimations . . . . . . . 637.2.2 Solver Modularity . . . . . . . . . . . . . . . . . . . . . 647.2.3 Inspirations from Printed Circuit Board Layout . . . . . . 647.2.4 Parametrisation for Quick Preview . . . . . . . . . . . . . 647.2.5 Inclusion of Dielectric Non-idealities in Physical Model . 657.2.6 Automatic Layout/Reverse Potential Solver . . . . . . . . 65Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74A.1 Verification by Full Depletion Approximation . . . . . . . . . . . 74A.2 Capacitance Estimation Algorithm . . . . . . . . . . . . . . . . . 74ixA.2.1 Capacitance Matrices for Different Clocking Schemes . . 76A.3 Creating a Weighted Graph From Electrode Network Geometry . . 77A.3.1 Example results . . . . . . . . . . . . . . . . . . . . . . . 78A.4 Power Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . 79A.5 Nonlinear Step Size Selection . . . . . . . . . . . . . . . . . . . 80xList of TablesTable 3.1 Table of parameters for the system under consideration. . . . . 17Table 4.1 Numerical methods and preconditioners supported by PoisSolver. 27Table 6.1 Area of components required for a 2 or 4 bit SiDB ADC. . . . 57xiList of FiguresFigure 2.1 Fabrication of a single SiDB on the Si(100) surface. . . . . . . 4Figure 2.2 SiDB band structure and operation example. . . . . . . . . . . 6Figure 2.3 Ball-and-stick model of a three-state QCA cell using mixedvalence molecules. . . . . . . . . . . . . . . . . . . . . . . . 7Figure 2.4 QCA gates forming a universal set of gates. . . . . . . . . . . 8Figure 3.1 Normalised four phase clocking signals. . . . . . . . . . . . . 11Figure 3.2 Examples of simple clocked QCA and SiDB wires. . . . . . . 14Figure 3.3 Schematic and examples of buried and suspended electrodeclocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 3.4 Clocking scheme layouts as depicted in the SiQAD GUI. . . . 18Figure 4.1 Schematic of the SiDB model and clocking electrode system(not to scale). . . . . . . . . . . . . . . . . . . . . . . . . . . 22Figure 4.2 Columnar network meshes generated by Gmsh and COMSOL. 26Figure 4.3 Comparison between PoisSolver and COMSOL results. . . . . 28Figure 4.4 Time to solution of COMSOL and PoisSolver. . . . . . . . . . 29Figure 4.5 Surface potentials of a simple system using different physicalmodels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Figure 4.6 Comparison of surface potential between linear and nonlinearmodels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Figure 4.7 Bird’s eye view of single-tile clocking results for the columnar,wave, and USE clocking schemes. . . . . . . . . . . . . . . . 33Figure 5.1 Four phase circuit model of the clocking network. . . . . . . . 36xiiFigure 5.2 Resistive power frequency response normalised to clocking area. 40Figure 5.3 Comparison of results from simulation in SiQAD/PoisSolverand approximations from existing literature for two phase colum-nar clocking layouts. . . . . . . . . . . . . . . . . . . . . . . 42Figure 5.4 Four phase circuit model of the clocking network with induc-tances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Figure 5.5 Power dissipation in four phase circuit with inductance. . . . . 44Figure 5.6 Relaxation mechanism for the SiDB 0/- charge state transition. 45Figure 5.7 OR gate simulation using SiQAD. . . . . . . . . . . . . . . . 46Figure 5.8 SiDB ripple carry adder. . . . . . . . . . . . . . . . . . . . . 47Figure 5.9 SiDB population/depopulation model for power estimation. . 48Figure 6.1 Digital and mixed signal domain MAC accelerator architectures. 51Figure 6.2 Circuit diagrams for an error-corrected flash ADC. . . . . . . 52Figure 6.3 Schematic of a double well system formed by a SiDB pair withvariable bias via external SiDBs and electrodes. . . . . . . . . 53Figure 6.4 A cross section schematic and top-down view of the proposedSiDB comparator design. . . . . . . . . . . . . . . . . . . . . 55Figure 6.5 A complete ADC layout using SiDBs, with examples of basiccircuit building blocks. . . . . . . . . . . . . . . . . . . . . . 57Figure 6.6 Component scaling trends for the SiDB ADC. . . . . . . . . . 58Figure 6.7 ADC survey adapted from literature, in power density. . . . . 60Figure 6.8 ADC survey adapted from literature, in energy. . . . . . . . . 61Figure 1 Comparing internal voltages of an abrupt PN junction with theFEM solver and the full depletion approximation. . . . . . . . 75Figure 2 Transformation of electrode geometry to a resistance graph foran H-shaped resistor set. . . . . . . . . . . . . . . . . . . . . 77Figure 3 Mesh and circuit schematic for a parallel resistance referencestructure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Figure 4 The internal potential of a PN junction as obtained by the Newton-Raphson method for various step sizes. . . . . . . . . . . . . 81xiiiGlossaryADC analog-to-digital converterAFM atomic force microscopyCAD computer aided designCMOS complementary metal-oxide semiconductorFCN field-coupled nanocomputingFEM finite element methodFPGA field programmable gate arrayGUI graphical user interfacePCB printed circuit boardPDE partial differential equationQCA quantum-dot cellular automataSiDB silicon dangling bondSTM scanning tunneling microscopeUSE universal, scalable, efficientxivAcknowledgmentsI would like to thank Dr. Konrad Walus for his guidance and insight, and for theopportunity to work with the astonishing team that is the Walus Laboratory. I’dalso like to thank Jake and Sam, for their friendship and advice throughout thistime, making the lab more than just another workplace.I thank my mother, who has always encouraged me to pursue an education andtaken care of me throughout my life. I thank my sister for the healthy dose ofsibling rivalry, giving me the mental kick to better myself all these years.Finally, I thank Christina for her love and continued support. To her, I promisemany more years of carelessness and neglect.xvChapter 1Introduction1.1 Background and MotivationAs complementary metal-oxide semiconductor (CMOS) technologies continue tominiaturise and approach the physical limits of transistor fabrication, alternativecomputing architectures are garnering significant research efforts to further ad-vance the development of computing devices. One category of these beyond-CMOS technologies is known as field-coupled nanocomputing (FCN). FCN tech-nologies are unique in that they have the potential to process information withoutcharge transfer [1], setting them apart from conventional electronic devices. Oneemerging example of a FCN technology is the silicon dangling bond (SiDB) plat-form [2].Recent advancements in SiDB fabrication [3, 4] has enabled the implemen-tation of logical circuitry [2] created with atomic precision. On the SiDB plat-form, devices encode information using charge state configurations, and coupletogether through electrostatic repulsion and quantum tunneling effects [4]. Thisnovel platform demonstrates the ultimate step in silicon system miniaturisation,and can potentially realise the historically theory-bound quantum-dot cellular au-tomata (QCA) computational paradigm [5].To date, the SiDB platform has experimentally shown results for combinatorialdesigns [3]. Devices surpassing combinatorial complexity on SiDB devices (orany other platform) require data synchronisation to perform sequential tasks and1implement feedback paths. These behaviours are achieved in QCA using clockingsignals [6]. In the domain of molecular QCA, control signals have been proposedusing electrodes [7, 8], influencing QCA cell polarisations through electric fields.Although clocking control has been considered for other FCNs, it has yet tobe considered for the SiDB platform. The SiDB platform bears multiple proper-ties that make it attractive for electrode clocking. The silicon substrate makes theplatform compatible with long established lithography techniques. Modulation ofcharges on the SiDB surface [9] has been previously proposed using metal islands,suggesting electric field-based modulation as a potential control mechanism.The addition of metal layer electrode control on the SiDB platform can reveala completely novel design space for low area, low power applications. Beforethese electrode structures can be used alongside SiDB designs, their effects needto be better understood and characterised. This exploration into the use of clockingmechanisms on SiDBs extends to all electric-field based FCNs, and can potentiallypave the way towards high complexity, low power devices.1.2 OverviewIn this thesis, we explore the effect of control electrodes on the SiDB system andtheir consequences on common device metrics. Chapter 2 details the fabricationof SiDBs, shows examples of SiDB circuits in operation, and introduces the con-cept of clocking in the context of QCA. Chapter 3 discusses a possible approachto clock and control electric field FCNs, and shows three examples of electrodelayouts that result in infinitely scalable clocking schemes. Chapter 4 presents Pois-Solver, a finite element model used to numerically estimate clocking effects onthe SiDB system as a result of arbitrary electrode layouts. Chapter 5 investigatesthe power consumption of clocking electrodes, and compares these against esti-mated SiDB dissipations. Chapter 6 unites these concepts, proposing a designfor an extremely low power and low area mixed CMOS/SiDB analog-to-digitalconverter (ADC). Finally, the thesis is concluded and future research paths areproposed in Chapter 7.2Chapter 2Electric Field-modulatedField-Coupled NanocomputingStructuresFCN technologies [1] are novel approaches to binary computation built from theregular placement of bistable nanostructures. Logic operations are implemented asspecific arrangements of nanostructures coupled to one another through field ef-fects. Information is encoded using the bistable configuration of underlying struc-tures and are potentially processed without charge transport, which is expected todissipate less energy [10] than CMOS equivalents. Many FCN platforms have beenproposed, with magnetic and electric domains garnering the majority of researchinterest. Although each platform faces challenges in fabrication and physical reali-sation [1], recent advancements in nano-scale fabrication techniques have resultedin atomically-precise construction of silicon-based devices [2].2.1 Silicon Dangling BondsSiDBs present a potential platform for atomically precise beyond-CMOS devices,with area consumptions at the absolute limit of silicon-based device miniaturisa-tion. This section will cover their fabrication, operation, and provide a brief de-scription of ongoing efforts to model the physical SiDB system.3Figure 2.1: Fabrication of a single SiDB on the Si(100) surface. An STMtip is brought close to a target hydrogen atom, “plucking” the hydrogenfrom the dimer silicon atom. Lattice vectors are depicted and labelled.This figure is adapted from [13].2.1.1 FabricationThe fabrication of SiDBs begins with a hydrogen-passivated silicon surface. Thespecific surface targeted here is the silicon (100) surface as in [2], although SiDBscan also be created on other surfaces, such as the silicon (111) surface [11]. Thesilicon (100) surface possesses dimer rows, which serve as a natural grid for po-tential SiDB sites. Figure 2.1 depicts the fabrication of an individual SiDB on theSi(100) surface along with lattice parameters for SiDB sites. Using a scanning tun-neling microscope (STM), a voltage pulse is applied to hydrogen atoms until thehydrogen atom desorbs to the STM tip [2, 12]. The newly-bare silicon atom nowbears a SiDB.SiDBs can be imaged using both atomic force microscopy (AFM) and STMtechniques, each serving a different purpose. STM images of SiDBs in Figure 2of [3] reveal the location of hydrogen uncapped silicon dimers. AFM images in thesame figure clearly distinguishes between SiDB charge states with single-electroncharge sensitivity. This separability is associated to differences in attractive forcesbetween the AFM tip and the neutral/negative SiDB charge states [3]. STM imag-4ing can also show charge states of SiDBs [14], but difference between states is lessclear due to the STM tip interacting strongly with the SiDB during imaging [12],by way of tip induced band bending.2.1.2 Electron Population and Device OperationSiDBs can be viewed as quantum dots with singly (neutral), doubly (negative),or unoccupied (positive) charge states [15]. The transition levels between chargestates are located within the silicon bandgap [14], with SiDB occupation deter-mined by the position of the transition levels relative to the Fermi level. Thesetransition levels can be shifted using external biases to control the electron popu-lation of SiDBs [13]. Figure 2.2a illustrates the band structure of a SiDB, as wellas the shifted transition levels as a result of band bending. As the bands bendupwards (red) or downwards (blue) by external bias at the silicon surface, the tran-sition levels shift by the same amount. The SiDB undergoes a change in electronoccupation/population when a transition level crosses the Fermi level as a resultof band bending. Band bending has been experimentally observed by the STMtip [15, 16], with similar bias fields proposed for other FCN systems using metalelectrodes [7].One model for SiDB populations is detailed in [13, 17], where the silicon bulkis considered to be an electron reservoir. This reservoir supplies electrons to SiDBsbased on local band bending at SiDB sites. Under this model SiDB device oper-ation is dictated purely by the local potential due to nearby SiDBs and externalbiases, and involves bulk-SiDB and inter-SiDB electron transfer events as devicepopulations evolve in time.Charges on SiDB systems tend to occupy lowest energy configurations, typ-ically involving maximising distance between charged SiDBs. Taking advantageof this behaviour, SiDBs can be arranged into devices similar to logic gates. Fig-ure 2.2b shows a binary wire, where the presence of a perturber on the left biasescharges in SiDB pairs towards the right, and vice-versa, and is one example of aSiDB device that encodes binary data using charge configurations. SiDB circuitbuilding blocks including wires and OR gates have been experimentally demon-strated in [2–4], and a full suite of simulated logic gates is presented in [13].5CBVBSiVacuumCharge transition levelsw/o BBTransition levels w/upward BBTransition levels w/downward BBDB(0/-)DB(+/0)EnergyDepth(a) Band structure of a silicon dangling bond.Perturber 1Perturber0 1 nm(b) Straight SiDB wire.Figure 2.2: SiDB band structure and operation example. (a) illustrates theband structure of a silicon dangling bond. CV, VB, and ESiF are theconduction band, valence band, and Fermi level respectively. The Fermilevel here is close to the conduction band due to high n-type doping.DB(0/-) and DB(+/0) denote the transition levels between charge states,found within the silicon bandgap. (b) shows an example of a binary wirecreated using SiDBs biased from both sides. Figures adapted from [13].6Figure 2.3: Ball-and-stick model of a three-state QCA cell using mixed va-lence molecules. The left side depicts an “active” cell, with the chargesoccupying the top layer of quantum dots. The right side depicts an “in-active” or “null” cell, with charges occupying the lower quantum dots.The block above the molecule represents a bias source exerting a controlfield on the molecule.2.2 Quantum Cellular AutomataQCA is a binary computation architecture with a diverse ecosystem of existingliterature. This section will consider the operating principle of QCA componentsand discuss the a few of the many proposed forms of QCA.2.2.1 Operating PrincipleAlthough the specific implementation of QCA differs depending on the techno-logical platform, the fundamental computational unit can always be abstracteddown to the QCA cell. This unit cell, responsible for all the complexities ofQCA design, consists of two charges free to tunnel among quantum dots arrangedin a square [18]. In isolation, electrons in a QCA cell occupy degenerate anti-diagonal/diagonal configurations, denoted as the +1 and −1 polarisations respec-tively. Two-state representations of QCA [19,20] can be described by the two-stateintercellular Hartree approximation [21]. Three-state QCA representations havebeen presented in [22] using mixed valence molecules, as shown in Figure 2.3.QCA systems are assumed to evolve adiabatically, with cells continually track-ing the ground state throughout operation [23] barring potential error mechanismssuch as thermal excitation [21]. QCA cells can be controlled using an external7(a) QCA majority gate. (b) QCA inverter.Figure 2.4: QCA gates forming a universal set of gates. (a) depicts a majoritygate, and (b) depicts an inverter. Inputs are shown in yellow, and outputsin blue. Molecular QCA cells are shown here, using a pair of 3-statemolecules to form each cell.field, causing them to take “inactive” configurations. In two-state QCA represen-tations [19, 20] this is a superposition of the usual polarisations, while three-staterepresentations include a separate 0 or null configuration.QCA cells are typically placed in a grid, with inter-cell coupling controlled bythe distance and orientation between cells. Field interactions between cells can bedesigned to perform binary logic [24]. Majority voters and inverters exist on theQCA platform as shown in Figure 2.4, enabling arbitrary digital logic.QCA has been proposed on a number of technological platforms, with promis-ing results in the magnetic and electric domains. Magnetic implementations useNiFe nanostructures coupled through their magnetic fields [20], resulting in two-state antiferromagnetically coupled nanomagnets. Molecular QCA has been pro-posed with organic [19] and iron-based molecules [25], yielding two-state andthree-state QCA cells respectively. This work will focus on three-state molecu-lar QCA implementations due to their similarity to SiDBs.82.2.2 Analogies Between Molecular QCA and SiDBsMolecular QCA is in many ways analogous to devices on the SiDB platform. Bothare planar technologies, and exhibit high device density [3, 26] at potentially lowenergy cost [1]. Molecular QCA and SiDBs both interact by electric field-coupling,and device behaviours can be induced by the addition of an external field [7, 12].Specifically, SiDBs can be populated and depopulated by band-bending in-duced from external biases, such as an STM tip [17]. In this model electron ex-change occurs between SiDBs on the surface and the silicon bulk, with the bulk act-ing as a charge reservoir [13]. Similarly as three-state zwitterionic nido-carborane-based molecular QCA [27] is biased, charges move between the ±1 and the nullquantum dot sites. In this case, the null state site of molecular QCA is analogousto the bulk charge reservoir of the SiDB platform. Due to these similarities, controlstructures proposed in QCA are likely to be compatible with the SiDB devices.Previous works have considered control of molecular QCA using in-plane elec-trode structures, [27], but is limited to two-state QCA cells. It does not address theuse of clocking for three-state devices, and does not consider the use of the general,repeatable control layouts shown in QCA [28–30]. Other works considering three-state devices [8,28] do not appear to handle the systems in three dimensions, nor dothey consider any part of the electrode networks aside from the clocking faces. Thiswork considers a combination of QCA concepts and the SiDB platform as a casestudy. From QCA we borrow the idea of clock zones and clocking schemes [7, 8],and investigate their use on the SiDB platform. These clocking methods (detailedin Chapter 3) would prove useful to all electric field-based FCNs, not just QCAand SiDBs.2.3 SummaryIn this chapter, FCNs were discussed, highlighting SiDBs as a novel platform. Sec-tion 2.1 discussed the creation of SiDBs as well as methods to manipulate SiDBsto perform binary logic. Section 2.2 touched on QCA computational paradigm,and presented advantages for its implementation on the SiDB platform, notably thepossibility for metal-layer clocking. For this reason, we investigate clocking con-trol methods and their associated metal electrode networks on the SiDB platform.9Chapter 3Clocking Field-CoupledNanocomputing StructuresTo drive information through a FCN circuit and enable sequential devices withfeedback, we rely on a process called clocking. While in CMOS clocking is largelyperformed using flip-flops, FCN clocking involves the precise application of time-varying control fields. This type of clocking is often described in the context ofQCA, and can be extended to many FCN devices.3.1 Multiple Phase ClockingThe purpose of clocking a FCN circuit is to selectively activate and deactivateportions of a circuit to synchronise data and facilitate circuit operation. A commonmethod of clocking used in existing QCA circuit design is four phase clocking [18],which we also apply to SiDB designs. Four phase clocking splits a clock cycle intofour regimes, or phases, with each phase having a different effect on a QCA cells.This section will detail four phase clocking for the molecular QCA platform.The four phases of a clock cycle are unlatched, switching, latched, relaxing.During the unlatched phase, electric fields push charges to lower inactive sites,suspending the influence of unlatched cells on neighbours. Cells in the latchedphase have their top quantum dot sites occupied, with cells locked into their currentpolarisations and acting as temporary drivers. The switching and relaxing phases10Figure 3.1: Normalised four phase clocking signals. The piecewise linearclocking signal is commonly found in literature. This work consid-ers the use of sinusoidal clocking, which closely approximates the be-haviour of the piecewise linear clocking signal. Dashed vertical linesdenote multiples of pi/2.behave similar to each other, with the cell in a transition between active/inactive.Figure 3.1 shows the typical four phase clock signal used in QCA literature as wellas a sinusoidal clock signal that approximates the four phase signal. Switching,latched, relaxing, and unlatched phases refer to QCA clocking, while populating,occupied, depopulating, and vacant refer to SiDB clocking. Although clocking inliterature is most commonly performed with four phases, clock cycles can be splitinto any number of phases for finer control.113.2 Clock Zones and ApplicationsAs one might imagine, clocking an entire circuit with a uniform field would yieldno benefit in driving information flow. Maintaining and propagating informationthrough a circuit requires multiple clock phases to be simultaneously active on acircuit. For this purpose QCA circuits are partitioned into regions affected by thesame clock phase. These cell groupings are called clock zones. Using multipleclock zones, the relax, switch, latched, unlatched phases can each be simultane-ously active on a single circuit. These resulting clock zones are crucial for a num-ber of fundamental circuit actions.3.2.1 Information TransferIn general, clock zones a single phase apart are placed sequentially along a chainof devices. Examples are shown for both QCA and SiDB wires in Figure 3.2. InFigure 3.2a, a QCA wire under four-phase clocking is depicted. Devices transitionin sequence between the latched, relax, unlatched, and switch phases.With devices in the latched state acting as a temporary driver, devices enter-ing the switch phase further along the circuit now align themselves accordingly.Unlatched cells are inactive, and do not participate in computation. This processrepeats for each pair of adjacent clock zones until information has fully propagatedthrough a FCN circuit, and results in a computational rising edge or wavefront asdevices transition from switching to latched. Data is propagated along these wave-fronts as the circuit is clocked. A clocked inverting SiDB wire chain is shown inFigure 3.2b. SiDB and molecular QCA wires operate similarly, with the SiDB siteand silicon bulk analogous to the top and bottom sites of a molecular QCA cell,respectively.This selective activation/deactivation of circuit components has a number ofuses. It reduces interactions that would would result in unwanted signal trans-fer [29], discourages the formation of “kinks” (see Figure 3d of [3]) due to back-driving, and can be used to implement feedback paths [6].123.2.2 DelayDigital sequential circuits require signals to be synchronised for both stability andpredictability. In CMOS circuitry, signal timing uses flip-flops and a circuit-wideclock signal. On the SiDB platform, signal timing is implemented by using clockzones. By densely placing clock zones information transfer can be delayed relativeto other data paths, effectively “stalling” information while other data is prepared.[30] shows that the layout of clock zones can impact the required delay of a deviceby up to a factor of 3. One specific example of delays in application is in ripplecarry adders (Figure 3 of [31]), where lower significance bits are delayed whilemore significant bits are calculated.3.2.3 Packeting and PipeliningMetal wires have equipotential surfaces, and are limited to carrying one voltage ata time. CMOS architectures address this issue with pipelining: breaking the wireinto smaller sections separated by flip-flops, with each section carrying a differ-ent signal. QCA allows data packets to be transported along the same wire in amanner analagous to flip-flop pipelines. As the clock cycle progresses, wavefrontsare formed and propagate data along a circuit [32]. By placing clock zones moredensely along the wire, more wavefronts are present simultaneously, each capableof carrying data and creating a natural pipeline that improves throughput at thecost of latency. A length of QCA wire pipelined with two latched wavefronts isdepicted in Figure 3.2a.3.3 Clocking Silicon Dangling Bonds Using ElectrodesClocking control for electric field FCNs have been proposed as transverse elec-tric fields provided by electrodes [8]. Through conventional CMOS techniques,electrodes would be fabricated using metal layers for horizontal runs and vias forvertical stacks. These electrodes are placed within a dielectric material above thesilicon surface, and connected to a set of signal generators. As the clock operates,FCNs at the device level are influenced by the electric fields created by clockingelectrodes.In molecular QCA, the clocking signal controls the charge distribution of the13(a) Clocked QCA straight wire.(b) Clocked SiDB binary wire.Figure 3.2: Examples of simple clocked (a) QCA and (b) SiDB wires. (b)adapted from [13].QCA cell, shifting the cell between active and inactive charge configurations. WithSiDBs, clocking control modulates electrons between SiDB sites and the bulkreservoir. Although the effects and physical assumptions may differ between thetwo technologies, both can make use of the same clocking structures. A schematicof clocking control is shown in Figure 3.3a. By applying external potentials to theSiDBs, local energy bands are bent either upwards or downwards [33]. Upwardband-bending makes the SiDB site energetically unfavorable, and electrons returnto the bulk. Downward band-bending makes SiDB sites more energetically favor-able, and electrons occupy the SiDB. In this sense, the entire silicon bulk acts acharge reservoir, providing and accepting electrons to facilitate the occupation ofSiDB sites.Figure 3.3b and Figure 3.3c show two dimensional simulation results for elec-trodes suspended above the silicon surface and buried in the silicon bulk, respec-tively. Both scenarios exert influence on the silicon surface through electrostatics,with the buried case exhibiting lower fields due to the higher permittivity of silicon.Though either case can take advantage of silicon fabrication techniques, the buriedcase will likely exhibit leakage currents due to the metal-semiconductor junction,making suspended electrodes more physically practical.[27] raises clocking specificity as an issue in QCA clocking methods. Theyperform simulations on 2-state QCA systems, using both uniform and varying14(a) Schematic of electrodes imposing transverse clocking fields for SiDBs (not to scale).(b) Suspended electrode clocking. (c) Buried electrode clocking.Figure 3.3: Schematic (a) and simulations of suspended (b) and buried (c)electrode clocking. (a) Electrode labels represent the clock phase of theelectrode. Electrode phases are assumed to repeat horizontally. SiDBswith red dots are populated (activated) by the clocking fields, whileempty SiDBs are depopulated (deactivated). Potentials in (b) and (c)are obtained by a two dimensional FEM solver.fields along a single axis. They point out an overbiasing issue that occurs whensystems are horizontally clocked, a pitfall avoided here by clocking vertically. [27]also neglects fringe fields from clocking electrodes, while this work considers themin Chapter 4.3.3.1 Electrode Design in SiQADOne of the main contributions of this work builds upon SiQAD’s [33] existing fea-tures by adding electrode design capabilities to the design tool. In SiQAD, individ-15ual electrodes are implemented as collections of cuboids with arbitrary dimensions,and can be freely rotated about the aˆz unit vector (normal to the silicon surface).Electrodes can be specified with a clocking voltage profile, with arbitrary swing,offset, and phase shift. Complex geometries and larger electrode networks are cre-ated by stacking and overlapping electrodes. A built-in command line interface isalso available to facilitate precise, automated electrode placement in SiQAD.3.4 Clocking Floorplans as a Design RuleA majority of clocked QCA designs in literature use arbitrarily placed clock zonesin their circuitry [34], leading to irregular electrode placement and increased rout-ing complexity if they were to be implemented on the SiDB platform. Proposals ofQCA circuit designs with clock zones spanning a single QCA cell also exist [31],requiring unrealistic clocking resolution at the 1-10A˚ scale. Finally, changes madeto FCN circuit designs with arbitrary clock zones will likely be accompanied byedits to the clock zone placement, requiring a redesign of the underlying clockingnetwork. These clocking methods are not generally practical, and burden the FCNcircuit designer with the nontrivial task of electrode routing and placement.Instead of clock zones with arbitrary location and placement, one approachplaces clock zones in repeatable and tileable arrangements. The advantage of sucha placement is the ability to define a static floor plan of clock zones. As such,repeatable and tileable clocking schemes can be viewed as design rules definedprior to circuit design. With these clocking schemes in the background, designerstailor their circuits to a selected clocking floor plan without the need to explicitlydefine any clock zone placements or custom electrode networks.Tileable clocking schemes have been previously considered for systolic arrays[35]. [32] shows a surface potential implementing wire crossings and data loopsfor FCNs. These types of tileable implementations are particularly beneficial fordevices that exhibit regular data paths. However, for devices where informationtransfer is less regular, forcing a design constraint would only serve to enlargedesigns and increase delays. Fortunately, there is nothing that prevents the hybridadaptation of both design approaches, and we envision future designs to utilisetileable clock schemes alongside custom-tailored clock zones.16Parameter Symbol ValueMinimum metal pitch λ 53.7 nmMinimum metal width w 14 nmMinimum metal thickness t 10 nmTable 3.1: Table of parameters for the system under consideration.For this work, we consider tileable clocking schemes in order to generalisethe results to as many potential devices as possible. Single tiles of three differentclocking schemes are shown in Figure 3.4. The schemes are designed with geo-metric parameters in Table 3.1. The pitch and width parameters are based off a14 nm technology node [36]. The metal thickness is achievable through electronbeam physical vapor deposition, which has been shown to be capable of depositingthin films ranging from <1 nm to several µm [37].3.4.1 One Dimensional ColumnarThe columnar clocking scheme is the simplest tilable clocking scheme, varyingonly in a single dimension. Clock zones are placed sequentially along a single axis,taking on rectangular shapes [28]. These clock zones create one dimensional wave-fronts, useful for wires and simple feed-forward circuits. The electrode networkimplementing the columnar clocking sheme is straightforward and easily routed,and is shown in Figure 3.4a.3.4.2 Two Dimensional WaveThe wave clocking scheme [29] functions identically to the columnar clocking,except it is rotated 45◦ relative to the the QCA cell axes. As a result, clockingwavefronts move diagonally relative to SiDB sites, moving data both verticallyand horizontally along circuits, particularly useful for fanouts. The SiQAD layoutfor this scheme is shown in Figure 3.4b.3.4.3 Universal, Scalable, EfficientIn [30], the authors propose the universal, scalable, efficient (USE) clocking schemeto enable two dimensional feedback circuits. They also propose a specific imple-17(a) Columnar scheme (b) Wave scheme(c) USE schemeFigure 3.4: Clocking scheme layouts as depicted in the SiQAD GUI. Elec-trodes are colour-coded and labelled by phase, with numbers indicatingits relative phase shift in four-phase clocking. Arrows indicate the di-rection of data flow. (a) implements one dimensional clocking wave-fronts [28]. (b) sends clocking wavefronts both horizontally and ver-tically relative to the SiDB sites [29]. (c) generates two dimensionalclocking wavefronts and enables feedback circuitry [30].18mentation for the main clocking electrodes and the routing between them, shown inFigure 3.4c. Clock zones are placed such that feedback datapaths are created, im-proving data routing to four directions. Feedback paths also propagate seamlesslyto adjacent tiles, not just internally within a single tile.3.5 SummaryIn this chapter, we discussed a potential method to clock and control electric fieldbased FCNs. Multiple phase clocking was reviewed in Section 3.1, emphasisingthe popular four phase clocking system. In Section 3.2 the application of clockzones in fundamental operations such as information transfer and delay were ex-amined. Section 3.3 outlined a clear method to implement these clock zones usingmetal layers on the SiDB platform. Section 3.4 showed three examples of regular,infinitely tileable clocking floor plans and their corresponding electrode layouts.19Chapter 4PoisSolver: a Finite ElementPoisson’s Equation SolverWith the band-bending perspective for population modulation of SiDBs and theclocking networks in place, we now direct our focus to investigating the poten-tial induced on the silicon surface (and thus the SiDBs) by a particular clockingnetwork. For this task a three dimensional potential solver has been developed,dubbed PoisSolver [38]. PoisSolver is implemented as a simulation engine in theSiQAD ecosystem [13], a CAD tool undergoing development intended for simulat-ing SiDB systems. The use of PoisSolver in SiQAD is preferred over commercialphysics solvers such as COMSOL [39] or ANSYS [40] for its relative light weightand its connection to the SiQAD interface. Generally, PoisSolver makes use of de-signs in SiQAD, solving the Poisson’s Equation over the physical system using theFEniCS [41] and DOLFIN [42] finite element backend. This chapter details thesystem under investigation, describes the finite element model, and shows threedimensional potential results obtained by PoisSolver.4.1 Physical Model in a Three Dimensional PotentialSolverThis section depicts the system under consideration and the associated physicalmodel used in PoisSolver. The system under investigation consists of a silicon sub-20strate, SiDBs placed on the hydrogen passivated silicon surface, dielectric abovethe surface, and metal layer electrodes suspended in the dielectric, as depicted inFigure 4.1. The silicon substrate is nonuniformly doped, and a reference voltageplane is set deep within the silicon bulk. Although there are works that use Schot-tky contacts on the silicon surface to control SiDBs [9], this work will mainlyconsider the use of suspended rather than buried electrodes. This is to avoid anyleakage currents that would result from contacts (both Ohmic and Schottky, de-pending on metal selection and doping profile) between clocked electrodes and thesilicon bulk.4.1.1 Poisson’s EquationTo obtain a potential solution from the model in Figure 4.1, Poisson’s Equationis solved according to user defined parameters. Formally, PoisSolver solves thefollowing partial differential equation (PDE):−∇ · (ε(x)∇u(x)) = ρ(x) x ∈Ω (4.1)with dielectric constant ε , three dimensional potential u, spatial charge density ρ ,position x, and simulation domain Ω.The dielectric constant ε varies based on material, and is assumed to be uniformwithin a material. Although these values are simulation parameters, for systemsconsidered in this work ε is typically chosen to be:ε(x) = εr(x)ε0, εr(x) =11.7, if x ∈ΩSi3.9, if x ∈ΩSiO2 (4.2)Variations can be made to the charge density ρ in Equation (4.1) to alter thephysical representation of spatial charge density in the system. PoisSolver supports21Figure 4.1: Schematic of the SiDB model and clocking electrode system (notto scale), with SiDBs on the silicon surface on dimer sites. A close upvisualisation of the dimers and well as a dangling bond is included. Thesilicon bulk has an nonuniform doping profile, and the reference groundplane is set at the bottom of the substrate. Coloured blocks above thesilicon surface represent the electrode network. Geometric parametersinclude λ the minimum metal pitch, w the minimum metal width, hthe electrode height, tel the metal thickness, and tSi the bulk thickness.Induced clocking potentials are indicated with colours on the siliconsurface.22four definitions of ρ:LE: ρ = 0 (4.3)PE: ρ = q(ND−NA+ p−n) (4.4)PBE: ρ = q(ND−NA+nie−qukT −niequkT ) (4.5)LPBE: ρ = q(ND+2q2nikTu) (4.6)Laplace’s Equation (LE) is used in the case of an intrinsic silicon substrate. Pois-son’s Equation (PE) uses static definitions for p and n, the hole and electron con-centrations, accounting for a doped silicon substrate. The Poisson-BoltzmannEquation (PBE) extends PE by including charge migration effects. The LinearisedPoisson-Boltzmann Equation (LPBE) is valid for systems with small u, and is alsoknown as the Debye-Hu¨ckel approximation.For the doped SiDB system, the PBE is the most physically representative,capturing effects from the doped silicon bulk as well as the movement of chargedue to internal and external biases. However, the PBE is nonlinear and convergesslowly. The LE, PE, and LPBE charge density definitions are linear and convergemuch quicker, but also have their respective drawbacks and limitations. The LEdefinition accounts only for voltages as a result of electrodes. The PE definitionincludes the user defined doping profile, but neglects the migration of charge dealtwith by the PBE. The LPBE definition captures these effects, but is only valid forvalues of u where sinh(u) =eu− e−u2≈ u. In Section 4.4.1 we will show that, withsome additional approximations, the LE can be used to approximate the potentialat the silicon surface obtained by the PBE.234.1.2 Boundary ConditionsJust as important as the PDE are the boundary conditions.u= fD x ∈ ΓD (4.7)εn ·∇u= gN x ∈ ΓN (4.8)εn ·∇u+hRu= 0 x ∈ ΓR (4.9)u(x+ xp) = u(x) xp ∈ R3 (4.10)where ΓD, ΓN , ΓR are the boundaries for the Dirichlet, Neumann, and Robinboundary conditions respectively, with boundary parameters fD, gN , and hR. Pe-riodic boundary conditions are also supported as in Equation (4.10), with the pe-riodicity vector xp. Generally, PDEs can only be solved up to a constant withthe information in Equation (4.1). These boundary conditions provide uniquenessto the PDE solution by pinning u, ∇u, or a combination of both to a particularvalue at simulation boundaries. In the clocked SiDB system, the Dirichlet bound-ary condition can be used to force electrode surfaces to be isopotential, therebyimplementing clocked voltages.4.1.3 Variational FormTo solve the PDE using the finite element method (FEM), we pose the problem inits variational form. The PDE in Equation (4.1) can be expressed as:a(u,v) =∫Ωε∇u ·∇vdx+∫ΓRhRuvds (4.11)L(v) =∫Ωρvdx+∫ΓNgnvds (4.12)where a(u,v) is the bilinear form, L(v) is the linear form, andV is a function spacewith u,v ∈ V . This formulation is easily accepted by the FEniCS and DOLFINbackend, and can be paired with a mesh to obtain approximate solutions for u.244.2 Finite Element Solver ImplementationIn this section, we describe the implementation details of the FEM setup, and howuser parameters and the physical model are combined to numerically solve thePDE.4.2.1 Mesh GenerationTo create the mesh required to solve the PDE, we utilise Gmsh [43], an open sourcefinite element mesh generator. Gmsh is chosen for its abundant documentation andits support of the OPENCASCADE [44] geometry kernel, which aids in construct-ing simple geometries. First, the simulation space is defined as a cuboid, withdimensions based on the implemented electrode network design. Electrodes areintroduced as arbitrary closed polyhedrals within this space. The dielectric inter-face is added to the simulation as a two dimensional surface.After defining these geometries, the entire simulation space is meshed, andis now represented by a set of connected triangular mesh elements. Mesh ele-ments near geometric boundaries (electrode surfaces, silicon-dielectric interface,simulation boundaries) are forced to align to these boundaries. Furthermore, meshelement size is varied such that elements are smaller near material boundaries, andlarger within material bulk. This increases simulation resolution at areas of interestwhile decreasing resolution at others, lightening the computational burden of theFEniCS solver and better capturing physical behaviour.A wrapper has been developed around the Gmsh software suite to performall these tasks automatically, transforming SiQAD’s exported design file into acomplete mesh with boundary and domain definitions with the push of a button.4.2.2 Material Parameters, Boundary Conditions, and NuancesWith the mesh created, material domains and boundary conditions are defined toreflect the system model shown in Figure 4.1. Material domain definitions includethe dielectric constants and charge density profiles. Electrode potentials are im-plemented as Dirichlet boundary conditions, pinning the potential at electrodes toa constant value. The ground plane on the bottom side of the substrate is imple-mented as a zero Dirichlet boundary condition, serving as a potential reference.25(a) COMSOL-generated mesh(b) Gmsh-generated mesh (Columnar) (c) Gmsh-generated mesh (USE)Figure 4.2: Columnar network meshes generated by (a) COMSOL (b), (c)Gmsh. Vertical pillars are assumed to connect to signal generators.Wireframes of physical domains are hidden here for visual clarity. TheUSE scheme is also shown to demonstrate multiple stacked metal lay-ers.26Methods PreconditionersBiconjugate gradient stabilised Algebraic multigridConjugate gradient Incomplete CholeskyGeneralised minimal residual Incomplete lower-upperMinimal residual JacobiRichardson Successive over-relaxationTranspose free quasi minimal residualTable 4.1: Numerical methods and preconditioners supported by PoisSolver.The simulation boundary at the extreme above the dielectric interface is imple-mented as a Robin boundary condition. The remaining four simulation boundariesdepend on user specification. The model supports Dirichlet, Neumann, and Robinboundary conditions for arbitrary simulations, as well as periodic boundary condi-tions to mimic infinite tiling.4.2.3 Numerical Solver ParametersUsing the FEniCS backend, PoisSolver offers a variety of numerical solver meth-ods and preconditioners. The combined choice of solver and preconditioner di-rectly affects the time to solution and convergence. The available linear numericalmethods and preconditioners are shown in Section 4.2.3. If the selected PDE isnonlinear, then the problem step size is selected to suppress oscillatory artifacts, asin Appendix A.5.4.3 VerificationTo verify that PoisSolver is producing reasonable results, solutions are comparedto the full depletion approximation (refer to Appendix A.1) and COMSOL [39].4.3.1 COMSOL ComparisonFor verification of a three dimensional system, we compare results for a four elec-trode layout from both PoisSolver and COMSOL. The layout consists of a row ofelectrodes, with two electrodes set at±1V surrounded by two grounded electrodeson either side, all suspended above a silicon substrate in dielectric. Figures 4.3a27(a) PoisSolver (b) COMSOL(c) Difference (d) SchematicFigure 4.3: Comparison between PoisSolver and COMSOL results. The con-sidered layout consists of a row of electrodes, with two electrodes set at±1V surrounded by two grounded electrodes on either side. All elec-trodes are suspended above the silicon substrate in dielectric.and 4.3b show surface potentials for the system as found by each simulator. Fig-ure 4.3c shows the difference when comparing the two tools. PoisSolver and COM-SOL results are on the same order of magnitude, with a maximum 25% error.Timing benchmarks were also performed to compare the performance of Pois-Solver and COMSOL. Figure 4.4 shows the time-to-solution of both methods. Re-ported times include time taken to mesh the simulation geometry and time takenby the solver to obtain a 3D potential solution. PoisSolver was executed using thegeneralised minimal residual method. The time difference between PoisSolver andCOMSOL is mostly attributed to the meshing time. While it takes COMSOL’smeshing algorithm 16 s to generate the ∼400,000 element mesh, GMSH requiresonly 0.4 s. Time-to-solution scaling is similar between the two simulators.280 100x103 200x103 300x103 400x103Number of elements0102030405060Time to solution (s)Time to solution for PoisSolver in SiQAD vs COMSOLCOMSOLSiQADFigure 4.4: Time to solution of COMSOL and PoisSolver. Each data point ismeshed and computed until convergence 10 times, with the data pointshowing the mean solution time.4.4 ResultsHere the solver is demonstrated using the columnar clocking system, to show anexample of surface clocking potentials induced by a clocking network. Simula-tions are performed using each of the physical models presented in Section 4.1.1.Then, the solver is used to find the surface potentials due to the clocking schemesaddressed in Section 3.4.4.4.1 Physical ModelsTo assess the effects of each physical model in in Section 4.1.1, a test system isimplemented. For this system, the simulation boundaries are governed by Neu-29(a) LE (b) PE(c) PBE (d) LPBEFigure 4.5: Surface potential of a simple system using different physicalmodels. Although each physical model offers a slightly different poten-tial solution, all supported physical models exhibit at a general clockingwaveform at the silicon surface.mann boundary conditions, and a potential reference plane is placed at the bottomnegative z extreme.The simulations are then performed, yielding a three dimensional potentiallandscape for each of the four charge density definitions. Figure 4.5a, Figure 4.5b,Figure 4.5d are results for the linear LE, PE, and LPBE models respectively. Fig-ure 4.5c uses the nonlinear PBE.Each of the supported physical models converges under columnar clockingstimulus, with the difference between models being the potential swing and po-tential offset. A two dimensional slice of electric potentials at the silicon-dielectricinterface is extracted for each physical model, shown in Figure 4.5. Inspecting the30results, we find that the surface potential from the linear PE in Figure 4.5b is nearlyidentical to results from the nonlinear PBE in Figure 4.5c. An offset is added tothe LE result in Figure 4.5a to account for the built-in potential difference from thenonuniform doping profile, resulting in the augmented Laplace’s Equation (ALE).To estimate this potential offset, we start with the electron concentration in then-doped silicon bulk:n(x) = ND(x)+ni(x) (4.13)Since we expect no current flow between the clocking circuit and the siliconbulk, the current density at equilibrium inside the material can be expressed as:J = qnµn~E+qDndndx= 0 (4.14)with current density J, electron density n, and electric field ~E. With some re-arrangement of Equation (4.14) and the application of the Einstein relation, onearrives at:qkTdV =dnn(4.15)Integrating, we have:qkT(V1−V0) = ln(n1n0 ) (4.16)with the reference potential and reference electron density V0,n0. This providesa straightforward relationship between charge density and potential difference atdifferent points in a material. Figure 4.6 compares the difference in surface po-tential between the linear ALE and PE models against the nonlinear PBE model.After accounting for the potential offset using Equation (4.16), the ALE model inFigure 4.6a is found to bear the smallest error from the PBE at the silicon surface.31(a) ALE vs. PBE (b) PE vs. PBEFigure 4.6: Comparison of surface potential between linear and nonlinearmodels. Errors from the nonlinear PBE model are shown for the (a)ALE and (b) PE physical models respectively. The simulated system isdescribed in Section 4.4.1. The offset used in (a) is obtained using Equa-tion (4.16) with parameter set [n1,n0,T ] = [1019cm−3,1010cm−3,77K].4.4.2 Clocking Scheme PotentialsWith the solver verified and the results of the demonstration system shown, we nowsimulate the clocking systems with explicitly defined electrode networks. Ratherthan performing a possibly time prohibitive nonlinear simulation for the entire sim-ulation space, this section will use the LE model for charge desity to approximatesurface potentials. This approximation is sufficiently valid for potentials on thesurface, which are the active clocking potentials affecting SiDB sites.Figure 4.7 shows the clocking patterns of the columnar, wave, and USE schemesas depicted in SiQAD. The potentials shown are centered around the built-in dopingoffset to better illustrate potential wavefronts generated by the clocking schemes.For each clocking pattern, it is evident that the direction of information flow is asproposed in Figure 3.4.The potentials obtained by PoisSolver are returned to SiQAD for a numberof applications. Clocked potentials can be overlayed on top of SiDB designs tovisualise the influence of electrodes on the silicon surface. The result can alsobe used as an input to other simulation engines. Two examples of engines thatcan make use of surface potentials from PoisSolver are SimAnneal and Hopping-32(a) Columnar clocking pattern (b) Wave clocking pattern(c) USE clocking patternFigure 4.7: Bird’s eye view of single-tile clocking results for the columnar(a), wave (b), and USE (c) clocking schemes. Numbers denote electrodephases, and arrows indicate the direction of information flow. Colourmap shows the potential swing on the silicon surface obtained by Pois-Solver. Simulations assume periodic boundary conditions.Dynamics [33], both of which optionally use surface potentials to determine thebehaviour of SiDBs.334.5 SummaryThis chapter explored the process PoisSolver uses to extract a three dimensionalelectric potential using a graphical representation of a clocking scheme. Section 4.1discusses the PDE and boundary conditions that capture the physical behaviour ofthe system, and touches on the physical consequence of using different represen-tations for charge density. The implementation of the FEM solver is examinedin detail in Section 4.2. Section 4.3 demonstrates the validity of the solver, byreproducing the well known internal potential of a PN junction and comparingto commercial solvers. Finally, clocking patterns on the silicon surface due todifferent clocking schemes are demonstrated and compared in Section 4.4 usingPoisSolver’s main potential solving functionality.34Chapter 5Power ConsiderationsAs with all computing devices, SiDB and QCA circuits consume power duringoperation. In the model considered here, power dissipation is dominated by themanipulation of SiDBs [16, 45] and clocking electrodes. One of the advantagesof the SiDB platform over conventional CMOS lies in low power applications. IfSiDB devices are to be controlled using electrode networks, the power characteris-tics of both SiDB and clocking components need to be quantified to identify bottle-necks and limitations. This section investigates the power consumption of both theSiDB devices and the underlying electrode control system. The clocking networkis modelled as a resistive-capacitive circuit, and circuit parameters are estimatedfrom network geometry. Power consumption of SiDBs are estimated according toexisting literature and by a population/depopulation model.5.1 Clocking Network Power DrawOne method of characterising clocking networks is by quantifying power dissipa-tion due to parasitic nonidealities. Since a large draw of FCNs is their supposed lowpower consumption, the power dissipated in clocking networks is of utmost impor-tance. In order to obtain an estimate of parasitic power draws, a circuit model ofthe electrode network is created and analysed.To model the clocking electrodes, the electrode network is mapped to a circuitas in Figure 5.1. Each electrode is modelled by a sinusoidal signal generator with35Figure 5.1: Four phase circuit model of the clocking network. Each clockphase is connected to a separate generator with amplitude Vi. The totalresistance between the generator and the bottom most clocking elec-trode face (depicted by central nodes) is represented by Ri. Ci j rep-resents the self capacitance of each electrode network for i = j, andinterelectrode capacitances for i 6= j.voltage amplitude Vi and a resistor Ri in series. The capacitance Ci j denotes theelectrode capacitance to ground for i = j, and the interelectrode capacitances fori 6= j. Parameters depend heavily on geometry and material properties.5.1.1 Capacitance EstimationCapacitances can be estimated using a number of approximations, the most com-mon being the parallel plate approximation. However, arbitrary user designs maynot always be compatible with geometrical assumptions inherent to the approxima-36tion method. Rather than using an approximation for assumed geometry, we em-ploy a Maxwell capacitance field solver method [46]. In this method, one electrodeis raised to 1 V while all others are held at 0 V. The three dimensional potentiallandscape is solved and the resulting electric field is used to obtain the sympatheticcharges induced on each electrode via Gauss’ Law. These sympathetic chargesare then used to populate the Maxwell capacitance matrix, yielding interelectrodeand self capacitances. The process is then repeated for each electrode to obtain allcapacitive parameters in the system model.To verify that the method produces reasonable capacitances, estimation resultsare compared using a capacitor formed by two copper blocks 100 nm long, 10 nmwide, 10 nm thick, and spaced 100 nm apart. The Maxwell capacitance matrixresult is found to be within 5% of the result obtained with the parallel plate ap-proximation. Please refer to Appendix A.2 for details.5.1.2 Resistance EstimationTo estimate the resistance of the electrode network, an inverse Laplacian methodfor effective graph resistance [47] is implemented. From the electrode geometryprovided by SiQAD, each electrode is modelled as a series of connected resistors.An equivalent graph G(V,E) is constructed, with edges E, vertices V , and a setof weights over the edges W (e),e ∈ E. Physically, E represents the set of straightresistors, V represents the circuit nodes, and W (e) represents the conductance ofedge e.To represent directional connections between all vertices V , we use the signedvertex adjacency matrix U written as:U =U((a,b),c) =1 a= c−1 b= c0 Otherwisea,b,c ∈V (5.1)This matrix U , when combined with the conductance matrix W , encodes in-formation of the physical connections between vertices. With the matrix U and37conductances W , Ohm’s Law can be expressed in matrix form as:i=WUv (5.2)with current i along each edge and voltage v at each node. This formulation stillrequires knowledge of either i at each edge, or v at each node to be useful. Bychanging the control variable from the current at each edge to an external stimuluscurrent iext, the problem can be expressed as:iext =UT i=UTWUv=L (G)v, (5.3)iext =1 Source node−1 Drain node0 Otherwise(5.4)whereL (G) is the Laplacian matrix of G and iext is the external stimulus current.This expression is analagous to flowing 1 A of current from the source node to thedrain node through all edges e ∈ E. With iext and L defined as above, v can beobtained byv=L +iext , (5.5)where + denotes the Moore-Penrose matrix inverse (or pseudoinverse). Since iextis defined as a unity current (1 A entering the source node, and 1 A exiting the drainnode), the obtained voltage v between source and drain is numerically equal to theeffective resistance r, accounting for all possible paths from source to drain. Theseresistances can then be scaled for temperature dependence.For verification, two parallel electrodes are created in SiQAD and connectedat their ends. Their combined parallel resistance is calculated using the both resis-tivity equation and using the inverse Laplacian method. The resistance from theinverse Laplacian method is within 3% of the reference calculation. For details,please refer to Section 5.1.2.385.1.3 Power Dissipation of Four Phase Clocking SchemesThe four phase clocking schemes are investigated using the circuit model shown inFigure 5.1, with parameters obtained using the methods detailed in Section 5.1.1and Section 5.1.2. Power estimations are obtained using a frequency sweep of theresistive losses for each clocking scheme. Each layout is created according to theparameter set from Table 3.1, with SiO2 as dielectric, and copper electrodes. Con-ductors routing the clocking electrodes between the silicon surface and the phasegenerators are also included here, reaching a height of 50 nm above the siliconsurface.Starting from the circuit model in Figure 5.1, we convert all capacitances toimpedances at arbitrary frequency. With the exception of the four central voltages,all parameters of this circuit model are known. In order to obtain power dissipa-tion quantities from this model, the circuit needs to be solved. Four equations arewritten to describe the flow of current using nodal analysis:Va−V1R1=V1−V2Z12+V1−V3Z13+V1−V4Z14+V1Z11(5.6)Vb−V2R1+V1−V2Z12=V2−V3Z23+V2−V4Z24+V2Z22(5.7)Vc−V3R3+V2−V3Z23+V1−V3Z13=V3−V4Z34+V3Z33(5.8)Vd−V4R4+V3−V4Z34+V1−V4Z14+V2−V4Z24+V4Z44(5.9)Which can rearranged to:Y˜1 −1Z12−1Z13−1Z14−1Z12Y˜2 −1Z23−1Z24−1Z13−1Z23Y˜3 −1Z34−1Z14−1Z24−1Z34Y˜4V1V2V3V4=VaR1VbR2VcR3VdR4 (5.10)Y˜i =1Ri+4∑j=11Zi j(5.11)39Figure 5.2: Resistive power frequency response normalised to clocking area.The black vertical lines indicate the 1 GHz and 1 THz frequency mark.Horizontal lines indicate the power dissipation of each clocking lay-out at 1 GHz and 1 THz. The power draw of each clocking layout isestimated to be 13.4, 56.3, and 189 µWcm−2 for the columnar, two di-mensional wave, and USE schemes respectively at 77 K temperature,1 GHz frequency, and copper electrodes. These powers increase to 1-10 Wcm−2 at 1 THz.Performing a frequency sweep on the impedances, the central voltages aresolved, revealing the resistive power loss frequency response of the system.The simulation can be performed at arbitrary temperature. A temperature of77 K is selected for Figure 5.3 due to it being a easily accessible laboratory tem-perature (nitrogen). Other suitable temperatures include 4.4 K (helium) and 293 K(room). The temperature dependence of electrode resistivity is accounted for byinterpolation of data found in [48]. The temperature dependence of the dielectricconstant of SiO2 is neglected here, as it is on the order of 0.0001 K−1 [49].40Figure 5.2 shows the power consumed by the clocking network through resis-tive losses for each scheme. At the operating frequency of 1 GHz and temperatureof 77 K, the clock schemes dissipate power on the order of 10-100µWcm−2.Limiting factors on the maximum frequency of these clocking schemes includedissipated heat, transmission line effects, and microstrip signal injection. Consider-ing state-of-the-art cooling techniques capable of maintaining temperatures underheat fluxes of 1 kWcm−2 [50], these particular clocking networks are viable in therange of 1-10 THz range. For high frequency signals such as those proposed here,transmission line effects need to be considered when conductor lengths approachthe length of the signal wavelength [51]. Here we use the general rule of thumbthat transmission line effects are negligible if the conductor length is less than 110of the signal wavelength. Using the same geometrical parameters as in Table 3.1, itis estimated that transmission line effects are negligible up to roughly the 300 THzrange, well above the expected operating limit of the clocking network. In [52], theauthors experimentally demonstrate the successful injection of 0.1-1 THz signalson microstrip lines. Under these constraints, the clocking schemes are expected toperform up to the 1 THz range.Of the three schemes considered here, the columnar network exhibits the low-est power dissipation, while the USE network has the highest power dissipationat any particular operating point with the wave scheme sitting in between thetwo. These differences are likely due to each scheme’s routing complexity, withcomplex schemes resulting in higher inter-electrode capacitances. Estimates forthese capacitances are shown in Appendix A.2.1. The matrices in Equation (4)are mutual capacitance matrices, with self-capacitances on the diagonal and inter-electrode capacitances on all other elements.For the purpose of comparison, a two phase columnar network is implementedand simulated using SiQAD and PoisSolver. Simulation results from PoisSolverand from [28] are plotted in Figure 5.3. Conducting pillars connecting to powersupplies are neglected as in [28] for comparison. Using resistance and capacitanceparameters obtained by PoisSolver and a simple series RC circuit model, the resultsfrom [28] are reproduced. Changing the model to the one shown in Figure 5.1pruned to two phases results in a increase in power dissipation by a factor of 20. Asthe capacitance and resistance parameters are nearly identical, this discrepancy is41(a) Power comparison with [28](b) Pruned two phase circuit (c) Simple two phase circuitFigure 5.3: (a) Comparision between results from simulation in SiQAD/Pois-Solver and approximations used in [28] for two phase columnar clock-ing layouts. The length, width, distance, and pitch of the electrodesare 1000 nm, 50 nm, 50 nm, 100 nm respectively, as in [28]. The simu-lation is performed at 293 K with copper electrodes. Using the circuitmodel in (b), SiQAD/PoisSolver (blue) estimates power dissipation at1.40 mWcm−2 at 1 GHz. The model in (c) estimates power dissipationat 74.1 µWcm−2 and 74.0 µWcm−2 at 1 GHz using SiQAD/PoisSolver(green) and from [28] (red) respectively.42Figure 5.4: Four phase circuit model of the clocking network with induc-tances.attributed to the inclusion of the self capacitances to ground and the use of multiplephase generators.Lumped inductances can also be included in the simulation, using approxima-tions methods in [53]. The resulting circuit is shown in Figure 5.4, with inductanceelements included for each conductor. The inductance parameters are estimatedusing the rectangular bar approximation in [53]. Including these inductance effectssignificantly increases the amount of power lost in the network, as shown in Fig-ure 5.5, surpassing the 1 kWcm−2 threshold at the 10 MHz range. The fall-off afterthe 10 THz is attributed to the cutoff frequency of the inductive elements. However,the approximations offered in [53] assume wires have negligible cross section com-pared to their characteristic length, which is neither the case for these designs, nor43Figure 5.5: Power dissipation in four phase circuit with inductance.general for arbitrary designs. Comparisons to other power costs will be performedusing data in Figure 5.3, neglecting conductor inductance for the time being. In-stead, we propose inclusion of inductances as a future work in Section 7.2.1.5.2 Comparison to Other Power CostsThe power densities investigated thus far have been related to the clocking actionof the electrodes, and are separate from the power dissipated in individual SiDBs.One possible mechanism for power loss in SiDBs is through lattice relaxation afterelectron transfer events [45]. After a SiDB shifts from singly to doubly occupied,the buckling of the silicon dimer changes, moving the SiDB site [54]. This∼30 pmpositional shift between the nuclear arrangements has a “level deepening” effect[55] on the SiDB, and serves to further stabilize the occupied charge state [16,56].A depiction of this mechanism is shown in Figure 5.6.To find the power in a clocked SiDB system, Figure 5.9 considers a single44Figure 5.6: Relaxation mechanism for the SiDB 0/- charge state transition.The top row shows a schematic of the SiDB bearing silicon dimer, andthe bottom row shows relevant energy levels (both not to scale). The leftcase is a relaxed neutral SiDB. The center shows a SiDB at the momentof electron occupation, before the lattice relaxes. The right case is thenegative SiDB after relaxation. The difference in the host atom positionis approximately 30 pm [16]. The buckling angles for the neutral andnegative nucleus arrangements are 1.2◦ and 7.6◦ respectively [54]. E ijdenotes the energy for the SiDB with charge i and nuclear configurationj. µ is the chemical potential, and ELattice is the energy associated withthe lattice relaxation.SiDB over one clock cycle. The clock signal does work on the SiDB system inFigure 5.9b. In making the SiDB site less energetically favorable, the clock needsto raise the energy of the SiDB by at least µ +ELattice. Electrons are assumed tomove between the bulk and SiDBs through tunneling, which is an elastic process.The energy used to induce band bending by µ is not lost through clock cycles,and is analogous to polarising a dielectric in a capacitor. ELattice however, is fullydissipated in the worst case, and has been estimated to be on the order of 200 meV[16,45]. This clocking action occurs once per clock cycle for every single “active”SiDB in the design.45Figure 5.7: OR gate simulation using SiQAD. Inputs are applied from the topof the OR gate, with a designated output at the bottom. The occupationof the output SiDB mirrors the truth table of an OR gate. Figure adaptedfrom [13].To determine the number of active SiDBs in a design we inspect the SiDB ORgate [3] simulated in SiQAD [13], as shown in Figure 5.7. Including inputs, the ORgate has 9 SiDBs in total, with 5 of them occupied. A full suite of logic gates andtheir derivative devices are presented in [13], with each design showing roughly12 of all SiDBs being occupied and active. For an OR gate with 5 active SiDBsand relaxation energy of 200 meV, this SiDBs circuit is expected to exceed coolinglimits at just under 1 GHz. This is an overestimate, as the SiDB density of an ORgate is very high, and not representative of larger devices. A work-in-progressripple carry adder design is estimated to dissipate 100 Wcm−2 at 1 GHz.The OR gate power densities are on par with some CMOS devices [57, 58].However, even with the pessimistic power densities, SiDBs are able to achievemuch more with the same area and power budget due to the high device density ofthe SiDB platform.For comparison, we refer to Figure 11 in [59], which estimates the powerconsumption of a QCA cell a with variable kink energy. A QCA cell based onSiDBs has an area of roughly 5.3 nm2 [33]. Fully relaxing a QCA cell would meanrelaxing two SiDBs (two occupied SiDBs per cell), leading to a kink energy of400 meV. With a cooling limit of 1 kWcm−2 and 400 meV kink energy, the powertrend in [59] suggests a maximum operating frequency of 1 GHz, consistent withthe model in Figure 5.9.These pessimistic estimates are orders of magnitude larger than the power con-4610 nmFAFAS1A1B1A0B0Cin S0CoutFigure 5.8: SiDB ripple carry adder. This design exhibits 0.04 SiDBs/nm2.Design created by Samuel S. H. Ng.sumption of the clocking network. However, the exact nature of the power dissi-pated after SiDB electron hop and population events is not well understood. [60]suggests that electrons along SiDB wires hop as polarons (a combination of a de-fect state and a trapped electron), possibly mitigating lattice relaxation losses. Untilthese complex mechanisms are better understood, we rely on these estimations.5.3 SummaryIn this section various types of power dissipation present in the SiDB system areexamined. In Section 5.1.3, the power of the clocking network is investigated usinga circuit model. Using PoisSolver, the resistance and capacitance parameters of acircuit are characterised, and resistive losses of the resulting circuit are found tooverwhelm thermal cooling at 1-10 THz. Section 5.2 covers pessimistic estimatesof power dissipation due to SiDB relaxations, and are expected to be orders ofmagnitude larger than resistive dissipation throughout clocked operation. Shouldissues associated with power dissipation for SiDB devices be significantly reduced,the clocking network power draw may become the remaining bottleneck.47(a) Idle (b) Clock biased(c) Clocking relaxed(d) Lattice relaxingFigure 5.9: SiDB population/depopulation model for power estimation. (a)shows the case when no clocking field is applied, and the chemical po-tential of the system keeps the lone SiDB occupied. (b) shows a clock-ing field being applied until the SiDB site is depopulated, and the latticeat the now empty site relaxes. (c) has the clocking field vanish, onceagain populating the SiDB. (d) shows the lattice relaxation at the newlyoccupied SiDB.48Chapter 6PoisSolver Application:Analog-to-Digital ConverterDesignAs a simulation engine in a design tool, PoisSolver’s true value is in aiding circuitdesign. In this section, we apply PoisSolver as part of the SiQAD design workflowto create a SiDB ADC concept. Section 6.1 motivates the selection of the ADC asan application case study. Section 6.2 investigates the full ADC design its requiredcircuit components, presenting one possible approach to a SiDB ADC layout. Sec-tion 6.3 compares the estimated power of the ADC against CMOS designs fromliterature.6.1 MotivationAt present, advancements in deep learning research carries a significant financialand environmental cost. Developing a state-of-the-art natural language processingpipeline required over 4700 training runs, and costed $360,000 USD in GPU timeand electricity costs, generating 78,500 lb in carbon emissions [61]. The most com-putationally expensive part of deep learning networks is the multiply-accumulate(MAC) operations, and one method to reduce costs is to improve energy efficiencyand speed using dedicated MAC circuitry, or accelerators.49There are two major types of commonly proposed MAC accelerators: digitaland mixed-signal, depicted in Figure 6.1. Mixed-signal accelerators perform theMAC operation in the analog domain, using voltage inputs and resistive weights toyield an analog result represented in electrical current. Digital accelerators improveMAC operation by heavily reusing weight resources. This work will focus onaccelerators in the mixed signal domain.One such accelerator reported in [62] attributes over 80% of power dissipationto be consumed by ADCs. At such steep financial and environmental costs, thereexists a need for ultra-low power ADCs. Recent CMOS ADC designs report powerconsumption, power densities, and areas on the order of 1 mW, 10 Wcm−2, and10−3 mm2 respectively. Here we explore the design of an ADC using a system ofsuspended electrodes and SiDBs, to improve upon these metrics.6.2 Analog-to-Digital Converter DesignFor this application, we select the flash ADC for its efficiency at low resolu-tion [64]. Flash ADCs can be broken down into modules, consisting of a com-parator array, error correction, and an encoder. The comparator array is used tosimultaneously compare an input to a number of references, thereby approximat-ing its magnitude. Error correction is used to address any faults that might occurdue to SiDB sensitivity to changes in its surroundings. Finally, the encoder is usedto convert the output into conventional binary representation. Figure 6.2 shows ablock and SiDB schematic of a flash ADC.6.2.1 Comparator ArrayIn CMOS circuitry, a comparator is a device that determines whether an input is ata higher voltage than a given reference. Here we propose a SiDB based comparatorwithout the use the transistors.Consider a double well system created from a pair of SiDBs as depicted inFigure 6.3a. In the absence of biases the double well is balanced, and the electronhas no preference for occupation resulting in a degenerate polarisation. Placing anegative SiDB on either side of the double well upsets this balance, and the electronoccupies the site which maximises distance between negative sites [3]. This results50(a) Analog resistive crossbar.(b) Digital MXUFigure 6.1: Digital and mixed signal domain MAC accelerator architectures.(a) depicts the resistive crossbar, used in [62]. The MAC operation isperformed with voltage inputs and resistive weights, taking advantageof Ohm’s Law to obtain electrical current results. (b) depicts the ma-trix unit (MXU) in Google’s tensor processing unit (TPU) [63] design.Weights are shifted into the array, and the MAC operation is improvedthrough heavy reuse of weight resources.51(a) IC circuit schematic(b) SiDB circuit schematicFigure 6.2: Circuit diagrams for an error-corrected flash ADC. (a) shows theschematic using conventional integrated circuit components. (b) showsthe schematic of the ADC implemented on SiDBs. COM, IFO, FO,and CX stand for the comparator, inverted fanout, fanout, and crossoverrespectively.52(a) Double well system with SiDB biases.(b) Double well system with electrode biases.Figure 6.3: Schematic of a double well system formed by a SiDB pair withvariable bias via external SiDBs and electrodes. The circles repre-sent the SiDB sites, with empty dots, filled dots, and partially filleddots representing neutral, negative, and degenerate sites respectively.Each schematic shows three cases: with degenerate, right- and left-polarisations shown from top to bottom. Polarisations depend on localbias of SiDB pair, either by other SiDBs or electrodes. Voltages createelectric fields that attract or repel electrons, emulating the effect of anoccupied SiDB. The double well acts as a comparator, with its outputdetermined by the left or right polarisation of the SiDB pair.in a comparator that can discern between left and right biases on the SiDB pair. Toachieve a comparator with more input freedom, we propose applying these biasesusing electric fields from charged electrodes, similar to the electrodes discussed inChapter 3.53Figure 6.3b shows an example of the system with electrode induced biases.With an electrode on either side, the SiDB pair can be used as a comparator. Thetwo electrodes act as inputs, and generate electric fields that push or pull on the oc-cupying electron. Assuming the induced potentials at the SiDB sites only influencepolarisation and not population, an electron would prefer to occupy the SiDB withmore positive potential. To selectively bias circuit sections, a metal layer is intro-duced between the input electrodes and the SiDB pair to act as a form of electricalshielding. Cutouts are formed in this shielding layer to allow input electric fieldsthrough to SiDB sites, while mitigating unwanted interactions. This design can betiled horizontally, forming a comparator array that can simultaneously test an inputagainst multiple references.Figure 6.4 shows the proposed physical setup of the SiDB comparator alongwith a set of simulation results as shown in SiQAD. For each comparator in Fig-ure 6.4, the left electrode acts as a reference voltage, and the right electrode asthe measured input voltage. Interpreting the comparator array in Figure 6.4, themeasured input is more between −0.5 V and −1 V. This result can be improvedby simply adding more steps to the reference ladder, comparing the input againstmore voltage references.Results from the comparator are propagated using an inverting wire chain. Theinverting wire is selected to keep the comparator balanced, as placing a straightchain as shown in Figure 3 of [3] would unbalance the double well to one side,possibly corrupting the result. The output can then be passed from inverting wiresto straight SiDB chains once they are sufficiently far to discourage coupling andinteractions with the comparator pair.6.2.2 Error CorrectionFor devices as sensitive to their surroundings as SiDBs, error correction is neededto improve reliability of the ADC design. The error correction used here is knownas bubble correction [65], and corrects a type of false positive known as bubbleerrors. Under typical operation, the comparator array produces an output in “ther-mometer” code. The comparator array defaults to all logical 1’s with a null input,and trips low (starting from the lowest magnitude references) as the input changes54(a) Side view of SiDB comparator setup.(b) Bird’s eye view of the SiDB under different references.Figure 6.4: A cross section schematic (a) and top-down view (b) of the pro-posed SiDB comparator design. (a) shows the input electrodes andshielding layer suspended in silicon dioxide, and the SiDB device layerat the silicon surface. A cutout in the shielding layer to allows electricfields to pass through to SiDBs. (b) shows results for three reference/in-put pairs using PoisSolver and SimAnneal. An inverting wire chain thenpropagates the result from the input pair to the next circuit stage.55from 0 V to−Vref. A “bubble error” occurs in the paradoxical case that a high mag-nitude reference comparator falsely trips before its lower magnitude counterparts.The error correction module detects the invalid result from the comparator array isinvalid and ignores the bubble error, prioritising valid intermediate outputs.6.2.3 Binary EncodingThe encoder portion of the ADC prepares the binary output before it is passedfurther down the circuit. The specific encoder required depends on the representa-tion that the intermediate result is expressed in before conversion to binary. In thiscase, the error correction outputs a result in one-hot encoding, requiring a one-hot-to-binary encoder.6.2.4 LayoutThe 2 bit flash SiDB ADC layout is shown in Figure 6.5. This compacted designcontaining the necessary components and wire buffers occupies roughly 33000 nm2.Although the full design of the ADC is too large to reliably simulate, the behaviourof each component is verified on an individual scale using SiQAD. For a clockedADC, wire buffers can be stretched to accommodate clocking tiles as described inSection 4.4.2. The resulting stretched design occupies 62500 nm2, or 6.25×10−10cm2.6.2.5 Area ScalingOne prevailing concern for any circuit device is its area scaling. Table 6.1 showsthe number of components required for a 2 bit and 4 bit ADC, and the area growthas a result of increasing bit length. The last two rows of Table 6.1 presents the areaoccupied by components for 2 and 4 bit ADC designs, neglecting area from wirebuffers.An n bit ADC requires 2n comparators for the comparator array, and 2n− 1inverters and NAND gates for error correction. Increasing the encoder from 2 bitsto a 4 bits increases the area of the encoder by roughly 16 times, which suggests 22nscaling. The difference in scaling is attributed to the increased use of crossoversand fanouts, which behave similarly to logic gates on the SiDB platform. At low56Figure 6.5: A complete ADC layout using SiDBs, with examples of basiccircuit building blocks. A total of 479 SiDBs are used in this design.ComponentArea percompo-nent(nm2)Numberof SiDBsNumberneededfor 2 bitADCNumberneededfor 4 bitADCComparator 2786.48 12 4 16ErrorInv.fanout49.128 11 3 15correction NAND 36.97 6 3 15Encoding Fanout 67.14 12 1 5Crossover 104.70 22 1 28NAND 36.97 6 2 162 bit ADC ∼12000 145 (479)*4 bit ADC ∼50000 1219(∼5000)Table 6.1: Area of components required for a 2 or 4 bit SiDB ADC.* Number in brackets includes wires to connect components, and minimalbuffering.57Comparator Err. Correction Encoding ADC w/ wires010002000300040005000Number of DBs48 51 46479192 2557725000Number of DBs by component2-bit ADC4-bit ADCFigure 6.6: Component scaling trends for the SiDB ADC. SiDB counts foreach component do not include routing wires, only the number of SiDBsconsumed by fanouts, logic gates, crossovers, etc.. SiDB count for thefull ADC designs do include routing wires.bit lengths the comparators dominate the area budget, while at larger bit lengths theencoders are expected to dominate due to the exponential demand for crossoversand fanouts.6.3 Power Comparison to Other Analog-to-DigitalConvertersThis section compares the power characteristics of the implemented SiDB ADCto CMOS ADCs in literature. Figure 6.7 and Figure 6.8 compares the power den-sity and energy per sample for the present ADC and those investigated in [66].Figure 6.7 compares the power density of the present ADC designs with CMOSdesigns. The red (resistive) data points lie along a straight line, because they are58directly extracted from Figure 5.2 at the 20 GHz operating frequency.Figure 6.8 compares devices energy, and is extended to the yoctojoule range,includes results from the present SiDB ADC design, as well as commonly usedfigures of merit for comparison. This comparison is more representative of a de-vice’s capabilities, with over 80% of devices in [66] operating at under samplingfrequencies of 1 GHz. The power estimations of the SiDB ADC clocking networkis obtained using both the area of the layout and the power density obtained in Sec-tion 5.1.3. Plotted in red is the ADC power resulting from only resistive clockinglosses as modelled in Figure 4.7. This is the case if relaxation energies are com-pletely elastic, resulting in a power dissipation of 3.2 pW at 20 GHz. Plotted inblue is the ADC power including both full relaxation losses from Section 5.2 andclocking losses. This is the case if relaxation energies are fully dissipated, resultingin a power draw of 300 nW at 20 GHz. These estimations assume chemical poten-tial active SiDB count N2 = 450, relaxation energy ELattice = 200meV, and areaof 62500 nm2 (the ADC is stretched to fit a columnar clock zone). Additionally,the ADC addressed in [62] is plotted in light green. The energy per operation ofa digital CNN engine [67] is plotted in orange. This comparison between ADCsand CNN engines can be performed because ADCs are expected to dominate theaccelerator power budget.On this figure, the bottom right region is optimal, representing designs withboth low energy and high resolution. The green line is the Scherier figure of merit[68] bordering all CMOS ADC designs, which encapsulates an energy trend forthermal noise limited ADCs. The red and blue lines are the same Scherier figure ofmerit lines, shifted to pass through the 2 bit ADC data points. These lines closelymatch the trend of the SiDB ADC designs as the bit length is varied from 2, 4, and8 bits.In the best case where relaxation energies are conserved, SiDB ADCs performmany orders of magnitude better than CMOS counterparts. In the worst case whererelaxation energies are completely dissipated, SiDB ADCs perform roughly on parwith CMOS devices.59Figure 6.7: CMOS data points obtained from [66]. Red dots are clockingpower density, blue dots are SiDB power density.6.4 SummaryIn this chapter, PoisSolver was used with other built-in simulation engines in SiQADto aid the design of SiDB circuits. An ADC based on SiDBs and suspended elec-trodes was designed, using PoisSolver to investigate the electric fields generatedby electrodes and SimAnneal to determine electron configuration. The area scal-ing of the design was analysed, and the comparators were found to dominate areaat low bit lengths, while the encoders take over at large bit lengths. Then, the powercharacteristics were compared between the designed SiDB ADC and select CMOSADCs from literature. It is found that SiDB performance can range from on parwith CMOS to orders of magnitude better depending on the elasticity of relaxationenergy.60Figure 6.8: CMOS data points obtained from [66]. Coloured dots are datapoints added through this work. Lines represent the Scherier [68] figureof merit, relating accuracy to energy for thermal noise throttled CMOSADCs. The green line intersects the best performing CMOS ADC. Theblue and red lines intersect the proposed 2-bit flash SiDB ADC design.61Chapter 7Conclusion7.1 ConclusionIncreased effort in the research of FCNs has resulted in significant advancementsin the fabrication of SiDBs, resulting in a device design platform with potentiallyimmense impact in low power and low area applications. While essential devicebuilding blocks including wires and logic gates have been experimentally demon-strated on the platform, this only scratches the surface of this novel design space.For devices with complexity involving signal synchronisation, directional dataflow,and feedback, clocking control similar to that on the CMOS platform becomes nec-essary. Clocking signals on molecular QCA platforms have been proposed as earlyas [7] as electric fields generated by out-of-plane electrodes. Applying this idea ofelectrode clocking with QCA clock zone layout concepts, this thesis proposed theuse of clocking electrodes on the SiDB platform.To investigate and consider clocking and controlling SiDBs with suspendedelectrodes, PoisSolver was built on top of the SiQAD simulation ecosystem. Tak-ing advantage of the design capabilities of the SiQAD interface and combining itwith PoisSolver, tools were created to quantitatively characterise and visualise theeffect of electrode clocking on the SiDB surface. Furthermore, geometry agnosticmethods were implemented to estimate the power draw of such clocked devicesdue to resistive losses in the electrode network.The practicality of these tools were then demonstrated through the SiQAD de-62sign flow for a novel SiDB/CMOS mixed ADC. A novel comparator array was de-signed and verified using PoisSolver in tandem with SiQAD’s built-in simulationsuite. This comparator array was then integrated with existing SiDB logic gatesto obtain a CMOS-to-SiDB 2-bit flash ADC design. Power characteristics wereestimated for the ADC, accounting for possible elasticity in SiDB relaxations. Inthe completely inelastic case, the present ADC was shown to perform on par withstate-of-the-art CMOS ADCs, whereas the optimistic elastic case showed severalorders of magnitude improvement.From layout design to FEM simulation to device power analysis, this thesishas covered multiple aspects of electrode-based SiDB clocking and control. TheADC design that resulted from this work is but a single example of a clockedfield controlled quantum dot device. This work sets the stage for circuit designersand researchers to come, bridging the gap between theoretical FCN designs andpractical FCN circuits.7.2 Future WorkWhile this thesis focused on the implementation of PoisSolver and its applicationsin clocking network characterisation and circuit design, other applications and im-provements have been left for the future. Future works derived from this thesisshould improve PoisSolver’s capabilities, extend on SiQAD’s feature set, or a com-bination of both. In no particular order, a handful of research paths are identifiedbelow.7.2.1 Inclusion of Inductance in Power EstimationsOne improvement that can be made is to solve for the inductance of the conductorsby considering the magnetic fields in the system. The inclusion of inductances hasa significant impact on the approximated clocking power dissipation, as depictedin Figure 5.5. However, using geometric approximations is not guaranteed to beable to produce representative results for arbitrary designs. One approach wouldbe to implement a magnetic FEM solver alongside PoisSolver, taking advantage ofa shared mesh and other simulation resources.637.2.2 Solver ModularityChapter 4 mentions the use of Gmsh for finite element mesh generation and FEn-iCS as a solver in PoisSolver. One improvement to PoisSolver involves improvingFEM solver modularity. Rather than being forced to use a specific open sourcemesh generator or solver backend, a user might opt to provide a custom mesh orsolver. By changing the requirement from a meshing tool to a valid mesh, thesolver also subverts the need to generate meshes at each invocation. Abstractingthe FEM solver would provide users with direct control over the solver, essentialfor those developing physical models for non-SiDB platforms. Additionally, thesimulator would be futureproofed, should any existing dependencies become dep-recated. Examples of open source meshing alternatives include libMesh [69] andTetGen [70]. Both open source and commercial alternatives exist for the solverbackend, including FreeFEM [71], COMSOL, and ANSYS.7.2.3 Inspirations from Printed Circuit Board LayoutThe problem of laying out electrode networks with stacked and rotated metal layersis identical to the problem that printed circuit board (PCB) tools such as Protel andAltium Designer aim to solve. Looking at these industry standard tools, we cantake inspiration to improve PoisSolver and SiQAD. SiQAD could be extended toinclude geometrical design rules for electrodes, such as minimum metal width andminimum metal pitch, and design rule checks can be implemented to ensure thatdesigns adhere to all rules. Sophisticated placement and routing tools already existfor field programmable gate array (FPGA) and PCB applications [72], and similaralgorithms could be adapted to route electrode networks as well. Making use ofthe layered electrode definition, SiQAD could also export electrode networks as.gds files, for use with lithographic equipment. These features would benefitusers looking to fabricate clocking schemes through a photolithographic process.7.2.4 Parametrisation for Quick PreviewPoisSolver has been shown to create estimations for clock patterns with relativeease. However, for a user engaged in designing a clocking scheme it may be ben-eficial to see real-time previews of induced clock patterns and clock zones. Pa-64rameter sweeps can be performed with PoisSolver on electrodes parametrised inelectrode height, size, applied voltage, and electric permittivity. The results fromthese sweeps could then be used as a rough guideline for electrode layout, withthe effect of all electrodes simply superimposed. Computation of these approxi-mations would be extremely light weight, requiring only linear interpolation alongeach parameter axis. In this approach, full PoisSolver simulations only need to becalled after coarse placement of electrodes for fine tuning.7.2.5 Inclusion of Dielectric Non-idealities in Physical ModelPermittivities of material domains have thus far been expressed as purely real quan-tities. As a result, electric potential simulations in this work have excluded the ef-fect of losses in dielectric materials. Expressing permittivities in the complex do-main would additionally account for damping losses in dielectric materials due tothe inclusion of imaginary components. Although the official releases of DOLFINand FEniCS do not support complex expressions, a fork of DOLFIN known asDOLFINX does. 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Si, “Tetgen, a delaunay-based quality tetrahedral mesh generator,” ACMTransactions on Mathematical Software (TOMS), vol. 41, no. 2, p. 11, 2015.64[71] O. Pironneau, F. Hecht, A. Hyaric, and K. Ohtsuka, “Freefem,” URL:http://www. freefem. org, 2006. 64[72] V. Betz and J. Rose, “Vpr: A new packing, placement and routing tool forfpga research,” in International Workshop on Field Programmable Logic andApplications, pp. 213–222, Springer, 1997. 6472[73] “Dolfinx.” https://github.com/FEniCS/dolfinx. Accessed:2020-03-30. 6573AppendixA.1 Verification by Full Depletion ApproximationThis section verifies PoisSolver’s one dimensional results, comparing to the fulldepletion approximation. Restricting PoisSolver to one dimension, the familiar PNjunction system is implemented. The system consists of a bar of silicon, heavilyn-doped on one end, and p-doped on the other. This junction is modelled usingPoisSolver and the classical full depletion approximation, for a range of trial con-centrations. The trial concentrations are selected such that the depletion widthstays within the extremes of the implemented system. Internal potentials of thesePN junctions are shown in Figure 1. The results of the FEM solver closely matchthe depletion approximation, lending confidence to PoisSolver.A.2 Capacitance Estimation AlgorithmThis section explains the method used to estimate capacitance for the electrodenetwork by the Maxwell capacitance matrix method [46] as noted in Section 5.1.1.This method uses the matrix form of the voltage-capacitance equation,Q=CV (1)where Q andV are the surface charge and voltage vectors, andC is the capacitancematrix. These surface charges are obtained by using Gauss’ Law,∮ε~E ·dA= Qenc (2)741000 800 600 400 200 0X (angstrom)0.40.20.00.20.4Internal potential (Volts)Depletion approximationPoisson-Boltzmann equation(a) ND = 1E19cm−3,NA = 1E19cm−31000 800 600 400 200 0X (angstrom)0.40.20.00.20.4Internal potential (Volts)Depletion approximationPoisson-Boltzmann equation(b) ND = 1E18cm−3,NA = 1E19cm−31000 800 600 400 200 0X (angstrom)0.40.20.00.20.4Internal potential (Volts)Depletion approximationPoisson-Boltzmann equation(c) ND = 1E19cm−3,NA = 1E18cm−31000 800 600 400 200 0X (angstrom)0.40.20.00.20.4Internal potential (Volts)Depletion approximationPoisson-Boltzmann equation(d) ND = 1E18cm−3,NA = 1E18cm−3Figure 1: Comparing internal voltages of an abrupt PN junction with theFEM solver and the full depletion approximation. Each figure showsa different combination of doping concentrations ND and NA. Concen-trations are selected such that depletion widths stay within the physicalboundaries of the system.where dA is a surface element of the electrode, ε is the electric permittivity, Qenc isthe charge enclosed by A, and ~E is obtained as the gradient of the potential solutionfrom PoisSolver. Selecting V to be a basis vector, columns of C are systematicallyextracted as the resulting charge vector Q. This C matrix can then be triviallytransformed into the mutual capacitance matrix, yielding interelectrode and self-75capacitances. By the parallel plate approximation:C =εAd(3)with area A, spacing d, and permittivity ε , the capacitance of a set of electrodeswith 10 nm thickness, 10 nm×10 nm cross sectional area, and 100 nm spacing isestimated to be 3.45 aF. By the Maxwell capacitance matrix method, the capaci-tance is estimated to be 3.64 aF, a roughly 5% difference in approximation.A.2.1 Capacitance Matrices for Different Clocking SchemesBelow we employ the Maxwell capacitance matrix method to the four phase clock-ing schemes shown in Section 3.4. Capacitances are arranged as in the mutualcapacitance matrix: self-capacitances on the diagonal, and interelectrode capaci-tances on all other matrix elements. Only the upper halves are shown, due to thematrices being symmetrical.CColumnar =1.43 3.50 0.92 2.591.00 3.42 0.891.25 3.481.20×10−18F (4a)CWave =16.1 6.19 1.81 5.6317.8 5.92 1.7715.7 5.5816.8×10−18F (4b)CUSE =13.1 2.15 7.34 7.3914.9 7.49 7.3615.2 2.4110.2×10−18F (4c)(4d)76Figure 2: Transformation of copper electrode geometry to a resistance graphfor an H-shaped resistor set. Each node of the graph represents a junc-tion between electrode segments. Edges on the graph represent the con-ductance between the nodes that they join, with conductances as edgeweights. A virtual node is added between the top-most nodes to denotethe common connection to a clock generator, depicted here as node 0.A.3 Creating a Weighted Graph From ElectrodeNetwork GeometryThis section details the method of transforming a geometrical description of a elec-trode network to a weighted graph for the purpose of estimating effective resis-tances. The method chosen here is the inverse Laplacian effective graph resistancemethod, general enough to account for all practical electrode setups arising fromarbitrary placement. For the sake of illustration, consider an H-shaped electrodenetwork. Figure 2 shows a such an network in two dimensions, and its conductivitygraph counterpart.To begin constructing the graph, we define a set of nodes which will serve asend points of the estimated effective resistance. Nodes are placed at the centerof the highest and lowest faces of the electrode network geometry, representing77the connection to the generator and the main clocking face respectively. Finally,nodes are placed at junctions where metal layers contact, in descending electrodeheight. Following node construction, the main graph is started with the top mostnodes connected to a virtual generator node (node 0 in Figure 2), representing thecommon connection to a power supply.Edges are added to the graph representing physical conductors. This is per-formed considering individual conductor lengths in order of descending height.All nodes associated with ith electrode are identified, and edges are placed on asubgraph containing only nodes involving the ith electrode. Assuming an elec-trode with N nodes, this subgraph can be fully connected with N− 1 edges. Foreach pair of nodes, an edge is created on the subgraph for shortest distance nodepairs with no existing path on the main graph or subgraph. After N− 1 edges arecreated, the subgraph is merged with the main graph, and the process is repeatedwith the i+1th electrode.After this operation performed for all electrodes, weights for each edge aredefined according to the conductance of the electrode they represent. Formally,these conductances are expressed as:G=1R=Aρl(5)with the conductanceG, resistance R, cross sectional area A, length l, and resistivityρ . This yields the conductance matrixW , which is used in the method described inSection 5.1.2.A.3.1 Example resultsAssuming a rectangular doughnut as in Figure 3, the effective resistance betweenthe top and bottom faces are estimated by both the inverse Laplacian method anda manual parallel resistance calculation. By manual calculation, the resistanceis found to be 10.92Ω, while the inverse Laplacian method finds a resistance of10.69Ω. The inverse Laplacian method is found to reproduce the manual calcula-tion within 3%.78(a) Mesh representation.(b) Circuit schematic.Figure 3: The (a) mesh visualisation and (b) circuit schematic for the parallelresistance reference structure. Simple example for resistance estimationverification. The top and bottom bars are 30 nm long, and the side bars are100 nm long. All conductors have a cross-sectional area of 10×10 nm2.A.4 Power EstimationIn order to perform the power analysis in Section 5.1.3, the resistance and capaci-tance estimations are required to obtain parameters for Figure 5.1. Regular, tileableclocking designs are used for simulations in Section 5.1.3 with periodic boundaryconditions. Potential sources of error in these results can stem from errors in eithercapacitance or resistance models. Errors in capacitance estimation are rooted inthe electric potential solution, and can be improved by increasing simulation res-olution and applying suitable boundary conditions to the system. For resistances,errors can range from small errors due to the sequence that the graph algorithmplaces nodes, or larger errors due to the estimation only considering explicitly de-signed electrodes, neglecting potential lateral connections from adjacent tiles. Fortiled schemes, this results in an overestimation of resistance due to the exclusionof more paths between bottom-most field-generating nodes and top-most generator79nodes. Power estimations for tileable clocking schemes presented in this paper aretherefore pessimistic overestimations.A.5 Nonlinear Step Size SelectionIf the PDE to be solved by is nonlinear, PoisSolver will use the Newton-Raphsonmethod. Generally, the Newton-Raphson method is a root finding algorithm, takingthe form:xn+1 = xn− γ f (xn)f ′(xn) (6)with a function f , previous approximation xn, new approximation xn+1, and astep size factor γ . One nuance for this method is that γ must be sufficiently smallin order to accurately capture the behaviour of the system. If γ is too large, thealgorithm overshoots, and diverges from the true solution. Smaller values of γare more likely to converge, but also result in slower convergence times. Figure 4shows the effect of reducing the step size. The step size used in simulation isselected such that oscillatory artifacts do not appear for a standard PN junction.801000 800 600 400 200 0Depth (ang)1.51.00.50.00.51.01.5Potential (V) = 1.0 = 0.2 = 0.05Figure 4: The internal potential of a PN junction as obtained by the Newton-Raphson method for various step sizes. At equilibrium, the internal poten-tial of a PN junction is nearly flat at its physical extrema, with a transitionregion in the center where the p- and n-doped materials make contact. Us-ing relatively large values for the step size factor γ results in oscillatoryartifacts (blue curve) in the solution. Reducing γ suppresses oscillations(red and green curves) at the cost of convergence time.81
Thesis/Dissertation
eng
Electrical Engineering
Vancouver : University of British Columbia Library
Attribution-NonCommercial-NoDerivatives 4.0 International
Graduate
Simulation and analysis of clocking and control for field-coupled quantum-dot nanostructures
Text