"Applied Science, Faculty of"@en . "Electrical and Computer Engineering, Department of"@en . "DSpace"@en . "UBCV"@en . "Lei, Yubo"@en . "2015-07-30T22:45:45Z"@en . "2015"@en . "Master of Applied Science - MASc"@en . "University of British Columbia"@en . "In this thesis, the implementation of an adaptive digital control scheme and the development process to implement it for an existing analog controlled LLC resonant converter is presented. The goal is to improve the dynamic performance (aka control bandwidth) and the disturbance rejection ability of the closed loop system using digital control. A brief analysis of the experimented on LLC resonant converter and simulations of its control-to-output frequency response characteristics under different operating conditions are initially performed in order to show its non-linear behavior. Then the design process and requirements for both the digital and analog components to make the existing LLC converter compatible with a digital signal microcontroller is presented in detail. The digital signal microcontroller (DSC), ADC, DPWM, sampling period, interrupt service routine (ISR), and the 2P2Z digital compensator implementation will be overviewed. Analog components such as the voltage/current sensors, the VCO, and other analog interfacing components will also be presented. After that, the complete design process to achieve optimized digital compensators for several different operating points is presented. This design process introduces the method of using either the uncompensated loop-gain frequency response data collected empirically from the physical converter or from a PSIM simulation and then using MATLAB\u00E2\u0080\u0099s System Identification software toolbox to generate an estimated mathematical model based on frequency response data. A digital compensator is then designed based on the estimated mathematical model. A comparison between the PSIM simulation and the empirical data of the LLC converter\u00E2\u0080\u0099s plant frequency response for several different operating conditions is also presented. A digital adaptive compensator algorithm is implemented so that the most optimized compensator design for a given converter operating range is selected. The algorithm uses the output voltage and current to determine the operating point of the converter, which then access a software look-up-table (LUT) for the optimized compensator. A complete prototype is built to experimentally validate the digital design process and the performance results of a classical single compensator design is compared with the adaptive compensator design in order to show the benefits of the adaptive compensator control scheme."@en . "https://circle.library.ubc.ca/rest/handle/2429/54254?expand=metadata"@en . " IMPLEMENTING DIGITAL CONTROL TO IMPROVE CONTROL BANDWIDTH AND DISTURBANCE REJECTION ON A LLC RESONANT DC-DC POWER CONVERTER by Yubo Lei B.A., The University of British Columbia, 2012 A THESIS SUBMITTED IN PARITAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in The Faculty of Graduate and Postdoctoral Studies (Electrical & Computer Engineering) THE UNIVERSITY OF BRITISH COLUMBIA (Vancouver) July 2015 \u00C2\u00A9Yubo Lei, 2015ii Abstract In this thesis, the implementation of an adaptive digital control scheme and the development process to implement it for an existing analog controlled LLC resonant converter is presented. The goal is to improve the dynamic performance (aka control bandwidth) and the disturbance rejection ability of the closed loop system using digital control. A brief analysis of the experimented on LLC resonant converter and simulations of its control-to-output frequency response characteristics under different operating conditions are initially performed in order to show its non-linear behavior. Then the design process and requirements for both the digital and analog components to make the existing LLC converter compatible with a digital signal microcontroller is presented in detail. The digital signal microcontroller (DSC), ADC, DPWM, sampling period, interrupt service routine (ISR), and the 2P2Z digital compensator implementation will be overviewed. Analog components such as the voltage/current sensors, the VCO, and other analog interfacing components will also be presented. After that, the complete design process to achieve optimized digital compensators for several different operating points is presented. This design process introduces the method of using either the uncompensated loop-gain frequency response data collected empirically from the physical converter or from a PSIM simulation and then using MATLAB\u00E2\u0080\u0099s System Identification software toolbox to generate an estimated mathematical model based on frequency response data. A digital compensator is then designed based on the estimated mathematical model. A comparison between the PSIM simulation and the empirical data of the LLC converter\u00E2\u0080\u0099s plant frequency response for several different operating conditions is also presented. A digital adaptive compensator algorithm is implemented so that the most optimized compensator design for a given converter operating range is selected. The algorithm uses the output voltage and current to determine the operating point of the converter, which then access a software look-up-table (LUT) for the optimized compensator. A complete prototype is built to experimentally validate the digital design process and the performance results of a classical single compensator design is compared with the adaptive compensator design in order to show the benefits of the adaptive compensator control scheme. iii Preface The experiments presented in this thesis were performed on a commercially available power converter provided by Delta-Q Technologies. Furthermore, some of the analog components presented in this thesis were part of the original LLC converter design such as the VCO and gain inverter op-amp circuit. Some components were also modified from their original design to better fit the digital design needs such as the sensors. All the prototyping work done was at Delta-Q technologies laboratories. My contributions include implementing digital control on the pre-existing LLC resonant power converter (model: IC650), which involved collecting data necessary to model the converter, using MATLAB to produce estimated models, and programming the digital signal microcontroller to implement the adaptive control algorithm. iv Table of Contents Abstract ........................................................................................................................................... ii Preface............................................................................................................................................ iii Table of Contents ........................................................................................................................... iv List of Tables ................................................................................................................................ vii List of Figures .............................................................................................................................. viii List of Symbols ............................................................................................................................ xiii List of Abbreviations ................................................................................................................... xiv List of Units and Prefixes ............................................................................................................ xvi Acknowledgements ..................................................................................................................... xvii Dedication .................................................................................................................................. xviii 1 Introduction ............................................................................................................................. 1 1.1 Overview .......................................................................................................................... 1 1.2 Digital Control.................................................................................................................. 1 1.3 Motivation and Objective ................................................................................................. 4 1.4 Outline .............................................................................................................................. 5 2 Literature Review.................................................................................................................... 7 2.1 Resonant Converters ........................................................................................................ 7 2.2 LLC Resonant Converter ................................................................................................. 9 2.3 LLC Converter Design Specifications ........................................................................... 13 2.4 LLC Plant Frequency Response ..................................................................................... 14 3 Digital Design Infrastructure Components and Considerations ........................................... 19 3.1 Digital Design Infrastructure Overview ......................................................................... 19 3.2 Digital Components & Consideration ............................................................................ 21 3.2.1 Analog-to-Digital Converter (ADC) ....................................................................... 21 v 3.2.2 High Resolution PWM (HRPWM) ......................................................................... 22 3.2.3 Digital 2P2Z Compensator ..................................................................................... 25 3.2.4 Sampling Rate ......................................................................................................... 26 3.2.5 Interrupt Selection ................................................................................................... 30 3.3 Analog Components: Sensors & Filters & VCO ........................................................... 30 3.3.1 RC Low-pass Filter ................................................................................................. 30 3.3.2 Gain Inverting Op-amp Circuit ............................................................................... 33 3.3.3 Voltage Controlled Oscillator (VCO) ..................................................................... 33 3.3.4 Voltage Sensor ........................................................................................................ 34 3.3.5 Current Sensor ........................................................................................................ 36 4 Digital Controller Design Implementation Process .............................................................. 38 4.1 Overview ........................................................................................................................ 38 4.2 Frequency Response Data .............................................................................................. 39 4.2.1 Venable Frequency Response Analyzer ................................................................. 40 4.2.2 PSIM ....................................................................................................................... 44 4.2.3 PSIM vs Venable Frequency Response Data.......................................................... 47 4.3 MATLAB System Identification Process ...................................................................... 52 4.4 Compensator Design & Performance Results ................................................................ 60 4.4.1 MATLAB SISO Toolbox ....................................................................................... 60 4.4.2 Compensator Design ............................................................................................... 61 4.4.3 Compensator and Performance Results .................................................................. 67 5 Adaptive Digital Control Software Architecture .................................................................. 77 6 Experimental Validation & Results ...................................................................................... 81 6.1 Prototype Setup and Design ........................................................................................... 81 6.2 Experimental Data & Performance Results ................................................................... 82 vi 7 Conclusions and Future Work .............................................................................................. 93 7.1 Conclusions .................................................................................................................... 93 7.1.1 Considerations of Implementing Digital Design on an Existing Analog Controlled Converter............................................................................................................................... 93 7.1.2 Effectiveness of the Empirical Data Modelling Approach ..................................... 94 7.1.3 Performance Improvements with Adaptive Compensation Design vs Single Compensation Design ........................................................................................................... 94 7.1.4 Venable vs PSIM Frequency Response Data Accuracy ......................................... 95 7.1.5 Obtaining the Frequency Response Data More Quickly and Efficiently ............... 95 7.2 Future Work ................................................................................................................... 96 Bibliography ................................................................................................................................. 97 Appendices .................................................................................................................................. 101 Appendix A: TI C2000 Piccolo TMSF28035 Specifications .................................................. 101 Appendix B: PSIM Simulation Schematics............................................................................. 103 vii List of Tables Table 2.1 - Full-Wave rectifier compared to Full-Bridge rectifier ............................................... 11 Table 2.2 - LLC Converter Specifications and component values ............................................... 14 Table 2.3 - Voltage Plant switching frequency for various operating points ............................... 16 Table 2.4 - Current Plant switching frequency for various operating points ................................ 18 Table 3.1 - Conventional PWM resolution vs HRPWM resolution ............................................. 25 Table 3.2 - Sampling frequency, sampling period, # of cycles for 60MHz CPU ......................... 27 Table 3.3 - Summary of sample timings for different sample window values ............................. 28 Table 3.4 \u00E2\u0080\u0093 Percentage CPU utilization for the interrupt service routine implemented ............... 29 Table 4.1 - Compensation stability objectives .............................................................................. 61 Table 4.2 - Optimized adaptive compensator designs using MATLAB SISO for continuous time and converted into discrete-time using bilinear transformation with a sampling period of Ts=1/400kHz ................................................................................................................................. 68 Table 4.3 - Step Response Settling Times for Single Compensator vs Adaptive Compensator Design (Simulated) ....................................................................................................................... 74 Table 4.4 - Single compensator performance results (MATLAB Simulated) .............................. 75 Table 4.5 - Adaptive compensation performance results (MATLAB Simulated) ........................ 76 Table 6.1 \u00E2\u0080\u0093 Single digital compensator experimental performance results .................................. 85 Table 6.2 - Adaptive digital control compensation experimental performance results ................ 86 viii List of Figures Figure 1.1 - Simplified block diagram of power converter with digital signal controller .............. 2 Figure 2.1 - Series Resonant Converter (SRC) ............................................................................... 7 Figure 2.2 - Parallel Resonant Converter (PRC) ............................................................................ 8 Figure 2.3 - Series Parallel Resonant Converter (SPRC) LCC ....................................................... 8 Figure 2.4 - LLC Resonant Converter ............................................................................................ 9 Figure 2.5 - Full-Bridge & Half-Bridge switching circuits .......................................................... 10 Figure 2.6 - LLC Resonant Tank .................................................................................................. 10 Figure 2.7 - Full-Bridge (left) and Half-Bridge (right) rectifier ................................................... 11 Figure 2.8 - Typical LLC Converter DC gain characteristic ........................................................ 12 Figure 2.9 - LLC resonant converter basic design and component values ................................... 13 Figure 2.10 - LLC circuit setup for the plant control-to-output frequency response measurement....................................................................................................................................................... 14 Figure 2.11 - LLC Voltage Plant frequency response with Load=3.5\u00E2\u0084\u00A6 (PSIM Simulation) ....... 15 Figure 2.12 - LLC Voltage Plant frequency response with Load=7\u00E2\u0084\u00A6 (PSIM Simulation) .......... 16 Figure 2.13 - LLC Current Plant frequency response with Load=3.5\u00E2\u0084\u00A6 (PSIM Simulation) ........ 17 Figure 2.14 - LLC Current Plant frequency response with Load=7\u00E2\u0084\u00A6 (PSIM Simulation)........... 17 Figure 3.1 \u00E2\u0080\u0093 High-level block diagram of the digital control infrastructure for the LLC converter....................................................................................................................................................... 19 Figure 3.2 - Continuous to discrete signal conversion .................................................................. 21 Figure 3.3 - Limit cycle effect ...................................................................................................... 23 Figure 3.4 - Conventional generated PWM resolution calculation............................................... 23 Figure 3.5 - Micro edge positioner (MEP) concept ...................................................................... 24 Figure 3.6 \u00E2\u0080\u0093 Graphical representation of a 2P2Z IIR Filter with a saturation limit ...................... 26 Figure 3.7 - Processor bandwidth vs control code ........................................................................ 27 Figure 3.8 - ADC sequential sample timing ................................................................................. 28 Figure 3.9 - PWM signal low pass filtered to a desired analog signal .......................................... 30 Figure 3.10 - Decomposition of PWM signal ............................................................................... 31 Figure 3.11 - RC 3rd order low-pass filter ..................................................................................... 31 Figure 3.12 - Frequency response of RC 3rd order low-pass filter (PSIM vs Venable) ................ 32 ix Figure 3.13 - Gain Inverting Op-amp (Gain Inverter) .................................................................. 33 Figure 3.14 - NCP1395 VCO operating frequency range............................................................. 34 Figure 3.15 - Voltage Sensor for the Load ................................................................................... 34 Figure 3.16 - Voltage Sensor Frequency Response (PSIM) ......................................................... 35 Figure 3.17 - Current Sensor for the Load .................................................................................... 36 Figure 3.18 - Current Sensor Frequency Response (PSIM Simulation) ....................................... 37 Figure 4.1 - High Level Overview of Digital Controller Design Process .................................... 39 Figure 4.2 - Uncompensated loop gain frequency response components ..................................... 40 Figure 4.3 \u00E2\u0080\u0093 Venable Software Program Frequency Response Analyzer Control Menu Settings 41 Figure 4.4 - Venable uncompensated voltage loop gain with load=3.5\u00E2\u0084\u00A6 (physical measurement data)............................................................................................................................................... 42 Figure 4.5 - Venable uncompensated voltage loop gain with load=7\u00E2\u0084\u00A6 (physical measurement data)............................................................................................................................................... 42 Figure 4.6 - Venable uncompensated current loop gain with load=3.5\u00E2\u0084\u00A6 (physical measurement data)............................................................................................................................................... 43 Figure 4.7 - Venable uncompensated current loop gain with load=7\u00E2\u0084\u00A6 (physical measurement data)............................................................................................................................................... 43 Figure 4.8 - PSIM AC Sweep setting............................................................................................ 44 Figure 4.9 - PSIM uncompensated voltage loop gain with load=3.5\u00E2\u0084\u00A6 ........................................ 45 Figure 4.10 - PSIM uncompensated voltage loop gain with load=7\u00E2\u0084\u00A6 ......................................... 45 Figure 4.11 - PSIM uncompensated current loop gain with load=3.5\u00E2\u0084\u00A6 ....................................... 46 Figure 4.12 - PSIM uncompensated current loop gain with load=7\u00E2\u0084\u00A6 .......................................... 46 Figure 4.13 - Voltage Plant, Vout=48V & 36V, Load=3.5\u00CE\u00A9 (PSIM vs Venable) ....................... 47 Figure 4.14 - Voltage Plant, Vout=24V, Load=3.5\u00CE\u00A9 (PSIM vs Venable) ................................... 48 Figure 4.15 - Voltage Plant, Vout=66V & 48V, Load=7\u00CE\u00A9 (PSIM vs Venable) .......................... 48 Figure 4.16 - Voltage Plant, Vout=36V, Load=7\u00CE\u00A9 (PSIM vs Venable) ...................................... 49 Figure 4.17 - Uncompensated voltage loop gain, Vout=48V & 36V, Load=3.5\u00E2\u0084\u00A6 (PSIM vs Venable) ........................................................................................................................................ 49 Figure 4.18 - Uncompensated voltage loop gain, Vout=66V & 48V, Load=7\u00E2\u0084\u00A6 (PSIM vs Venable) ........................................................................................................................................ 50 x Figure 4.19 - Uncompensated voltage loop gain, Vout=42V & 36V, Load=7\u00E2\u0084\u00A6 (PSIM vs Venable) ........................................................................................................................................ 50 Figure 4.20 - Uncompensated current loop gain, Iout=13A & 10A, Load=3.5\u00E2\u0084\u00A6 (PSIM vs Venable) ........................................................................................................................................ 51 Figure 4.21 - Uncompensated current loop gain, Iout=9A & 7A, Load=7\u00E2\u0084\u00A6 (PSIM vs Venable) 51 Figure 4.22 - System identification toolbox main workspace (left) & data importing window (right) ............................................................................................................................................ 53 Figure 4.23 - System identification toolbox model estimation structure GUI (right) & model order selection (left) ...................................................................................................................... 54 Figure 4.24 - Uncompensated voltage loop gain, Venable data vs State-space estimation, Load=3.5\u00E2\u0084\u00A6 .................................................................................................................................... 56 Figure 4.25 - Uncompensated voltage loop gain, Venable data vs State-space estimation, Load=7\u00E2\u0084\u00A6 ....................................................................................................................................... 57 Figure 4.26 - Uncompensated current loop gain, Venable data vs State-space estimation, Load=3.5\u00E2\u0084\u00A6 .................................................................................................................................... 58 Figure 4.27 - Uncompensated current loop gain, Venable data vs State-space estimation, Load=7\u00E2\u0084\u00A6 ....................................................................................................................................... 59 Figure 4.28 - MATLAB SISO Tool Design GUI ......................................................................... 60 Figure 4.29 - Frequency response of: uncompensated loop gain, compensator, compensated loop gain ................................................................................................................................................ 63 Figure 4.30 - Frequency response of: compensated loop gain, sensitivity function, complementary sensitivity function .............................................................................................. 64 Figure 4.31 - Closed-loop reference step response ....................................................................... 65 Figure 4.32 - Continuous vs discrete compensator ....................................................................... 67 Figure 4.33 - Single compensation control voltage loop gain (Simulated) .................................. 69 Figure 4.34 - Single compensation control current loop gain (Simulated) ................................... 70 Figure 4.35 - Closed loop (Voltage Mode Control) reference step response with single compensator (Simulated) .............................................................................................................. 70 Figure 4.36 - Closed loop (Current Mode Control) reference step response with single compensator (Simulated) .............................................................................................................. 71 Figure 4.37 - Adaptive compensation control voltage loop gain (Simulated) .............................. 72 xi Figure 4.38 - Adaptive compensation control current loop gain (Simulated) .............................. 72 Figure 4.39 - Closed loop (Voltage Mode Control) reference step response with adaptive compensator (Simulated) .............................................................................................................. 73 Figure 4.40 - Closed loop (Current Mode Control) reference step response with adaptive compensator (Simulated) .............................................................................................................. 73 Figure 5.1 \u00E2\u0080\u0093 Adaptive control software architecture overview ..................................................... 77 Figure 5.2 - Background loop (BG) in charge of selecting optimal compensator for a range of operating points ............................................................................................................................. 78 Figure 5.3 - Interrupt service routine (ISR) control loop .............................................................. 79 Figure 6.1 - Experimental prototype lab bench setup for digital control of LLC converter ......... 81 Figure 6.2 - Experimental closed loop frequency response loop gain measurement setup overview using Venable ................................................................................................................ 82 Figure 6.3 - Single compensation digital voltage loop gain (Experimental Data) ........................ 83 Figure 6.4 - Adaptive compensation digital voltage loop gain (Experimental Data) ................... 83 Figure 6.5 - Single compensation digital current loop gain (Experimental Data) ........................ 84 Figure 6.6 - Adaptive compensation digital current loop gain (Experimental Data) .................... 84 Figure 6.7 \u00E2\u0080\u0093 Venable experimental data vs MATLAB simulation, Adaptive Compensation, Voltage Loop Gain, Vout=48V Load=3.5\u00E2\u0084\u00A6 ................................................................................. 87 Figure 6.8 - Venable experimental data vs MATLAB simulation, Adaptive Compensation, Voltage Loop Gain, Vout=36V Load=3.5\u00E2\u0084\u00A6 ................................................................................. 87 Figure 6.9 - Venable experimental data vs MATLAB simulation, Adaptive Compensation, Voltage Loop Gain, Vout=66V Load=7\u00E2\u0084\u00A6 .................................................................................... 88 Figure 6.10 -Venable experimental data vs MATLAB simulation, Adaptive Compensation, Voltage Loop Gain, Vout=54V Load=7\u00E2\u0084\u00A6 .................................................................................... 88 Figure 6.11 - Venable experimental data vs MATLAB simulation, Adaptive Compensation, Voltage Loop Gain, Vout=42V Load=7\u00E2\u0084\u00A6 .................................................................................... 89 Figure 6.12 - Venable experimental data vs MATLAB simulation, Adaptive Compensation, Current Loop Gain, Iout=13A Load=3.5\u00E2\u0084\u00A6 ................................................................................... 89 Figure 6.13 - Venable experimental data vs MATLAB simulation, Adaptive Compensation, Current Loop Gain, Iout=10A Load=3.5\u00E2\u0084\u00A6 ................................................................................... 90 xii Figure 6.14 - Venable experimental data vs MATLAB simulation, Adaptive Compensation, Current Loop Gain, Iout=9A Load=7\u00E2\u0084\u00A6 ........................................................................................ 90 Figure 6.15 - Venable experimental data vs MATLAB simulation, Adaptive Compensation, Current Loop Gain, Iout=7A Load=7\u00E2\u0084\u00A6 ........................................................................................ 91 Figure 6.16 - Venable experimental data vs MATLAB simulation, Adaptive Compensation, Current Loop Gain, Iout=6A Load=7\u00E2\u0084\u00A6 ........................................................................................ 91 xiii List of Symbols \u00F0\u009D\u0091\u008E\u00F0\u009D\u0091\u009B \u00F0\u009D\u0091\u009B\u00F0\u009D\u0091\u00A1\u00E2\u0084\u008E numerator coefficient of 2P2Z transfer function \u00F0\u009D\u0091\u008F\u00F0\u009D\u0091\u009B \u00F0\u009D\u0091\u009B\u00F0\u009D\u0091\u00A1\u00E2\u0084\u008E denominator coefficient of 2P2Z transfer function \u00F0\u009D\u0090\u00B6\u00F0\u009D\u0091\u009F Resonant Tank Capacitor \u00F0\u009D\u0090\u00B6\u00F0\u009D\u0091\u00A0 Series Resonant Tank Capacitor \u00F0\u009D\u0090\u00B6\u00F0\u009D\u0091\u00A0\u00F0\u009D\u0091\u009F Series Resonant Tank Capacitor for the Series Resonant Parallel Converter \u00F0\u009D\u0090\u00B6\u00F0\u009D\u0091\u009D\u00F0\u009D\u0091\u009F Parallel Resonant Tank Capacitor for the Series Resonant Parallel Converter \u00F0\u009D\u0091\u0093\u00F0\u009D\u0091\u0090 Cross-over Frequency \u00F0\u009D\u0091\u0093\u00F0\u009D\u0091\u009C Resonant Frequency \u00F0\u009D\u0091\u0093\u00F0\u009D\u0091\u00A0\u00F0\u009D\u0091\u00A4 Switching Frequency \u00F0\u009D\u0090\u00BA\u00F0\u009D\u0091\u009C Controller Gain \u00F0\u009D\u0091\u0094\u00F0\u009D\u0091\u009A Gain Margin \u00F0\u009D\u0090\u00BF\u00F0\u009D\u0091\u009A Magnetizing Inductor \u00F0\u009D\u0090\u00BF\u00F0\u009D\u0091\u009F Resonant Inductor \u00F0\u009D\u0091\u009B Transformer Ratio \u00F0\u009D\u0091\u0084 Quality Factor \u00F0\u009D\u0091\u0087\u00F0\u009D\u0091\u00A0 Sampling Period \u00F0\u009D\u0091\u0089\u00F0\u009D\u0091\u0090 Control Voltage \u00F0\u009D\u0091\u0089\u00F0\u009D\u0091\u00A0\u00F0\u009D\u0091\u009E Square Wave Voltage \u00F0\u009D\u009C\u0083\u00F0\u009D\u0091\u009A Phase Margin xiv List of Abbreviations 2P2Z Two Pole Two Zero AC Alternating Current ADC Analog-to-Digital Converter CLA Control Law Accelerator CPU Central Processing Unit DC Direct Current DPWM Digital Pulse-Width Modulation DSC Digital Signal Controller DSP Digital Signal Processing FLC Fuzzy Logic Control FRA Frequency Response Analyzer GUI Graphic User Interface HRPWM High Resolution Pulse Width Modulator IIR Infinite Impulse Response ISR Interrupt Service Routine LPF Low-pass Filter LSB Least Significant Bit MAC Multiply and Accumulate MEP Micro Edge Positioner MSPS Million Samples per Second OCP Overcurrent Protection OE Output-Error OVP Overvoltage Protection PI Proportional-Integral PID Proportional-Integral-Derivative PRC Parallel Resonant Converter PWM Pulse-Width Modulation RC Resistor Capacitor SISO Single Input Single Output SMPS Switch Mode Power Supply xv SOC Start of Conversion SPRC Series Parallel Resonant Converter SRC Series Resonant Converter VCO Voltage Controlled Oscillator ZVS Zero Voltage Switching xvi List of Units and Prefixes A Amperes dB Decibels Hz Hertz s Seconds V Volt W Watt \u00E2\u0084\u00A6 Ohm \u00E2\u0081\u00B0 Degree p Pico (10\u00E2\u0088\u009212) n Nano (10\u00E2\u0088\u00929) \u00C2\u00B5 Micro (10\u00E2\u0088\u00926) m Mili (10\u00E2\u0088\u00923) k Kilo (103) M Mega (106) xvii Acknowledgements I would like to express my sincere gratitude towards my university supervisor, Dr. William Dunford for his guidance throughout my graduate studies. Mainly, I would like to thank him for giving me the opportunity to pursue my interest in this rewarding field and his always welcome insights in both academia and life. I am very grateful for his patience and support. I would also like to thank Delta-Q for generously allowing me to use their lab space, equipment, and for their financial support. Most of all, I would like to thank the employees at Delta-Q. I would like to thank my industrial supervisors Chris Botting, Murray Edington, and Dr. Fariborz Musavi. I would also like to thank Delta-Q\u00E2\u0080\u0099s hardware team: Marian Craciun for his valuable time and experienced insight into real world applications, Deepak Gautam for all his kind help and guidance, and David Matalpi for all his help and hands-on expertise. Special thanks to Muntasir Alam for his friendship and support. Finally, I would like to thank all the Delta-Q employees I have had the pleasure of getting to know. Next, I would like to thank the Natural Sciences and Engineering Research Council of Canada (NSERC) for their generous financial support. I would also like to thank Mr. Brian Bella of the Faculty of Graduate Studies at UBC for his assistance with the NSERC IPS scholarship application. Lastly, I would like to thank my family and friends for their support over the years. To my parents, thank you for your endless love, support, and encouragement throughout my life. xviii Dedication Dedicated to my parents.1 1 Introduction 1.1 Overview Switch-mode power supplies (SMPS) drive many of today\u00E2\u0080\u0099s industrial applications because of their superior performance, efficiency, size, and cost [1], [2], [3]. The increased demand to provide tightly regulated voltage and current to the load has sparked interest in more advanced control algorithms for SMPS. Many applications demand strict regulation of output voltage or current while maintaining good dynamic performance during transients, which means voltage or current deviation should be small and settle to the reference value quickly [1], [4]. This requires a well-designed closed loop controller to give the system a high feedback loop bandwidth. However, achieving a high feedback loop bandwidth with analog components is challenging because converter characteristics change with varying operating conditions such as load, input voltage, and component variations [5]. This thesis presents the design process and implementation of digital control on a DC-DC LLC resonant converter in order to improve overall dynamic performance and disturbance rejection. In addition, although not the main focus of this thesis, it is still important to describe the LLC converter characteristics which will be presented in Chapter 2. 1.2 Digital Control Digital control of power converters offers many advantages over their analog counterparts. Digital control is more flexible, reliable, provides better integration, cost-effective, and less susceptible to noise [6], [7]. The following is a more detailed list of the advantages associated with digital control over analog control for power converter applications [1]: \u00EF\u0082\u00B7 The ability to implement sophisticated algorithms for increasing efficiency and dynamic performance of power converters. \u00EF\u0082\u00B7 The flexibility of reconfiguring control parameters without the need for changes in hardware. \u00EF\u0082\u00B7 Less susceptible to controller component variation and noise sensitivity. \u00EF\u0082\u00B7 Integration of multiple functionalities on one microcontroller helps reduce cost. Because of these benefits, digital control is becoming more popular in high frequency DC-DC converters. The transition from analog control to widespread digital control has been slow 2 because operating at high frequencies requires high performance processors, analog-to-digital converters (ADCs), and digital pulse-width modulators (DPWMs), all of which comes at a price. However, recent technological advances are making low cost high performance digital signal controllers (DSC) possible (a DSC is a microcontroller specially designed to provide fast signal processing abilities) [8]. There are also challenges to keep in mind when implementing digital control. Limited resolution of the ADC and DPWM leads to quantization errors, high frequency operations can result in low resolution DPWM that may lead to limit cycle oscillations, and a slow processor clock speed limits the control bandwidth of the system [8], [9]. ADCDigital CompensatorRefDigi al Square-Wave ModulatorDriverPower ConverterInputOutputDSC Figure 1.1 - Simplified block diagram of power converter with digital signal controller Figure 1.1 shows a simplified block diagram of a power converter being controlled by a DSC and some inner components of the DSC. The power converter output signal is fed into the ADC, which digitizes the signal. The digital signal is subtracted from the reference signal and the error is fed into the digital compensator for computation. The calculated value of the digital compensator is normalized and is fed into the digital square wave modulator, which can vary duty cycle or frequency. In [6], the author presents a method for digital voltage mode control on a nonresonant-coupled parallel resonant converter. It was found that the nonresonant-coupled parallel resonant converter\u00E2\u0080\u0099s control-to-out frequency response shape did not change much under different operating conditions. It was found that only the magnitude (or gain) of the frequency response changed. As a result, a gain-scheduled digital controller was proposed which adaptively varies the gain of the digital compensator in order to compensate for the changing frequency response of the converter under different operating conditions. The author used Saber simulation software to simulate the gain at the 10kHz point over the entire converter operating range and constructed a look-up-table of 32x32 gain value points for the different operating points. It was shown that 3 the gain-scheduled digital control method increased bandwidth performance by four times over a classical analog control approach while not compromising stability margins. The digital implementation however did result in higher sub-harmonic noise in the converter\u00E2\u0080\u0099s output compared with the analog implementation. The author claims such noise can be improved upon with a higher resolution digital PWM output. There is however, an issue with this control technique for LLC resonant converters. The non-resonant parallel converter can only operate above resonant frequency in order to achieve zero-voltage switching (ZVS). As a result, its frequency response characteristics do not have the double pole effect experience by LLC converters operating close to or below resonant frequency. That is to say, the LLC frequency response shape varies much more under different operating conditions. Therefore, simply changing the gain may not enough to ensure best performance. In [10], the author presents a digital control scheme for charging a capacitor using a high voltage output LCC resonant converter. The control scheme uses current control mode (for constant current charging) and voltage control mode (for constant voltage charging). A large signal state-space model of 18 operating points throughout the charging cycle was developed using a generalized averaging modeling method with MATLAB. The author implemented a gain-scheduled PI controller for each operating point where the output current was used as the gain-scheduling variable for determining the correct gain value. It was found that the transition from current control mode to voltage control mode during the charging cycle produces a large step change because the difference between the output voltage and reference voltage was large. As a result, the control loop will introduced to a large step change, which would introduce a large voltage overshoot. The author\u00E2\u0080\u0099s solution to this issue is to add an adaptive first order low-pass voltage reference filter in order to ensure no overshoot during the transition. The adaptive filter adapts the voltage level of the current to voltage mode transition and adapts the filter corner frequency to the rate of the voltage rise measured for a given load with a constant current. A disadvantage in adding this extra filter is the sacrifice in rise time (or bandwidth) of the control system. In [11], the authors implements and compares a digital PID and fuzzy logic controller (FLC) on a half-bridge DC/DC LLC resonant converter. The inputs to the FLC are the error, the difference of error, and the sum of error and they are divided into nine triangular membership functions with a total of 81 rules. Each rule consists of a weighting factor and the degree of 4 change of switching frequency. The authors\u00E2\u0080\u0099 simulation and experimental results indicated that the fuzzy logic controller was able to achieve faster dynamic response in comparison with the PID controller. A load variation experiment showed that the output voltage responded to a step change in load in about 15ms for the PID controller whereas the fuzzy logic controller responded to the same step change in about 5ms. In [12], the author presents an adaptive digital PID control scheme in order to improve the dynamic performance of power converters. The main idea is to have a slower but more stable PID controller for steady-state operations and a faster PID controller during the transients. The Kp and Ki constants in the PID controller are increased during the transient in order to achieve a higher temporary bandwidth which corresponds to improved dynamic performance. The adaptive controller observes the error caused by the difference between the output voltage and reference voltage. Once the error is outside a pre-defined threshold, the Ki and Kp values are increased abruptly to a large value in order to increase the bandwidth and speed of the closed loop system. The controller then monitors when the error signal starts to reach steady state and then gradually reduce the Ki and Kp values to their original steady-state values. The author built a proof of concept experimental prototype of the digital adaptive control scheme on a single-phase DC-DC buck converter. Experimental results showed a 26% reduction in voltage overshoot and a >50% reduction in settling time for a particular case of a step load change compared to a conventional PID. 1.3 Motivation and Objective Advantages such as higher efficiency, greater power density, lower component stress, and higher switching frequency make DC-DC resonant converters topologies more attractive over their traditional PWM counterparts [6], [13]. However, the main disadvantage of resonant converters is that they require complex control because of their sensitivity to operating conditions and parameter tolerances. Because of the complex control nature of resonant converters, they stand the most to benefit from digital control [5]. In traditional analog design, a controller is designed for a particular power operating point. The controller is designed with a reduced bandwidth so that stable operation under varying conditions and parameters can be maintained. Such design often greatly limits the dynamic performance and disturbance rejection of the system. Attempting to increase the gain and 5 bandwidth of the system further may cause instability during both steady state and dynamic operations [1]. The main objective of this thesis is to improve the dynamic performance and the AC line ripple rejection ability on a commercially available analog controlled DC-DC LLC resonant converter by implementing digital control. In order to design a compensator, a mathematical model of the power converter is needed. Because of the non-linear nature of resonant converters, it is difficult to model them with traditional mathematical modelling methods and those methods are either over simplified (such as the using the first harmonic approximation), not very accurate, or overly complex and difficult to use. As a result, this thesis also presents an approach to accurately model a resonant power converter while simplifying and speeding up the modelling process, which would avoid the inaccurate/complex traditional mathematical modelling methods. As will be discussed later, this approach involves empirically gathering the frequency response data from the physical converter. With the frequency response data, a mathematical transfer function is estimated using a software tool and then the compensator is designed. 1.4 Outline This thesis is organized into seven chapters. In Chapter 1, the importance and advantages of digital control is introduced and the motivation to implement digital control on a resonant converter is established. Some previous digital control work done on power converters are also presented along with a summary of their advantages and disadvantages. Chapter 2 provides a brief literature review of some basic resonant converter topologies. The LLC resonant converter experimented on in this thesis is presented in more detail along with its specifications. In addition, a simulation of the LLC converter\u00E2\u0080\u0099s control-to-output frequency response for several different operating conditions is shown to emphasize its dynamic differences. In Chapter 3, a detailed overview of the design infrastructure and analysis of the components used to implement digital control on the LLC resonant converter is presented. Digital design considerations such as the digital signal microcontroller (DSC), analog-to-digital converter (ADC), digital PWM (DPWM), sampling rate, and more are covered. In addition, the analog components needed to integrate the DSC with the LLC converter are presented. 6 In Chapter 4, the complete design process to achieve optimized digital compensators for varying operating points of the LLC converter is presented. The process involves introducing an approach of modelling the LLC resonant converter by gathering its uncompensated loop-gain frequency response data for various operating points and then using MATLAB to estimate mathematical models based on gathered data. With the estimated models, optimized digital compensators are designed. A comparison between the simulated PSIM control-to-output frequency response and the physically measured data is also presented and analyzed. An overview of the hardware and software tools used in the digital compensator design process will also be shown. Finally, a summary of the performance result of a single compensation design vs an adaptive compensation design is shown. (The performance is evaluated by the system\u00E2\u0080\u0099s stability margins, bandwidth, and 120Hz disturbance rejection ability.) Chapter 5 provides an overview of the digital control software architecture. Details on the adaptive compensation algorithm, which includes the responsibilities of the background loop and interrupts service routine task are covered. Chapter 6 presents the experimental results to validate the work done in this thesis. First, an overview of the experimental prototype lab bench setup is shown. The modifications performed on the closed loop digital controlled system done to obtain the experimental loop-gain frequency response is measurements are presented. Next, the experimental data and performance results of the digitally compensated loop gain will be presented. Finally, comparisons between the experimental data and simulation will be shown. Chapter 7 summarizes the work done in this thesis and provides further discussion insight regarding the overall work. Future work and possible improvements are also discussed. 7 2 Literature Review This chapter provides a review of the fundamental operation and characteristics of some common resonant converter topologies as well as highlighting their limitations. More emphasis will be placed on the LLC resonant converter topology and the specification for the LLC converter experimented on in this thesis is presented. Furthermore, the LLC converter\u00E2\u0080\u0099s control-to-output (plant) frequency response for several different operating conditions is shown. 2.1 Resonant Converters A resonant converter contains a resonant tank that consists of L-C type networks. The resonant tank is driven by a periodic (voltage or current) square wave which results in the voltage and current of the resonant tank varying sinusoidally [14]. Frequency modulation is used to control the resonant type converter. Varying the switching frequency changes the impedance of the resonant tank, which results in the regulation of the voltages and currents [15]. There are three main well-known topologies for resonant converters: the series resonant converter SRC, the parallel resonant converter PRC, and the series-parallel resonant converter SPRC. The following is a brief overview of these topologies along with their advantages and disadvantages. The series resonant converter (SRC) shown in Figure 2.1 [16] has a resonant tank consisting of an inductor Lr and a capacitor Cr in series. VinQ1Q2npLrnsnsCoLoadCrSRC Figure 2.1 - Series Resonant Converter (SRC) As discussed in [16], the SRC acts like a voltage divider by having its resonant tank in series with the load. By changing the impedance of the resonant tank, the voltage divider equation will change therefore changing the gain of the converter. Because the load is in series with the resonant tank, the circulating energy in the tank is small which means less conduction losses. The DC gain of the SRC is always lower than one. A gain of one is achieved at resonant 8 frequency where the impedance of the series resonant tank is small and all the input voltage drops on the load. The SRC is non-ideal for practical DC-DC converter applications because it requires a high range of switching frequencies for light load regulation. It also has high circulating energy that results in conduction losses and the switches experience high turn off current. VinQ1Q2npLrnsnsCoLoadCrPRCLf Figure 2.2 - Parallel Resonant Converter (PRC) The parallel resonant converter (PRC) is shown in Figure 2.2 [16]. It is essentially a series resonant converter expect for the fact the load is in parallel with the resonant capacitor. The converter\u00E2\u0080\u0099s operating region is much smaller compared to the SRC and can have a DC gain greater than one. The main problem of the PRC is its high circulating current even at no load conditions because the load is in parallel with the resonant capacitor. Therefore, the PRC experiences even higher conduction losses. The PRC also suffers from high turn off current just like the SRC [16]. VinQ1Q2npLrnsnsCoLoadCprSPRC - LCCLfCsr Figure 2.3 - Series Parallel Resonant Converter (SPRC) LCC A LCC type series parallel resonant converter SPRC shown in Figure 2.3 [16] can been viewed as a combination of the SRC and the PRC. The resonant tank consists of three resonant components: Lr, Csr, and Cpr. The LCC combines the good characteristics of the SRC and the 9 PRC by having less circulating current and smaller sensitivity to load change. However, it still suffers with wide input ranges, which leads to high conduction and switching losses under high input voltages [16]. 2.2 LLC Resonant Converter In this section, the LLC converter is presented in more detail and its advantages over the series resonant converter (SRC), parallel resonant converter (PRC), and the LCC series parallel resonant converter (SPRC) is presented. VinCr/2Cr/2Q1Q2LmLrCoLoadLLC Figure 2.4 - LLC Resonant Converter The LLC resonant converter shown in Figure 2.4 [17] is essentially the dual of the LCC resonant converter. Its resonant tank is composed of two inductors (Lr and Lm) and one capacitor (Cr). The major advantage of the LLC resonant converter is it allows for zero-voltage switching (ZVS) operation for a variety of loads. It can also operate with a narrow switching frequency range [17]. Another advantage of LLC compared to the LCC topology is the two inductors Lr and Lm of the LLC can be combined into one physical component therefore saving cost whereas the LCC converter requires two large high cost capacitors [18]. The LLC resonant converter can be broken down into four sections: the bridge inverter, the LLC resonant tank, the high frequency transformer, and the rectifier [19]. 10 Full-BridgeQ3Q1Q2 Q4VinVsqHalf-BridgeC1C2Q1Q2VsqVin Figure 2.5 - Full-Bridge & Half-Bridge switching circuits A full-bridge and half-bridge inverter is shown in Figure 2.5 (the half-bridge inverter is used for this thesis). It is the first stage of the LLC converter, which converts a DC input voltage into a square wave of switching frequency (\u00F0\u009D\u0091\u0093\u00F0\u009D\u0091\u00A0\u00F0\u009D\u0091\u00A4). The duty cycle of the square wave is typically 50% with a small dead time to help with zero voltage switching (ZVS). The mathematical equation of the square wave \u00F0\u009D\u0091\u0089\u00F0\u009D\u0091\u00A0\u00F0\u009D\u0091\u009E generated by the half-bridge inverter is shown in Equation 2-1 [15] where \u00F0\u009D\u0091\u0091 represents the duty cycle. \u00F0\u009D\u0091\u0089\u00F0\u009D\u0091\u00A0\u00F0\u009D\u0091\u009E \u00E2\u0089\u00884\u00F0\u009D\u009C\u008B\u00F0\u009D\u0091\u0089\u00F0\u009D\u0091\u0096\u00F0\u009D\u0091\u009B2sin(\u00F0\u009D\u009C\u008B\u00F0\u009D\u0091\u00912) sin(\u00F0\u009D\u009C\u0094\u00F0\u009D\u0091\u00A1) Equation 2-1 Ultimately, the main advantage of a half bridge is its reduced cost (because of fewer switches) with the sacrifice of increased power loss because of the increased RMS current going through the switches (which causes increased losses) [19]. The half-bridge is usually used for lower power levels (<1000W) where the power loss is deemed acceptable compared to the decrease in cost [16]. LmLrCrVsq Figure 2.6 - LLC Resonant Tank The square wave generated by the half-bridge inverter is fed into the resonant tank as shown in Figure 2.6. The LLC tank consists of a series resonant inductor Lr, a series resonant capacitor Cr, and a parallel resonant inductor Lm. It is shown in [20] that the impedance of the resonant tank can be varied by changing the frequency of the square wave fed into it. The high frequency transformer shown in Figure 2.4 is used to decrease/increase the secondary side voltage and provide galvanic isolation to the input for safety. Using integrated 11 magnetic technology for the transformer allows the Lr and Lm inductors to be a part of the same magnetic structure, which is useful in terms of increasing the converter\u00E2\u0080\u0099s power density [18], [21]. Full-Bridge Rectifier Full-Wave RectifierD1D2Co VoutD1D2CoD3D4Vout Figure 2.7 - Full-Bridge (left) and Half-Bridge (right) rectifier The last stage of the LLC resonant converter is the bridge rectifier with a capacitor output filter Co as shown in Figure 2.7 [19]. Figure 2.7 shows both a full-bridge and a full-wave rectifier. The function of this section is to transform the scaled AC voltage output from the transformer to a DC output. Full-Wave compared to Full-Bridge Rectifier Diode Voltage Rating # of Diodes Diode Conduction Losses # of Secondary Windings Rsec per winding IRMS per winding Transformer Secondary loss \u00C3\u00972 \u00C3\u00B72 \u00C3\u00B72 \u00C3\u00972 \u00C3\u00972 \u00C3\u0097\u00E2\u0088\u009A0.5 \u00C3\u00972 Table 2.1 - Full-Wave rectifier compared to Full-Bridge rectifier As summarized in Table 2.1 [19], the diodes of the full-wave rectifier experience twice the voltage compared to the full-bridge rectifier. However, the full-wave rectifier only has two diodes while the full-bridge rectifier has four diodes resulting in the full-wave rectifier having half the total diode conduction losses. The full-wave has two secondary windings therefore the resistance is doubled for the same winding area. Each winding in the full-wave rectifier caries a RMS current that is \u00E2\u0088\u009A0.5 times the RMS current of the full-bridge rectifier. In all, the total secondary winding copper losses of the full-wave rectifier is two times more compared to the full bridge rectifier. The full-bridge rectifier\u00E2\u0080\u0099s advantage of experiencing only half the amount of voltage when compared with the full-wave rectifier makes it a good candidate for high output voltage applications. The full-wave rectifier is best used for low output voltages and high 12 currents applications because of its lower conduction losses (the full-wave rectifier is used in this thesis). Normalized FrequencyGain0.3 0.75 1.2 1.65 2.090.50.60.70.80.911.11.21.31.41.51.61.71.81.92fnmins fnmaxShort Circuit Gain No Load GainRegion 1 ZVSRegion 2 ZVSRegion 3 ZCSMax GainMin GainNom GainUnity Gain Resonant Frequency Figure 2.8 - Typical LLC Converter DC gain characteristic Figure 2.8 [22] shows the normalized gain vs frequency characteristic of a LLC converter. As can be seen from Figure 2.8, the characteristics are split into three regions (the boundaries shown by the solid blue lines): Region 1, Region 2, and Region 3. It is desirable to operate the converter under ZVS conditions therefore the converter is operated in Region 1 and Region 2. Region 1 and 2 are located on the negative gradient of the DC gain curve and Region 3 is located on the positive gradient [23]. The resonant frequency \u00F0\u009D\u0091\u0093\u00F0\u009D\u0091\u009C of the circuit is dependent on the series resonant inductor Lr and series resonant capacitor Cr that can be seen in Equation 2-2 [20]. \u00F0\u009D\u0091\u0093\u00F0\u009D\u0091\u009C =12\u00F0\u009D\u009C\u008B\u00E2\u0088\u009A(\u00F0\u009D\u0090\u00BF\u00F0\u009D\u0091\u009F\u00F0\u009D\u0090\u00B6\u00F0\u009D\u0091\u009F) Equation 2-2 13 The magnetizing inductor Lm introduces a second resonant frequency when there is not load and it is given by Equation 2-3 [13], [20]. \u00F0\u009D\u0091\u0093\u00F0\u009D\u0091\u009D =12\u00F0\u009D\u009C\u008B\u00E2\u0088\u009A(\u00F0\u009D\u0090\u00BF\u00F0\u009D\u0091\u009F + \u00F0\u009D\u0090\u00BF\u00F0\u009D\u0091\u009A)\u00F0\u009D\u0090\u00B6\u00F0\u009D\u0091\u009F Equation 2-3 The LLC converter can operate in three modes depending on the input voltage and load conditions. The three modes of operations are [12], [20], [18]: \u00E2\u0080\u00A2 At resonant frequency operation, fsw=fo. \u00E2\u0080\u00A2 Above resonant frequency operation, fsw>fo. \u00E2\u0080\u00A2 Below resonant frequency operation, fsw 60\u00C2\u00BA, gain margin >10dB). However, the control bandwidth improved by a factor of 3-5 times and the compensated loop gain magnitude at 120Hz achieved 95 greater than around 20dB for all operating points. In all, the adaptive compensation method provided superior dynamic and noise rejection results while maintaining adequate stability for all operating conditions when compared to the single compensation design method. 7.1.4 Venable vs PSIM Frequency Response Data Accuracy The overall frequency response shape from the PSIM simulation data matches well when compared to the Venable data for the varying operating points as was shown in Figure 4.13 to Figure 4.21. However, the magnitude of the frequency response between PSIM and Venable can vary up to 8dB. In particular, it was noticed that as the output voltage or current was set lower (which corresponds to increasing the switching frequency), the more the PSIM data deviated away from the Venable data. It was also noticed that the Venable magnitude is always lower than its corresponding PSIM simulation. The difference in magnitude may be caused by the ideal characteristics of the PSIM simulation components and the overall simplified converter model. At higher frequencies, the non-idealities of the resonant tank components (the inductor and capacitor) become more profound, which may result in reduced gains. Adding non-ideal factors such as parasitic effects increases complexity of the model, which also significantly increase an already long simulation time and may not even guarantee better accuracy. As a result, I decided the PSIM model was not accurate enough to design the compensator and therefore the Venable frequency response data was used instead. However, if the physical converter is not available or built, PSIM may be used to provide a viable rough estimate of the converter. The digital signal microcontroller\u00E2\u0080\u0099s flexibility to adjust the control may be used to compensate for any discrepancies between the simulation and physical results. 7.1.5 Obtaining the Frequency Response Data More Quickly and Efficiently Obtaining the frequency response data using the Venable method can be quite tedious because each measurement has to be manually setup for each operating point. In addition, increasing the data points to measure for the frequency response also increases the time to complete the measurement. This issue is compounded if the designer needs data for a large amount of operating points. An automated test bench can help speed up the data collection time significantly because it would not require someone to monitor and adjust the system constantly. For the PSIM frequency response simulation, each simulation can take up to 2-8 hours depending on the chosen starting frequency and the level of complexity of the circuit model. The 96 simulation time goes up exponentially for a lower starting frequency and increased circuit complexity. It was noticed that a single PSIM simulation takes up 25% of a computer\u00E2\u0080\u0099s CPU utilization. Therefore, running four simulations at the same time will take up 100% of the CPU utilization while not slowing down any of the individual simulation times. It would also be helpful to somehow automate this process. 7.2 Future Work 1) Use the control law accelerator (CLA) module in the DSC to compute the 2P2Z compensator calculations. This will reduce the load of the main processor allowing for benefits such as faster sampling rates, more complex control algorithms, and additional software features. 2) Investigate the stability of the system when increasing the software background loop update rate (which is in charge of selecting the optimal compensator). 3) Find possible relationships between the 2P2Z coefficients with changing operating points. This may allow an algorithm to change the coefficients of the compensator to move with the changing operating points. The benefit is the elimination of the need to collect a large amount of frequency response data and store large amounts of compensator coefficients in the microcontroller memory. 4) Implement time domain step change experimental tests to compare with the simulated ones in this thesis. 5) Directly drive the LLC converter with DPWM frequency modulation therefore eliminating the need for the analog VCO. This will allow for better control bandwidth because of the elimination of the RC filter. 6) Create a more accurate PSIM model of the LLC resonant converter including parasitic effects. Evaluate how well creating a more complex PSIM model can help accuracy and determine if the expected much increased simulation time is worth it. 7) Model the converter and its digital components using direct digital design technique. 97 Bibliography [1] V. Arikatla, \"Adaptive Control Methods for DC-DC Switching Power Converters,\" PhD Thesis, Tuscaloosa, 2011. [2] C.-L. Liu, Y.-H. Chiu, Y.-F. Lo, S.-C. Wang and Y.-H. Liu, \"Design and implementation of a digitally-controlled LLC resonant converter for battery charging applications,\" Power Electronics and Drive Systems (PEDS), 2013 IEEE 10th International Conference on, pp. 804-808, April 2013. [3] S. Choudhury, \"Digital Power Supplies EVMs using c2000 Piccolo MCU,\" Texas Instruments. [4] V. Arikatla and A. Qahouq, \"Adaptive digital proportional-integral-derivative controller for power converters,\" Power Electronics, IET, vol. 5, no. 3, pp. 341-348, March 2012. [5] M. Vulovic, \"Digital Control of a High Frequency Parallel Resonant DC-DC Converter,\" MASc Thesis, Blacksburg, 2010. [6] M. Vulovic, D. Boroevich and P. Mattavelli, \"Digital gain-scheduled control of a high frequency parallel resonant DC-DC converter,\" Applied Power Electronics Conference and Exposition (APEC), 2012 Twenty-Seventh Annual IEEE, pp. 1814-1820, Feb 2012. [7] L. Hang, Z. Lu and Z. Qian, \"Research of Digital Control Strategy for Multi-Resonant LLC Converter,\" Industrial Electronics, 2007. ISIE 2007. IEEE International Symposium on, pp. 479-484, June 2007. [8] S. Chon, \"What it Takes to do Efficient and Cost-Effective Real-Time Control with a Single Microcontroller - The C2000\u00E2\u0084\u00A2 Advantage,\" 2011. [9] Control Theory Workshop Student Manual, Texas Instruments, 2011. [10] C. Ditmanson, H. Guldner, F. Gleisberg and M. Rentzsch, \"Digital voltage/current control of a high voltage output LCC resonant converter based power supply for capacitor charging,\" Industrial Technology, 2009. ICIT 2009. IEEE International Conference on, pp. 1-6, Feb 2009. [11] C. Buccella, C. Cecati, H. Latafat and K. Razi, \"Digital control of a half-bridge LLC resonant converter,\" Power Electronics and Motion Control Conference (EPE/PEMC), 2012 15th International, pp. LS6a.4-1-LS6a.4-6, Sept 2012. [12] V. Arikatla and J. Qahouq, \"DC-DC Power Converter with digital PID controller,\" Applied Power Electronics Conference and Exposition (APEC), 2011 Twenty-Sixth Annual IEEE, pp. 327-330, March 2011. [13] B. Cheng, F. Musavi and W. Dunford, \"Novel small signal modeling and control of an LLC resonant converter,\" Applied Power Electronics Conference and Exposition (APEC), 2014 Twenty-Ninth Annual IEEE, pp. 2828-2834, March 2014. 98 [14] B. Cheng, \"Modelling and Control of the LLC Resonant Converter,\" MASc Thesis, Vancouver, 2012. [15] V. Panov, \"LLC Resonant Converter Modelling,\" Vancouver, 2014. [16] B. Yang, \"Topology investigation of front end DC/DC converter for distributed power system,\" Virgina Polytechnic Institute and State University, 2003. [17] S. Maniktala, Understanding and using LLC Converters to Great Advantage, Microsemi, 2013. [18] H. Huang, \"Designing an LLC Resonant Half-Bridge Power Converter (SLUP263),\" 2010. [19] S. Abdel-Rahman, Resonant LLC Converter: Operation and Design, Durham: Infineon Technologies North America, 2012. [20] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd ed., Springer, 2001. [21] Design and Optimization of a High-Performance LLC Converter, Texas Instruments, 2012. [22] F. Musavi, M. Craciun, D. Gautam, M. Edington and W. Eberle, \"Control strategies for a LLC multi-resonant DC-DC converter in battery charging applications,\" Applied Power Electronics Conference and Exposition (APEC), 2013 Twenty-Eighth Annual IEEE, pp. 1804-1811, March 2013. [23] An introduction to LLC resonant half-bridge converter (AN2644), ST, 2008. [24] B. McDonald, LLC Converter Small Signal Modeling, Texas Instruments, 2013. [25] TMS320F2803x ( Piccolo\u00E2\u0084\u00A2) MCUs Datasheet (SPRS584I), Texas Instruments, 2012. [26] D. Chang, High-Voltage Half-Bridge LLC Resonant DC/DC Converter With Synchronous Rectification Hardware Kit (SPRABS1), Texas Instruments, 2013. [27] TMS320F2803x Piccolo System Control and Interrupts Reference Guide (SPRUGL8C), Texas Instruments, 2013. [28] TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and Comparator Reference Guide (SPRUGE5F), Texas Instruments, 2011. [29] TMS320x2802x, 2803x Piccolo High Resolution Pulse Width Modulator (HRPWM) Reference Guide (SPRUGE8E), Texas Instruments, 2011. [30] M. Peretz and S. Ben-Yaakov, \"Digital Control of Resonant Converters: Resolution Effects on Limit Cycles,\" Power Electronics, IEEE Transactions on, vol. 25, no. 6, pp. 1652-1661, June 2010. [31] M. Peretz and S. Ben-Yaakov, \"Digital Control of Resonant Converters: Enhancing Frequency Resolution by Dithering,\" Applied Power Electronics Conference and Exposition, 2009. APEC 2009. Twenty-Fourth Annual IEEE, pp. 1202-1207, Feb 2009. 99 [32] C28x\u00E2\u0084\u00A2 Digital Power Supply Workshop, Texas Instruments, 2008. [33] M. Peretz and S. Ben-Yaakov, \"Revisiting the closed loop response of PWM converters controlled by voltage feedback,\" Applied Power Electronics Conference and Exposition, 2008. APEC 2008. Twenty-Third Annual IEEE, pp. 58-64, Feb 2008. [34] C28x Digital Power Library v3.4 Module User\u00E2\u0080\u009Fs Guide, Texas Insturments, 2012. [35] M. Shaik and R. Kankanala, Digital Compensator Design for LLC Resonant Converter (AN1477), Microchip Technology Inc, 2012. [36] S. Raghunath, Digital Loop Exemplified (SLU622), Texas Instruments, 2011. [37] T. Patarau, D. Petreus, R. Duma and P. Dobra, \"Comparison between analog and digital control of LLC converter,\" Automation Quality and Testing Robotics (AQTR), 2010 IEEE International Conference on, pp. 1-6, May 2010. [38] S. Choudhury, Designing a TMS320F280x Based Digitally Controlled DC-DC Switching Power Supply (SPRAAB3), Texas Instruments, 2005. [39] A. Bersani, A. Dumais and S. Khare, DC/DC LLC Reference Design Using the dsPIC\u00C2\u00AE DSC (AN1336), Microchip Technology Inc, 2010. [40] A. Shirsavar, Designing Stable Digital Power Supplies, Texas Instruments, 2011. [41] \"C2000 Archived Workshops,\" Texas Instruments, December 2010. [Online]. Available: http://software-dl.ti.com/trainingTTO/trainingTTO_public_sw/c28x28035/C28x_Piccolo_MDW_2-1.pdf. [42] D. M. Alter, Using PWM Output as a Digital-to-Analog Converter on a TMS320F280x Digital Signal Controller (SPRAA88A), Texas Instruments, 2008. [43] B. Nisarga, PWM DAC Using MSP430 High-Resolution Timer (SLAA497), Texas Instruments, 2011. [44] P. Drgona, M. Frivaldsky and A. Prikopova, \"Optimal design of digital control system for LLC resonant converter,\" Applied Electronics (AE), 2010 International Conference on, pp. 1-4, Sept 2010. [45] P. Drgona, M. Frivaldsky and A. Simonova, \"A New Approach of Control System Design for LLC Resonant Converter,\" in MATLAB for Engineers - Applications in Control, Electrical Engineering, IT and Robotics, InTech, 2011, pp. 321-338. [46] \"PSIM User Manual,\" Powersim. [47] \"MathWorks System Identification Toolbox,\" MathWorks, [Online]. Available: http://www.mathworks.com/help/ident/index.html. [48] \"Estimate State-Space Model With Order Selection,\" [Online]. Available: http://www.mathworks.com/help/ident/ug/estimate-state-space-model-with-order-selection.html. 100 [49] \"MathWorks SISO Design Tool,\" MathWorks, [Online]. Available: http://www.mathworks.com/help/control/getstart/siso-design-tool.html#brz1_7y. [50] E. Asa, K. Colak, D. Czarkowski, F. de Leon and I. Sefa, \"PLL control technique of LLC resonant converter for EVs battery charger,\" Power Engineering, Energy and Electrical Drives (POWERENG), 2013 Fourth International Conference on, pp. 1382-1386, May 2013. [51] S. Pidaparthy, C. Byungcho and J. Jinhaeng, \"Design and performance evaluation of digital control for LLC series resonant dc-to-dc converters,\" Power Electronics Conference (IPEC-Hiroshima 2014 - ECCE-ASIA), 2014 International, pp. 3638-3645, May 2014. [52] M. S. Fadali and A. Visioli, Digital Control Engineering, 2nd ed., Elsevier, 2013. [53] \"Continuous-Discrete Conversion Methods,\" MathWorks, 2014. [Online]. Available: http://www.mathworks.com/help/control/ug/continuous-discrete-conversion-methods.html. [Accessed 12 2014]. [54] \"Discretize a Compensator,\" MathWorks, 2014. [Online]. Available: http://www.mathworks.com/help/control/ug/discretize-a-compensator.html. [Accessed 12 2014]. [55] R. Poley, \"Digital control theory seminar student manual,\" Texas Instruments. [56] B. Larimore and M. Bhardwaj, System Framework Overview Guide and Instructions on How to Use the Template Projects, Texas Instruments, 2008. [57] C28x Digital Power Library v3.3 Module User\u00E2\u0080\u0099s Guide, Texas Instruments, 2011. 101 Appendices Appendix A: TI C2000 Piccolo TMSF28035 Specifications Appendix A.1 - TI C2000 Piccolo TMSF2803x General Specifications 102 Appendix A.2 - TI C2000 Piccolo TMSF2803x Interrupt Vector Table 103 Appendix B: PSIM Simulation Schematics Appendix B.1 - PSIM model of LLC converter Appendix B.2 - PSIM model of Loop Gain Components including: RC Filter, Gain Inverter, VCO, LLC converter, Voltage/Current Sensors "@en . "Thesis/Dissertation"@en . "2015-09"@en . "10.14288/1.0166466"@en . "eng"@en . "Electrical and Computer Engineering"@en . "Vancouver : University of British Columbia Library"@en . "University of British Columbia"@en . "Attribution-NonCommercial-NoDerivs 2.5 Canada"@en . "http://creativecommons.org/licenses/by-nc-nd/2.5/ca/"@en . "Graduate"@en . "Implementing digital control to improve control bandwidth and disturbance rejection on a LLC resonant DC-DC power converter."@en . "Text"@en . "http://hdl.handle.net/2429/54254"@en .