"Applied Science, Faculty of"@en .
"Electrical and Computer Engineering, Department of"@en .
"DSpace"@en .
"UBCV"@en .
"AlSharidah, Michel E."@en .
"2013-03-05T10:17:56Z"@en .
"2012"@en .
"Doctor of Philosophy - PhD"@en .
"University of British Columbia"@en .
"A development of an island stabilizing element (ISE) for use in the IEEE 1547 unintentional islanding test is introduced. The new test setup for non- islanding inverters interconnected with the grid is proposed. The current testing standard uses discrete RLC elements to simulate the test-island. Even though the RLC simulated test-island is useful for its reproducibility, relative scalability and short setup time, as inverter power ratings increase so does the size and cost of the RLC simulated island. The proposed island stabilizing element can represent the function of the resonant part of the test island as well as provide compensation for dynamic changes in power during the test for producing near worst case conditions for an islanding test. This work introduces improvements to the unintentional islanding test. The island stabilizing element is designed and developed. Test cases proved the efficient application of the ISE as means to replace the LC elements in the unintentional islanding test."@en .
"https://circle.library.ubc.ca/rest/handle/2429/44001?expand=metadata"@en .
"An Active Method for Implementing the Unintentional Islanding Test in Distributed Generation Systems by Michel E. AlSharidah B.Sc., The University of Arizona, 1995 M.Sc., Portland State University, 1999 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY in The Faculty of Graduate Studies (Electrical and Computer Engineering) THE UNIVERSITY OF BRITISH COLUMBIA (Vancouver) December 2012 \u00C2\u00A9 Michel E. AlSharidah 2012 Abstract A development of an island stabilizing element (ISE) for use in the IEEE 1547 unintentional islanding test is introduced. The new test setup for non- islanding inverters interconnected with the grid is proposed. The current testing standard uses discrete RLC elements to simulate the test-island. Even though the RLC simulated test-island is useful for its reproducibility, relative scalability and short setup time, as inverter power ratings increase so does the size and cost of the RLC simulated island. The proposed island stabilizing element can represent the function of the resonant part of the test island as well as provide compensation for dynamic changes in power during the test for producing near worst case conditions for an islanding test. This work introduces improvements to the unintentional islanding test. The island stabilizing element is designed and developed. Test cases proved the e\u000Ecient application of the ISE as means to replace the LC elements in the unintentional islanding test. ii Table of Contents Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Island De\u000Cnitions . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 Islanding Prevention . . . . . . . . . . . . . . . . . . . . . . . 2 1.2.1 Passive Methods . . . . . . . . . . . . . . . . . . . . . 2 1.2.2 Active Methods . . . . . . . . . . . . . . . . . . . . . 5 1.2.3 Alternative Methods . . . . . . . . . . . . . . . . . . 10 1.3 Standard Test of Unintentional Islanding . . . . . . . . . . . 11 1.4 Advantages and Shortcomings of the Standard Test . . . . . 13 1.5 Motivation and Dissertation Outline . . . . . . . . . . . . . . 14 2 The Standard Unintentional Islanding Test . . . . . . . . . 16 2.1 Simulation Environment . . . . . . . . . . . . . . . . . . . . 18 2.2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3 Simulated Island Parameters . . . . . . . . . . . . . . . . . . 20 2.4 Test Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.5 Simulation Results of the Standard Unintentional Test . . . 21 2.5.1 Equipment Under Test (EUT) . . . . . . . . . . . . . 21 2.5.2 Test Start/Stop . . . . . . . . . . . . . . . . . . . . . 22 2.5.3 Case 1: The Single-Phase Islanding EUT . . . . . . . 22 2.5.4 Case 2: The Single-Phase EUT with AFD . . . . . . 27 iii Table of Contents 2.5.5 Case 3: The Single-Phase EUT with RPV . . . . . . 30 2.5.6 Case 4: An Islanding Three-Phase EUT . . . . . . . . 31 2.5.7 Case 5: A Three-Phase EUT with Negative Sequence Injection . . . . . . . . . . . . . . . . . . . . . . . . . 34 3 Proposed Island Stabilizing Element (ISE) . . . . . . . . . . 36 3.1 Overview of Advantages and Disadvantages of Standard Is- landing Test . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.2 Modi\u000Ced Unintentional Islanding Test . . . . . . . . . . . . . 36 3.3 Island Load P & Q . . . . . . . . . . . . . . . . . . . . . . . 37 3.4 ISE Representing Qload . . . . . . . . . . . . . . . . . . . . . 38 3.5 ISE Representing Pload & Qload . . . . . . . . . . . . . . . . . 39 3.6 ISE Representing Mismatch in P and Q . . . . . . . . . . . . 40 3.7 Initial Design of the ISE . . . . . . . . . . . . . . . . . . . . 40 3.7.1 Small-Signal Model of the Single-Phase ISE . . . . . 42 3.7.2 PI-Controller Design . . . . . . . . . . . . . . . . . . 43 3.7.3 PI-Controller Analysis . . . . . . . . . . . . . . . . . 44 3.7.4 Average and Ripple Current . . . . . . . . . . . . . . 46 4 Improved Control Design for the ISE . . . . . . . . . . . . . 49 4.1 Synchronous Frame Model of the Single-Phase ISE . . . . . . 49 4.2 Synchronous Frame Model of the Three-Phase ISE . . . . . . 51 4.3 Proposed Synchronous Frame Digital Current Control . . . . 54 4.3.1 Current Reference Calculation . . . . . . . . . . . . . 54 4.3.2 Synchronous Frame Current Control . . . . . . . . . . 55 4.4 Space Vector PWM (SVPWM) Generation . . . . . . . . . . 60 4.5 Veri\u000Ccation of Islanding PWM Inverter Performance . . . . . 64 4.5.1 Veri\u000Ccation of Single-Phase PWM Inverter Islanding 64 4.5.2 Veri\u000Ccation of Three-Phase PWM Inverter Islanding . 66 4.5.3 Islanding Detection Method Employed . . . . . . . . 66 5 Modi\u000Ced Unintentional Islanding Test . . . . . . . . . . . . 71 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.2 Case 1: A Single-Phase Islanding Inverter . . . . . . . . . . . 72 5.2.1 Inverter Voltage & Frequency . . . . . . . . . . . . . 73 5.2.2 Inverter Real and Reactive Power . . . . . . . . . . . 74 5.3 Case 2: A Single-Phase Inverter with AFD . . . . . . . . . . 75 5.4 Case 3: A Single-Phase Inverter with RPV . . . . . . . . . . 78 iv Table of Contents 6 Experimental Development . . . . . . . . . . . . . . . . . . . 83 6.1 Hardware Circuit . . . . . . . . . . . . . . . . . . . . . . . . 83 6.2 Simulated Inductance (Lsim) . . . . . . . . . . . . . . . . . . 83 6.3 Simulated Capacitance (Csim) . . . . . . . . . . . . . . . . . 84 6.4 ISE Series Inductance and Switching Frequency . . . . . . . 84 6.4.1 ISE Current Ripple Experimental Results and Analy- sis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.4.2 Lsim ISE Current Ripple . . . . . . . . . . . . . . . . 85 6.4.3 Csim ISE Current Ripple . . . . . . . . . . . . . . . . 85 7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.1 Improvements to the Standard Test . . . . . . . . . . . . . . 92 7.2 Limitations of Proposed Test Setup . . . . . . . . . . . . . . 93 7.3 Broader Application and Future Work . . . . . . . . . . . . . 93 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Appendices A Space Vector PWM . . . . . . . . . . . . . . . . . . . . . . . . 104 A.1 Three-Phase PWM Inverter Model . . . . . . . . . . . . . . . 104 A.2 Sampled Space Vector Phase Angle . . . . . . . . . . . . . . 105 A.2.1 Solution for t1 and t2 in Sector S1 . . . . . . . . . . . 105 A.2.2 Solving for t2 and t3 in Sector S2 . . . . . . . . . . . 106 A.3 Sampled Phase Voltage Amplitudes . . . . . . . . . . . . . . 109 A.4 Space Vector PWM ON-Time Durations for Three-Phase In- verter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 B Hardware Implementation . . . . . . . . . . . . . . . . . . . . 117 B.0.1 Inverter Using IGBT Model MUBW 20-06 A7 . . . . 118 B.0.2 Driver Circuit . . . . . . . . . . . . . . . . . . . . . . 119 B.0.3 Mode Selection . . . . . . . . . . . . . . . . . . . . . 119 B.0.4 Dead Time . . . . . . . . . . . . . . . . . . . . . . . . 119 B.0.5 Voltage Measuring Circuit . . . . . . . . . . . . . . . 120 C Circuit and PCB . . . . . . . . . . . . . . . . . . . . . . . . . . 130 C.1 Schematics of Control Board . . . . . . . . . . . . . . . . . . 131 C.2 Schematics of Power Board . . . . . . . . . . . . . . . . . . . 135 C.3 PCB Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 v Table of Contents D Schematics for 3-Phase Islanding Test . . . . . . . . . . . . . 143 E Unintentional islanding test conditions . . . . . . . . . . . . 145 vi List of Tables 2.1 Unintentional islanding test parameters . . . . . . . . . . . . 20 4.1 PI controller design parameters . . . . . . . . . . . . . . . . . 60 4.2 Space vectors and corresponding switching states . . . . . . . 62 4.3 ON-time durations for three-phase SVPWM control . . . . . 64 5.1 ISE case 1 parameters . . . . . . . . . . . . . . . . . . . . . . 72 6.1 ISE inductive or capacitive load speci\u000Ccation . . . . . . . . . 84 A.1 ON-time durations for space vector PWM . . . . . . . . . . . 110 A.2 ON-time duration using sampled phase voltages . . . . . . . . 116 vii List of Figures 1.1 Power \row before (a) and after (b) grid-disconnection. . . . . 3 1.2 Voltage and current output of EUT implementing AFD . . . 9 1.3 Initial islanding test circuit with matched load . . . . . . . . 12 1.4 Islanding test circuit according to the German proposal [15] . 12 1.5 IEEE Std 1547 unintentional anti-islanding test circuit . . . . 13 2.1 Unintentional islanding test per-phase circuit . . . . . . . . . 16 2.2 Per-phase unintentional islanding test circuit. . . . . . . . . . 19 2.3 Voltage and frequency . . . . . . . . . . . . . . . . . . . . . . 23 2.4 EUT, EPS, and load currents (pu). . . . . . . . . . . . . . . . 24 2.5 Real and reactive power . . . . . . . . . . . . . . . . . . . . . 25 2.6 Frequency response of EUT during the standard islanding test. 26 2.7 EUT PI-controller with AFD control scheme. . . . . . . . . . 27 2.8 EUT current with AFD implementation . . . . . . . . . . . . 28 2.9 Frequency response for EUT under standard isalnding test . . 29 2.10 EUT trip time for AFD chopping fraction of 0.05 . . . . . . . 29 2.11 EUT with modi\u000Ced AFD trip times (CF=\u00065%). . . . . . . . 30 2.12 RPV current control loop . . . . . . . . . . . . . . . . . . . . 31 2.13 EUT with RPV islanding test . . . . . . . . . . . . . . . . . . 32 2.14 EUT trip times . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.15 Real and reactive power of the inverter, load and grid . . . . 33 2.16 PCC voltage magnitude and frequency . . . . . . . . . . . . . 33 2.17 Inverter V and I before and after grid-disc. . . . . . . . . . . 34 2.18 Negative sequence voltage component at PCC . . . . . . . . . 35 3.1 Standard unintentional islanding test . . . . . . . . . . . . . . 37 3.2 Modi\u000Ced island load with R and ISE . . . . . . . . . . . . . . 38 3.3 Modi\u000Ced island load with ISE only . . . . . . . . . . . . . . . 39 3.4 Addition of ISE to island load . . . . . . . . . . . . . . . . . . 40 3.5 Proposed test island stabilizing element . . . . . . . . . . . . 41 3.6 Per-phase circuit diagram . . . . . . . . . . . . . . . . . . . . 41 3.7 Closed-loop PI-Control system . . . . . . . . . . . . . . . . . 43 viii List of Figures 3.8 Generation of the pulse width modulated signal . . . . . . . . 44 3.9 Generation of the pulse width modulated signal . . . . . . . . 44 3.10 Generation of the pulse width modulated signal . . . . . . . . 45 3.11 Bode plot of control to output TF . . . . . . . . . . . . . . . 45 3.12 Simulated impedance of ISE relationship to current ripple . . 48 4.1 Per-phase circuit diagram . . . . . . . . . . . . . . . . . . . . 49 4.2 Transfer function block diagram . . . . . . . . . . . . . . . . . 51 4.3 Per-phase equivalent circuit of a three-phase PWM inverter . 52 4.4 Proposed synchronous frame digital current control . . . . . . 54 4.5 Closed loop current current control in synchronous frame . . 55 4.6 Simpli\u000Ced reference frame current control transfer function . 56 4.7 Current control discrete-time block diagram . . . . . . . . . . 56 4.8 Current control open-loop poles and zeros and desired pole z\u0003 58 4.9 Design veri\u000Ccation of the synchronous frame current controller 59 4.10 Three-phase two-level inverter . . . . . . . . . . . . . . . . . . 61 4.11 Space vector representation for all possible switching states . 61 4.12 Switching commands generated for SVPWM . . . . . . . . . 63 4.13 SVPWM phase A voltage outputs . . . . . . . . . . . . . . . 63 4.14 Single-phase inverter output under islanding condition . . . . 65 4.15 Three-phase inverter output under islanding condition . . . . 67 4.16 AFD implemented in the single-phase PWM control . . . . . 68 4.17 AFD implemented in the single-phase PWM control . . . . . 68 4.18 Negative sequence voltage injection at 0, 2 and 5% . . . . . . 69 4.19 0%, 2% and 5% negative sequence injection . . . . . . . . . . 70 4.20 Output of negative sequence islanding detection . . . . . . . . 70 5.1 Modi\u000Ced island load with ISE . . . . . . . . . . . . . . . . . . 72 5.2 VPCC and IEUT under zero mismatch condition . . . . . . . 73 5.3 f , V, and Iinv results . . . . . . . . . . . . . . . . . . . . . . . 74 5.4 P and Q of inverter results under islanding condition . . . . . 75 5.5 Voltage and frequency response of inverter with AFD . . . . . 76 5.6 Real and reactive power of the inverter with AFD . . . . . . 77 5.7 f comparison between the standard and modi\u000Ced test . . . . 78 5.8 f comparison with reactive power compensation . . . . . . . 79 5.9 Voltage and frequency response of inverter with RPV . . . . . 80 5.10 Real and reactive power of the inverter with RPV . . . . . . 81 5.11 RPV frequency results comparison . . . . . . . . . . . . . . . 81 5.12 Standard and modi\u000Ced test frequency results comparison . . 82 ix List of Figures 6.1 Experimental system . . . . . . . . . . . . . . . . . . . . . . . 86 6.2 Control circuit board . . . . . . . . . . . . . . . . . . . . . . . 86 6.3 Power circuit board . . . . . . . . . . . . . . . . . . . . . . . . 86 6.4 The whole circuit . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.5 ISE hardware prototype system . . . . . . . . . . . . . . . . . 86 6.6 Lsim = 0:5p:u: at fpwm = 20kHz . . . . . . . . . . . . . . . . 87 6.7 Lsim = 1p:u: at fpwm = 20kHz . . . . . . . . . . . . . . . . . 87 6.8 Csim = 0:5p:u: at fpwm = 20kHz . . . . . . . . . . . . . . . . 88 6.9 Csim = 1p:u: at fpwm = 20kHz . . . . . . . . . . . . . . . . . 88 6.10 L = 2:6mH, Rsim = 2p:u: and fpwm = 20kHz . . . . . . . . . 89 6.11 Current Ripple at L = 2:6mH . . . . . . . . . . . . . . . . . . 89 6.12 L = 26mH, Rsim = 2p:u: and fpwm = 20kHz . . . . . . . . . 89 6.13 Current ripple at L = 26mH . . . . . . . . . . . . . . . . . . 89 6.14 L = 2:6mH ,Lsim = 1p:u: and fpwm = 20kHz . . . . . . . . . 90 6.15 L = 26mH ,Lsim = 1p:u: and fpwm = 20kHz . . . . . . . . . 90 6.16 Current ripple at L = 2:6mH . . . . . . . . . . . . . . . . . . 90 6.17 Current ripple at L = 26mH . . . . . . . . . . . . . . . . . . 90 6.18 L = 2:6mH ,Csim = 1p:u: and fpwm = 20kHz . . . . . . . . . 91 6.19 L = 26mH ,Csim = 1p:u: and fpwm = 20kHz . . . . . . . . . 91 6.20 Current ripple at L = 2:6mH . . . . . . . . . . . . . . . . . . 91 6.21 Current ripple at L = 26mH . . . . . . . . . . . . . . . . . . 91 A.1 Three-phase two-leve inverter . . . . . . . . . . . . . . . . . . 104 A.2 Sectors of SVPWM . . . . . . . . . . . . . . . . . . . . . . . . 105 A.3 Sector 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 A.4 Three-phase VSI . . . . . . . . . . . . . . . . . . . . . . . . . 111 A.5 ( ~V\u000B, ~V\u000C) transformation in sector S1 . . . . . . . . . . . . . . . 112 A.6 Sector 2 \u000B,\u000C transformation . . . . . . . . . . . . . . . . . . . 114 A.7 Three-phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 B.1 ISE hardware layout . . . . . . . . . . . . . . . . . . . . . . . 117 B.2 IGBT Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 B.3 Block diagram of IGBT module . . . . . . . . . . . . . . . . . 121 B.4 The circuit of the voltage sensor . . . . . . . . . . . . . . . . 122 B.5 Voltage scaling circuit . . . . . . . . . . . . . . . . . . . . . . 123 B.6 Voltage scaling from sensor output . . . . . . . . . . . . . . . 124 B.7 Voltage bu\u000Ber circuit . . . . . . . . . . . . . . . . . . . . . . . 125 B.8 Current sensor circuit . . . . . . . . . . . . . . . . . . . . . . 126 B.9 Measured current scaling . . . . . . . . . . . . . . . . . . . . . 127 B.10 Temperature sensor circuit . . . . . . . . . . . . . . . . . . . . 128 x List of Figures B.11 Temperature hysteresis loop . . . . . . . . . . . . . . . . . . . 129 C.1 PowerSupply AD.SCHDOC [38] . . . . . . . . . . . . . . . . . 131 C.2 VoltageSensor.SCHDOC [38] . . . . . . . . . . . . . . . . . . 132 C.3 CurrentSensor.SCHDOC [38] . . . . . . . . . . . . . . . . . . 133 C.4 TMPSensor.SCHDOC [38] . . . . . . . . . . . . . . . . . . . . 134 C.5 Driver.SCHDOC [38] . . . . . . . . . . . . . . . . . . . . . . . 135 C.6 MUBW20.SCHDOC [38] . . . . . . . . . . . . . . . . . . . . . 136 C.7 Control board PCB [38] . . . . . . . . . . . . . . . . . . . . . 137 C.8 Control board PCB top layer [38] . . . . . . . . . . . . . . . . 138 C.9 Control board PCB bottom layer [38] . . . . . . . . . . . . . 139 C.10 Power board PCB [38] . . . . . . . . . . . . . . . . . . . . . . 140 C.11 Power board PCB top layer [38] . . . . . . . . . . . . . . . . . 141 C.12 Power board PCB bottom layer [38] . . . . . . . . . . . . . . 142 D.1 Schematics for 3-phase islanding test [38] . . . . . . . . . . . 144 xi Glossary DG Distributed Generation PV Photovoltaic EPS Electrical Power System EUT Equipment Under Test AFD Active Frequency Drift DR Distributed Resources PJD Phase Jump Detection PCC Point of Common Coupling IEEE Institute of Electrical and Electronics Engineers PSIM PowerSIM simulation software MATLAB MathWorks simulation software PWM Pulse-Width Modulation RPV Reactive Power Variation PLL Phase-Lock Loop THD Total Harmonic Distortion NDZ Non-Detection Zone SMS Sliding Mode frequency Shift MSD Main Monitoring with Allocated Switching Devices PLCC Power Line Carrier Communication SCADA Supervisory Control and Data Acquisition xii Acknowledgements I would like to acknowledge the patience and support of my advisor Professor William G. Dunford. Without him I would not have the guidance and drive to move forward. I would also like to acknowledge my colleague Wei Feng for our collaboration in this research and the long hours spent working on the hardware. I would also like to acknowledge all my colleagues in the power lab for their support. To my parents for being patient and their prayers. To Chris Westcott and his family for their constant love and support. To my late brother who was my example of living life fully and believing in me. I miss you very much! xiii Chapter 1 Introduction The popularity of distributed generation (DG) systems has improved in recent years due partially to development in performance and largely to government deregulation. For example, the increase in the number of pho- tovoltaic PV systems naturally drives cost down as more units are produced. Generally, PV systems generate distribution level voltage and can be inte- grated to the utility grid using inverters. Bene\u000Cts of using PV systems are not limited to only the customer. Distribution and transmission relief, peak shaving, deferral of high cost transmission and distribution upgrades are some utility bene\u000Cts. From the customer prospective, e\u000Bective use of en- ergy, better power quality and reliability, tax and subsidization incentives, and positive environmental impact are some bene\u000Cts customers would enjoy. In spite of these bene\u000Cts there are hazards when PV systems in partic- ular, or DG systems in general, are connected to the utility grid. When local power generation energizes a portion of the distribution network with- out supervision and control of the utility, it would be a source for potential hazards that can be summarized as causing: 1. harm to maintenance personnel when servicing the energized feeder. 2. damage to utility customer equipment due to voltage and or frequency being uncontrolled. 3. damage to switching or measuring devices due to unsynchronized re- closure 4. malfunction of automatic re-closing devices. The previous concerns are amongst other factors that highlight the im- portance of the standard of interconnection of distributed resources (DR) with the utility. IEEE standard 1547-2005 de\u000Cnes islanding and sets a test to measure the e\u000Bectiveness of islanding detection schemes. In the process of investigating the standard's test of unintentional islanding, a clear de\u000Cnition of an island becomes critical for proper identi\u000Ccation. 1 1.1. Island De\u000Cnitions 1.1 Island De\u000Cnitions The term island might be misleading but in power systems an island is de\u000Cned as A portion of an Area EPS is energized solely by one or more Local EPSs through the associated PCCs while that portion of the Area EPS is electrically separated from the rest of the Area EPS [1]. where Area EPS is the facility of the electrical power system that delivers power to local electrical power systems (Local EPS) at a point in the grid. That point, the point of common coupling (PCC), the Local EPSs such as distributed resources (DR) could sustain the local load demand creating an island that the Area EPS has no control over. Identi\u000Ccation of such an island is critical at the PCC for safety reasons. When islanding conditions exist, isolation of the island is critical and usually occurs on the distribution line, but islanding may also occur on transmission lines when large numbers of grid-connected inverters or other distributed generation are present. The islanding condition covered in this document occurs when the low voltage distribution lines are interrupted. A worst case scenario for this condition is when the island is localized and not including the main transformer. Another de\u000Cnition for an island is described as a portion of the distribu- tion system that is self energized intentionally or accidentally and isolated from the utility grid. 1.2 Islanding Prevention Numerous islanding prevention methods have been developed. These meth- ods can be organized in three main categories. Passive, active, and al- ternative methods. A review of islanding detection methods is included to better understand the worst case scenario under unintentional islanding conditions. The review will brie\ry describe the most common methods and some recently developed ones based on principle of detection, strengths ,and weaknesses. 1.2.1 Passive Methods Passive methods monitor selected system parameters. If monitored parame- ters are out of the permitted operational range, a potential island is identi\u000Ced 2 1.2. Islanding Prevention (a) (b) Figure 1.1: Power \row before (a) and after (b) grid-disconnection. and a cessation of energy command is issued. An advantage of implementing a passive method is its zero in\ruence on the Area EPS. Over/Under Voltage and Frequency Detection The principle of over/under voltage and over/under frequency detection methods is to monitor the grid-connected DG inverter voltage and frequency. If either is out of the recommended threshold range1, a potential islanding condition is con\u000Crmed and the DG inverter ceases to energize the Local EPS. The recommended threshold voltage and frequency ranges are according to [1] and [2]. At the moment of disconnection, if local generation and Local EPS load are not under balanced power conditions, there is real and reactive power mismatch supplied by the Area EPS and is de\u000Cned as illustrated in Fig- ure 1.1. The real and reactive power mismatch is the di\u000Berence between the real and reactive power supplied by the DG inverter and the real and reactive power consumed by the local load, respectively, just before the moment of utility disconnection. Pload = Pinv +\u0001P Qload = Qinv +\u0001Q (1.1) The average inverter real and reactive power supplied is de\u000Cned as Pinv = VinvIinv cos(\u001E) Qinv = VinvIinv sin(\u001E) (1.2) 10 :88 \u0014 V \u0014 1:1p:u: , 59:3 \u0014 f \u0014 60:5Hz 3 1.2. Islanding Prevention Vinv and Iinv are the rms values at the PV inverter terminals and cos(\u001E) is the displacement power factor (d :p:f). The island load is modelled as parallel RLC components. Real power is expressed as, Pload = V 2inv R (1.3) reactive power is expressed as, Qload = V 2 inv \u0012 1 !L \u0000 !C \u0013 (1.4) After disconnection, the voltage and frequency are uncontrolled and the new operating point should satisfy the balance of real and reactive power be- tween the DG inverter and island load. Under such conditions, the following could be concluded: \u00E2\u0080\u00A2 In most cases real and reactive power mismatch is large. \u0001P > \u000620% or \u0001Q > \u00065%. \u00E2\u0080\u00A2 If reactive power mismatch is positive (\u0001Q > 0), then the inverter frequency will increase until the reactive power supplied by the local EPS capacitance equals that consumed by the island load inductance. On the other hand, if reactive power mismatch is negative (\u0001Q < 0), then the inverter frequency will decrease until the reactive power supplied by the local EPS capacitance equals that consumed by the island load inductance. \u00E2\u0080\u00A2 If real power mismatch is positive (\u0001P > 0), then the inverter voltage will be higher than the Area EPS voltage and if real power mismatch is negative (\u0001P < 0), then the inverter voltage will be lower than the Area EPS voltage. Literature Opinion suggest that islanding conditions of \u0001P and \u0001Q falling into the none-detection zone (NDZ) of the over-voltage/under-voltage or over-frequency/under-frequency protection could be signi\u000Ccant [3]. Phase Jump Detection (PJD) Phase jump detection (PJD) is to monitor the phase di\u000Berence between the Area EPS voltage and DG inverter current. In the presence of Area EPS, the voltage source can be assumed sti\u000B at system voltage and frequency. The 4 1.2. Islanding Prevention DG inverter operates as a power conditioner, regulating sinusoidal current impressed onto Area EPS voltage. The phase of the DG inverter current is synchronized to the Area EPS voltage via phase-lock loop (PLL). At the instant of island creation (grid-disconnection), power mismatch between island load and DG inverter will force the voltage to phase jump to a new operating condition to balance power Equation 1.1. An island is con\u000Crmed if the phase error due to the island inductance exceeds a predetermined threshold phase angle [4]. This method is simple and easy to implement using phase-lock loop by analog circuit or digital signal processor (DSP). The size of NDZ is reduced by setting the threshold phase angle \u001Eth to a small value. The disadvantage is with smaller \u001Eth, false detection can occur due to start-up of induction motor or switching power factor correction capacitor. This method also fails when power factor is near unity. Voltage Harmonic Detection The principle of voltage harmonic islanding detection is to monitor the to- tal harmonic distortion (THD) of the DG inverter for certain change in harmonic distortion. At the point of common coupling, voltage harmonic distortion content increases signi\u000Ccantly due to interaction between island loads (high impedance), DG inverter current harmonics, presence of non- linear power electronic loads in the island, non-linear excitation current of distribution power transformer and other local EPS harmonic sources. In this method, islanding is con\u000Crmed when total harmonic distortion exceeds certain set threshold values [5]. This method is e\u000Bective due to the fact that it does not rely on power mismatch. However, this method is computationally expensive compared to other passive methods. Also, if an island has a load with a high load quality factor, Qf = R p C=L, it would serve as a low-pass \u000Clter for wide range of frequencies. Thus, THD might remain within threshold and detection fails. Finally, setting a value for threshold THD might be di\u000Ecult. If the selected value for THD is too low 2, it will render the method impractical due to failure in detection. 1.2.2 Active Methods The principle of this category of methods is to slightly perturb a system variable such as voltage or frequency and simultaneously observe their im- 2(THD < 0:5%) 5 1.2. Islanding Prevention pact. Islanding is detected if observed variables are forced out of threshold range. Output Real or Reactive Power Variation The principle of output power, real or reactive, variation is to perturb the output power of the DG inverter and simultaneously monitor the voltage magnitude if real power is varied, or frequency if reactive power is varied at the inverter terminals. Islanding is con\u000Crmed when the inverter voltage or frequency falls out of the threshold limits 3. Let real and reactive power be de\u000Cned as P = \u0016P +\u0001P (1.5) Q = \u0016Q+\u0001Q (1.6) where \u0016P and \u0016Q are the average real and reactive power, respectively. While \u0001P and \u0001Q are the perturbed real and reactive power, respectively. Voltage variation, \u0001V , can be expressed as a function of real power variation and load real power (see Equation 1.7) [6{8]. Frequency variation, \u0001!, can also be expressed as a function of reactive power. \u0001V = \u0001P 2 r R Pload (1.7) This method is robust and e\u000Ecient in reducing the NDZ to zero in the case of single inverter connected to the utility network. The e\u000Eciency of this method starts to decline as more inverters are connected to the utility network. Statistically, the NDZ will increase as more inverters start varying power without any synchronization. The result of the multiple independent inverters varying real or reactive power without synchronization will produce an inadequate real power mismatch (\u0001P = \u000620 p.u.) in the case of real power variation and the voltage at the inverter terminals remain within threshold. This method is e\u000Bective in a single inverter connected to the grid case, but probability of failure increases in multiple inverter penetration. Also, large power variation might cause poor power quality. i.e. voltage \ricker and grid instability. Impedance Measurement The impedance measurement method is derivative of the output variation method. The real output power is frequently varied while simultaneously 30 :88 \u0014 V \u0014 1:1p:u: , 59:3 \u0014 f \u0014 60:5Hz 6 1.2. Islanding Prevention calculating the network impedance by determining the rate of change of the inverter voltage with respect to the inverter current. An island is con\u000Crmed if signi\u000Ccant increase in network impedance is observed above a predetermined impedance threshold. Z = \u0001V \u0001I (1.8) This method is similar to output power variation method but it is dif- \u000Ccult to set a threshold for implementation. With local load varying over time, the threshold impedance could be rendered ine\u000Bective or cause incon- venient tripping of the inverter. For proper implementation and avoiding false detection, an accurate value of grid impedance must be arrived at which might not be known or available. Hence, this renders this method impractical [8]. Sliding Mode Frequency Shift (SMS) In this method, the grid voltage frequency is monitored and any increase in frequency from the nominal value will trigger the control of the DG inverter to increase the phase angle between the grid voltage and generated inverter current. In the absence of the grid, the increase in phase angle will result in a closer zero crossing and further increase in frequency and an uncontrolled slip occur until the frequency is no longer within nominal operating limits. The same concept is applied for any decrease in grid voltage frequency which will trigger the DG to further decrease the phase angle [9, 10]. In both cases, the voltage at the point of common coupling is moni- tored for frequency slip due to the unstable inherent nature of the detection method. This method is e\u000Bective in detecting the islanding state and reduces the NDZ greatly except for a perfectly matched load which will maintain an unchanged frequency. To vary the inverter frequency, the starting phase angle of the inverter current is controlled via a sinusoidal function that is suggested for varying the starting phase angle of the current. \u0012 = \u0012max \u0001 sin 8>>: \u0019(f \u0000 f0) 2(fmax \u0000 f0) 9>>; (1.9) where \u0012max is the max phase shift corresponding to the max frequency change; change of fmax. In the presence of utility, it is assumed that in- verter supplies constant real power output and zero reactive power. f0 is the utility frequency. 7 1.2. Islanding Prevention This method is e\u000Ecient in reducing the NDZ close to zero. It provides a good compromise option between output power quality and accurate detec- tion. This method would fail if the load phase angle and the starting phase angle are matched within the NDZ. Another possibility of unsuccessful de- tection is if the rate of change of the starting phase angle of the inverter is less than that of the load line with respect to frequency [8]. Active Frequency Drift (AFD) The method of active frequency drift is to push the inverter current fre- quency higher or lower by a positive feedback control design. Again, island- ing is con\u000Crmed if inverter current frequency is pushed out of threshold limit [10]. The current waveform that implements a positive active frequency drift is shown in Figure 1.2. Since the inverter current is generated with a fre- quency slightly higher than that of the utility voltage, when the inverter current reaches zero it is held at zero for a chopping period Teff until next zero crossing of utility voltage. Similarly, for the negative half cycle of the inverter current, when the current reaches zero, it is held for a period of Teff until the utility voltage crosses zero again. When the inverter is connected to the Area EPS, reactive power is sup- plied to utility and can be expressed as Q = Vinv \u0001 Iinv \u0001 sin(\u001Epf ) (1.10) where Vinv and Iinv are the rms inverter terminal voltage and current, re- spectively. \u001Epf is the phase o\u000Bset due to perturbing the frequency. Since the local EPS load is a parallel RLC load, the reactive power is expressed as Qload = V 2 \u0012 1 ! \u0001 L\u0000 ! \u0001 C \u0013 (1.11) and the reactive power mismatch can be expressed as \u0001Q = Qinv \u0000Qload (1.12) Therefore, it can be concluded that: \u00E2\u0080\u00A2 If (\u0001Q > 0) reactive power mismatch is positive, the frequency will increase gradually so the load can supply reactive power to match that supplied by the inverter and (\u0001Q = 0). \u00E2\u0080\u00A2 If (\u0001Q < 0) reactive power mismatch is negative, the frequency will decrease so the load produces less reactive power to match that sup- plied by the inverter and (\u0001Q = 0). 8 1.2. Islanding Prevention Figure 1.2: Voltage and current output of EUT implementing AFD This method of drifting the inverter frequency up/down is e\u000Bective in detecting islanding and eliminating NDZ to almost zero. However, this method is rendered ine\u000Bective if the phase o\u000Bset generated by perturbing the inverter frequency matches that of the load and within the NDZ region. Also, for widespread penetration, interaction amongst inverters implementing this method might render it ine\u000Bective and could cause detection failure. Except when all inverters adopt the same drifting direction. In Figure 1.2, when the island is formed, the voltage will change frequency matching the current and detection is achieved in principle. Main Monitoring Units with Allocated All-Pole Switching Devices (MSD) The principle of this method is to employ two separate mains monitoring with allocated switching devices (MSD) in cascade to perform a self test to ensure reliability of both islanding detection devices. The design of auto- matic disconnection devices allocated all-pole switches must be electrome- chanical with load break rating. i.e. relays or magnetic contactors. Any of the islanding methods can be employed in both MSDs. Over/under voltage and frequency can be employed. Impedance measurement method can be employed too. For grid impedance method, islanding is con\u000Crmed when a change in network impedance is observed [11]. Advantages and disadvantages of this method are similar to that of impedance measurement. In addition, the redundant design and automatic self test improves reliability of detection. Periodic approval of inverters re- quested by the distributed network operator (DNO!) is not required. The dispensable switches (SW2) in the redundant design adds additional cost to 9 1.2. Islanding Prevention the inverter. 1.2.3 Alternative Methods These alternative methods employ di\u000Berent techniques that are neither ac- tive nor passive methods. They are often employed at utility level and include: \u00E2\u0080\u00A2 Reactance insertion. \u00E2\u0080\u00A2 Carrier communication method. \u00E2\u0080\u00A2 Supervisory control and data acquisition. Reactance Insertion This method depends on the insertion of a low-value impedance to a distri- bution feeder with a short delay of time after disconnection [8]. If a capacitor bank is inserted a short delay after disconnection, it will supply additional reactive power to the load and unbalances reactive power between inverter and load. If this unbalance drives the island frequency out of threshold range, the newly created island is detected. Another variation of this method is the insertion of a low-value resistance to unbalance real power between inverter and load and drive the voltage out of threshold limits. This method is highly e\u000Bective and reduces the NDZ to zero, if a capac- itor bank is installed and coordinated with additional delay time. However, this method has a slow response time compared to active methods. Also, the cost for implementing this method is signi\u000Ccantly higher as every dis- connection switch need to be set up and equipped [6]. Power Line Carrier Communication (PLCC) The principle of this method is to use a low-power communication signal (beacon) sent by a transmitter at utility side through the distribution net- work. Islanding is con\u000Crmed if a receiver installed at the inverter can not receive the signal from the transmitter [12]. For a continuity test, a continuous communication signal is preferred since it is more reliable than a discrete or digital signal. With intermittent signals, loss of signal due to discontinuity or cessation of transmitter signal can not be distinguished without further encoding and decoding. Trans- mitter signal need to be of low frequency (i.e. < 500Hz) so it can pass 10 1.3. Standard Test of Unintentional Islanding inductance without di\u000Eculty. In addition, subharmonic signals are desired because loads are not are not able to reproduce it. This method is highly e\u000Bective and e\u000Ecient. It eliminates NDZ and is una\u000Bected by the number of inverters connected to the utility. With existing automatic meter reading, a setup can be constructed to use AMR signal in conjunction with an inexpensive receiver. However, for now, this method is not as attractive due to the fact that this transmitter is uncommon and expensive. This method is most attractive for high density distributed generation penetration. Supervisory Control and Data Acquisition (SCADA) The principle of the SCADA method is to monitor the state of the entire distribution system (V; f; etc). When an inverter is installed, a voltage sens- ing device need to be installed for that part of the network [8, 13]. Through communication links with the control station, all sensing devices feed in their local information. If voltage is still sensed after utility disconnected from a particular part of the network, islanding is con\u000Crmed and measures are taken to cease generation in that part of the network to avoid personal injuries while servicing the isolated feeder. Out of phase re-closure can also be avoided. This method is highly e\u000Bective and eliminates NDZ if proper imple- mentation of instruments and control is applied. The cost of this method makes it unattractive as every inverter need to be \u000Ctted with a sensor. The cost of the sensor and communication to send information to central station makes this method impractical for the time being. With higher density of distributed generation and reduced cost of the instrument and communica- tion in the future, might turn this method to be well suited for islanding detection amongst other applications. 1.3 Standard Test of Unintentional Islanding Present electrical power systems are designed to supply power unidirection- ally. With more DG systems being connected to the EPS network, there are safety and power quality concerns that need to be addressed. A uniform standard of interconnection was established in the form of IEEE Std 1547 - IEEE Standard for Interconnecting Distributed Resources with Electric Power Systems. Of particular interest to this work is the test procedure for unintentional islanding test outlined in IEEE Std 1547.1-(5.7.1) [14]. 11 1.3. Standard Test of Unintentional Islanding Figure 1.3: Initial islanding test circuit with matched load Figure 1.4: Islanding test circuit according to the German proposal [15] Islanding condition of matched real power between DG inverter and local EPS load to obtain as close as possible zero current from the utility is some- times su\u000Ecient for the creation of a stable island [15]. For newer inverters with unity power factor and no islanding detection control the probability of islanding is greatly increased. Figure 1.3 shows an earlier islanding test circuit used to island the test DG inverter [15]. The procedure was to vary the resistive load to obtain as close as possible zero current from the grid side. As inverter technology advances, more inverters with low frequency ring- core transformers are manufactured. These inverters inherently draw a cer- tain amount of reactive power from the grid. Therefore, an earlier German proposal [15] suggested the addition of a resonant LC elements to simulate the mains with limits of \u0006100 VARs in addition a resistive impedance in parallel with switch SW as in Figure 1.4. The matching of real and reactive power with the load increases the probability of islanding especially if the load resonant frequency is tuned to the EPS frequency. The German pro- posed test added discrete island stabilizing elements, L and C, which made it closer to actual islanding conditions. (EUT). Another islanding test circuit was proposed in Japan that is similar to the German proposal except with the addition of an idling ac motor of around 500W and without the mains simulated oscillator circuit and Z =1 [16]. The standard for interconnecting DR with electric power systems was 12 1.4. Advantages and Shortcomings of the Standard Test Figure 1.5: IEEE Std 1547 unintentional anti-islanding test circuit developed due to a growing concern for the probability of unintentional is- landing and to have a uniform benchmark for interconnecting fuel cells, pho- tovoltaics, distributed generation, and energy storage units with electrical power systems [1]. The standard requires all equipment meant for connecting with the grid EPS to pass an unintentional anti-islanding test. The EUT must detect the simulated island of the circuit in Figure 1.5 within a speci\u000Ced time limit (2 sec) to be certi\u000Ced as a non-islanding inverter appropriate for interconnection with the grid systems. 1.4 Advantages and Shortcomings of the Standard Test For an unintentional islanding test, the reactive-power portion originating from the active frequency drift for example is not compensated for by the test LC load [13]. That means reactive power mismatch typically is not zero and hence implies that the conditions of the test do not simulate a worst-case scenario. In addition, the case where other detection methods dynamically perturb or indirectly change the inverter output reactive power, the static LC load is not capable of tracking changes to reactive power mismatch. The same applies for methods based on voltage or real power variation. The static RLC load in the unintentional islanding test poses the ques- tion of how e\u000Bective will the static RLC load be in an islanding test with more advanced DG systems being developed? The island RLC load is clearly e\u000Bective in matching the bulk power generated by the DG unit under test but there is a clear need for a dynamic element to guarantee matching P and Q of the load to that of the equipment being tested. Another shortcoming of the discrete simulated island load is the fact that cost, size, test environment and setup time are factors that need to be considered when testing higher power inverters. Due to the unity quality 13 1.5. Motivation and Dissertation Outline factor required in the test, inductance and capacitance size increases dra- matically. As an example, a quality factor of 0.5 would lead to a signi\u000Ccant value for inductance and capacitance [17]. 1.5 Motivation and Dissertation Outline Initially, approaching the islanding issue from the probability of its occur- rence has raised some serious questions of how valuable the research would be in this topic. As reviews of the problem take shape considering future implication of higher penetration and distributed generation, the islanding problem becomes a key topic in the interconnection of DG inverters with the EPS network. Researching the methods for islanding detection has motivated this re- search initially to investigate the possibility of improving some already es- tablished detection methods by reducing their non-detection zone. Active frequency drift was one method that was investigated as well as negative sequence current injection. As the research and researcher matures in the topic of islanding, focus was shifted to how these methods are evaluated. The numerous islanding detection methods approach islanding detection in di\u000Berent and some in radical ways. From passive measurement and analysis, to actively perturbing system parameters, to using carrier signals to exclusively determine the state of the local EPS network. The accurate representation of the lab simulated island is key to e\u000Bec- tively determining the actual NDZ of the islanding detection method under test. The motivation for this research stemmed the problem of how to ac- curately represent the simulated island in order to reproduce a worst case islanding scenario in a lab environment that meets the criteria of IEEE 1547 and be accurate, cost e\u000Bective, reproducible, scalable, and portable. The thesis \u000Crst reviews the islanding problem and methods of detecting islanding conditions. In chapter 2, the unintentional islanding test of IEEE 1547 is presented and simulated. The results of the test will be discussed and a test bench is established for accurate comparison between the proposed islanding test and the standard one. Next, the proposed unintentional is- landing test is introduced in all it's derivatives in chapter 3. An initial and a more robust designs of the ISE are presented in chapter 4 for single and three phase circuits. Chapter 5, will include results of the proposed unintentional islanding test and a comparison to the standard test. Experimental results of the development of the ISE is presented in chapter 6 and \u000Cnally conclu- 14 1.5. Motivation and Dissertation Outline sion of the work done and results are summarized in chapter 7 in addition to future work. 15 Chapter 2 The Standard Unintentional Islanding Test Islanding condition of matched real power between DG inverter and Local EPS load to obtain as close as possible to zero current from the utility is sometimes su\u000Ecient for the creation of a stable island [15]. For newer inverters with unity power factor and no islanding detection control the probability of islanding is greatly increased. The standard for interconnecting distributed resources with the electric power systems was developed as a result of the growing concern regarding the probability of unintentional islanding and to have a uniform benchmark for interconnecting fuel cells, photovoltaics, distributed generation, and energy storage units with the electrical power systems [1]. The standard requires all equipment meant for connecting with the grid EPS to pass an unintentional islanding test. The equipment under test (EUT) must detect the simulated island in the circuit of Figure 2.1 within a speci\u000Ced time limit to be certi\u000Ced as a non-islanding equipment appropriate for interconnection with the grid EPS. According to IEEE Std-1547.1, an EUT passes the unintentional islanding test if detection occurs within a 2 sec window beginning from the time of the simulated island creation [1]. The unintentional islanding test of IEEE's Std. 1547 is used here to measure the e\u000Bectiveness of the proposed method. Since the simulated island Figure 2.1: Unintentional islanding test per-phase circuit 16 Chapter 2. The Standard Unintentional Islanding Test is represented by a parallel RLC load, the power delivered to the simulated island is governed by Pload = V 2 R (2.1) Qload = V 2 \u0014 1 !L \u0000 !C \u0015 (2.2) where Pload and Qload are the real and reactive power delivered to the load, respectively. In the presence of the utility and assuming the EUT operate at unity power factor, real power will be governed by the voltage at PCC as per Equation 2.1. Since the EUT is programmed to supply the full load real power at utility voltage, voltage imbalance after utility disconnect will be minimized and would remain within nominal operating limits. On the other hand, in the absence of the utility, the voltage at PCC is unregulated and any mismatch in real power will either drive the voltage up or down to achieve real power equilibrium between the EUT and the simulated island load (R). In the same circumstance, any reactive power mismatch will drift the island frequency to the simulated island (LC) resonant frequency of Equation 2.2 to achieve reactive power equilibrium. In order to establish the simulated island, a matched resonant LC load tuned at utility frequency will ensure maintaining the frequency within nominal operating limits after grid- disconnection. Also, to maintain the voltage within threshold limits, real power generated by the EUT should be as closely matched to the simulated island load (R) to maintain nominal voltage at PCC. These two conditions ensure sustaining the island and maintaining normal voltage and frequency operating conditions. For the circuit of the unintentional islanding test of Figure 2.1, the RLC elements could be calculated based on the following equations: L = R !Qf (2.3) C = Qf !R (2.4) Qf = R r C L = p QLQC P (2.5) where Qf is the quality factor for the parallel RLC load and QL and QC are the reactive powers for L and C, respectively. According to IEEE 1547 and the European standard for interconnection IEC 62116, Area EPS is typically operated at a power factor higher than 17 2.1. Simulation Environment 0.75 under normal conditions. In the unintentional islanding test, a unity load quality factor would ensure testing the EUT under near real-world con- ditions. In the European standard a load quality factor of 0.65 is speci\u000Ced for the unintentional islanding test which would imply an uncorrected line power factor of 0.84. The lower the load quality factor, the easier it is to design perturbation based active methods that do not in\ruence power qual- ity negatively. Requirements of the IEEE Std. 1547 unintentional islanding test stipulate a Qf of 1, an equivalent to an uncorrected line power factor of 0.707, which is a closer representation of real-world line power factor for a possible island as opposed to the wider range of IEEE Std. 929-2000 load quality factor of \u00142.5 that represents an uncorrected line power factor of 0.37 or higher [2]. This islanding test setup and parameters conditions ensures minimal power mismatch supplied to or delivered from the grid EPS. In this chapter, The simulation tool used to build the models is described and the standard unintentional islanding test circuit is detailed. Then the test circuit parameters are calculated and a veri\u000Ccation of the proper per- formance of the circuit is conducted to ensure the creation of a sustainable island. After which unintentional islanding tests are carried out for both the single and three-phase inverters referred to them as EUTs. Finally, analysis of unintentional islanding tests are discussed and possible improvements are suggested. 2.1 Simulation Environment The simulation software that was most appropriate for this research is PSIM [18]. It is a power electronics simulation software with the capability of fast simulation and of switch based circuits. Also it o\u000Bers ease of use within powerful simulation environment. The complex design of the islanding test becomes apparent with an accurate design of the non-islanding inverter, sin- gle or three phase. PSIM o\u000Bers an intuitive and straight forward graphic user interface for the design. The large design of the proposed island sta- bilizing element, the inverter model and control of both inverters, became an evident issue with other simulation environments. PSIM provided a sub- circuit container which made it possible to compartmentalize distinct parts of the circuit for ease of tracing, debugging and the power of scalability and reproducibility in other simulations. PSIM is e\u000Ecient for simulations of circuits with convergence problems and long simulation time. Its simulation engine is faster than other simula- 18 2.2. Test Circuit IC IR IL A A SW3 SW2 SW1 I_EUTI_util I_Load o Simulated Island Area EPS EUT VPCC Figure 2.2: Per-phase unintentional islanding test circuit. tion software and it allows for repetitive simulation runs reducing the design cycle. PSIM's unique features in the handling of power converter circuits, con- trol circuits, and system integrated simulation with MATLAB through Sim- Coupler made it the ideal simulation software to be used to simulate the majority of the simulation for this research. 2.2 Test Circuit The outline of the islanding test circuit is illustrated in Figure 2.2. If the resonant LC load in the \u000Cgure is matched at a resonant frequency equal to the power system frequency, that will ensure minimal \ructuation in oper- ating frequency at the the moment of island creation (grid-disconnection). Also, when real power is balanced between load and EUT, it would maintain the voltage at PCC within nominal operating limits. 19 2.3. Simulated Island Parameters Table 2.1: Unintentional islanding test parameters Parameter Single-phase Pinv 1 kW Qinv 0 kVAR Vn 120 Vrms Iinv 8.33 Arms fo 60 Hz fs 4 10 kHz R 14.4 L 38.179 mH C 184.207 \u0016F PF 1 Qf 1 According to IEEE 929-2000, a simulated island load with a load to gen- eration ratio between 50% and 150% and resonant frequency of 60Hz/50Hz with quality factor Qf = 2:5 or less will satisfy all distribution line power factors and will provide a lab simulated environment to test single inverters unintentional islanding detection [2]. In the more recent IEEE standard of 1547, the quality factor is set to Qf = 1\u0006 0:05 as the simulated island quality factor. It is found to be more realistic to covers most distribution line power factors and provide closer to worst case conditions [1]. 2.3 Simulated Island Parameters In Figure 2.2 the layout of the standard unintentional islanding test required in IEEE Std 1547 was shown. To calculate the size of the simulated island load, the EUT power rating and power factor, Area EPS nominal voltage and frequency need to be speci\u000Ced. Simulated island load can be calculated using Equation 2.3, Equation 2.4 and Equation 2.5. Table 2.1 shows the un- intentional islanding test speci\u000Ccations and the simulated island parameters fR,L,Cg for both single- and three-phase PWM EUT. 20 2.4. Test Procedure 2.4 Test Procedure The standard test applies for both single and three-phase systems. The simulated island load (RLC) is calculated per-phase. Therefore, for the three-phase EUT test, there will be three identical sets of simulated island loads assuming a balanced testing conditions. The initial test starts at the balanced condition between load and EUT with load quality factor set to one. Once the results of this stage are ob- tained, the reactive load is adjusted between 1\u00060:05 in 1% increments from the initial balanced load condition. It is possible ,if convenient, to adjust the EUT output reactive power to produce 1% increments up to \u00065 from the initial balanced condition. If islanding detection time remain increasing, further test iterations of 1%increments of reactive power are performed until the detection time begin to decrease. The next stage of the test reviews the results and two more test iterations are performed for the three longest trip times with the same 1% increments. Next, the test is repeated for 66%5 and 33% EUT output power settings if permissible. 2.5 Simulation Results of the Standard Unintentional Test The standard islanding test was carried out for \u000Cve EUT cases. In the \u000Crst case the EUT tested did not implement any islanding detection scheme in the control. The purpose of this experiment is to verify the parameters chosen for the simulated island (RLC load) and the proper performance of the islanding EUT in maintaining the island during the test. In the second and third cases the standard islanding test was carried out using an EUT implementing an active frequency drift(AFD) and reactive power variation (RPV) anti-islanding control schemes, respectively. The fourth and \u000Cfth cases tested a three-phase EUT with no islanding detection and with RPV anti-islanding control scheme, respectively. 2.5.1 Equipment Under Test (EUT) The Single-Phase EUT: is a single-phase 1kW/120V inverter switching at 20kHz connected to a 300V DC bus. The control implemented is a 550% to 95% output power settings are allowed 21 2.5. Simulation Results of the Standard Unintentional Test simple PI-control and phase-lock loop (PLL) to maintain unity power factor operation. The Three-Phase EUT: is a three-phase 3kW/208V inverter switching at 10kHz connected to a 300V DC bus. The control implemented is a synchronous frame space vector modulation control and the unit is operating at unity power factor. Note: The EUTs power rating used was not due to limitations in the design but to illustrate a per unit rating. The single phase EUT could be scaled (10kW, 100kW, 200kW, etc.) and the same respectively applies for the three-phase EUT. 2.5.2 Test Start/Stop All simulation was carried out for the circuit in Figure 2.3a for single-phase and in the case of three-phase EUT the same circuit is used per-phase. During the test, the Area EPS disconnection occur at t=0.5 sec and the simulation ends at 3.5 seconds. The initial 0.06 seconds are omitted as it is a transient period of the simulation that is not part of the test. In order to determine a PASS or FAIL result, the EUT voltage and frequency Over/Under trip signal is added to the \u000Cgures respectively to show proper islanding detection if the trip signals occur within the 2 seconds test window from the time the Area EPS disconnects. 2.5.3 Case 1: The Single-Phase Islanding EUT An islanding EUT is connected to the test circuit to verify creating and sustaining the island within nominal operating voltage and frequency lim- its. In Figure 2.3a, the magnitude of the PCC voltage before and after grid-disconnection is shown to remain within the upper and lower voltage limits for the period of the test. The minimal change in voltage amplitude indicates that real power matching condition is achieved. For the frequency of the EUT, Figure 2.3b shows the frequency also with in upper and lower limits. The frequency remaining virtually constant before and after grid- disconnection is an indication that the reactive power matching condition is also achieved. These two parameters are enough to successfully establish and sustain the simulated island. Figure 2.4 illustrates the EUT output current and PCC voltage before and after grid-disconnection. The control for this EUT samples the PCC 22 2.5. Simulation Results of the Standard Unintentional Test (a) Voltage magnitude (pu). (b) Frequency (Hz). Figure 2.3: Voltage and frequency 23 2.5. Simulation Results of the Standard Unintentional Test Figure 2.4: EUT, EPS, and load currents (pu). voltage and calculate the reference current according to the command power then synchronize the current to PCC voltage via PLL for unity power factor operation. During this test, real and reactive power are monitored and the expected mismatch in this case is zero. Power-matching of the EUT and the simulated island (RLC) in the presence or absence of the Area EPS is expressed as P load = PEUT +\u0001P (2.6) Q load = QEUT +\u0001Q (2.7) The EUT, Area EPS, and load real and reactive powers are shown in Figure 2.5a and Figure 2.5b. The simulated Area EPS real and reactive power \row immediately before the moment of grid-disconnection is almost zero ( \u0016PEPS = 0:5 \u0002 10\u00003pu ; \u0016QEPS = 0:06 \u0002 10\u00003pu). While the EUT and load are matched at 1pu of real power and since the load LC are matched, the apparent load is resistive and the EUT operating at unity power factor therefore the reactive power produced by the EUT is also negligible ( \u0016QEPS = 0:39\u0002 10\u00003pu). The compared results con\u000Crm the matching power condition and con\u000Crm the ability of the EUT to sustain the simulated island throughout the test period. Continuing the test for the purpose of illustrating the test circuit proper performance, the reactive EUT power was incremented by 1% to \u00065% from initial balance condition (QEUT = 0). Trip times have been recorded as 24 2.5. Simulation Results of the Standard Unintentional Test (a) Real power (pu). (b) Reactive power (pu). Figure 2.5: Real and reactive power . 25 2.5. Simulation Results of the Standard Unintentional Test Figure 2.6: Frequency response of EUT during the standard islanding test. 26 2.5. Simulation Results of the Standard Unintentional Test shown in Figure 2.6. In this case, the EUT fails to detect islanding between +2% and -1% increments of reactive power. For negative reactive power increments, the trip times are noticed to reduce while the positive increments increase between 3% and 4% and then reduce at 5%. This EUT failed the standard test since no islanding detection was imple- mented and it is noted that the NDZ for this device is roughly within +3% and -2% of reactive power mismatch, the EUT over and under frequency controls would detect islanding. 2.5.4 Case 2: The Single-Phase EUT with AFD Figure 2.7: EUT PI-controller with AFD control scheme. In this experiment the EUT control implements an active frequency drift scheme for islanding detection as shown in Figure 2.7. The control imple- mented is similar to that reviewed in chapter one. The control of frequency drift is achieved through the chopping fraction expressed as CF = tz 0:5TEPS (2.8) where TEPS is the Area EPS frequency and tz is the time where the EUT current remain zero until the Area EPS voltage reaches zero again (See Figure 2.8). The EUT frequency could be calculated as fEUT = 1 TEPS \u0000 tz (2.9) 27 2.5. Simulation Results of the Standard Unintentional Test and the drift in frequency is the di\u000Berence between the Area EPS and the EUT frequencies. In the \u000Crst part of this case, the chopping factor was set to a constant +5% representing a constant current command frequency of 63Hz. Figure 2.8: EUT current with AFD implementation Figure 2.9 shows the frequency response of the EUT to the 1% increments in load mismatch in reactive power starting from the balanced condition of matched load to \u00065%. It is clear from this graph that the EUT manages to detect islanding for these conditions. Figure 2.10 presents the frequency out of nominal limit trip times. The three largest trip times occur at 0.97, 0.96, 0.95 of load reactive power, hence requiring further 1% increments until trip times begin to reduce. Further 1% increment of load mismatch in reactive power reveal increas- ing trip times. At 0:94QL ttrip = 0:02479 and at 0:93QL ttrip = 0:03314. However, at 0:92QL the EUT fails to detect the island and fails the test. The next part of this case involves adjusting the AFD scheme to be able to detect islanding. The adjustment was made to the chopping fraction so that is varies every Area EPS cycle from +5% to -5%. This simple adjust- ment ensures the ability to detect islanding within the allowed window. results of this part of the case is summarized in Figure 2.11. The 1% increments in load mismatch in reactive power had to be continued to 0:88QL to observe a decrease in trip times. Hence, this EUT passes the \u000Crst part of the standard islanding test. The test requires, if possible, that the EUT output power be adjusted to 28 2.5. Simulation Results of the Standard Unintentional Test Figure 2.9: Frequency response for EUT under standard isalnding test Figure 2.10: EUT trip time for AFD chopping fraction of 0.05 29 2.5. Simulation Results of the Standard Unintentional Test Figure 2.11: EUT with modi\u000Ced AFD trip times (CF=\u00065%). 66% and 33% and repeat the procedure. For the purpose of this research, this portion of the test will not be carried out since it would not add more value for the comparative analysis with the to be proposed test adjustment. 2.5.5 Case 3: The Single-Phase EUT with RPV Reactive power variation is implemented in the EUT control. The current reference is manipulated through a digital PLL [19] to generate a periodical (0.5 s) change in EUT reactive power in an attempt to drive the frequency out of nominal limits. This method was also described in chapter one. An implementation of this method is illustrated in Figure 2.12 which shows the current control loop. In the \u000Crst stage, Figure 2.12a, the PCC voltage is used to generate an in-phase and 90 degree shifted reference signals labeled PLL sin and PLL cos, respectively. In order to generate the required in-phase and 90o phase shifted sinusoidal, \u000C is required and calculated as \u000C = \u00001 + 0:5aTd 1 + 0:5aTd (2.10) where a is the inverse of the all pass \u000Clter time constant and Td is the discrete time step. The next step in this method is to manipulate the output signals of the digital PLL and scale them according to the real and reactive power com- mands. For unity power factor EUT, zero reactive current is commanded, yet for RPV the reactive power current reference is slightly adjusted to generate a periodical reactive power variation with zero average over 0.5 seconds. Figure 2.12b shows the current reference loop for the EUT. Qpct 30 2.5. Simulation Results of the Standard Unintentional Test (a) (b) Figure 2.12: RPV current control loop is the percent reactive power for islanding detection. In this case, reactive power variation is chosen as \u00065%. The period of the reactive power varia- tion of 0.5 seconds was chosen so that within the required 2 seconds window at least two detection cycles are possible and reducing the NDZ as a result. The results of the standard islanding test for an EUT with reactive power variation are shown in Figure 2.13 for a matched load. Islanding detection for this iteration of the test occur at 0.05041 seconds. The test's test results are summarized and shown in Figure 2.14. It is can be observed that trip times are decreasing as mismatch in reactive power increase up to 2% mismatch where the longest trip time is recorded. This test case provide a successful islanding detection by the EUT under standard islanding test procedure. 2.5.6 Case 4: An Islanding Three-Phase EUT The 3kW-120V inverter was connected to the simulated island RLC load and run at 100% rating for 2.5s. The grid-disconnection occurred at 0.25s. Figure 2.15a shows the load active power, and the active power supplied by the inverter and the grid before and after grid-disconnection. It is clear to depict that the inverter active power (Pinv) is almost matching that of the load (Pld) before and after grid-disconnection. Figure 2.15b illustrates the inverter reactive power (Qinv), grid reactive 31 2.5. Simulation Results of the Standard Unintentional Test Figure 2.13: EUT with RPV islanding test Figure 2.14: EUT trip times 32 2.5. Simulation Results of the Standard Unintentional Test (a) Active power (b) Reactive power Figure 2.15: Real and reactive power of the inverter, load and grid power mismatch (\u0001Q), and one of the load passive element's (L or C) reac- tive power. The load quality factor of 1 required by the standard islanding test could be veri\u000Ced from Figure 2.15b. The active and reactive power mismatch between the island load and the inverter supplied by the grid is shown to be almost zero supporting a worst case islanding scenario and the unity power factor operation of the controlled inverter. The voltage and frequency at PCC before and after grid-disconnection are shown in Figure 2.16. From this \u000Cgure, it can be noticed that the voltage and frequency are within nominal operating limits after grid-disconnection for over 2s con\u000Crming a complete islanding creation. (a) Inverter voltage amplitude (b) Inverter voltage frequency Figure 2.16: PCC voltage magnitude and frequency 33 2.5. Simulation Results of the Standard Unintentional Test Figure 2.17: Inverter voltage and current before and after grid-disconnection 2.5.7 Case 5: A Three-Phase EUT with Negative Sequence Injection This case is based on generating an unbalanced reference current commands for the space vector modulation. The synchronous frame V \u0003d and V \u0003 q of the reference current control are transformed into rotating frame and injected with a set of three 1% perturbation shifted by 120o at each phase zero cross- ing. Then the modi\u000Ced rotating reference current commands transformed back to synchronous frame for space vector modulation processing to gen- erate the modi\u000Ced gate signal commands for the three-phase inverter. The objective of this test is to determine the e\u000Bect of unbalance in in- verter currents on the inverter terminal voltages and consequently PCC voltages. In the case of grid connection, the voltage of the PCC is governed by the utility voltage and no signi\u000Ccant e\u000Bect is noticed. In the absence of the grid and continuous stable islanding operation by the inverter, the voltage of the PCC will be a\u000Bected by the current unbalance due to negative sequence current injection. By monitoring the negative sequence component of PCC voltage, island- ing detection could be observed and cease to energize command is issued in the presence of negative sequence PCC voltage above a predetermined threshold level. In Figure 2.18, the instantaneous negative sequence component in the PCC voltage under islanding operating conditions without the propose cur- rent space vector reference command perturbation. Also, it shows the same component after perturbing the reference current SVM voltage commands by 1% and 2%. From this \u000Cgure, it is worthy to point that the instantaneous 34 2.5. Simulation Results of the Standard Unintentional Test negative sequence component at PCC is almost unity with grid connection even with 1% or 2% of negative sequence current injection. After grid- disconnection, 2% and 6% change in negative sequence component appears at 0% and 2% injection. This change in negative sequence component is enough to detect the islanding condition. While it is widely assumed that the grid is naturally balanced, there is an inherent minimal level of unbalance that would enable the negative sequence threshold level to be determined based on this reference negative sequence voltage. In recent studies, the negative sequence voltage of a 100MVA, 600V bus system ranged from 0.14 to 0.63V while the negative sequence current ranged from 1.0 to 11.7A [20]. Figure 2.18: Negative sequence voltage component at PCC 35 Chapter 3 Proposed Island Stabilizing Element (ISE) 3.1 Overview of Advantages and Disadvantages of Standard Islanding Test In the previous chapter, the standard islanding test was demonstrated. It was concluded that there are limitations to the current standard test which are summarized in the following: 1. The RLC load is a static load, hence any changes during the test are not compensated. 2. The RLC load tend to increase dramatically in size with higher EUT power rating. 3. The cost for the RLC and setup cost will increase with the power rating of the EUT. 4. The RLC load does not monitor the PCC for any mismatch in power on the EPS side. A more accurate unintentional islanding test is desired. A test that addresses the previous points and recreates in a lab controlled conditions worst case islanding scenario. For reference, the circuit of the unintentional islanding test is shown in Figure 3.1. In the next sections, three islanding test topologies will be introduced and an initial design for the island stabilizing element proposed will be discussed. 3.2 Modi\u000Ced Unintentional Islanding Test The modi\u000Ccation proposed for the islanding test is intended to address the issues discussed in the previous section. In order to eliminate the size issue with larger power EUTs, a power electronic solution is proposed to replace 36 3.3. Island Load P & Q Figure 3.1: Standard unintentional islanding test the RLC load of Figure 3.1 fully or partially. A current controlled current source is used as an island stabilizing element, their after labeled ISE. The main function of the ISE is to monitor the voltage at the point of common coupling and current of the EUT and match the active and reactive power so that the mismatch in P and Q is reduced to zero. In this method, a worst case scenario for islanding is achieved while maintaining a relatively contained size for the load while reducing cost and setup time. In addition, the ISE makes it possible to dynamically match the EUT real and reactive power during the test so that any mismatch produced during the test is matched by the load. In the following sections, an initial investigation into di\u000Berent proposed unintentional islanding tests topologies is carried out. The \u000Crst topology is replacing the resonant elements with the ISE (representing Qload only) and analyzing the performance of the island. The second topology is a more en- compassing approach by letting the ISE represent the complete island load (producing Pload and Qload). The last topology option places the ISE in parallel with the bulk island load (RLC). In this setup, the ISE will func- tion as a P and Q mismatch compensator during the test. These di\u000Berent topologies have advantages and disadvantages that will be discussed in each section accordingly. 3.3 Island Load P & Q Referring to the standard test circuit of Figure 2.1, Equation 2.6 and Equa- tion 2.7, repeated below for convenience, hold true for any of the proposed unintentional islanding test topologies. Pload = PEUT +\u0001P (3.1) Qload = QEUT +\u0001Q (3.2) 37 3.4. ISE Representing Qload while within the island load, Pload and Qload are dependent on the function of the ISE and its location. A general form of the load active and reactive power can be arrived at when considering all possible elements. Pload = PR \u0006 PISE (3.3) Qload = QL \u0000QC \u0006QISE (3.4) The ISE real and reactive power sign will depend on the amount of mismatch in power between the load and the EUT in the presence of the area EPS. After area EPS disconnects, the voltage of the island will be in sync with the EUT current and the amount of reactive power mismatch after area EPS disconnection will force a frequency shift. 3.4 ISE Representing Qload Figure 3.2: Modi\u000Ced island load with R and ISE The ISE is used to replace the function of the LC components of the simulated test island. Figure 3.2 shows the proposed circuit. The ISE will be responsible for representing the LC elements internally and producing current only in speci\u000Cc reactive power mismatch conditions. Under these conditions, the ISE will produce a current with appropriate magnitude and phase to eliminate any mismatch in reactive power or generate an inten- tional mismatch in reactive power according to the demanded quality factor through out the test. It is important to note here that there are two kinds of reactive power mismatch conditions. The \u000Crst is produced by the EUT during the test, i.e. due to islanding detection method implemented or none unity power factor operation. The second mismatch in reactive power is an intentional one that is part of the unintentional islanding test. In the later case, the ISE is required to produce reactive power mismatch in increments of 1% of the load quality factor6. 6Qf range: 1 \u0006 0.05 38 3.5. ISE Representing Pload & Qload Therefore, in the case of matched LC Equation 3.4 will be the same as Equation 3.2 and that will maintain zero reactive power sourced from the EPS side (\u0001Q = 0). On the other hand, since the ISE represents only the LC elements, PISE = 0 and PR has to be manually matched to PEUT to insure that there is no mismatch in active power. The ISE unit current rating will depend only on the amount of mismatch in reactive power of the LC elements in addition to any reactive power from the EUT. For 3-phase 100KVA 480V EUT, the inductive reactance is compensated by the reactive reactance simulated within the ISE so that only the amount of mismatch between them need to be generated. Therefore, for a unity power factor EUT with no change in voltage or frequency, the ISE current is ideally zero. The disadvantages in this setup is that the real power is wasted as heat in the resistor. With higher power EUTs the resistor bank becomes less economical and could be replaced by the ISE. 3.5 ISE Representing Pload & Qload Figure 3.3: Modi\u000Ced island load with ISE only As in the previous section, the ISE will replace the function of the RLC in the unintentional islanding Test. Figure 3.3 shows the layout of the circuit. As described before, the ISE will simulate the function of the LC elements in addition to representing R. The ISE will function as a real power dump load by matching the EUT sourced active power and either storing it into a battery management system or converting it in multistage back to AC and injecting it into the EPS network. In this case, rather than exhausting power as heat, a power management system ensures the recycling of the power generated by the EUT and min- imizing the wasted energy almost to zero. This setup will be optimum for low to mid power rated EUTs but requires design considerations for higher power units with regards to storage capacity and power recycling back to 39 3.6. ISE Representing Mismatch in P and Q the EPS network. 3.6 ISE Representing Mismatch in P and Q Figure 3.4: Addition of ISE to island load In this last con\u000Cguration, as illustrated in Figure 3.4, the ISE will mon- itor the load and EUT for any mismatch in power and will source or drain power accordingly. For the situations where the available RLC bank is not su\u000Ecient to match the EUT rated power, the ISE would supply the di\u000Ber- ence in power as in PISE = PEUT \u0000 PR (3.5) QISE = QEUT \u0000QLC (3.6) which will result in \u000Cxing the size of the RLC load. In this setup, the ISE rated current will be dependent on the size of available RLC load used in the test. The advantages of this test setup rather than the previous ones is the fact that both P and Q are monitored by the ISE and only the di\u000Berence in power would be supplied by the ISE. On the other hand, the design of the ISE needs prior knowledge of the size of RLC load used in the test. Also, the size of the test equipment is relatively larger than the case of representing only the reactive loads. 3.7 Initial Design of the ISE Since the island load in the islanding test is applied per-phase, the ISE unit design is based on a current controlled current source and the single phase circuit diagram is shown in Figure 3.5. The ISE circuit topology in 40 3.7. Initial Design of the ISE s1 s2 s3 EUT Area EPS R rL L C Vdc Proposed Test Island Figure 3.5: Proposed test island stabilizing element this \u000Cgure shows the case of replacing the LC elements and chosen in this section to illustrate the design and control of the unit. The process of modelling of the island stabilizing element to replace the island load in the standard test was in two stages. Initially, a small-signal based model of the ISE was developed. Later, a synchronous reference frame model of the ISE was developed. The reason for developing the two models is the di\u000Berent control strategy that could be applied and improvement in control. The circuit of Figure 3.6 shows a per-phase representation of the ISE. Here, the single phase inverter could be represented as a sinusoidal volt- age source connected to the utility via an L \u000Clter considering fundamental frequency only and neglecting the higher switching frequencies [21]. Figure 3.6: Per-phase circuit diagram Where ua, ia and EPS (va) are the PWM inverter voltage, inductor current and utility voltage, respectively. 41 3.7. Initial Design of the ISE 3.7.1 Small-Signal Model of the Single-Phase ISE To derive the transfer function of the ISE, a small-signal circuit analysis is carried out to obtain the input-to-output and control-to-output transfer functions. The small-signal analysis was carried out for one switching period, Ts, and the complete (DC & AC) mathematical representation of Figure 3.6 is expressed as d : va = ua + rL \u0001 hiai+ L \u0001 d dt hiai (3.7) d0 : va = \u0000ua + rL \u0001 hiai+ L \u0001 d dt hiai (3.8) It is noted here that hiai is the average of the inverter current over a switching period and while in Figure 3.6 the inverter is not explicitly shown to reverse polarity during d0Ts, it is implied to reverse polarity when switches change con\u000Cguration from state dTs to d 0Ts. In Equation 3.7 and Equation 3.8 ua, va, hiai, d and d0 are de\u000Cned as follows ua = Ua + bua va = Va + bva hiai = Ia +bia d = D + bd d0 = 1\u0000 d (3.9) Where the term accented with a (b) is a small signal variable and capital terms denote a quiescent variable. Equation 3.7 and Equation 3.8 are added to obtain the average inverter voltage over one switching period. va = (d\u0000 d0)ua + rLia + L d dt hiai = (2d\u0000 1)ua + rLia + L d dt hiai (3.10) Replacing the variables in Equation 3.10 with their quiescent and small signal terms of Equation 3.9 yields a full expression of the single-phase PWM inverter. Va + bva = (2D + 2bd\u0000 1)(Ua + bua)\u0000 rL(Ia +bia)\u0000 L d dt (Ia +bia) (3.11) 42 3.7. Initial Design of the ISE Considering only the small signal terms of Equation 3.11 to obtain the input-to-output and control-to-output transfer functions, the equation will be expressed as bva = (2D + 2bd\u0000 1)bua + 2bdUa \u0000 rLbia \u0000 L d dt bia (3.12) Taking the Laplace transformation of Equation 3.12 yields bVa(s) = (2D \u0000 1)bUa(s) + 2 bD(s)bUa(s) + 2Ua bD(s)\u0000 (rL + sL)bIa(s) (3.13) The input-to-output transfer function of the single-phase PWM inverter is arrived at by setting the small signal utility voltage, bVa(s), and pertur- bation in duty cycle, bD(s), to zero and solving for G(s) = jbIa(s)=bUa(s)j yields G(s) = 2D \u0000 1 rL + sL (3.14) The control-to-output transfer function could be obtained by following the same procedure of setting the small signal utility voltage, bVa(s), and inverter voltage, bUa(s), to zero and solving for G(s) = jbIa(s)= bDa(s)j yields Gbd(s) = \u0000 2UarL + sL (3.15) 3.7.2 PI-Controller Design A PI controller , Gc(s), is implemented to improve the control system perfor- mance and provide compensation for the single pole Gbd(s) transfer function. The traditional PI compensator transfer function is expressed as Gc(s) = Kp \u0001 sTI + 1 sTI (3.16) where KI = Kp=TI . Figure 3.7: Closed-loop PI-Control system In Figure 3.7 the compensated closed-loop control system is presented. In order to translate the output of the PI-controller to the input of the 43 3.7. Initial Design of the ISE control-output transfer function Gbd, a comparator is used to generate the duty cycle after a comparison of the output of Gc with a saw-tooth function. Figure 3.8 shows the two inputs of the pulse-width modulator, Vsaw and Vc. From the graph, the linear relationship between the output of the PI controller to the duty cycle is evident and the transfer function of the pulse- width modulator is found to be 1=VM . Figure 3.8: Generation of the pulse width modulated signal 3.7.3 PI-Controller Analysis Figure 3.9: Generation of the pulse width modulated signal Using PSIM software the closed loop control-to-output loop was imple- mented as in Figure 3.9. Values for the PI controller were arrived at using iterative trials. Optimum values for Kp and Ti were found to be 7.785 and 0.0001, respectively. a saturation block was used to limit the PI output between \u00062:48 and VM was set to 2.5 at switching frequency of 10kHz. Also, a unit step response was obtained for the control-to-output loop as in Figure 3.10. It can be seen that the percent overshoot is within 10% and the response of the system is critically damped. A bode plot of the open-loop control-to-output TF is shown in Fig- ure 3.11 where it con\u000Crms the stability of the system with the phase mag- nitude is well below the 0 degrees. 44 3.7. Initial Design of the ISE Figure 3.10: Generation of the pulse width modulated signal 10\u00E2\u0088\u00921 100 101 102 103 104 105 Bode plot of Control to Output TF Frequency (Hz) Figure 3.11: Bode plot of control to output TF 45 3.7. Initial Design of the ISE 3.7.4 Average and Ripple Current To obtain the average and ripple currents in the output stage of the ISE inductor L in Figure 3.6, a list of assumptions are speci\u000Ced as below: 1. During one switching period, the area EPS voltage could be assumed constant and is replaced with a DC voltage source. 2. The ripple is calculated over the window dTs. 3. For values of simulated impedance Zpq \u001D rL, voltage drop across rL could be ignored. 4. For simulated reactive loads, the maximum inductor ripple occur when the area EPS voltage va is at zero. The ISE inductor voltage is de\u000Cned as vL = L dia dt (3.17) also, in terms of the Equation 3.7, the inductor voltage is found to be equal to vL = ua \u0000 va + vr (3.18) From Equation 3.17, Equation 3.18 and ignoring vr, the peak-peak current ripple can be calculated as \u0001ia = ua \u0000 va L \u0001 dTs (3.19) Since both ua and va are DC values, a constant k relating both could be used to simplify the equations. It expressed in terms as k = ua va (3.20) where k is a scalar value and the peak-peak current ripple expressed in terms of area EPS voltage is \u0001ia = (k \u0000 1) L \u0001 dTs \u0001 va (3.21) To solve for the average ISE inductor current, Equation 3.10 is used and the current is expressed as Ia = 1\u0000 (2d\u0000 1)k rL \u0001 va (3.22) 46 3.7. Initial Design of the ISE Since the ISE is designed to represent active or reactive elements, the ISE inductor current could also be expressed in terms of real and reactive power as Ia = q P 2 ISE +Q2 ISE va = jZISE j\u00001 \u0001 va (3.23) Equating Equation 3.22 to Equation 3.23, we can obtain a solution for the duty ratio in terms of P and Q as in d = (k + 1)jZISE j \u0000 rL 2kjZISE j (3.24) Having de\u000Cned the duty cycle in terms of circuit parameters, the ripple ratio could be solved as in \u0001ia 2Ia = (k2 \u0000 1)Ts 4kL \u0001 jZISE j \u0000 rL(k \u0000 1)Ts 4kL (3.25) = \u000BISE [(k + 1)jZISE j \u0000 rL] (3.26) where \u000BISE is a constant de\u000Cned as \u000BISE = (k \u0000 1)Ts 4kL From the above equations, it is evident that the amount of ISE current ripple is related directly to the impedance being simulated within the ISE. Figure 3.12 illustrates how the DC gain factor k could be used as an extra degree of freedom to simulate ZISE at the same time limiting current ripple. For example, at a \u000Cxed ripple ratio of 10%, the ISE DC voltage source could be varied between k=1.1 to 1.8 to obtain a magnitude of simulated impedance in the range between 32 - 209 . From Equation 3.26, it is noted that there is a minimum simulated ZISE at zero current ripple de\u000Cned as ZISE = rL (k + 1) (3.27) 47 3.7. Initial Design of the ISE 0.05 k ripple_ratio 0.10 0.20 0.150 0.00 200 100 z 1.2 300 400 1.4 1.6 1.8 Figure 3.12: Simulated impedance of ISE relationship to current ripple 48 Chapter 4 Improved Control Design for the ISE 4.1 Synchronous Frame Model of the Single-Phase ISE As in chapter 3, the phase equivalent circuits of the ISE is a single-phase PWM inverter as shown in Figure 4.1. The inverter is represented as a voltage source operating at fundamental frequency only and neglecting any higher switching frequency. In frequency domain, the ISE is modelled as a \u000Crst-order system. The transfer function can be obtained in synchronous frame by selecting the inductor current as a state variable and the ISE gen- erated voltage as the control input. The value of rL in Figure 4.1 represents the inductor resistance. Let the ISE DC bus voltage ua, inductor current ia and utility (area EPS) voltage va be expressed as va = Va \u0001 sin (!t) (4.1) ia = I \u0003 a \u0001 sin (!t+ \u001E) (4.2) ua = rL \u0001 ia + !L \u0001 dia dt + va (4.3) where Va and I \u0003 a are the area EPS voltage and reference current maximum amplitudes, respectively. In order to obtain the ISE voltage in synchronous Figure 4.1: Per-phase circuit diagram 49 4.1. Synchronous Frame Model of the Single-Phase ISE frame, a virtual second phase (B) that is 90o shifted from phase A is assumed and expressed as vb\u0003 = Vb\u0003 \u0001 sin (!t+ \u0019 2 ) (4.4) ib\u0003 = Ib\u0003 \u0001 sin (!t+ \u0019 2 + \u001E) (4.5) ub\u0003 = rL \u0001 ib\u0003 + !L \u0001 dib\u0003 dt + vb\u0003 (4.6) Equation 4.3 and Equation 4.6 are combined in a two-phase system that is expressed as \u0014 ua ub\u0003 \u0015 = rL \u0001 \u0014 ia ib\u0003 \u0015 + L d dt \u0014 ia ib\u0003 \u0015 + \u0014 va vb\u0003 \u0015 (4.7) The input-to-output transfer function could be arrived at using the fol- lowing two-phase Park's transformation vdq = Sdq \u0001 vab\u0003 (4.8) \u0014 vd vq \u0015 = \u0014 cos (!t) \u0000 sin (!t) sin (!t) cos (!t) \u0015 \u0014 va vb\u0003 \u0015 (4.9) For the above transformation into synchronous frame, the direct axis fd-axisg lags the quadrature axis fq-axisg by \u0019/2. Since the dq-axis rotates at the system frequency counter-clockwise, values of the voltage and current transformed into this synchronous frame will have constant (DC) values. Multiplying Park's transformation matrix, Sdq, by the system Equa- tion 4.7 will yield Sdq \u0014 ua ub\u0003 \u0015 = rL \u0001 Sdq \u0014 ia ib\u0003 \u0015 + L \u0012 dSdq dt \u0014 ia ib\u0003 \u0015 + Sdq d dt \u0014 ia ib\u0003 \u0015\u0013 + Sdq \u0014 va vb\u0003 \u0015 (4.10) It can be seen that the di\u000Berentiation of the transformation matrix with respect to time will introduce a cross-coupling voltage term between dq-axis and the synchronous frame system equation will be\u0014 ud uq \u0015 = rL \u0001 \u0014 id iq \u0015 + !L \u0001 \u0014 \u0000iq id \u0015 + L \u0001 d dt \u0014 id iq \u0015 + \u0014 vd vq \u0015 (4.11) Taking the Laplace transform of Equation 4.11, the system equation in frequency domain will be\u0014 Ud Uq \u0015 = (sL+ rL) \u0001 \u0014 Id Iq \u0015 + !L \u0001 \u0014 \u0000Iq Id \u0015 + \u0014 Vd Vq \u0015 (4.12) 50 4.2. Synchronous Frame Model of the Three-Phase ISE Figure 4.2: Transfer function block diagram where Ud, Uq, Id, Iq, Vd and Vq are the Laplace transforms of the variable in Equation 4.11. The term (sL+ rL) is the inverse of the transfer function G(s) representing the ISE. The single-phase transfer function block diagram of the synchronous frame controlled ISE is shown in Figure 4.2. It shows that cross-coupling term between the d and q axis, !L and \u0000!L, act as a feedback loop between them. 4.2 Synchronous Frame Model of the Three-Phase ISE Modelling the three-phase ISE is approached in the same manner as in the synchronous frame modelling of the single-phase ISE. From the per-phase three-phase PWM circuit of Figure 4.3, let the area EPS voltages, fva,vb,vcg, and the three-phase currents, fia,ib,icg, be expressed as 51 4.2. Synchronous Frame Model of the Three-Phase ISE Figure 4.3: Per-phase equivalent circuit of a three-phase PWM inverter va = Va \u0001 sin (!t) vb = Vb \u0001 sin (!t\u0000 2\u0019 3 ) vc = Vc \u0001 sin (!t+ 2\u0019 3 ) (4.13) ia = I \u0003 a \u0001 sin (!t+ \u001E) ib = I \u0003 b \u0001 sin (!t\u0000 2\u0019 3 + \u001E) ic = I \u0003 c \u0001 sin (!t+ 2\u0019 3 + \u001E) (4.14) where fVa,Vb,Vcg and fI\u0003a ,I\u0003b ,I\u0003c g are the maximum area EPS voltage and reference current amplitudes, respectively. For the equivalent model of Fig- ure 4.3 and under balanced conditions, the circuit can be represented as a system of three equations as in24 uaub uc 35 = rL \u0001 24 iaib ic 35+ L \u0001 d dt 24 iaib ic 35+ 24 vavb vc 35 (4.15) A transformation of the three-phase system of Equation 4.15 into syn- chronous reference frame is possible using Park's transformation matrix Tdq0 52 4.2. Synchronous Frame Model of the Three-Phase ISE as in Tdq0 = 24 cos (!t) cos (!t+ 2\u00193 ) cos (!t\u0000 2\u00193 )sin (!t) sin (!t+ 2\u00193 ) sin (!t\u0000 2\u00193 ) 1 2 1 2 1 2 35 (4.16) where vdq0 could be obtained from24 vdvq v0 35 = 2 3 Tdq0 24 vavb vc 35 (4.17) The three-phase system of Equation 4.15 is transformed to synchronous reference frame using Tdq0 as follows Tdq0 24uaub uc 35=rL\u0001Tdq0 24iaib ic 35+L\u0001 0@dTdq0 dt 24iaib ic 35+Tdq0 d dt 24iaib ic 351A+Tdq0 24vavb vc 35 (4.18) And in the same manner as in Equation 4.10, udq0 is arrived at for the three-phase system and described as24uduq u0 35=rL \u0001 24idiq i0 35+!L\u0001 24\u0000iqid i0 35+L\u0001 d dt 24 idiq i0 35+ 24 vdvq v0 35 (4.19) In frequency domain, the Laplace transform of Equation 4.19 is found to be 24UdUq U0 35=(sL+ rL)\u0001 24IdIq I0 35+!L\u0001 24\u0000IqId I0 35+ 24 VdVq V0 35 (4.20) where Udq0, Idq0, and Vdq0 are the synchronous frame Laplace domain func- tions of the ISE voltages, ISE currents and area EPS voltages, respectively. The three-phase ISE transfer function in frequency domain is identical to Equation 3.14 and repeated here for convenience. G(s) = 1 rL + sL (4.21) It is worthy to note that by assuming a balanced three-phase system and neglecting the zero-sequence component of Equation 4.20, the system equation of the three-phase ISE is identical to that of the single-phase ISE in Equation 4.12. Hence the transfer function of the three-phase ISE is also represented in Figure 4.2. 53 4.3. Proposed Synchronous Frame Digital Current Control Figure 4.4: Proposed synchronous frame digital current control 4.3 Proposed Synchronous Frame Digital Current Control The proposed current control calculates a reference current command based on real and reactive power commands in synchronous frame. The input stage of the digital current controller of Figure 4.4 is the synchronous frame current commands. The second stage is a PI controller that will regulate the error between actual and command current signals. The decoupling stage outputs the ISE synchronous frame voltages Udq which are the input commands to the space vector PWM generator. The following sections will include detailed descriptions of the current reference calculation, synchronous frame current control and space vector PWM generation. 4.3.1 Current Reference Calculation The current command calculation in synchronous frame is expressed in terms of real and reactive power commands and inverter terminal voltages in syn- chronous frame according to\u0014 i\u0003d i\u0003q \u0015 = \u0014 vd \u0000vq vq vd \u0015 \u0014 P \u0003 Q\u0003 \u0015 (4.22) where fvd,vqg are the ISE terminal voltages in synchronous reference frame and are equal to the area EPS voltages before island creation. fP \u0003,Q\u0003g are the command power desired and for unity power factor operation Q\u0003 is set to zero [22]. 54 4.3. Proposed Synchronous Frame Digital Current Control Figure 4.5: Closed loop current current control in synchronous frame 4.3.2 Synchronous Frame Current Control The closed loop synchronous frame current control block is detailed in Fig- ure 4.5. The \u000Crst stage is to compare the ISE currents in synchronous reference frame to the calculated reference currents according to the com- manded currents fi\u0003d,i\u0003qg from Equation 4.22 and then pass the error through a PI controller as expressed in Gc(s) = Kp \u0012 1 + sTi sTi \u0013 (4.23) where Ki is de\u000Cned as Kp=Ti. The second stage is used to remove the e\u000Bect of the terminal voltages and the cross-coupling terms f-!LIq, !LIdg in a forward path to obtain the ISE space-vector voltage commands fU\u0003d ,U\u0003q g in synchronous reference frame. It can be shown that the closed-loop transfer function for both d and q of Figure 4.5 is decoupled and simpli\u000Ces to the block diagram of Figure 4.6. In order to realize the current control proposed, a discretized version of the closed-loop decoupled system is presented in Figure 4.7. The zero-order hold (ZOH) is used to represent the function of the pulse width modulation of the ISE. The transfer function of the ISE in discrete-time domain is 55 4.3. Proposed Synchronous Frame Digital Current Control Figure 4.6: Simpli\u000Ced reference frame current control transfer function Figure 4.7: Current control discrete-time block diagram represented as G(z) = (1\u0000 z\u00001) Z(G(s) s ) = 1 rL \u0012 1\u0000 p z \u0000 p \u0013 (4.24) where p is de\u000Cned in terms of the discrete time step Td as p = e\u0000rLTd=L (4.25) The PI controller transfer function Gc(s) is transformed into discrete- time domain and expressed as Gc(z) = Kp zpi \u0012 z \u0000 zpi z \u0000 1 \u0013 (4.26) 56 4.3. Proposed Synchronous Frame Digital Current Control where zpi is de\u000Cned as zpi = 1 1 + 1Ti (4.27) From Equation 4.24 and Equation 4.26 the open-loop transfer function in discrete-time domain is obtained as in Gc(z) \u0001G(z) = Kp zpi (1\u0000 p) rL \u0012 z \u0000 zpi z2 \u0000 (1 + p)z + p \u0013 (4.28) For design of the current control system, complex z-domain closed-loop poles will be chosen based on performance speci\u000Ccations such as settling time and percent overshoot, Ts and POS respectively. Let the complex closed-loop pole be de\u000Cned as z\u0003 = e(\u0000\u001B\u0006j!d)Td (4.29) where Td is the discrete time step and \u001B and the damped frequency !d are de\u000Cned as \u001B = \u0010 \u0001 !n !d = !n p 1\u0000 \u00102 !n = 4 \u0010 \u0001 Ts POS = 100e \u0000\u0019\u0010!n !d (4.30) For pole placement of the closed-loop system, Figure 4.8 shows the un- compensated open-loop poles fp,1g and zerofz0g in addition to the desired closed-loop pole fz\u0003g. Note that in order to satisfy angle condition, the closed-loop pole must satisfy the open-loop condition \fGc(z)G(z)g = \u0006\u0019(2k + 1) k = 0; 1; 2; : : : (4.31) From Figure 4.8, it can be shown that the PI controller zero could be found from zpi = 300 , and the output voltage signal, U3A, is zero. Once the temperature reaches the maximum allowed, U3A will switch to a high signal of 5 V. Implementing the hysteresis temperature loop, R12, the lower voltage limit can be calculated as VinMIN = VREF \u0000 R16 k R15 R16 k R15 +R12 \u0001 VH (B.3) Substituting the circuit parameters into the above equation to obtain VinMIN will yield a voltage of 2.35V. This means that Vout will only be zero when Vin is less than 2.35V rather than 2.5V. Figure B.11 shows the hysteresis temperature loop in which Vin is correlated to a resistance value from 300 to 338 . 127 Appendix B. Hardware Implementation 2 4 5 3 1 2 U3A LM339AM 1.5K R14 300 R15 5K R12 3K R13 D4 2.5v +5 +5 100nF C31 Vout R16 Vin VREF Figure B.10: Temperature sensor circuit [38] DSP Control A DSP control is used to control the ISE based on TI's TMS320LF2407A digital processor. The eZDSPLF2407A control board includes a JTAG con- nector for interface and debugging programs. The CPU speed is 40MHz, 64kB RAM, 32kB ROM or Flash EEPROM, 64kB program, 64kB of data and \u000Cnally 64kB of I/O space addressing. The board includes 16 multi- plexed analog input 10-bit ADC with built-in S/H circuit. The conversion rate is 375ns. It supports 4 trigger sources for start-of-conversion sequence and auto-sequencing functions. For motor control applications, irrelevant here, the board includes an event manager (EV) module for a broad range of features that are useful in motion control applications. The board has 40 multiplexed I/O general purpose pins. For system reset, a watchdog timer is included for monitoring of software or hardware operation and implement system reset. A CAN, controller area network, is included on the board and a serial communication interface (SCI). It is noted here that the EV manager has a variety of features that are worth including in the description of the board. A Two general purpose timers, three general-purpose up and up/down timers are available. Each of these timers are 16-bit compare unit capable of generating an independent PWM output. The EV manager also includes a PWM circuit that can 128 Appendix B. Hardware Implementation \u00E2\u0084\u0083 \u00E2\u0084\u0083 \u00E2\u0084\u0083 Figure B.11: Temperature hysteresis loop [38] produce an SVPWM signals, dead-band generation and output logic. A three capture units are available via the EV manager as well as a QEP, a quadrature encoder pulse. Power Supply A commercial switching power supply, VOF-65-15, are used to supply the PCB with required power. Also, two commercial DC-DC converters were used to supply the required DC power needed by the circuit. A 5V DC-DC converter, CC10-1205SF-E, supplies the eZDSP board, temperature sensor and protection circuits. A \u000615V DC power supply, CC10-1212DF-E, pro- vides power for the OpAmp circuits and another power supply, VOF-65-15, feeds the driver circuit. Input \u000Clters and output smoothing capacitors are incorporated in the power supply circuits as recommended by the data sheet and application notes. The power supply circuit is shown in Appendix C. 129 Appendix C Circuit and PCB 130 C .1. S ch em atics of C on trol B oard C.1 Schematics of Control Board 1 2 3 4 CN1 +15 +15 10uF C6 10uF C7 10uF C8 10uF C9 10uF C10 10uF C3 10uF C12 10uF C11 10uF C4 10uF C5 3.5uH L1 +Vin1 RC2 -Vout 4 Com 5 Trim 6 +Vout 7 -Vin3 CC1 CC10-1212DF-E 10uF C2 10uF C14 0.1uF C1 0.1uF C13 D1 16V D2 16V +15i -15i +15 10uF C20 10uF C21 10uF C22 10uF C23 10uF C24 10uF C17 10uF C26 10uF C25 10uF C18 10uF C19 3.5uH L2 +Vin1 RC2 NC 4 -Vout 5 Trim 6 +Vout 7 -Vin3 CC2 CC10-1205SF-E 10uF C16 0.1uF C15 D3 5V +5 Figure C.1: PowerSupply AD.SCHDOC [38] 131 C.1. Schematics of Control Board 5.1K R20 30K R17 12K R21 3.3K R19 100nF C33 100nF C34 150pF C32 -15i 1 2 3 CN7 -15i +15i +15i -15i VM1 30K R23 12K R26 3.3K R25 150pF C35 1 2 3 CN8 -15i +15i VM2 30K R28 12K R31 3.3K R30 100nF C37 100nF C38 150pF C36 1 2 3 CN9 -15i +15i +15i -15i VM3 2 3 1 4 11 1 U4A LM324AM 4 11 5 6 72 U4B LM324AM 4 11 8 10 9 3 U4C LM324AM 4 11 14 12 13 4 U4D LM324AM 2 3 1 4 11 1 U6A LM324AM 4 11 5 6 72 U6B LM324AM +15I +15I +15I -15I -15I -15I -15I +15I 30K R18 Res1 30K R24 30K R29 240 R16 Res1 240 R22 Res1 240 R27 Res1 1 2 N C 3 U5 LM4040A30IDBZR-3.0 4 11 8 10 9 3 U3C LM324AM 4 11 14 12 13 4 U3D LM324AM 4 11 8 10 9 3 U6C LM324AM +15i -15i +15i -15i +15i -15i Figure C.2: VoltageSensor.SCHDOC [38] 132 C.1. Schematics of Control Board 5.1K R5 30K R2 12K R6 3.48K R4 100nF C28 100nF C29 150pF C27 -15i 1 2 3 CN2 -15i +15i +15i -15i CM1 30K R8 12K R11 3.48K R10 150pF C30 1 2 3 CN3 -15i +15i CM2 2 3 1 4 1 1 1 U1A LM324AM 4 1 1 5 6 72 U1B LM324AM 4 1 1 8 10 9 3 U1C LM324AM 4 1 1 14 12 13 4 U1D LM324AM -15I -15I -15I +15I +15I +15I 1 2 N C 3 U2 LM4040A30IDBZR-3.0 62 R1 Res1 62 R7 Res1 32K R9 Res1 32K R3 Res1 2 3 1 4 1 1 1 U3A LM324AM 4 1 1 5 6 72 U3B LM324AM +15i -15i +15i -15i Figure C.3: CurrentSensor.SCHDOC [38] 133 C.1. Schematics of Control Board 2 4 5 3 1 2 U3A LM339AM 1.5K R14 300 R15 5K R12 3K R13 D4 2.5v +5 +5 +15 +5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 JP1 CM1 CM2 VM1 VM2 VM3 1 2 3 4 CN6 Header 4 +5 1 2 CN5 100nF C31 FRQCN FRQCN SW SW TMP TMP TMP9 TMP9 1 2 3 4 CN4 Figure C.4: TMPSensor.SCHDOC [38] 134 C .2. S ch em atics of P ow er B oard C.2 Schematics of Power Board GND1 U_SO22 U_Mod3 U_RC24 U_InB5 U_InA6 U_RC17 U_VL8 U_SO19 GND10 GND11 VDC12 VDC13 V_SO214 V_Mod15 V_RC216 V_InB17 V_InA18 V_RC119 V_VL20 V_SO121 GND22 GND23 VDD24 VDD25 W_SO226 W_Mod27 W_RC228 W_InB29 W_InA30 W_RC131 W_VL32 W_SO133 GND34 W_G1 35 W_E1 36 W_Rth1 37 W_C1 38 Free 39 Free 40 W_G2 41 W_E2 42 W_Rth2 43 W_C2 44 Free 45 Free 46 V_G1 47 V_E1 48 V_Rth1 49 V_C1 50 Free 51 Free 52 V_G2 53 V_E2 54 V_Rth2 55 V_C2 56 Free 57 Free 58 U_G1 59 U_E1 60 U_Rth1 61 U_C1 62 Free 63 Free 64 U_G2 65 U_E2 66 U_Rth2 67 U_C2 68 Concept1 6SD106E R2 4.7K R3 22K 22K R4 4.7KR5 4.7KR1 22K R6 22KR7 4.7KR8 4.7K R9 22K R10 22K R11 4.7K R12 39KR13 180 R14 39K R15 180R16 39K R17 180 R18 39K R19 180 R20 39K R21 180 R22 39K R23 180 R24 150pF C3 150pF C4 150pF C5 150pF C6 150pFC7 150pFC8 D24V7 D3 4V7 D4 4V7 D5 D6 D7 D8 D9 D10 +15 +15 +15 +5 +15 +15 +15 +5 +15 +15 +15 +5 12 34 56 78 910 1112 1314 1516 1718 1920 2122 2324 2526 2728 2930 3132 3334 3536 3738 3940 JP1 UC1 UC2 UG1 UG2 UE1 UE2 VC1 VC2 VG1 VG2 VE1 VE2 WC1 WC2 WG1 WG2 WE1 WE2 +5 +15 10uF C1 0.1uF C2 D1 16V 1 2 3 4 P1 Header 4 +5 1 2 P2 Header 2 TMP9 TMP TMP 14 7 1 2 4 5 6 U1A SN74ALS21AD D22 15V D21 15V D20 15V D19 15V D18 15V D17 15V D15 15V D14 15V D13 15V D12 15V D11 15V D16 15V 6 1 U2A SN74LVC2GU04 Figure C.5: Driver.SCHDOC [38]135 C.2. Schematics of Power Board 11 22 33 4 4 5 5 6 6 7 7 8 8 9 9 1010 1111 1212 1313 1414 1515 1616 1717 1818 1919 2020 2121 2222 2323 2424 Inv1 MUBW20-06A7 TMP9 1 2 3 JP2 1 2 3 JP3 UC1 UC2 UG1 UG2 UE1 UE2 VC1 VC2 VG1 VG2 VE1 VE2 WC1 WC2 WG1 WG2 WE1 WE2 2700uF C9 * 1.5uF C10 * 1.5uF C11 * +5 5 R25 Thermistor Figure C.6: MUBW20.SCHDOC [38] 136 C.3. PCB Layouts C.3 PCB Layouts Figure C.7: Control board PCB [38] 137 C.3. PCB Layouts Figure C.8: Control board PCB top layer [38] 138 C.3. PCB Layouts Figure C.9: Control board PCB bottom layer [38] 139 C.3. PCB Layouts Figure C.10: Power board PCB [38] 140 C.3. PCB Layouts Figure C.11: Power board PCB top layer [38] 141 C.3. PCB Layouts Figure C.12: Power board PCB bottom layer [38] 142 Appendix D Schematics for 3-Phase Islanding Test 143 A p p en d ix D . S ch em atics for 3-P h ase Islan d in g T est Figure D.1: Schematics for 3-phase islanding test [38] 144 Appendix E Unintentional islanding test conditions Unintentional\u00C2\u00A0Islanding\u00C2\u00A0Test Test\u00C2\u00A0conditions: 1. Single Phase120V /60HZ /1kW 2. PF=[1,0.37, 0.707 ] \u00E2\u0087\u0094 Q f=[0,2.5, 1 ] Values\u00C2\u00A0Table: Criteria Value Unit Notes Pload 1000 W Qload 0 VAR Matched\u00C2\u00A0LC VEPS 120 V RMS fEPS 60 Hz VIUT 120 V Inverter\u00C2\u00A0Under\u00C2\u00A0Test PIUT 1000 W IIUT 8.33 A RMS PFIUT 0.95 \u00EF\u0081\u00B1=18.195o Qf 1 RLC\u00C2\u00A0below\u00C2\u00A0designed\u00C2\u00A0for\u00C2\u00A0this\u00C2\u00A0Qf Rload 14.4 OHM V2/P LLoad 38.197 mH R / \u00EE\u0082\u009E2\u00EE\u0083\u0086 f oQ f \u00EE\u0082\u009F ,\u00C2\u00A0iL(0)=11.785A CLoad 184.207 \u00EF\u0081\u00ADF Q f / \u00EE\u0082\u009E2\u00EE\u0083\u0086 f o R\u00EE\u0082\u009F Qf 2.5 RLC\u00C2\u00A0below\u00C2\u00A0designed\u00C2\u00A0for\u00C2\u00A0this\u00C2\u00A0Qf Rload 14.4 OHM V2/P LLoad 15.28 mH R / \u00EE\u0082\u009E2\u00EE\u0083\u0086 f oQ f \u00EE\u0082\u009F ,\u00C2\u00A0iL(0)=11.785A CLoad 460.52 \u00EF\u0081\u00ADF Q f / \u00EE\u0082\u009E2\u00EE\u0083\u0086 f o R\u00EE\u0082\u009F Q f=R\u00EE\u0082\u008DCL for\u00C2\u00A0a\u00C2\u00A0parallel\u00C2\u00A0RLC\u00C2\u00A0load,\u00C2\u00A0and QF=\u00EE\u0082\u008D 1PF 2\u00E2\u0088\u00921 . P IUT=PLoad\u00EE\u0082\u0083PEPS & QIUT=QLoad\u00EE\u0082\u0083QEPS 145"@en .
"Thesis/Dissertation"@en .
"2013-05"@en .
"10.14288/1.0073604"@en .
"eng"@en .
"Electrical and Computer Engineering"@en .
"Vancouver : University of British Columbia Library"@en .
"University of British Columbia"@en .
"Attribution-NonCommercial 3.0 Unported"@en .
"http://creativecommons.org/licenses/by-nc/3.0/"@en .
"Graduate"@en .
"An active method for implementing the unintentional islanding test in distributed generation systems"@en .
"Text"@en .
"http://hdl.handle.net/2429/44001"@en .