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UBC Theses and Dissertations

12nm Finfet aging characterization through wear-out sensor design Rendon, Mateo Jose

Abstract

Reliability in electronics is becoming increasingly crucial as semiconductor markets diversify, economic and policy trends point to sustainability, and transistors scale into more aging-sensitive devices. This thesis studies the wear-out mechanisms at the center of device aging and failure in advanced technology nodes by creating a testing platform for characterization across several circuit design variables. We start with the physical explanations and device effects of bias temperature instability (BTI), hot-carrier injection (HCI), electromigration (EM), and time dependent dielectric breakdown (TDDB). Then, a survey on state-of-the-art wear-out mitigation techniques reveals that developing aging mechanisms sensors aids academia and industry alike by serving as tools for model characterization and monitors for dynamic on-silicon aging relief. Therefore, the core of this thesis presents four wear-out sensor designs by recollecting learnings from similar literature approaches, detailing their circuit topologies, and discussing the specifics of their implementation in a 12nmLP FinFET technology. The experimental methodology includes the tapeout of a test platform chip featuring over 150 sensor variants to verify the topologies. Additionally, we introduce a firmware-based dual PCB solution capable of automatically measuring the sensor outputs while replicating accelerated aging testing industry standards. After presenting initial measurements, we perform a 1000-hour 125°C stress test to estimate the test platform’s 10-year aging. The first 600-hour experimental results verify the developed sensors and provide insights on how transistor type, size, threshold voltage, and power supply impact BTI, HCI, EM, and soft and hard-breakdown TDDB in the 12nm FinFET technology.

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Attribution-NonCommercial-NoDerivatives 4.0 International