- Library Home /
- Search Collections /
- Open Collections /
- Browse Collections /
- UBC Theses and Dissertations /
- Design of a high-efficiency load-insensitive Class-E...
Open Collections
UBC Theses and Dissertations
UBC Theses and Dissertations
Design of a high-efficiency load-insensitive Class-E CMOS power amplifier for wireless power transfer applications Rennick, Elaine
Abstract
Radio-frequency (RF) switching power amplifiers (PAs) are an advantageous option for implementation of the inverter in near-field wireless power transmission (WPT) systems due to their ability to operate at high efficiencies. Integrated RF switching PAs are highly useful for compact applications of WPT such as biomedical implants and Internet of Things (IoT) sensors. WPT systems are subject to many system-level variables that affect the load impedance of the PA. The performance of RF switching PAs is sensitive to load impedance variations. In this thesis, a load-insensitive Class-E PA is presented. The circuit is duty-cycle programmable and can maintain soft-switching conditions necessary for high-efficiency operation across a wide range of resistive and inductive loading effects. The design trade-offs are discussed in detail in terms of size, efficiency, device reliability, programmability, sensitivity to variations in load impedance, and output power. Multiple power combinations of the load-insensitive Class-E power amplifier are designed and fabricated in a 0.13-μm CMOS technology. The PAs operate at 13.56 MHz, within the Industrial, Scientific, and Medical (ISM) band for WPT. The output power, efficiency, and load-sensitivity of these power combined PAs are simulated. The simulation results show that high efficiency operation can be maintained across resistive and inductive variations in load impedance for a single PA and for a parallel combination of two sub-PAs. The fabricated integrated circuit (IC) has been measured at nominal load conditions and exhibits unexpected voltage waveforms, likely due to an unwanted DC offset on-chip, resulting in lower output power and efficiency than expected. Future work is needed to debug the fabricated chip, resubmit the finalized design for fabrication and evaluate the load-insensitivity of the designs.
Item Metadata
Title |
Design of a high-efficiency load-insensitive Class-E CMOS power amplifier for wireless power transfer applications
|
Creator | |
Supervisor | |
Publisher |
University of British Columbia
|
Date Issued |
2024
|
Description |
Radio-frequency (RF) switching power amplifiers (PAs) are an advantageous option for implementation of the inverter in near-field wireless power transmission (WPT) systems due to their ability to operate at high efficiencies. Integrated RF switching PAs are highly useful for compact applications of WPT such as biomedical implants and Internet of Things (IoT) sensors.
WPT systems are subject to many system-level variables that affect the load impedance of the PA. The performance of RF switching PAs is sensitive to load impedance variations. In this thesis, a load-insensitive Class-E PA is presented. The circuit is duty-cycle programmable and can maintain soft-switching conditions necessary for high-efficiency operation across a wide range of resistive and inductive loading effects. The design trade-offs are discussed in detail in terms of size, efficiency, device reliability, programmability, sensitivity to variations in load impedance, and output power.
Multiple power combinations of the load-insensitive Class-E power amplifier are designed and fabricated in a 0.13-μm CMOS technology. The PAs operate at 13.56 MHz, within the Industrial, Scientific, and Medical (ISM) band for WPT. The output power, efficiency, and load-sensitivity of these power combined PAs are simulated. The simulation results show that high efficiency operation can be maintained across resistive and inductive variations in load impedance for a single PA and for a parallel combination of two sub-PAs. The fabricated integrated circuit (IC) has been measured at nominal load conditions and exhibits unexpected voltage waveforms, likely due to an unwanted DC offset on-chip, resulting in lower output power and efficiency than expected. Future work is needed to debug the fabricated chip, resubmit the finalized design for fabrication and evaluate the load-insensitivity of the designs.
|
Genre | |
Type | |
Language |
eng
|
Date Available |
2024-05-09
|
Provider |
Vancouver : University of British Columbia Library
|
Rights |
Attribution-NonCommercial-NoDerivatives 4.0 International
|
DOI |
10.14288/1.0442421
|
URI | |
Degree | |
Program | |
Affiliation | |
Degree Grantor |
University of British Columbia
|
Graduation Date |
2024-11
|
Campus | |
Scholarly Level |
Graduate
|
Rights URI | |
Aggregated Source Repository |
DSpace
|
Item Media
Item Citations and Data
Rights
Attribution-NonCommercial-NoDerivatives 4.0 International