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UBC Theses and Dissertations

Efficient layout-aware statistical analysis for photonic integrated circuits Jhoja, Jaspreet Singh

Abstract

Fabrication variability significantly impacts the performance of photonic integrated circuits (PICS), which makes it crucial to quantify the impact of fabrication variations at the design and simulation stage. The variability analysis enables circuit and system designers to optimize their designs to be more robust and obtain maximum yield when designing for manufacturing. The variability analysis requires a total of six parameters to model spatially correlated manufacturing variations in photonic circuits: mean, standard deviation, and correlation length for both width and thickness variations of photonic components. The correlation lengths are spatial parameters that describe how the width and thickness variations are distributed along a chip’s or a wafer’s surface. The methods that allow for the non-invasive characterization of variations are limited to extracting mean and standard deviations of width and thickness variations. In this thesis, we present a method to extract the physical correlation lengths, which are crucial to model manufacturing variations. In this thesis, we also present the Reduced Spatial Correlation Matrix based Monte Carlo (RSCM-MC), a methodology to study the impact of spatially correlated manufacturing variations on the performance of photonic circuits. The presented methodology is compared with another layout-dependent Monte Carlo (MC) simulation methodology, called Virtual Wafer-based Monte Carlo (VW-MC). First, we describe the process of generating spatially correlated physical variations using the presented methodology and use the generated correlated physical variations to conduct MC simulations. We then use a Mach-Zehnder lattice filter photonic circuit as a benchmark circuit to study the accuracy of the proposed method. We compare the statistical parameters of quantities defining the flatness of the transmission spectra of the filter. We then compare the computation performance of RSCM-MC with VW-MC using a combination of a small-sized circuit (two-stage Mach-Zehnder filter) and a large circuit (a 16x16 ring matrix) with thousands of components. For the best case, i.e. the small-sized circuit, we observe a decrease in computational times by 98.9% and a reduction in memory requirement by 72%. For the worst case, i.e. the 16x16 ring matrix, we observe a decrease in computational times by 99.8% and a reduction in memory requirement by 87%.

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Attribution 4.0 International