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Rapid instrumentation for debug and verification of circuits on FPGAs

University of British Columbia

Field-Programmable Gate Array (FPGA) technology is rapidly gaining traction in a wide range of applications. Nonetheless, FPGA debug productivity is a key challenge. For FPGAs to become mainstream, a debug ecosystem which provides the ability to rapidly debug and understand designs implemented on FPGAs is essential. Although simulation is valuable, many of the most elusive and troublesome bugs can only be found by running the design on an actual FPGA. However, debugging at the hardware level is challenging due to limited visibility. To gain observability, on-chip instrumentation is required. In this thesis, we propose methods which can be used to support rapid and efficient implementation of on-chip instruments such as triggers and coverage monitoring. We seek techniques that avoid large area overhead, and slow recompilation of the user circuit between debug iterations. First, we explore the feasibility of implementation of debug instrumentation into FPGA circuits by applying incremental compilation techniques to reduce the time required to insert trigger circuitry. We show that incremental implementation of triggers is constrained by the mapping of the user circuits. Second, we propose a rapid triggering solution through the use of a virtual overlay fabric and mapping algorithms that enables fast debug iterations. The overlay is built from leftover resources not used by the user circuit, reducing the area overhead. At debug time, the overlay fabric can quickly be configured to implement desired trigger functionalities. Experimental results show that the proposed approach can speed up debug iteration runtimes by an order of magnitude compared to circuit recompilation. Third, to support rapid and efficient implementation of complex triggering capabilities, we design and evaluate an overlay fabric and mapping tools specialized for trigger-type circuits. Experimental evaluation shows that the specialized overlay can be reconfigured to implement complex triggering scenarios in less than 40 seconds, enabling rapid FPGA debug. The final contribution is a scalable coverage instrumentation framework based on overlays that enables runtime coverage monitoring during post-silicon validation. Our experiments show that using this framework to gather branch coverage data is up to 23X faster compared to compile-time instrumentation with a negligible impact on the user circuit.

Text

2018-08-02

Attribution-NonCommercial-NoDerivatives 4.0 International

http://hdl.handle.net/2429/66654

Electrical and Computer Engineering

University of British Columbia

UBCV

http://creativecommons.org/licenses/by-nc-nd/4.0/