UBC Undergraduate Research

A 400MHz Direct Digital Synthesizer with the AD9912 : Part I : design and fabrication of the device Da Costa, Daniel; Mulholland, Brendan 2012

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A 400MHz Direct Digital Synthesizer with the AD9912 Daniel Da Costa Brendan Mulholland Project Sponser: Dr. Kirk W. Madison Project 1160 Engineering Physics 479 The University of British Columbia January 9, 2012Part I Design and Fabrication of the Device iExecutive Summary Part I of this report discusses the design and and fabrication stage of this project. At time of writing, testing is on hold while a complete prototype device has been assembled. Part II will follow and will include documentation the testing procedures, the results and all recommendations. This project aimed to design, build and test a complete and functional Direct Digital Synthesizer (DDS) device with output frequencies of up to 400MHz. A DDS is a device capable of digitally generating sinusoidal waves with programmable frequency and phase. The Analog Devices 9912 (AD9912) was chosen as a suitable DDS Integrated Circuit (IC) and this was used in the project design. An enclosure also had to be built to house the DDS device. The device had to be compatible with an existing parallel control interface used in the lab, requiring a parallel-to-serial converter, as the AD9912 requires a serial interface. This parallel-to- serial converter was designed and prototyped on a breadboard to verify correct operation. It was also necessary for the device to minimize noise. This was accomplished with a passive analog  lter circuit that was simulated in SPICE and con rmed to meet design speci cations. Complete designs and fabrication  les for the circuit and enclosure had to be provided. The schematics for the board were completed and a PCB layout was designed from this schematic. The PCB layout generated all  les required for manufacturing. The enclosure was modi ed from an existing design to better accommodate the PCB layout and to improve heat dissipation. Twenty PCBs had to be manufactured and parts had to be ordered for 15 boards. These have all arrived and a prototype device is currently being assembled. Enclosures for 15 boards also had to be ordered and these are all currently being manufactured. iiContents Executive Summary ii Contents iv List of Figures vi List of Tables vii Glossary viii Acronyms ix Acknowledgements x 1 Introduction 1 2 Discussion 4 2.1 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.1 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.2 The AD9912 Direct Digital Synthesizer . . . . . . . . . . . . . . . . . . . . . 4 2.1.2.1 DAC Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . 6 2.1.3 RF Output and the Reconstruction Filter . . . . . . . . . . . . . . . . . . . . 6 2.1.3.1 SPICE Veri cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.4 Clock Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.5 Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.5.1 SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.5.2 SYSCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.5.3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.6 Digital Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.6.1 The UTBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.6.2 The AD9912’s Serial Control Port . . . . . . . . . . . . . . . . . . . 11 2.1.6.3 Parallel-to-Serial Converter . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.6.4 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.7 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.1 Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.2 Power Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.3 Heat Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.4 Characteristic Impedance and Trace Width . . . . . . . . . . . . . . . . . . . 15 2.3 Design and Fabrication Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.1 Schematic Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.2 PCB Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.3 PCB Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 iiiCONTENTS iv 2.3.4 Enclosures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4 Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.1 Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.2 DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.3 Con guration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.3.1 SYSCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.3.2 SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.3.3 SCLK Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.3.4 CMOS Clock Driver Voltage . . . . . . . . . . . . . . . . . . . . . . 25 2.4.3.5 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.3.6 RF Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.5 Breadboard Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3 Conclusions 29 4 Project Deliverables 30 4.1 List of Deliverables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2 Financial Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 References 32 A Schematic Diagrams 33 B PCB Fabrication Drawings 43 C 3D PCB Renderings 48 D PCB Parts List 51List of Figures 1.1 Photo of the 150MHz AD9852-based DDS . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Block diagram of the full DDS device, showing input and outputs. . . . . . . . . . . 5 2.2 Block diagram showing internal functionality of the AD9912. . . . . . . . . . . . . . 6 2.3 Reconstruction  lter schematic used for SPICE simulation. . . . . . . . . . . . . . . 7 2.4 Reconstruction  lter transfer function generated from SPICE simulation. . . . . . . 8 2.5 Diagram of the 50-Pin UTBus Connector . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 Timing diagram for the UTBus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7 The PCB power plane design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.8 Diagram of microstrip trace geometry. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.9 Diagram of stripline trace geometry. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.10 PCB layout, top side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.11 PCB layout, bottom side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.12 Device Assembly diagram, top side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.13 Device Assembly diagram, bottom side. . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.14 Photo of the PCB, top side. Some components have been installed. . . . . . . . . . . 20 2.15 Photo of the PCB, bottom side, no components. . . . . . . . . . . . . . . . . . . . . 21 2.16 Labelled diagram of the enclosure body. . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.17 Diagram of the enclosure lid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.18 3D rendering of the enclosure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.19 Parallel-to-serial converter breadboard test results. . . . . . . . . . . . . . . . . . . . 28 A.1 Schematic diagram, top level. Top Level.SchDoc . . . . . . . . . . . . . . . . . . . . 33 A.2 Schematic diagram, clocks. CLK.SchDoc . . . . . . . . . . . . . . . . . . . . . . . . . 34 A.3 Schematic diagram, digital. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 A.4 Schematic diagram,  ip- ops and board select comparator. . . . . . . . . . . . . . . 36 A.5 Schematic diagram, parallel-to-serial converter. . . . . . . . . . . . . . . . . . . . . . 37 A.6 Schematic diagram, AD9912. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 A.7 Schematic diagram, power 1 (voltage regulators). . . . . . . . . . . . . . . . . . . . . 39 A.8 Schematic diagram, power 2 (bypass capacitors and ferrite beads). . . . . . . . . . . 40 A.9 Schematic diagram, analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 A.10 Schematic diagram, reconstruction  lter. . . . . . . . . . . . . . . . . . . . . . . . . . 42 B.1 Fabrication Drawings, top copper layer. . . . . . . . . . . . . . . . . . . . . . . . . . 43 B.2 Fabrication Drawings, ground plane (negative). . . . . . . . . . . . . . . . . . . . . . 44 B.3 Fabrication Drawings, power plane (negative). . . . . . . . . . . . . . . . . . . . . . . 44 B.4 Fabrication Drawings, bottom copper layer. . . . . . . . . . . . . . . . . . . . . . . . 45 B.5 Fabrication Drawings, top silkscreen. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 B.6 Fabrication Drawings, bottom silkscreen. . . . . . . . . . . . . . . . . . . . . . . . . . 46 B.7 Fabrication Drawings, top soldermask. . . . . . . . . . . . . . . . . . . . . . . . . . . 46 B.8 Fabrication Drawings, bottom soldermask. . . . . . . . . . . . . . . . . . . . . . . . . 47 B.9 Fabrication Drawings, drill drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 vLIST OF FIGURES vi C.1 3D Rendering of the DDS, top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 C.2 3D Rendering of the DDS, bottom view. . . . . . . . . . . . . . . . . . . . . . . . . . 49 C.3 3D Rendering of the DDS, angled view. . . . . . . . . . . . . . . . . . . . . . . . . . 50List of Tables 2.1 Serial control port instruction word bit functionality. . . . . . . . . . . . . . . . . . . 11 2.2 AD9912 byte transfer count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 Sample DDS Device Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 List of connection pads available on the Printed Circuit Board (PCB) designed for BNC Connector mounting. Note that only J3, J5 and J6 are intended for mass production, and the enclosure design re ects this. . . . . . . . . . . . . . . . . . . . . 24 2.5 Options for Power-Up Default Frequencies on the AD9912 . . . . . . . . . . . . . . . 25 2.6 Recommended Loop Filter Values for a Nominal 1.5 MHz SYSCLK PLL Loop Band- width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.7 Device Con guration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1 Financial Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2 DDS Enclosure Costs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 D.1 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 viiGlossary AD9852 is a DDS IC produced by Analog Devices, with a maximum system clock of 300MHz. AD9912 is Analog Devices’ highest-performance DDS IC, with a maximum system clock of 1GHz. DDS is a device capable of digitally generating sinusoidal waves with programmable frequency and phase. ferrite bead is a passive component which is primarily resistive at high frequencies. Therefore, they act to block high-frequency noise and are useful as an inexpensive means of isolating noisy power supply groups. FSC is a digitally programmable 10-bit scale factor that sets the peak output current of the AD9912 Digital-to-Analog Converter (DAC)[3]. prepreg is a shorthand term for pre-impregnated material. In this report, it is a name for the dielectric material placed between copper layers on a PCB. via is a connection between one or more copper layers on a PCB. viiiAcronyms CSB Chip Select Bit. DAC Digital-to-Analog Converter. DAQ Data Acquisition System. DIP Dual In-line Package. EMI Electromagnetic Interference. FTW Frequency Tuning Word. IC Integrated Circuit. LDO Low-Dropout. NI National Instruments. PCB Printed Circuit Board. PHAS Department of Physics and Astronomy. PLL Phase-Locked Loop. QDG Quantum Degenerate Gasses. SMD Surface-Mount Devices. UTBus University of Texas Bus. VCO Voltage-Controlled Oscillator. ixAcknowledgements We’d like to thank Kirk Madison and Jon Nakane for taking their time to review our in-progress designs. Extra thanks to Kirk having enough con dence in us amateur PCB designers to fund the project. Thanks to Will Gunton for being our reliable contact at the QDG lab and for administrating the purchasing for the project. Thanks to Pavel Trochtchanovitch, Richard, Gar and Dave at the PHAS electronics shop for assembling our boards and having patience when our instructions didn’t make sense. Extra thanks to Richard for spending time on several occasions to review out PCB layout. x1 Introduction The Quantum Degenerate Gasses (QDG) Laboratory at the University of British Columbia inves- tigates the applications of ultra-cold gases to the physics of many-body quantum systems [8]. One such investigation attempts to trap, isolate and precisely control the movement of ultra-cold atoms. Naturally, this experiment requires precise control of experimental conditions. To achieve this, they employ a complex computer-controlled electronic system. Contained within this control system are several devices called Direct Digital Synthesizer (DDS)s. The current generation of these devices are designed by Todd Meyrath and are capable of producing radio frequency signals between DC and 135MHz [9]. Todd Meyrath’s device is shown in Figure 1.1. The DDSs are based around the Analog Devices 9852 (AD9852), a highly integrated 300MBPS CMOS digital synthesizer. This IC provides a highly stable frequency-, phase-, and amplitude-programmable cosine output[2]. Other key features of the AD9852 are the ability to internally multiply an external clock up to a maximum of 300MHz (20  15MHz) and an output update of speed up to 108Hz. The AD9852 supports Phase-Shift Keying (PSK) and Frequency-Shift Keying (FSK), which allow switching be- tween two pre-programmed phases or frequencies based upon the level of a digital signal. Further, a high-speed integrated analog comparator allows the AD9852 to be used as a programmable clock source. The QDG lab requires eight devices capable of analog sinusoidal outputs with programmable frequencies of up to 400MHz. These devices will be used to control acousto-optic modulators, which can be used to precisely control the frequency of the laser beams. The QDG lab uses these lasers to control ultra-cold atoms in experiments that are beyond the scope of this document. To  t the lab requirements, this project aims to redesign, implement and test a new DDS device, the AD9912, which replaces the AD9852 microchip with a similar chip, the AD9912. This IC is a newer and faster edition of the AD9852 - a 1GBPS digital synthesizer capable of producing radio frequency signals at frequencies of up to 400MHz and an output update speed of up to 2MHz. To simplify usage in the lab, the AD9912-based DDS device must support the existing AD9852 DDS device control interface. As the AD9912 is a faster IC than the AD9852, it has several requirements that make a designing an AD9912-based DDS device more challenging. For example, the higher speed signals involved require much more careful impedance control of the signal lines than the AD9852 DDS devices. There are feature di erences as well: the AD9912 does not support PSK or FSK, though the AD9852 does, and supports serial programming in place of a parallel control bus. The AD9912 also requires voltage supplies at 1.8V on top of the 3.3V the AD9852 required. Like the AD9852, the AD9912’s output must be  ltered to remove noise resulting from the digital synthesis process; this  lter must be designed and characterized. Due to these di erences, the design for DDS device built for this project did not begin with the AD9852 DDS device. Instead, the design began with the AD9912 evaluation board. This is evident in the analog portion of the AD9912 DDS device, which uses similar structure and components choice as the evaluation board. However, the AD9912 DDS device did draw inspirations from the AD9852 device[9]. In particular, the digital control and power circuitry design is heavily based upon 11. INTRODUCTION 2 the AD9852 device and the overall PCB layout is very similar. To house the DDS device, an enclosure must be designed. This should securely fasten the AD9912 DDS device, provide noise isolation and be compatible with the rack mount solution used for the AD9852. Both the enclosures and the front panel mounting mechanism should be ordered. This project is sponsored by Dr. Kirk Madison, Assistant Professor with the department of Physics and Astronomy at The University of British Columbia and head of the QDG Laboratory. This report is organized into several chapters: Discussion, Conclusions and Project Deliverables. A chapter on recommendations will be included with Part II of this report. The Discussion is broken into Theory of Operation, PCB Layout Considerations, Design and Fabrication Methods, Board Features and Breadboard Testing. The Discussion aims to provide a quantitative description of the expected operation of the device and give insight into the methodology of the design process. The Conclusions provide closure to the report, summarise the important results and  ndings. The Project Deliverables describe the physical and electronic results of this project which are to be handed over to the QDG Laboratory. Finally, the Appendices present the design schematics, fabrication drawings, 3D renderings of the PCB and a full parts list.1. INTRODUCTION 3 Figure 1.1: Photo of the 150MHz AD9852-based DDS designed by Todd Meyrath[9].2 Discussion 2.1 Theory of Operation This section will begin by giving an overview of the functionality of the device. Next, the internal workings of the AD9912 IC itself will be discussed, providing an understanding what to expect from the IC’s RF and clock outputs. Afterwards the supporting circuitry will be described block by block, returning as needed to the AD9912 IC to explain related concepts. 2.1.1 Device Overview The device is designed to generate a sinusoidal or square output signal with a frequency of up to 400MHz. The frequency and phase of both output signals can be rapidly digitally programmed (but not independently). The output signal is generated by the AD9912, a high-performance, low-noise 14-bit DDS[3]. The sinusoidal output is  ltered through a 400MHz low-pass  lter to remove unwanted high- frequency noise. Depending on board con guration, the  ltered RF signal can then be taken as the primary device output or it can be brought back to the AD9912 to become the input signal for either of the AD9912’s two clock drivers - the CMOS output driver and the HSTL output driver (see Section 2.1.4). Figure 2.1 is a high-level block diagram of the newly designed AD9912-based DDS device. The block diagram shows all existing BNC connection pads. Only three of these are intended for use in the  nished devices. These are SYSCLK, the system clock input, RF, the sinusoidal signal output and CMOS, the CMOS clock driver output. The remaining connections are intended primarily for testing. Signi cant omissions from the block diagram are the Phase-Locked Loop (PLL) loop  lter (see Section 2.1.5.3) and the voltage regulation circuitry (see Section 2.2.2). 2.1.2 The AD9912 Direct Digital Synthesizer Figure 2.2 is a block diagram showing the core internal functionality of the AD9912, reproduced from the datasheet[3]. This diagram consists of three main blocks: the 48-bit accumulator, angle to amplitude conversion and the DAC. fs is the DAC sample rate[3]. Each cycle of fs, the accumulator increments its running total by the 48-bit value of the Frequency Tuning Word (FTW)[3]. The accumulator will periodically reach its maximum value (248) and roll over. The rate of roll over is equal to the frequency of the sinusoidal output, fDDS , and is given by fDDS = FTW 248 fs[3]: (2.1) Equation 2.1 can be solved to give FTW = round(248( fDDS fs ))[3]: (2.2) 42. DISCUSSION 5 AD9912 RF Reconstruction Filter (400 MHz Low-Pass) DAC_OUT FDBK_IN OUT_P OUT_N CMOS SYSCLK OUT/OUTB OUT_CMOS FDBK_IN/ FDBK_INB DAC_OUT/ DAC_OUTB SYSCLK/ SYSCLKB SDIO SCLK Clock Oscillator (~25MHz) Board Address Comparator Parallel-to- Serial Converter Parallel Data  Input Address Data Strobe 10-Pos DIP Switch Startup Config Board Address 46 616 SZ CSB SCLK Figure 2.1: Block diagram of the full DDS device, showing input and outputs. Switches are imple- mented as 0 resistors. The crystal oscillator shown is optional and replaces the external SYSCLK input. The output of the accumulator is o set by the 14-bit value Phase O set. This results in a phase o set to fDDS of   given by   = 2 (  phase 214 )[3]: (2.3) Both the FTW and the Phase O set can be digitally controlled by the user (see Section 2.1.6), allowing the frequency and phase of the output sinusoid to be controlled with 48 and 14 bits of precision, respectively. This corresponds to increments of approximately 3:6 Hz (at fs = 1GHz) and 3:8 10 4rads. After the phase o set, the accumulator output (which is a digital representation of the phase of the output sinusoid) is converted to a 14-bit digital value representing the amplitude of the output sinusoid. The DAC then converts this value to an analog di erential signal pair (DAC OUT/ DAC OUTB). The frequency, phase and peak output current (see Section 2.1.2.1) of this signal are digitally controllable. It will be transformed into a single-ended signal and low-pass  ltered (see Section 2.1.3) before becoming the output RF signal of the DDS device.2. DISCUSSION 6 2.1.2.1 DAC Peak Output Current The peak output current of the DAC is determined by two factors: a reference current on the DAC RSET pin (IDAC RESET ) and a digitally programmable 10-bit scale factor referred to as the FSC[3]. The DAC RSET pin is internally connected to a reference voltage of 1.2V and externally connected to ground through the resistor RDAC REF (R26 on the PCB), and therefore IDAC REF = 1:2V RDAC REF [3]: (2.4) The AD9912 datasheet recommends IDAC REF = 120 A which implies taking RDAC REF = 10k . The DAC full-scale output current (IDAC FS) is given by IDAC FS = IDAC REF (72 + 192FSC 1024 )[3]: (2.5) Digital control of the FSC allows the DAC output current to be digitally controlled in increments of 0.1875 A from a minimum of 8.64 A to a maximum of 31.68 A1. Figure 2.2: Block diagram showing internal functionality of the AD9912, reproduced from the datasheet[3]. 2.1.3 RF Output and the Reconstruction Filter The AD9912’s DAC produces a sampled reconstruction of the desired sinusoidal signal. A basic result in Fourier Analysis says that this reconstructed signal contains both the desired baseband signal, extending from DC to the Nyquist frequency (fs=2), as well as images of this baseband signal which appear periodically at intervals of fs=2 and theoretically extend to in nity[3]. Note that the  rst unwanted image is that of the baseband signal, mirrored about fs=2. This means that as the DDS output frequency is increased, the frequency of the fundamental spur in the  rst image decreases. For example, if the DDS output frequency is 400MHz, the  rst spur will appear at 600MHz. At an output frequency of 490MHz, the  rst spur will appear at 510MHz. So as the output frequency increases, the requirements on the  lter become more stringent. The result is a practical limitation on the DDS output frequency which is less than the Nyquist frequency of fs=2. The actual limit will depend upon the properties of the  lter used and the requirements of the application. Our application desires only the baseband signal, and therefore the DAC output must be low-pass  ltered to remove higher frequency noise. This  lter is referred to as the reconstruction  lter. It is desired that this  lter have a cut-o frequency of 400MHz, as steep a roll-o as possible (rejection at 500MHz is desired) and very good rejection in the stop-band (60dB attenuation at a minimum). 1This follows from Equation 2.4. Comparably, the datasheet’s AC speci cations table gives the DAC’s typical and maximum full-scale output current as 20 A and 31 A, respectively.2. DISCUSSION 7 Following from the AD9912 evaluation board design, a 50 surface mount RF transformer (ADT2-1T-1P+, Mini-Circuits) is used to transform the di erential signal pair of Figure 2.2 (DAC OUT/ DAC OUTB) into a single-ended signal prior to  ltering[4]. A single-ended  lter design is less sus- ceptible to component variations than its di erential counterpart[4]. A di erential  lter design might be more appealing to users who were only interested in the clock generation feature of the AD9912 (see Section 2.1.4), not the RF output, since no transformers would be required. However, our application requires a single-ended RF output, and so one the transformer would still be required. Note that the RF transformers have a (7 8)mm2 footprint and cost approximately $4.25. Note that since transformers do not function at low frequencies, the RF output will be attenuated at very low frequencies and will not function near DC2. The ADT2-1T-1P+ RF transformers are rated for frequencies in the range of 8 to 600 MHz. The reconstruction  lter design is based on that of the AD9912 evaluation board, Rev. B3. It is a 7th-order passive elliptic low-pass  lter, shown in Figure 2.3. 2.1.3.1 SPICE Veri cation The reconstruction  lter design was veri ed through a SPICE simulation (AC Analysis in NI Mul- tiSim v11.0). Figure 2.3 shows the schematic used for SPICE simulation and Figure 2.4 shows the resulting transfer function. As we can see from the transfer function, the cut-o frequency is 400MHz, the roll-o occurs in 100MHz and the stop-band attenuation is about 60dB. The data used to generate the plot shows that the pass-band ripple is a maximum of about 1.5dB. Figure 2.3: Reconstruction  lter schematic used for SPICE simulation. This is a 7th order elliptic low-pass  lter with a 400MHz cut-o frequency. Designators were taken to match the PCB. 2.1.4 Clock Drivers The AD9912 has two on-board clock drivers, the CMOS output driver and the HSTL output driver. These clock drivers share the di erential FDBK IN/FDBK INB inputs and e ectively serve to trans- form the  ltered sinusoidal DAC output into a square clock signal. A second ADT2-1T-1P+ RF 2This is not a concern for the QDG lab, as the existing AD9852-based devices function at frequencies from DC to 135MHz[9]. 3Rev. A uses a 240 MHz low-pass  lter with very similar design.2. DISCUSSION 8 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500−120 −100 −80 −60 −40 −20 0 Magnitude (dB ) Frequency (MHz) Magnitude Plot 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 −180 −135 −90 −45 0 45 90 135 180 Phase (deg ) Frequency (MHz) Phase Plot Figure 2.4: Reconstruction  lter frequency-domain transfer function generated from a SPICE sim- ulation of the circuit shown in Figure 2.3 transformer is used to transform the single-ended  lter output into a di erential signal suitable for the FDBK IN/FDBK INB inputs. The CMOS output driver provides a CMOS-level clock signal and is suitable for frequencies in the range 8kHz to 150MHz[3]. The device can be con gured at component population to have a CMOS voltage of either 3.3V or 1.8V (see Section 2.4). The CMOS output driver includes an integer divider which can be enabled or bypassed. When bypassed, the CMOS output frequency is the same as the signal on the FDBK IN/FDBK INB inputs. When enabled, this frequency can be reduced. At frequencies below 30MHz, noise on the CMOS output can be reduced by enabling the CMOS divider and running the DAC at a higher frequency[3]. See the AD9912 datasheet for more information. The HSTL output driver provides a 1.8V di erential clock signal and is suitable for frequencies in the range 20MHz to 725MHz[3]. Frequencies above the Nyquist rate fo the AD9912 are achieved with a 2 frequency multiplier. The datasheet claims a duty cycle between 48% and 52%, while the CMOS driver’s duty cycle is given as being between 45% and 55%. Note that unlike the AD9852, the AD9912 does not support digital control of the duty cycle of the output clock. 2.1.5 Clock Inputs The DDS device has two clocks on-board. These are referred to as SYSCLK and SCLK. SYSCLK drives fs, the internal DAC sample rate of the AD9912. The frequency of fs is directly proportional to the output frequency of the DDS. If PLL is enabled on the AD9912, fs can be made to have a frequency up to 66 times greater than that of SYSCLK. SCLK is the digital control clock and controls the frequency of the AD9912’s serial control interface.2. DISCUSSION 9 2.1.5.1 SCLK SCLK controls the frequency of the AD9912’s serial control input. This clock is also used to convert the incoming digital programming parallel signal into the serial signal used by the AD9912. Our implementation allows for two possible sources for SCLK: an external connection and an on-board clock oscillator (TXC 7C Series). The external connection is intended for testing purposes, particu- larly to determine the maximum frequency at which the serial input can reliably operate (see next paragraph). Once this frequency has been determined, an appropriately selected TXC 7C IC will be placed on board and used as SCLK. An important note is that the TXC 7C datasheet does not specify whether the enable pin is active high or active low. The board includes jumpers to allow for both possibilities; see Section 2.4 for information on switching between these two options. According to the AD9912 datasheet SCLK is limited to a maximum of 50MHz[3]. However, the maximum value of SCLK will likely be limited by the digital control logic and not the AD9912. Timing analysis based upon information in all relevant components’ datasheets suggests that the maximum SCLK frequency should be around 25MHz; see Section 2.1.6 for details. 2.1.5.2 SYSCLK SYSCLK is the main system clock. The DAC sample rate, fs, is controlled by SYSCLK. As discussed below, the AD9912 has PLL multiplier circuitry which allows fs to be up to 66 times greater than the frequency of SYSCLK. From the AD9912 datasheet, fs is limited to a maximum of 1GHz, so the SYSCLK and PLL multiplier must be carefully chosen to be less than this speed[3]. The AD9912 supports the use of either a crystal oscillator or a clock oscillator; the DDS device supports both an on-board crystal oscillator and an external clock source (recommended). Depending on which is to be used, the jumpers necessary to connect the clock source or crystal oscillator to the AD9912 must be installed; see Table 2.7. 2.1.5.3 PLL The AD9912’s PLL circuitry allows the frequency of SYSCLK to be increased by any even multiple between 4 and 66. This circuitry generates an internal clock using a Voltage-Controlled Oscillator (VCO). The voltage that controls the VCO is generated by a current pump and an external loop  lter consisting of components de ned in Table 2.6 and is related to the phase di erence between the internal clock, divided by a number set by the PLL register, and the SYSCLK. The voltage then raises and lowers to converge the internal clock on a set multiple of the SYSCLK[3]. The AD9912 PLL also includes a frequency doubler before the PLL circuitry itself. This func- tionality creates a clock pulse on both the rising and falling edge of SYSCLK, doubling the frequency. Using the frequency doubler creates a clock output that has an improved phase noise performance over simply using double the PLL multiplier instead. Unfortunately, the frequency doubler does not produce a clean rectangular pulse with constant duty cycle. That is, subharmonics are introduced at multiples of the SYSCLK input frequency. The PLL multiplier should be chosen to suppress these subharmonics[3]. Using the PLL allows for a slower clock to be used as the input to the DDS device. Slower clock sources are much cheaper and easier to acquire. However, the PLL will introduce additional noise and inaccuracy into the system, especially as the PLL multiplier approaches the maximum of 66 . The ideal con guration of the PLL loop  lter depends on the multiplier to be used. If PLL is to bypassed, then the loop  lter can also be bypassed. See Section 2.4 for details. 2.1.6 Digital Control The devices are controlled through an existing parallel interface called the University of Texas Bus (UTBus). Custom circuitry on board our devices has been designed to interface the parallel UTBus with the AD9912’s serial control port. This section will describe the UTBus, the serial control port and the custom interface between the two.2. DISCUSSION 10 2.1.6.1 The UTBus The UTBus is an existing parallel programming interface used by the QDG lab and based upon Todd Meyrath’s work[9]. As the UTBus is already in use in the lab4, supporting this interface was a design requirement. The interface uses ribbon cable and a 50-pin Molex connector with pin functionality as de ned in Figure 2.5. As shown, these 50 pins are divided into 25 grounded pins, 8 address bits, 16 data bits and one additional bit, called the strobe. The 8 address bits are used to specify which device should receive the 16 bit command. The strobe bit is e ectively a clock with a 1/3 duty cycle; when the strobe bit is high, the address and command are guaranteed to be stable. The UTBus address and data pins are asserted for three distinct periods with equal length: once, while the strobe remains low, a second time while the strobe is high, and a third time while the strobe is low[7]. These three periods together comprise one UTBus command. This timing is illustrated in Figure 2.6. Figure 2.5: Diagram of the 50-Pin UTBus Connector, reproduced from [9]. Figure 2.6: Timing diagram for the UTBus, showing the strobe, address, data and NI-DAQ clock. Each command sent to a device requires three periods of the NI-DAQ clock to complete. Reproduced from Keith Ladouceur’s Master’s Thesis[7]. The QDG lab currently uses an NI-DAQ, controlled by a desktop computer running a custom python script, to drive the UTBus. Current uses of the UTBus send one command at a time, with an NI-DAQ clock frequency of up to 5MHz. 4The UTBus is used to control various devices in the QDG lab, including analog output devices and the existing AD9852-based DDSs[7].2. DISCUSSION 11 2.1.6.2 The AD9912’s Serial Control Port In contrast with the parallel programming interface of the AD9852, which was used on the previous generation of DDS devices, operation of the AD9912 is controlled through a serial interface. This is inconvenient from a design standpoint because the UTBus provides 16 bits of data in parallel and no suitable clock. Section 2.1.6.3 describes the hardware solution which interfaces the UTBus with the serial control port. A detailed discussion of the serial control port is given in the AD9912’s datasheet, including multiple timing diagrams. Here we summarize the essential elements. The serial control port of the AD9912 consists of four pins: a clock (SCLK), an I/O pin (SDIO), an active-low control pin which gates the I/O cycles (Chip Select Bit (CSB)) and an output pin (SDO). SDO is unnecessary for our application and has been left unconnected on the board5. Control of the AD9912 is established through the writing of binary data to various registers. Each register has a unique 13-bit address and some functionality which is documented in the datasheet. For example, the DDS output frequency can be controlled by writing to the 48-bit register containing the FTW. Note that all registers are not equal in size. Each communication cycle consists of two parts: the writing of a 16-bit instruction word and the reading of or writing to a register. Table 2.1 shows the 16-bits of the instructions words mapped to their corresponding bits in the UTBus. The instruction word contains a 13-bit register address (A12,. . . ,A0), two bits indicating the length of the coming data transfer (W1 and W0, see Table 2.2) and a single bit indicating whether the transfer is to be a read or a write (R/W ). Note that our device supports only only one- and two-byte transfers and does not support reads. Writing to registers larger than two bytes will require multiple communication cycles. Table 2.1: Serial control port instruction word bit functionality. D0,. . . ,D15 correspond to DAT0,. . . ,DAT15 in our design and schematics (see Figures A.3 and A.5). The last row corresponds to the 16 bits of the instruction word. Adapted from the AD9912 datasheet[3]. MSB LSB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Table 2.2: Decoding of the W1 and W2 bits in an instruction sent the AD9912’s serial control port. These two bits control the number of bytes to be transferred in the current communication cycle and describe the number of bytes transferred in this command cycle, excluding the 2-byte instruction. W1 and W0 correspond to the DAT14 and DAT13 data bits on the UTBus, respectively. Note that the AD9912 DDS device does not support all byte lengths. Reproduced from the AD9912 datasheet[3]. W1 W0 Bytes to Transfer Supported? 0 0 1 Yes 0 1 2 Yes 1 0 3 No 1 1 Streaming mode No The CSB must be held low in order for the AD9912 to recognize data on the SDIO. Accordingly, the CSB should be held low during writing of the instruction word. Afterwards, the CSB can remain low and data transfer can begin immediately. Alternatively, the CSB can be brought high to disable the serial control port until the user is ready to transfer data. Data transfer is similar: the CSB must be held low during the writing of each byte of data. Between each byte, the CSB can be brought high to pause the transfer if desired6. 5Actually, the pin itself is connected to a trace leading away from the AD9912 IC and to a via. This is to facilitate testing. 6Streaming mode is an exception to this; during streaming mode, a rising edge on the CSB indicates the end of the communication cycle.2. DISCUSSION 12 Some registers on the AD9912 are bu ered so that writing to these registers does not a ect the device output until an I/O update operation is performed to transfer the data from the bu er registers to the control registers. This can be accomplished by toggling the IO UPDATE pin or by writing a 1 to the register update bit. To simplify the design of the interface between the UTBus and the serial control port, the IO UPDATE pin is disabled on our devices, and so the latter method will be used in practice. In practice, the CSB will be brought high between commands sent on the UTBus in order to stall the communication cycle and allow time for the UTBus to send the next command. 2.1.6.3 Parallel-to-Serial Converter Schematics for the parallel-to-serial converter are shown in Figures A.3, A.4 and A.5. An 8-bit comparator is used to compare bits A7 to A2 of the UTBus address bits (the lower 2 bits are not used as addresses) against the board address. The board address, which can be set using a Dual In-line Package (DIP) switch, is a 6-bit address which should be unique for each device connected to the UTBus. If the address bits match the address set on the DIP switch, a custom arrangement of  ip  ops listens for a rising edge on the strobe bit. When this happens, a pulse is generated that latches the 16 bit command into two SN74HC166 8-bit shift registers. These 8-bit shift registers are daisy-chained together to form a 16-bit shift register. Once the data is loaded in, the shift registers output the UTBus data into the AD9912’s serial port one bit at a time beginning with DAT0. The number of data bits clocked into the AD9912 is an option set by the UTBus address bus bit 1 (A1), renamed to SZ in our schematics. The SZ bit switches between using all 16 bits of the data bus (SZ=0) or only the lower 8 bits of the data bus (SZ=1). The SZ bit will be critical when programming the AD9912; see Section 2.1.6.4. To implement the switch between 8 and 16 bits, the DDS device design takes advantage of the CSB pin on the AD9912. Since the AD9912 can only be programmed when the CSB is held low, the DDS device ensures that the CSB is only held low for either 8 or 16 bits. This is accomplished by using a mirrored set of SN74HC166 8 bit shift registers. These second set of shift registers are loaded with either all logic low, or 8 bits of logic low followed by 8 bits of logic high. The output from these shift registers is directly connected to the CSB and is clocked out at the same time as the shift registers containing the command. This ensures that the AD9912 is only able to receive data on the serial port for exactly the time it takes to clock in one of 8 or 16 bits. Parts of this circuit have been prototyped and tested; see Section 2.5. A timing diagram is presented in this section using the data collected; see Figure 2.19. 2.1.6.4 Programming Programming the DDS device consists of sending a series of commands on the UTBus. On each command, 8 or 16 bits of data on the UTBus are clocked into the DDS one bit at a time beginning with DAT0. The UTBus address bit A1 (renamed to SZ in our schematics) controls the length of the data transfer (low for a 16-bit transfer). Thus (see Section 2.1.6.2), each communication cycle with the AD9912 requires two commands to be sent on the UTBus. The  rst command sent will always be 16-bits and tells the AD9912 which register is to be written to as well as how much data is to be written (8 or 16 bits; see Table 2.2). The second command can be either 8-bits or 16-bits and is the actual data to be written to the register addressed previously. If the register being written is a bu ered register (see Section 2.1.6.2), an additional register must be written to update the DDS output. This can be done immediately or after multiple registers have been written to. If the register to be written to is larger than 16-bits, multiple communication cycles are required, as illustrated in the example below. The following is an example of a series of commands to set the FTW to 68DB8BAC7167 (FTW controls the output frequency; see Section 2.1.2). With fs=1GHz, this sets the AD9912 output to 100MHz. The FTW is 48 bits, and so requires 3 communication cycles to completely overwrite. The 768DB8BAC716 = 0000 0000 0000 0110 1000 1101 1011 1000 1011 1010 1100 011122. DISCUSSION 13 fourth communication cycle shown below is a write to the I/O Update register, which causes the output frequency to be updated. The address and strobe bits are not shown. Table 2.3: Sample DDS Device Commands to set the output frequency to 100MHz and subsequently update the output. The  rst 6 commands set the FTW to the value required for at output frequency of 100MHz, while the last two commands tell the AD9912 to update the output. Data SZ 0-3 4-7 8-11 12-15 Description 0 0010 0001 1010 1011 Send (0) the next two bytes (01) of data to register 01AB16 (0001101010112), the register containing the top 8 bits of the FTW 0 0000 0000 0000 0110 Write 000000002 to register 01AB16 and 000001102 to regis- ter 01AA16 0 0010 0001 1010 1001 Send (0) the next two bytes (01) of data to register 01A916 (0001101010012) 0 1000 1101 1011 1000 Write 100011012 to register 01A916 and 101110002 to regis- ter 01A816 0 0010 0001 1010 0111 Send (0) the next two bytes (01) of data to register 01A716 (0001101001112) 0 1011 1010 1100 0111 Write 101110102 to register 01A716 and 110001112 to regis- ter 01A616, bits 15:8 of the FTW 0 0000 0000 0000 0101 Send (0) the next byte (00) of data to register 000516 (00000000001012), the IO UPDATE register that tells the AD9912 to update the output 1 1000 0000 0000 0000 Write 1 to the 1 bit IO UPDATE register 2.1.7 Power Management The AD9912 has stringent power requirements to ensure the highest-performance operation. Both 3.3V and 1.8V power supplies are needed. While it would be possible to implement an AD9912- based device using only two power rails, the datasheet highly recommends isolation between each group of power supplies on the AD9912. The extent to which isolation is required depends on the requirements of the application. See Power Supply Partitioning in the AD9912 datasheet for a detailed description of which pins can be grouped together and which should be isolated. The isolation between power supply groups can be achieved by using separate regulators for each group or by placing a ferrite bead between a common regulator and each rail. Separate voltage regulators provide better isolation but require more PCB area, increase the cost of the device8 and increase the power consumption of the device9. Our design uses four regulators, two at each of 1.8V and 3.3V, each separated into the broad groups analog and digital. Five ferrite beads are then used to isolate  ve power supply groups, each sourcing from the 1.8V analog regulator. See the schematics shown in Figures A.7 and A.8. The CMOS clock driver power supply (VDD CMOS) can either be connected to the analog 3.3V regulator through a ferrite bead (F4) or to the analog 1.8V regulator through a 0 jumper (W14)10, depending on the desired CMOS output voltage level. All power pins on the AD9912 and digital logic ICs have a 0.1 F bypass capacitor connected as close as possible to the supply connection. Bypass capacitors serve as power reservoirs, providing instantaneous power to the IC. They prevent that power from needing to travel over a long connection to the voltage regulator, introducing delays due to parasitic inductance of the traces involved. Instead 8The cost of each high-performance Low-Dropout (LDO) voltage regulator used was about $4.50. 9This is not a signi cant concern for this application. 10See the datasheet for more information on the CMOS power supply recommendations. W14 uses the same 0805 package as the ferrite beads, allowing a ferrite bead to be used instead of a jumper if desired.2. DISCUSSION 14 the power comes directly from the capacitor, which is placed as close as possible to the IC in order to minimize parasitic inductance. This capacitor is then recharged by power from the voltage regulator at a speed much closer to DC. 2.2 PCB Layout Considerations Major sources of inspiration were the AD9912 evaluation board and Todd Meyrath’s AD9852 design[9] (shown in Figure 1.1). Here we discuss the components chosen for the DDS device, the considerations needed for power management, techniques for managing heat and how trace widths were chosen to ensure signal integrity. 2.2.1 Components All parts and components used on the DDS device were selected and sourced, beginning by con- sidering the components used on either the AD9912 evaluation board or Todd Meyrath’s AD9852 design[9]. Many of these parts were re-used, as re ected in the complete Bill of Materials, which is given in Appendix D. For this application, Surface-Mount Devicess (SMDs) were preferred to through-hole components due to reduced inductances and the possibility of higher component density, which is ideal for high frequency design[10]. For these reasons (and following the example of the AD9912 evaluation board and the old AD9852 DDS), most components on our board are surface-mount. There are only three through-hole components: the 50-pin Molex UTBus connector, the 3-pin Molex power con- nector (5V) and the 10-Pos switch (sets the board address and the AD9912 start-up con guration). Component choice for the UTBus and power connectors is compatible with those used in previous generation devices. Most common passive components use either 1206 (3.2mm 1.6mm) or 0402 (1.0mm 0.51mm) surface-mount packages. The 1206 packages is preferred for its larger footprint11, but 0402 is pre- ferred near the AD9912 IC in order to shorten the trace lengths between the AD9912 IC and its bypass capacitors12. Most components are placed on the top side of the board. Bottom-side components are limited to resistors, capacitors and ferrite beads. The BNC connectors are mounted to the enclosure and solder directly to 2.54 6.35mm pads on the PCB. This design is identical to that used in Todd Meyrath’s AD9852 design[9]. The linear regulators used for this board (Texas Instruments TPS78633 and TPS78618) were selected due to their proven use in Todd Meyrath’s AD9852 design[9]. These are  xed-voltage 1.5A LDO voltage regulators suitable for use with a 5V supply. Four regulators are used. See Section 2.1.7 for more information. 2.2.2 Power Plane The third layer of the 4-layer PCB is a dedicated power plane, shown in Figure 2.7. This power plane was split into  ve regions. Around the outside perimeter of board is a 5V plane which is supplied by the 3-pin external power connector. A 470 F tantalum capacitor near the connector stabilizes this supply and ensures constant voltage levels. The 5V supply is used by the four on-board linear power regulators which power the remaining four regions. The left side of the power plane (labelled Digital 3.3V) is used to supply a 3.3V signal to the digital components which provide the digital interface between the UTBus and the AD9912. The Digital 3.3V power plane also provides power for the AD9912’s serial control port. The three other power planes (Digital 1.8V, Analog 1.8V and Analog 3.3V) provide power to the appropriate sections of the AD9912 IC. These are all required to be independently supplied and 11The small 0402 footprint requires a steady hand and some skill in order to install manually. 12To reduce Electromagnetic Interference (EMI), a Texas Instruments white paper recommends that the length-to- width ratio of traces between an IC and its voltage source should not exceed 3:1[10].2. DISCUSSION 15 there are stringent requirements on bypass capacitors and ferrite beads, as listed by the AD9912 datasheet. These recommendations have been followed wherever practical.     Digital 3.3V Digital 1.8V Analog 1.8V Analog 3.3V 5V 5V 5V Figure 2.7: The PCB power plane design. This is a negative fabrication image; black areas indicate removal of copper. The plane is split into  ve region, labelled in the  gure. There are analog and digital 1.8V and 3.3V power planes as well as a 5V plane which serves to supply the four on-board LDO voltage regulators. The PCB areas taken up by each voltage regulator and bypass capacitors are shown outlined in dashed green lines. 2.2.3 Heat Dissipation Power dissipation is an important consideration for the voltage regulators and the AD9912. Both ICs have grounded thermal contacts which are to be soldered directly to copper  lls on the top side of the PCB. As recommended by both ICs’ datasheets, an array of thermal vias is located under each of these pads and serves to conduct heat away from the ICs. All empty areas on the bottom side of the PCB are ground- lled and this serves to increase the heat capacity. Areas on the bottom layer which are to be in contact with the aluminium enclosure have the insulating soldermask removed, increasing heat transfer to the enclosure (as well as grounding the enclosure). Figures 2.10 and 2.11 show the full PCB layout from the top and bottom sides. 2.2.4 Characteristic Impedance and Trace Width Characteristic impedance is the instantaneous impedance of a PCB trace. It is the impedance that a high-speed signal will encounter as it propagates along a trance, charging up the metal of the trace as it goes. This charging is essentially charging a capacitor where the signal trace is the top of the capacitor, the PCB prepreg is the dielectric and the ground plane is the bottom of the capacitor[1]. As the signal’s edge travels along the trace, it charges the trace itself before encountering any other electrical components. If the trace impedance is di erent from the source or destination impedance, it is possible that the signal’s energy will not be completely transferred, with some of the energy returning back through the trace. This can cause constructive or destructive interference, resulting in a less accurate signal.2. DISCUSSION 16 To avoid this, our design ensured that high-frequency signal traces were 50 . 50 is a common standard and matches the input impedance of the ampli er that the RF output is intended to drive. All other components along these signal paths should be 50 as well, including the RF transformers, BNC connectors and coaxial cables. Equation 2.6 gives a formula for calculating the characteristic impedance of a rectangular trace[5], where W, T and H are in common units.  r is the dielectric constant of the PCB prepreg. This equation is an approximation and it most accurate for Z0 between 50 and 100  [5]. It is the same equation that Altium Designer uses by default for calculating the characteristic impedance of traces. Z0( ) = 87 p  r + 1:41 ln 5:98H 0:8W + T (2.6) Figure 2.8 shows the trace geometry assumed by Equation 2.6. This trace geometry is referred to as a microstrip. Figure 2.8: Diagram of microstrip trace geometry. Use this  gure for characteristic impedance calculations following Equation 2.6. Reproduced from [5]. The situation is slightly more complicated for di erential signals. Equation 2.7 can be used for di erential signals [6]. S is the spacing between the two traces carrying the di erential signal. Zdiff = 2Z0( )[1 0:48e  0:96 SH ] (2.7) An alternative trace geometry is referred to as the stripline, and is shown in Figure 2.9. Striplines have the advantage of having lower impedance than the equivalent microstrip and of providing natural shielding for high-frequency signals, thus reducing emissions and reducing interference from incoming signals[5]. Emissions and external interference is not a signi cant concern for us, as the boards are to be enclosed in a solid aluminium enclosure. Also, striplines are not accessible from the exterior of the board, making testing more di cult. We do not use striplines on our board. Figure 2.9: Diagram of stripline trace geometry. This  gure is shown for comparison only; striplines do not appear on our device. Reproduced from [5].2. DISCUSSION 17 Using Equations 2.6 and 2.7 and the following parameters,  r = 4.350 (FR-406 dielectric material) T = 2.8 mils (0.071 mm or the thickness of 2 oz/ft2 copper) H = 9.6 mils (0.244 mm) S = 9.0 mils (0.229 mm) trace widths giving 50 were calculated as 14.75mils (0.375mm) for single-ended signals and 26.5mils (0.673mm) for di erential signals. Wherever practical13, these widths were used in the design. 2.3 Design and Fabrication Methods This section describes the methods used in designing and fabricating the PCB and enclosure. 2.3.1 Schematic Design Altium Designer was the software tool used to design the new device, both for a connectivity-level schematics to the generation of layer-by-layer PCB fabrication  les. Due to similarities, the design was largely based upon the AD9912 reference board schematic. This included the schematic for the DDS output, including the Reconstruction Filter, but did not include digital input or power designs. These additional designs were based upon Todd Meyrath’s AD9852 design[9] but were extensively modi ed due to the di erences between the AD9912 and the AD9852. All schematic diagrams are shown in Appendix A. 2.3.2 PCB Design As mentioned, Altium Designer was the software tool used design the PCB layout. Once the design was complete, Altium was used to generate layer-by-layer PCB fabrication  les (Gerber  les) and drill  les. Printouts of these Gerber  les are shown in Appendix B. The drill  les instruct the PCB manufacturer on the size and location of all holes to be drilled. Section 2.2 discusses several considerations which in uenced the PCB design. Figures 2.10 and 2.11 show the full PCB layout from the top and bottom sides. Figures 2.13 and 2.12 show assembly diagrams for the PCB. The top and bottom pastemasks and silkscreens are shown above the enclosure and IC mechanical drawings. 13Very close to the AD9912 it is nessessary to reduce the width of the traces, due to the small pin spacing of the IC.2. DISCUSSION 18 Figure 2.10: Top Side PCB layout. The top copper layout is shown in red. The top pastemask is shown in purple (shown on top of the copper layer). Figure 2.11: Bottom Side PCB layout. The bottom copper layout is shown in blue. The bottom pastemask is shown in pink (shown on top of the copper layer). Notice the bottom of the PCB is ground- lled and that large areas of this ground  ll have been exposed (see pink areas). These regions are located along the edges of the PCB and below the AD9912 IC and the voltage regulators. They allow the PCB to be grounded to the enclosure and improve heat dissipation.2. DISCUSSION 19 Figure 2.12: Assembly diagram showing the top pastemask and silkscreen above the enclosure and IC mechanical drawings. Figure 2.13: Assembly diagram showing the bottom pastemask and silkscreen above the enclosure drawings.2. DISCUSSION 20 2.3.3 PCB Fabrication The PCB layout design was used to generate fabrication  les. There is a drill  le, eleven Gerber  les and a README  le with basic fabrication instructions. The eleven Gerber  les are shown in Appendix B. The boards are 5:300  300, which is the same size as the previous generation DDS devices. They are four-layer boards (top signal, ground, power, bottom signal), which is again the same as the previous generation DDS devices. They were fabricated using FR-406 dielectric material (4.350 dielectric constant, 9.6 mils (0.244 mm) thick). Each side of the board is protected and insulated with a green solder-mask and is annotated with a white silkscreen. The PCBs were fabricated by Advanced Circuits. An electrical test was also performed by Advanced Circuits. Most components were sourced by our team and ordered from Newark. At time of writing, the Department of Physics and Astronomy (PHAS) electronics shop was in the process of assembling a single prototype device. The device is expected to be complete within two or three days of the submission of this report. We provided them with all necessary parts (except ferrite beads) and assembly instructions. Figures 2.14 and 2.15 are photos of the top and bottom of the PCBs. These photos were taken after the assembly process had begun. Several components are installed, including the AD9912 IC itself. Figure 2.14: Photo of the PCB, top side. Some components have been installed.2. DISCUSSION 21 Figure 2.15: Photo of the PCB, bottom side, no components. 2.3.4 Enclosures The enclosure is made of aluminium and has two pieces: a body and a lid. The enclosure design was based upon Todd Meyrath’s work[9]. Due to the increased complexity of our design, it was found that the original enclosures would short many of the PCB vias. Avoiding these shorts through changing the PCB was found to be impractical due to space constraints. For this reason, the original enclosure was modi ed to minimize the metal surface in contact with the PCB while maintaining structural integrity. The decreased contact area provided adequate area for the vias. The enclosure was grounded in a number of ways. The primary method of grounding is through the screws attaching the PCB to the enclosure, which ensures both a tight  t and adequate return paths. However, the areas of the bottom of the PCB in direct contact with the enclosure were also ground  lled and exposed to allow for further contact. This grounding is particular important, as the BNC connectors used obtain their ground only from the enclosure itself. The New Jersey-based on-line machine shop company eMachineShop was chosen as the sup- plier (www.emachineshop.com). eMachineShop was the supplier for the enclosures used for the AD9852-based DDSs (upon which the new design is based). The enclosures were designed using eMachineShop’s proprietary software, also called eMachineShop. Fifteen enclosures have been or- dered from eMachineShop and are expected to arrive within two to three weeks of the submission of this report. Figure 2.16 is a labelled diagram of the enclosure body, shown from the top. Green dotted lines indicate the approximate outlines on the PCB of the four LDO voltage regulators and the AD9912 IC. Shown are ten 4-40 threaded holes and fourteen 8-32 threaded holes, used for mounting the enclosure lid and the PCB, respectively. Gray dotted lines indicate sixteen 4-40 threaded mounting holes, twelve of which are for mounting three BNC receptacles and four of which are for mounting the enclosure to a rack. The lid is unchanged from the previous design and is shown in Figure 2.17. Shown are twelve 4-40 clearance holes, used to mount the enclosure lid onto the body (two of these holes will be unused as they have no matching hole in the body). Two spaces are cut into the lid to allow for the 50-pin data and 3-pin power connectors. Designs for rack mounting brackets also exist. Each bracket allows up to eight DDS devices to be mounted to the electronics racks in the QDG lab. The design was modi ed slightly from an existing design; the spacing of mounting holes were changed to be compatible with the intended2. DISCUSSION 22 racks. Five14 brackets have been ordered. At time of writing, the rack mounting brackets have already been fabricated and are in transit. Figure 2.18 shows a 3D rendering of the enclosure, created using eMachineShop software. DD?  ?? ??? ??? Digital 3.3V Digital 1.8V Analog 1.8V Analog 3.3V 5V Conn. 5?-?in ????? ?onn. ???? ??? ??? ?????? ?? ??? Figure 2.16: Labelled diagram of the enclosure body (top view). Green dotted lines indicate the approximate outlines on the PCB of the four LDO voltage regulators and the AD9912 IC. 14Not all of these brackets are intended for this project. Extra backets were ordered at the request of the QDG lab.2. DISCUSSION 23 Figure 2.17: Diagram of the enclosure lid (top view). This design is unchanged from the design used for the previous generation DDS devices at the QDG lab. Figure 2.18: 3D rendering of the enclosure, created using eMachineShop software.2. DISCUSSION 24 2.4 Board Features This section will begin by discussing the device’s available inputs and outputs, the 10-position switch used to specify the board address and AD9912 start-up con guration, and the possible con gurations which are possible when the device is assembled. 2.4.1 Inputs and Outputs Table 2.4 lists the connection pads available on the PCB for BNC Connector mounting. Note that only J3, J5 and J6 are intended for mass production, and the enclosure design re ects this (see Section 2.3.4). Table 2.4: List of connection pads available on the PCB designed for BNC Connector mounting. Note that only J3, J5 and J6 are intended for mass production, and the enclosure design re ects this. Designator Name Mass Production? Description J1 SCLK No digital control clock input J2 DAC OUT No un ltered RF signal, or input to reconstruction  lter for debugging J3 RF Yes  ltered RF output signal J4 FDBK IN No input to the AD9912’s on-chip comparator J5 SYSCLK Yes main clock input J6 CMOS Yes programmable clock output (CMOS-level) J7 OUT N No di erential programmable clock output (nega- tive) J8 OUT P No di erential programmable clock output (posi- tive) 2.4.2 DIP Switch A 10-position DIP-package single-pole single-throw switch is shared between the six board address bits and the four AD9912 start-up con guration bits (S1,S2,S3 and S4). Each switch is labeled on the silkscreen on the top side of the PCB. With the switches closed, the connections are grounded. With the switches open, the connections are pulled to the 3.3V digital rail through 10k resistors. The AD9912 start-up con guration bits on the AD9912 allow control of the default start-up output frequency and the system clock input mode (PLL enabled or bypassed). A decoding of the con guration bits is reproduced from the AD9912 datasheet in Table 2.5[3]. 2.4.3 Con guration Options The DDS device has various functionality and options that may be enabled, disabled or switched between by placing or not placing various components. Here we summarise all options of the board and provide details on how to use them. Table 2.7 summarizes the key options and gives details on speci c components which need to be omitted for each option. 2.4.3.1 SYSCLK The DDS device is intended to be clocked with an external clock source on BNC connector J5. However, the option is provided to use an onboard crystal oscillator. In the QDG lab, the o -board SCLK will originate from a 10MHz rubidium clock with another DDS being used to increase the frequency as needed (the CMOS clock driver of the AD9912 or AD9852 equivalent are possible). For more information, see Section 2.1.5.2.2. DISCUSSION 25 Table 2.5: Options for Power-Up Default Frequencies on the AD9912, for 1GHz System Clock. Adapted from the AD9912 datasheet[3]. These options can be changed on the device by toggling four PCB-mounted switches. S4 S3 S2 S1 SYSCLK Input Mode Output Frequency (MHz) 0 0 0 0 Xtal/PLL 0 0 0 0 1 Xtal/PLL 38.87939 0 0 1 0 Xtal/PLL 51.83411 0 0 1 1 Xtal/PLL 61.43188 0 1 0 0 Xtal/PLL 77.75879 0 1 0 1 Xtal/PLL 92.14783 0 1 1 0 Xtal/PLL 122.87903 0 1 1 1 Xtal/PLL 155.51758 1 0 0 0 Direct 0 1 0 0 1 Direct 38.87939 1 0 1 0 Direct 51.83411 1 0 1 1 Direct 61.43188 1 1 0 0 Direct 77.75879 1 1 0 1 Direct 92.14783 1 1 1 0 Direct 122.87903 1 1 1 1 Direct 155.51758 2.4.3.2 SCLK It is possible to use either a clock oscillator or an external clock source to drive SCLK. The intention is to use an on-board clock oscillator (nominally 25MHz, but this will be determined after testing). For more information, see Section 2.1.5.1. 2.4.3.3 SCLK Enable Pin If the on-board clock oscillator is to be used, one of W4, W5 and W6 must be installed in order to enable the clock oscillator. The board provides jumpers allowing the SCLK enable pin to be connected to ground (W4), 3.3V (W5) or the address comparator output15 (W6). The address comparator output is LOW when the address matches. 2.4.3.4 CMOS Clock Driver Voltage The CMOS clock driver output voltage can be con gured to be either 1.8V or 3.3V, depending on the supply voltage present on the VDD SCLK pin. The board provides two 0805 footprints (F4 and W14) allowing a jumper or ferrite bead to connect the pin to either voltage rail. For more information, see Section 2.1.1. 2.4.3.5 PLL When the PLL is enabled, follow Table 2.6 when choosing values for the loop  lter components. See the circuit schematic shown in Figure A.6 for context. The PLL can be enabled or bypassed on the AD9912 by writing a 0 or 1 to Register 0x0010, Bit 4[3]. The default can be controlled through startup pin S4. The N-divider should also be set (Register 0x0020, bits 4:0); see the AD9912 datasheet for more information. This N divider will be half of the PLL multiplier; since N is restricted to 2 < N < 33, 4 <PLL multiplier< 66. For more information, see Section 2.1.5.3. 15We aren’t really sure if this is useful, but we thought it might be, so we included it. The idea is that the clock oscillator will turn o if the board isn’t being talked to by the UTBus. This would reduce power usage and possibly noise, but may introduce new complication during programming.2. DISCUSSION 26 Table 2.6: Recommended Loop Filter Values for a Nominal 1.5MHz SYSCLK PLL Loop Bandwidth. Adapted from the AD9912 datasheet[3]. Designators have been taken to match actual designators in PCB design. See the circuit schematic shown in Figure A.6. Multiplier R4 Series C46 Shunt C45 8 390 1nF 82pF 10 470 820pF 56pF 20 1k 390pF 27pF 40 (default) 2:2k 180pF 10pF 60 2:7k 120pF 5pF 2.4.3.6 RF Path It is desirable to be able to characterise the reconstruction  lter. To do so, the board provides an option to connect BNC connector J2 directly to the input of the reconstruction  lter. To use this option, place jumper W3 and do not place jumpers W2 or W7. To monitor the pre- lter single-ended AD9912 DAC output on BNC connector J2 instead, place W2. For normal operation, place only W7. The jumper W8 can be used to connect the  ltered DAC output to the AD9912 FDBK IN inputs (these drive the clock drivers). If either clock driver is to be used, install W8. If the clock drivers are not used, W8 should be omitted, and T2 and R5 are unnecessary. Table 2.7: List of all device con guration options. In general, all components should be installed except those listed beside the desired options. Option Components to omit SYSCLK (1) XTal C53 C54 R7 R8 R9 R14 T3 W151 (2) External W11 W12 X1 C48 C51 W161 SCLK (1) Clock Oscillator2 W1 (2) External U2 W4 W5 W6 CMOS Voltage (1) 1.8V F41 (2) 3.3V3 W141 PLL (1) Disabled C45 C46 R4 W10 (2) Enabled4 R3 W9 RF Signal Path5 (1) Clock Drivers Disabled C55 C60 C61 C63 R5 R6 R10 R11 R12 R13 T2 W2 W3 W8 W13 (2) Clock Drivers Enabled W2 W3 1 These components are located on the bottom side of the PCB. 2 The clock oscillator used has an enable pin that could be either active high or active low; see Section 2.1.5.1. 3 W14 uses the same (0805) package as the ferrite beads, allowing a ferrite bead to be used instead of a jumper if desired. See Section 2.1.7 4 If PLL is enabled, the loop  lter components must be chosen according to Table 2.6 5 These are the conventional options are for normal operation. There are several other possible con gurations available; see Section 2.4.3.6.2. DISCUSSION 27 2.5 Breadboard Testing In order to verify functionality of the parallel to serial converter, the circuit was constructed and tested on a breadboard. The PHAS electronics shop provided 8-bit shift registers (CD74HCT165E) and  ip- ops (74HCT74N) in DIP packages for testing. The components used are functionally similar to the SN74HC166 shift registers and SN74HC74  ip- ops, which are the intended components. However, the HCT165E shift registers have an asynchronous load while the SN74HC166 have a synchronous load. The slight di erence in shift register functionality does not fully compromise the test, however it does lead to some undesirable output as discussed below. Switches were used to statically simulate the address comparator output, the strobe and 16- bit data input (arbitrarily set to 1010 1010 1001 01012). The outputs were monitored with an oscilloscope. Results are shown in Figure 2.19. Note that, as expected, the CSB was held low while the data was clocked out on SDIO. The undesirable output is indicated graphically on the SIO and CSB subplots of Figure 2.19. Both signals responded too soon to the SH/LD signal due to the asynchronous load of the HCT165E shift registers. The DDS device is designed to use the SN74HC74 shift registers, which have a synchronous load. The result will be that the output will not respond to a change in the SH/LD signal until a rising edge of the clock. The red lines shown in Figure 2.19 indicate the desired output.2. DISCUSSION 28 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 0 2 4 SCLK (Clock) Time (µs) Voltage (V ) −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 −2 0 2 4 6                   SH/LD (Shift/Load) Time (µs) Voltage (V ) −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 −2 0 2 4 6                  SIO (Serial Data) Time (µs) Voltage (V ) −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 −2 0 2 4 6                      CSB (Chip Select Bit) Time (µs) Voltage (V ) Figure 2.19: Parallel-to-serial converter breadboard test results. This test simulates the writing of the (arbitrarily chosen) 16-bit number 1010 1010 1001 01012 to the AD9912 serial control port. The top graph shows the clock, which was operating at 5.642MHz. A function generator was used. Below this, the SH/LD graph illustrates the functioning of the load pin. When this signal is low, the 16-bits of data on the UTBus are latched into two 8-bit shift registers on the DDS device. When high, shift register contents are clocked into the AD9912. Second from the bottom, the SIO data plot illustrates the data output from the shift registers. The results are not as desired, but this is expected due to using parts not from the design (CD74HCT165E shift registers were used in place of SN74HC74). The red lines illustrate the desired behaviour. The bottom graph shows that the CSB, which is implemented identically to the SIO and demonstrates the same issue.3 Conclusions This report studied the operation of the AD9912 and described in detail the elements of its operation which are relevant to the project. A conceptual design satisfying the project requirements has been created and presented. As required, the design is compatible with the existing UTBus control interface and is designed to provide a sinusoidal output signal at frequencies from 8 to 400MHz. The reconstruction  lter design was borrowed from the design given for the AD9912 evalua- tion board, Rev. B. This design has been veri ed through a SPICE simulation and the resulting theoretical transfer function has been presented. This transfer function meets the desired perfor- mance speci cations: 400MHz cut-o frequency, a roll-o within 100MHz and a minimum of 60dB of attenuation in the stop-band. Altium Designer was used as the software tool in creating connectivity-level schematics and PCB fabrication  les. The new PCB design uses the same board dimensions, I/O connectors and layer stack-up as Todd Meyrath’s AD9852 design. The functionality of the parallel to serial converter design has been veri ed through a physical breadboard test. Unfortunately, the exact components speci ed by the design were not available at the time and so substitutes of similar functionally were used instead. This did lead to some undesirable output, however it did not fully compromise the test. The di erence between the desired output and actual output was minor and easily predictable given the functionality of the devices as described in their datasheets. Twenty PCBs have been fabricated by Advanced Circuits and are now in the possession of the QDG lab. Enclosures for the devices were designed using eMachineShop’s proprietary software. The design is a modi cation of the previous generation AD9852 enclosure design. It is not conveniently compat- ible with the previous generation devices. Fifteen enclosures have been ordered from eMachineShop and are expected to arrive within two to three weeks of the submission of this report. Five rack mounting brackets have been ordered, each supporting up to eight DDS devices. The rack mounting brackets have already been fabricated and at time of writing are in transit. At time of writing, the PHAS electronics shop was in the process of assembling a single prototype device. The device is expected to be complete within two or three days of the submission of this report. Our team provided them with all necessary parts1 and assembly instructions. Since the prototype device was not complete at time of writing, no testing has been done. As such, no claims are made regarding the actual functionality and performance of the device. Our team intends to test the prototype device and either verify correct basic operation or identify any serious issues. Part II to this report will document testing procedures, testing results and all recommendations. It will be submitted January 9, 2012. 1With the exception of ferrite beads. 294 Project Deliverables At time of writing, a single PCB is in the PHAS electronics shop being assembled. The board is expected to be complete during the week of January 9, 2012. Our team will test the device in order to verify correct basic operation of the device or detect any serious issues. No extensive performance characterization will be performed. A Part II to this report will be submitted on January 20, 2012, documenting the testing procedures, the results and all recommendations. 4.1 List of Deliverables The following is a list of the deliverables given in the original proposal for this project, Proposal to Construct a Direct Digital Synthesizer. The description of each deliverable is copied verbatim. For each deliverable the current state is described.  The results of the SPICE simulation of the low-pass  lter. In particular, a plot showing the transfer function of the circuit will be provided. { The simulation is complete and shows that the  lter should work as desired. { The design was borrowed from the design given for the AD9912 evaluation board, Rev. B. { Electronic copies of the  les used for testing and the results will be provided.  Schematic diagram of the DDS device and a full parts list. { The schematics are complete and all parts have been chosen and sourced. { Electronic copies of the schematics, parts list and a working Bill of Materials will be provided electronically.  PCB layout of the DDS device. { The PCB layout is complete and has been used to build a PCB with no issues during manufacturing. { The PCBs will be left in the drawer the QDG lab has provided for DDS parts.  Detailed description of testing procedures and results. Performance of the device will be quanti ed wherever possible. { The testing has not yet been completed due to time constraints. { An assembled board should be received on January 9, 2012 and testing will begin then. { Details of testing procedures and results will follow this report in a Part II.  The functioning prototype device. 304. PROJECT DELIVERABLES 31 { The prototype device is expected to be received the week of January 9, 2012. { Once testing is complete, the prototype device will be left in the DDS board drawer in the QDG lab.  Modi ed enclosure design, if required. { Enclosures for the devices were designed. { The design is a modi cation of the previous generation AD9852 enclosure design and is not conveniently compatible with the previous generation design. { Fifteen enclosures as well as rack mounting brackets have been ordered from eMachi- neShop and are expected to arrive within two to three weeks of the submission of this report.  Eight or more  nished DDS devices, ready for integration into the QDG labs electronic exper- iment control system. { Due to time constraints, this milestone was not and will not be accomplished as part of this ENPH 479 project.  Engineering recommendation report. { This document, submitted January 9, 2012, is the Engineering recommendation report. 4.2 Financial Summary See Table 4.2 for a brief  nancial summary of the project. See Table 4.2 for a breakdown of the enclosure costs. Table 4.1: Summary of costs associated with this project. Enclosure costs do not include front panels. Extra PCBs were ordered since the marginal cost is very low. The evaluation board was ordered because it should be a useful benchmark during performance characterization. Description Quantity Vendor Unit Cost Total Cost PCBs 20 Advanced Circuits $44.92 $898.30 Enclosures 15 eMachineShop $60.59 $908.85 AD9912 15 Analog Devices $50 $750 Other Components 15 sets Newark, Mousser, Digikey $43.35 $650.26 Evaluation Board 1 Analog Devices $500 $500 Table 4.2: DDS Enclosure Costs. All parts were ordered from eMachineShop. Note that only 2 of 5 front panels are intended for the AD9912 DDS devices. Description Quantity Unit Cost Total Cost Lid 15 $10.87 $163.05 Enclosures 15 $49.72 $745.73 Front Panels 5 $67.29 $336.47References [1] Advanced Layout Solutions, Ltd., Control Impedance. 2009. [2] Analog Devices CMOS 300 MSPS Complete DDS, Analog Devices 9852. 2007. [3] Analog Devices, Analog Devices 9912 1 GSPS Direct Digital Synthesizer with 14 Bit DAC. 2010. [4] Analog Devices, AD9912 Evaluation Board, Rev.0. 2008. [5] Analog Devices, Microstrip and Stripline Design. 2009. [6] Douglas Brooks, Di erential Impedance. Miller Freeman, 1998. [7] Keith Ladouceur, Experimental Advances toward a Compact Dual-Species Laser Cooling Appa- ratus. 2008. [8] Sanaz Footohi, Control System of Quantum Degenerate Gases Laboratory. 2006. [9] Todd P. Meyrath, Digital RF Synthesizer: DC to 135 MHz. 2005. [10] Texas Instruments, PCB Design Guidelines For Reduced EMI. November 1999. 32Appendix A Schematic Diagrams This section contains the full schematic diagrams for the DDS circuit. Altium Designer was used to create these  gures. 1 1 2 2 3 3 4 4 D D C C B B A A FDBK_INB FDBK_IN OUT_CMOS OUTB OUT DAC_OUTB DAC_OUT SYSCLK SYSCLKB SCLK CSB SDIO S[4..1] U_DDS_IC DDS_IC.SchDoc FDBK_INB FDBK_IN OUT_CMOS OUTB OUT DAC_OUTB DAC_OUT U_Analog Analog.SchDoc CSB SDIOSCLK S[4..1]BRDSel U_Digital Digital.SchDoc SYSCLK SYSCLKB SCLKSCLK_EN U_CLK CLK.SchDoc U_Power Power.SchDoc Clock Digital DDS Analog Power Figure A.1: Schematic diagram, top level. Top Level.SchDoc 33APPENDIX A. SCHEMATIC DIAGRAMS 34 1 1 2 2 3 3 4 4 D D C C B B A A SYSCLK SYSCLKB R7 25 R9 25 R8 25 (OPT) C53 0.1uF C54 0.1uF 1 34 5 T3 ETC1-1-13 GND SCLK GND GND EN1 GND2 OUT 3 VDD 4 U2 TXC 7C GND VDD_DGT Serial Input Clock Primary Clock J1 SCLK_IN GND W1 0 1 3 X1 25MHz (OPT) W11 0 W12 0 C48 10pF C51 10pF GND GND Refer to crystal data sheet for capacitor values (C48 & C51). Clock Oscillator (~25MHz) Input BNC for Testing GND W4 0 SCLK_EN W6 0 SYSCLK_N SYSCLK_P J5 SYSCLK_IN W5 0 VDD_DGT R14 25 (OPT) GND Refer to AD9912 data sheet for a list of compatible crystal oscillators. PIC4801 PIC4802 COC48 PIC5101 PIC5102 COC51 PIC5301 PIC5302 COC53 PIC5401 PIC5402 COC54 PIJ101 PIJ102 COJ1 PIJ501 PIJ502 COJ5 PIR701 PIR702 COR7 PIR801 PIR802 COR8 PIR901 PIR902 COR9 PIR1401 PIR1402 COR14 PIT301 PIT303PIT304 PIT305 COT3 PIU201 PIU202 PIU203 PIU204 COU2 PIW101 PIW102 COW1 PIW401PIW402 COW4 PIW501PIW502 COW5 PIW601PIW602 COW6 PIW1101PIW1102 COW11 PIW1201PIW1202 COW12 PIX101 PIX103 COX1 PIX102PIX104 POSCLK POSCLK0EN NLSYSCLK0N POSYSCLK NLSYSCLK0P POSYSCLKB Figure A.2: Schematic diagram, clocks. CLK.SchDocAPPENDIX A. SCHEMATIC DIAGRAMS 35 1 1 2 2 3 3 4 4 D D C C B B A A 12 34 56 78 910 1112 1314 1516 1718 1920 2122 2324 2526 2728 2930 3132 3334 3536 3738 3940 4142 4344 4546 4748 4950 P2 Header 25X2 GND DAT[15..0] ADR[7..0] CSB SDIO DAT[15..0] SH/LD SC LK SZ U_Par2Ser Par2Ser.SchDoc CSB SDIO STROBE 50-Pin Molex Header (UTBus) S[4..1]S[4..1] ADR1 ADR0 ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 DAT0 DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7 DAT8 DAT9 DAT10 DAT11 DAT12 DAT13 DAT14 DAT15 S1 S2 S3 S4 AD9912 Startup Config. Parallel to Serial Data Converter R21 10K VDD_DGT R22 10K R23 10K R24 10K GND SCLK SH/LD STROBE ADR[7..2] SC LK BRDSel U_BoardSel BoardSel.SchDoc ADR[7..2] Board Select Address Buss Functionality: ADR[7..2]    Board address. In order for the strobe to be recognized, this must match the board address set with the DIP switch. ADR1:    Low => 16-bit data transfer    High => 8-bit data transfer, DAT[15..8] ignored ADR0:   Unused 7 8 9 10 177 8 9 10 18 19 20 SW1B SDA10H0KD BRDSel CSB PIP201PIP202 PIP203PIP204 PIP205PIP206 PIP207PIP208 PIP209PIP2010 PIP2011PIP2012 PIP2013PIP2014 PIP2015PIP2016 PIP2017PIP2018 PIP2019PIP2020 PIP2021PIP2022 PIP2023PIP2024 PIP2025PIP2026 PIP2027PIP2028 PIP2029PIP2030 PIP2031PIP2032 PIP2033PIP2034 PIP2035PIP2036 PIP2037PIP2038 PIP2039PIP2040 PIP2041PIP2042 PIP2043PIP2044 PIP2045PIP2046 PIP2047PIP2048 PIP2049PIP2050 COP2 PIR2101 PIR2102 COR21 PIR2201 PIR2202 COR22 PIR2301 PIR2302 COR23 PIR2401 PIR2402 COR24 PISW107 PISW108 PISW109 PISW1010 PISW1017 PISW1018 PISW1019 PISW1020 COSW1B POBRDSel NLCSB POCSB POSCLK POSDIO NLSTROBE NLADR070000 NLADR0 NLADR1 NLADR070020 NLADR2 NLADR3 NLADR4 NLADR5 NLADR6 NLADR7 NLDAT0150000 NLDAT0 NLDAT1 NLDAT2 NLDAT3 NLDAT4 NLDAT5 NLDAT6 NLDAT7 NLDAT8 NLDAT9 NLDAT10 NLDAT11 NLDAT12 NLDAT13 NLDAT14 NLDAT15 NLS040010 NLS1 POS040010 NLS2 NLS3 NLS4 POBRDSEL POS1234 Figure A.3: Schematic diagram, digital.APPENDIX A. SCHEMATIC DIAGRAMS 36 1 1 2 2 3 3 4 4 D D C C B B A A SH/LD R15 10K VDD_DGT OE1 P02 Q03 P14 Q15 P26 Q27 P38 Q39 GND10 P411 Q412 P513 Q514 P615 Q616 P717 Q718 P=Q 19 VCC 20 U1 SN74HC688DW GND GND Board Address Comparator GND Board Address DIP Switch Byte Comparator R16 10K R17 10K R18 10K R19 10K R20 10K ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 GND STROBE ADR[7..2] SCLK SCLK ADR[7..2] This active-low output will stay low for one period of SCLK after a 0-to-1 transistion on STROBE, if the board address matches. VDD_DGT 4 CLK3 D2 1 Q 5 Q 6CLR PR U3A SN74HC74D 10 CLK11 D12 13 Q 9 Q 8CLR PR U3B SN74HC74D 1 11 2 3 4 5 6 12 13 14 15 16 1 2 3 4 5 6 SW1A SDA10H0KD 4 CLK3 D2 1 Q 5 Q 6CLR PR U4A SN74HC74D VDD_DGT VDD_DGTVDD_DGT VDD_DGT VDD_DGT CLR and PRE are active-low asychronous clear and preset pins. 10 CLK11 D12 13 Q 9 Q 8CLR PR U4B SN74HC74D VDD_DGT VDD_DGT GND GND BRDSel Board Select Can be used to turn the clock oscillator on or off. Unused flip-flop PIR1501 PIR1502 COR15 PIR1601 PIR1602 COR16 PIR1701 PIR1702 COR17 PIR1801 PIR1802 COR18 PIR1901 PIR1902 COR19 PIR2001 PIR2002 COR20 PISW101 PISW102 PISW103 PISW104 PISW105 PISW106 PISW1011 PISW1012 PISW1013 PISW1014 PISW1015 PISW1016 COSW1A PIU101 PIU102 PIU103 PIU104 PIU105 PIU106 PIU107 PIU108 PIU109 PIU1010 PIU1011 PIU1012 PIU1013 PIU1014 PIU1015 PIU1016 PIU1017 PIU1018 PIU1019 PIU1020 COU1 PIU301 PIU302 PIU303 PIU304 PIU305 PIU306 COU3A PIU308 PIU309 PIU3010 PIU3011 PIU3012 PIU3013 COU3B PIU401 PIU402 PIU403 PIU404 PIU405 PIU406 COU4A PIU408 PIU409 PIU4010 PIU4011 PIU4012 PIU4013 COU4B PIU307 PIU407 POBRDSel POSH0L\D\ POSTROBE NLSCLKPOSCLK PIU3014 PIU4014 NLADR070020 NLADR2 POADR070020 NLADR3 NLADR4 NLADR5 NLADR6 NLADR7 POADR234567 POBRDSEL Figure A.4: Schematic diagram,  ip- ops and board select comparator.APPENDIX A. SCHEMATIC DIAGRAMS 37 1 1 2 2 3 3 4 4 D D C C B B A A GND GND VDD_DGT VDD_DGT CSB SDIO DAT[15..0] SH/LD GND VDD_DGT VDD_DGT GND DAT[15..0] GND VDD_DGT SH/LD SCLK SCLK DAT0 DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7 DAT8 DAT9 DAT10 DAT11 DAT12 DAT13 DAT14 DAT15 GND VDD_DGT SCLK SZ SZ = 0 for 16-bit transfer SZ = 1 for 8-bit transfer GND VDD_DGT SCLK GND VDD_DGT SCLK GND VDD_DGT SCLK SZ 8-Bit Shift Reg. 8-Bit Shift Reg. 8-Bit Shift Reg. 8-Bit Shift Reg. SH/LD SH/LD SH/LD SH/LD CLR9 S/L15 CLK INH6 CLK7 SI1 A2 B3 C4 D5 E10 F11 G12 H14 QH 13 VCC 16 GND8 U7 SN74HC166D CLR9 S/L15 CLK INH6 CLK7 SI1 A2 B3 C4 D5 E10 F11 G12 H14 QH 13 VCC 16 GND8 U9 SN74HC166D CLR9 S/L15 CLK INH6 CLK7 SI1 A2 B3 C4 D5 E10 F11 G12 H14 QH 13 VCC 16 GND8 U8 SN74HC166D CLR9 S/L15 CLK INH6 CLK7 SI1 A2 B3 C4 D5 E10 F11 G12 H14 QH 13 VCC 16 GND8 U5 SN74HC166D PIU501 PIU502 PIU503 PIU504 PIU505 PIU506 PIU507 PIU508 PIU509 PIU5010 PIU5011 PIU5012 PIU5013 PIU5014 PIU5015 PIU5016 COU5 PIU701 PIU702 PIU703 PIU704 PIU705 PIU706 PIU707 PIU708 PIU709 PIU7010 PIU7011 PIU7012 PIU7013 PIU7014 PIU7015 PIU7016 COU7 PIU801 PIU802 PIU803 PIU804 PIU805 PIU806 PIU807 PIU808 PIU809 PIU8010 PIU8011 PIU8012 PIU8013 PIU8014 PIU8015 PIU8016 COU8 PIU901 PIU902 PIU903 PIU904 PIU905 PIU906 PIU907 PIU908 PIU909 PIU9010 PIU9011 PIU9012 PIU9013 PIU9014 PIU9015 PIU9016 COU9 POCSB POSDIO NLSCLKPOSCLK NLSH0L\D\POSH0L\D\ NLSZPOSZ NLDAT0150000 NLDAT0 PODAT0150000 NLDAT1 NLDAT2 NLDAT3 NLDAT4 NLDAT5 NLDAT6 NLDAT7 NLDAT8 NLDAT9 NLDAT10 NLDAT11 NLDAT12 NLDAT13 NLDAT14 NLDAT15 PODAT0123456789PODAT1 Figure A.5: Schematic diagram, parallel-to-serial converter.APPENDIX A. SCHEMATIC DIAGRAMS 38 1 1 2 2 3 3 4 4 D D C C B B A A AVDD_211 AVDD_319 AVDD_423 AVDD_536 AVDD_624 AVDD_742 AVDD_825 AVDD_944 AVDD_1026 AVDD_1145 AVDD_1229 AVDD_1353 AVDD30 AVDD3_237 AVDD3_314 AVDD3_446 AVDD3_547 AVDD349 AVSS_233 AVSS_339 AVSS_443 AVSS52 DVDD_23 DVDD_35 DVDD7 DVDD_I/O1 DVSS_22 DVSS_34 DVSS_46 DVSS_58 DVSS_656 DVSS57 S19 S210 S354 S455 SDIO63 SDO62 PWRDOWN 58 DAC_OUT 50 DAC_OUTB 51 DAC_RSET 48 OUT 35 OUTB 34 OUT_CMOS 38 LOOP_FILTER 31 IO_UPDATE 60 CSB 61 FDBK_IN 41 FDBK_INB 40 RESET 59 CLKMODESEL 32 SYSCLK 27 SCLK 64 SYSCLKB 28 EP 65 NC_2 12 NC_3 13 NC_4 15 NC_5 16 NC_6 17 NC_7 18 NC_8 20 NC_9 21 NC 22 U6 AD9912 R28 10K FDBK_INB FDBK_IN OUT_CMOS OUTB OUT DAC_OUTB DAC_OUT GND GND GND GND GND GND GND GND GND GND GND AVDD_1 VDD_SYSCLK_2 VDD_SYSCLK_2 VDD_SYSCLK_1 VDD_DACDEC VDD_CMOS VDD_SIO VDD_DAC3 VDD_DAC3 VDD_DAC3 DVDD DVDD DVDD VDD_SIO SYSCLK SYSCLKB SCLK GND R3 OPT (1K) W9 0 W10 0 R4 2.2K C45 10pF C46 180pF S[4..1] CSB SDIO R29 510 W16 0 W15 0 GND CRYSTAL GNDS1 S2 S3 S4 S[4..1] Startup Config. Pins IO Pin Summary: All are 3.3V CMOS IO_UPDATE (active high, internal 50k pull-down resistor) RESET (active high, ground with 10k resistor if not used) PWRDOWN (active high, internal 50k pull-down resistor) CSB (active low, internal 100k pull-up resistor) SDO SDIO SCLK (internal 50k pull-down resistor) R26 10K GND These pins are part of the fanout and are connected to vias to allow easier probing, but are otherwise unconnected: IO_UPDATE PWRDOWN RESET SDO GND SDIO SDO PWRDOWN LOOP_FILTER IO_UPDATE CLKMODESEL RESET R27 10K GND R25 10K DAC_RSET VDD_SYSCLK_1 AVDD_1 AVDD_1 AVDD_1 AVDD_2 AVDD_2 AVDD_2 AVDD_2 VDD_SYSCLK_2 AVDD The loop filter component values shown above (R4, C45 and C46) depend on the PLL multiplier used and should be chosen accordingly (see Table 6 of the AD9912 datasheet). Values shown are appropriate for the default multiplier (40). EXTERNAL CLOCK OR OSCILLATOR PIC4501 PIC4502 COC45 PIC4601 PIC4602 COC46 PIR301 PIR302 COR3 PIR401PIR402 COR4 PIR2501 PIR2502 COR25 PIR2601 PIR2602 COR26 PIR2701 PIR2702 COR27 PIR2801 PIR2802 COR28 PIR2901 PIR2902 COR29 PIU601 PIU602 PIU603 PIU604 PIU605 PIU606 PIU607 PIU608 PIU609 PIU6010 PIU6011 PIU6012 PIU6013 PIU6014 PIU6015 PIU6016 PIU6017 PIU6018 PIU6019 PIU6020 PIU6021 PIU6022 PIU6023 PIU6024 PIU6025 PIU6026 PIU6027 PIU6028 PIU6029 PIU6030 PIU6031 PIU6032 PIU6033 PIU6034 PIU6035 PIU6036 PIU6037 PIU6038 PIU6039 PIU6040 PIU6041 PIU6042 PIU6043 PIU6044 PIU6045 PIU6046 PIU6047 PIU6048 PIU6049 PIU6050 PIU6051 PIU6052 PIU6053 PIU6054 PIU6055 PIU6056 PIU6057 PIU6058 PIU6059 PIU6060 PIU6061 PIU6062 PIU6063 PIU6064 PIU6065 COU6 PIW901 PIW902 COW9 PIW1001PIW1002 COW10 PIW1501 PIW1502 COW15 PIW1601 PIW1602 COW16 NLCLKMODESEL NLDAC0RSET NLIO0UPDATE NLLOOP0FILTER POSYSCLK POSYSCLKB POOUTB POOUT POOUT0CMOS POFDBK0INB POFDBK0IN PODAC0OUT PODAC0OUTB POCSB POSCLK NLPWRDOWN NLRESET NLSDIOPOSDIO NLSDO NLS040010 NLS1 POS040010 NLS2 NLS3 NLS4 POS1234 Figure A.6: Schematic diagram, AD9912.APPENDIX A. SCHEMATIC DIAGRAMS 39 1 1 2 2 3 3 4 4 D D C C B B A A 1 2 3 P1 GND 5VGND EN1 IN2 G N D 3 Out 4 Bypass 5 UP1 TPS78618 EN1 IN2 G N D 3 Out 4 Bypass 5 UP3 TPS78618 EN1 IN2 G N D 3 Out 4 Bypass 5 UP4 TPS78633 GND GND C59 0.1uF C57 0.01uF 5V GND C6 0.1uF C8 0.01uF 5V GND C56 0.1uF C58 0.01uF 5V EN1 IN2 G N D 3 Out 4 Bypass 5 UP2 TPS78633 GND C7 0.1uF C9 0.01uF 5V AVDD AVDD3DVDD 5V Molex Connector Analog 1.8V Analog 3.3V Digtal 3.3V Digital 1.8V 470uF C64 T491X 10uF C50 T491B 10uF C52 T491B 10uF C3 T491B 10uF C5 T491B 10uF C2 T491B 10uF C4 T491B 10uF C65 T491B 10uF C62 T491B DVDD3 U_Power2 Power2.SchDoc Power2 Bypass Capacitors and Ferrite Beads PIC201 PIC202 COC2 PIC301 PIC302 COC3PIC401 PIC402 COC4 PIC501 PIC502 COC5 PIC601 PIC602 COC6 PIC701 PIC702 COC7 PIC801 PIC802 COC8 PIC901 PIC902 COC9 PIC5001 PIC5002 COC50 PIC5201 PIC5202 COC52 PIC5601 PIC5602 COC56 PIC5701 PIC5702 COC57 PIC5801 PIC5802 COC58 PIC5901 PIC5902 COC59 PIC6201 PIC6202 COC62 PIC6401 PIC6402 COC64 PIC6501 PIC6502 COC65 PIP101 PIP102 PIP103 COP1 PIUP101 PIUP102 PIUP103 PIUP104 PIUP105 COUP1 PIUP201 PIUP202 PIUP203 PIUP204 PIUP205 COUP2 PIUP301 PIUP302 PIUP303 PIUP304 PIUP305 COUP3 PIUP401 PIUP402 PIUP403 PIUP404 PIUP405 COUP4 PIUP106 PIUP206 PIUP306PIUP406 Figure A.7: Schematic diagram, power 1 (voltage regulators).APPENDIX A. SCHEMATIC DIAGRAMS 40 1 1 2 2 3 3 4 4 D D C C B B A A AVDD VDD_DAC3 AVDD3 VDD_DACDEC DVDD DVDD3VDD_SIO Local Nets Main Net Analog 1.8V Analog 3.3V Digtal 3.3V Digital 1.8VDVDD VDD_DGT AD9912 Digital Input Logic C31 0.1uF DVDD3 GND C49 0.1uF C1 0.1uF C40 0.1uF C47 0.1uF C10 0.1uF C11 0.1uF C12 0.1uF DVDD GND C28 0.1uF AVDD3 GND C33 0.1uF GND C36 0.1uF C27 0.1uF C26 0.1uF C38 0.1uF C37 0.1uF C30 0.1uF C29 0.1uF C32 0.1uF C39 0.1uF C44 0.1uF C20 0.1uF VDD_DACDEC GND C25 0.1uF C34 0.1uF DVDD3 GND C41 0.1uF C43 0.1uF C42 0.1uF C66 0.1uF C35 0.1uF C67 0.1uF F1 Ferrite bead VDD_SYSCLK_1 F6 Ferrite bead F5 Ferrite bead F2 Ferrite bead AVDD_1 VDD_CMOS VDD_SYSCLK_1 GNDGND Pins 26, 29 & loop filter Pins 25 & 30 Pin 53 Pin 36 Pins 3, 5 & 7 Pins 1 & 14 Pins 46, 47 & 49 Pins 11, 19, 23 & 24 AVDD_1 1206 footprint for logic IC bypass caps (these are shown in the top row: C31,C49,...,C12) 0402 footprint for AD9912 bypass caps AVDD_2 F3 Ferrite bead Pins 36, 42, 44 & 45 VDD_SYSCLK_2 F4 Ferrite bead All ICs except AD9912 W14 0 GND AVDD_2 VDD_SYSCLK_2 VDD_CMOS GND Power Isolation Diagram Bypass Capacitors 0805 footprint for all ferrite beads and W14 PIC101 PIC102 COC1 PIC1001 PIC1002 COC10 PIC1101 PIC1102 COC11 PIC1201 PIC1202 COC12 PIC2001 PIC2002 COC20 PIC2501 PIC2502 COC25 PIC2601 PIC2602 COC26 PIC2701 PIC2702 COC27 PIC2801 PIC2802 COC28 PIC2901 PIC2902 COC29 PIC3001 PIC3002 COC30 PIC3101 PIC3102 COC31 PIC3201 PIC3202 COC32 PIC3301 PIC3302 COC33 PIC3401 PIC3402 COC34 PIC3501 PIC3502 COC35 PIC3601 PIC3602 COC36 PIC3701 PIC3702 COC37 PIC3801 PIC3802 COC38 PIC3901 PIC3902 COC39 PIC4001 PIC4002 COC40 PIC4101 PIC4102 COC41 PIC4201 PIC4202 COC42 PIC4301 PIC4302 COC43 PIC4401 PIC4402 COC44 PIC4701 PIC4702 COC47 PIC4901 PIC4902 COC49 PIC6601 PIC6602 COC66 PIC6701 PIC6702 COC67 PIF101PIF102 COF1 PIF201PIF202 COF2 PIF301PIF302 COF3 PIF401PIF402 COF4 PIF501PIF502 COF5 PIF601PIF602 COF6 PIW1401PIW1402 COW14 Figure A.8: Schematic diagram, power 2 (bypass capacitors and ferrite beads).APPENDIX A. SCHEMATIC DIAGRAMS 41 1 1 2 2 3 3 4 4 D D C C B B A A RF_IN RF_OUT U_Reconstruction Filter Reconstruction Filter.SchDoc 1 2 34 5 6 T1 ADT2-1T-1P+ 1 2 34 5 6 T2 ADT2-1T-1P+ R5 100 R1 OPT R2 OPT GND GND J2 DUT OUT/FILTER IN W2 0 W7 0 J3 DUT FILTER OUT W8 0 J4 FDBK_IN J8 OUT J7 OUTB R11 1K R13 10K R12 10K R10 10K R6 10K C61 10nF C60 10nF C55 0.1uF GND GND GND J6 CMOS OUT W13 0 C63 OPT FDBK_INB FDBK_IN OUT_CMOS OUTB OUT DAC_OUTB DAC_OUT RF Transformer RF Transformer GND GND GND GND GND GND GND GND DAC_OUT_N DAC_OUT_P FDBK_IN_P FDBK_IN_N OUT_P OUT_N OUT_CMOS OUT OUTB FILT_IN FILT_OUT FDBK_IN W3 0 PIC5501PIC5502 COC55 PIC6001 PIC6002 COC60 PIC6101 PIC6102 COC61 PIC6301 PIC6302 COC63 PIJ201 PIJ202 COJ2 PIJ301 PIJ302 COJ3 PIJ401 PIJ402 COJ4 PIJ601 PIJ602 COJ6 PIJ701 PIJ702 COJ7 PIJ801 PIJ802 COJ8 PIR101 PIR102 COR1 PIR201 PIR202 COR2 PIR501 PIR502 COR5 PIR601 PIR602 COR6 PIR1001 PIR1002 COR10 PIR1101 PIR1102 COR11 PIR1201 PIR1202 COR12 PIR1301 PIR1302 COR13 PIT101 PIT102 PIT103PIT104 PIT105 PIT106 COT1 PIT201 PIT202 PIT203PIT204 PIT205 PIT206 COT2 PIW201 PIW202 COW2 PIW301 PIW302 COW3 PIW701 PIW702 COW7 PIW801 PIW802 COW8 PIW1301 PIW1302 COW13 NLDAC0OUT0NPODAC0OUT NLDAC0OUT0PPODAC0OUTB NLFDBK0IN NLFDBK0IN0NPOFDBK0IN NLFDBK0IN0PPOFDBK0INB NLFILT0IN NLFILT0OUT NLOUT NLOUT0CMOSPOOUT0CMOS NLOUT0NPOOUTB NLOUT0PPOOUT NLOUTB Figure A.9: Schematic diagram, analog.APPENDIX A. SCHEMATIC DIAGRAMS 42 1 1 2 2 3 3 4 4 D D C C B B A A RF_IN RF_OUT C13 5.6pF L1 18nH C15 2.7pF C18 1.0pF C14 2.7pF C16 5.6pF C17 6.8pF C19 3.9pF C21 2.7pF C22 5.6pF C23 6.8pF C24 3.9pF L2 22nH L3 27nH GND GND GND GND GND GND GND GND 400MHz 7th Order Elliptic Low-Pass Filter 0402 footprint for all components shown here PIC1301 PIC1302 COC13 PIC1401 PIC1402 COC14 PIC1501 PIC1502 COC15 PIC1601 PIC1602 COC16 PIC1701 PIC1702 COC17 PIC1801 PIC1802 COC18 PIC1901 PIC1902 COC19 PIC2101 PIC2102 COC21 PIC2201 PIC2202 COC22 PIC2301 PIC2302 COC23 PIC2401 PIC2402 COC24 PIL101 PIL102 COL1 PIL201 PIL202 COL2 PIL301 PIL302 COL3 PORF0IN PORF0OUT Figure A.10: Schematic diagram, reconstruction  lter.Appendix B PCB Fabrication Drawings This section contains printouts generated from the Gerber  les used for PCB fabrication. These  les, along with hole/via drilling information provide the PCB manufacturer with most of the information needed to construct the boards. Unless noted in the caption, the Gerber  les shown are positive, meaning that dark areas indicate that material should be present (either copper, the insulating soldermasks or the silkscreens). The ground and power plane  les are negative, meaning that dark areas indicate that material should be removed. Figure B.1: Fabrication Drawings, top copper layer. 43APPENDIX B. PCB FABRICATION DRAWINGS 44 Figure B.2: Fabrication Drawings, ground plane (negative). Figure B.3: Fabrication Drawings, power plane (negative).APPENDIX B. PCB FABRICATION DRAWINGS 45 Figure B.4: Fabrication Drawings, bottom copper layer. Figure B.5: Fabrication Drawings, top silkscreen.APPENDIX B. PCB FABRICATION DRAWINGS 46 Figure B.6: Fabrication Drawings, bottom silkscreen. Figure B.7: Fabrication Drawings, top soldermask.APPENDIX B. PCB FABRICATION DRAWINGS 47 Figure B.8: Fabrication Drawings, bottom soldermask. Figure B.9: Fabrication Drawings, drill drawing.Appendix C 3D PCB Renderings This section contains 3D renderings of the top and bottom of the PCB. Altium Designer was used to create these  gures. Figures C.1 and C.2 use a somewhat realistic colour scheme. Figure C.1: 3D Rendering of the DDS, top view. Created using Altium Designer. 48APPENDIX C. 3D PCB RENDERINGS 49 Figure C.2: 3D Rendering of the DDS, bottom view. Created using Altium Designer.APPENDIX C. 3D PCB RENDERINGS 50 Figure C.3: 3D Rendering of the DDS, angled view. Created using Altium Designer.Appendix D PCB Parts List Table D.1: Bill of Materials Comment Description Footprint Designator 0.1 F Capacitor 1206 C1, C6, C7, C10, C11, C12, C31, C40, C47, C49, C56, C59 T491B Solid Tantalum Chip Capacitor, Standard T491 Series - Industrial Grade B C2, C3, C4, C5, C50, C52, C62, C65 0.01 F Capacitor 1206 C8, C9, C57, C58 5.6pF Capacitor 0402 C13, C16, C22 2.7pF Capacitor 0402 C14, C15, C21 6.8pF Capacitor 0402 C17, C23 1.0pF Capacitor 0402 C18 3.9pF Capacitor 0402 C19, C24 0.1 F Capacitor 0402 C20, C25, C26, C27, C28, C29, C30, C32, C33, C34, C35, C36, C37, C38, C39, C41, C42, C43, C44, C66, C67 10pF Capacitor 0402 C45, C48, C51 180pF Capacitor 0402 C46 0.1 F Capacitor 0402 C53, C54, C55 10nF Capacitor 0402 C60, C61 OPT Capacitor 1206 C63 T491X Solid Tantalum Chip Capacitor, Standard T491 Series - Industrial Grade X C64 Ferrite bead Ferrite Bead 0805 F1, F2, F3, F4, F5, F6 SCLK IN BNC Elbow Connector BCN Pads J1 51APPENDIX D. PCB PARTS LIST 52 Comment Description Footprint Designator DUT OUT/FILTER IN BNC Elbow Connector BCN Pads J2 DUT FIL- TER OUT BNC Elbow Connector BCN Pads J3 FDBK IN BNC Elbow Connector BCN Pads J4 SYSCLK IN BNC Elbow Connector BCN Pads J5 CMOS OUT BNC Elbow Connector BCN Pads J6 OUTB BNC Elbow Connector BCN Pads J7 OUT BNC Elbow Connector BCN Pads J8 18nH Inductor 0402 L1 22nH Inductor 0402 L2 27nH Inductor 0402 L3 70543-0107 Header, 3-Pin Power Header P1 Header 25X2 N2550-5002RB UTBUS P2 50 Resistor 0402 R1, R2 1k Resistor 0402 R3 2.2k Resistor 0402 R4 100 Resistor 0402 R5 10k Resistor 0402 R6, R10, R12, R13 25 Resistor 0402 R7, R9 25 Resistor 0402 R8 1k Resistor 0402 R11 25 Resistor 1206 R14 10k Resistor 1206 R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28 510 Resistor 1206 R29 SDA10H0KD C&K SDA Series Low Pro le DIP Switches, 10 Pos DIPSW20 SW1 ADT2-1T- 1P+ 6-Pin Transformer CD542 T1, T2 ETC1-1-13 E-Series RF 1:1 Trans- mission Line Trans- former, 4.5-3000MHz SM22 T3 SN74HC688DW8-Bit Identity Com- parator DW020 M U1 TXC 7C TXC Clock Oscillator (SCLK) 4-pin SMD U2APPENDIX D. PCB PARTS LIST 53 Comment Description Footprint Designator SN74HC74D Dual D-Type Positive- Edge-Triggered Flip- Flop with Clear and Preset D014 N U3, U4 SN74HC166D 8-Bit Parallel-Load Shift Register D016 N U5, U7, U8, U9 AD9912 Direct Digital Synthe- sizer 64-pin SMD U6 TPS78618 Texas Instruments 5- Pin Voltage Regulator SOT223- 6M UP1, UP3 TPS78633 Texas Instruments 5- Pin Voltage Regulator SOT223- 6M UP2, UP4 0 Jumpers 1206 W1, W2, W3, W4, W5, W6, W7, W8, W13, W15, W16 0 Jumpers 0402 W9, W10, W11, W12 0 Jumpers 0805 W14 Fox HC49SDLF 25MHz Crystal Oscilla- tor (SYSCLK) 4-pin SMD X1

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