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A transistorized decoder for pulse code modulation Chang, Juang-Chi 1961

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A TRANSISTORIZED DECODER FOR PULSE CODE MODULATION  by  JUANG-CHI CHANG B.S., National Taiwan University, 1959  A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in the Department of E l e c t r i c a l Engineering We accept this thesis as conforming to the standards required from candidates f o r the degree of Master of Applied Science  Members of the Department of E l e c t r i c a l Engineering  THE UNIVERSITY OF BRITISH COLUMBIA August 1961  In p r e s e n t i n g the  t h i s thesis i n p a r t i a l fulfilment of  r e q u i r e m e n t s f o r an advanced degree a t t h e U n i v e r s i t y  British  Columbia, I agree t h a t the  a v a i l a b l e f o r reference  and  of  L i b r a r y s h a l l make i t f r e e l y  study.  I f u r t h e r agree t h a t  permission  f o r e x t e n s i v e copying o f t h i s t h e s i s f o r s c h o l a r l y purposes may g r a n t e d by  the  Head o f my  It i s understood t h a t f i n a n c i a l gain  Department  representatives.  copying or p u b l i c a t i o n of t h i s t h e s i s f o r  s h a l l not  be  a l l o w e d w i t h o u t my  of  The U n i v e r s i t y o f B r i t i s h Vancouver 8, Canada. Date  Department o r by h i s  be  {Upt^ttsjf /£",  Columbia,  /  /  written  permission.  i  ABSTRACT This t h e s i s i s concerned with the construction of a t r a n s i s t o r i z e d pulse code modulation decoder, the purpose of which i s to decode the d i g i t a l s i g n a l into the continuous analog form. The e a r l i e r part of t h i s t h e s i s describes the design and c o n s t r u c t i o n of a t r a n s i s t o r i z e d decoder using the c i r c u l a t e d pulse p r i n c i p l e .  This turned out to be not  too p r a c t i c a l . The l a t t e r part concerns the design and construction of a PCM decoder using a f e r r i t e - c o r e s h i f t r e g i s t e r . This design was s u c c e s s f u l .  The decoder has been tested  i n conjunction with the coder b u i l t by R.A.  Hafer,  TABLE OP CONTENTS  •Afc S "fc X £L C "fc XiXS*tr  o o o o a e s o o o o o v o o o o o o o o o o o o o o o o o o o o o o o o o  O f IXXllS"fcl*3f"fcX0IjlS  Ack.HO WX 0(1^0111611 "fc  Xo  Xll"trO(iU.C"t»l OR  o o o o e o o o o e o o o o o o o o o o o o e o o e  o o e o o o o o c o o o o o o o o o o o o o o o o a o o o o o o  o  o o o e o o o o o o o o o o o o o o o o o o o o o o o o o e o  2. Pulse Code Modulation Systems i n General.... 2.1 Coding o * } * o * « o o o o o o o o o o o o o o o o o o o o o o o o o o o o 2.2 Decoding .  0  0  O  O  0  O  O  O  O  0  0  O  0  O  0  O  O  O  0  0  O  0  0  0  0  0  0  0  O  6  O  0  2.3 Multiplexing and Repeating..... e o o o o o e o o 2.4 Synchronizing and Framing. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3. Organization of a Particular PCM System... 3.1 Arrangement of the Coder  o . o . . . o . . o . . « .  3.2 Arrangement of the Similar Decoder.... 4. The Decoder Using Circulating Pulses 0 0 0 0 0 0 0 4.1 Timing Pulse Generators' o o o o o o o o o o o o o a o o 4.2 Decoding C i r c u i t r y  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  *  0  0  0  0  0  4.2.1 The Summing C i r c u i t and the Charg Transfer Gate 0  0  0  0  0  0  0  0  0  0  0  0  0  0  *  0  0  0  *  4.2.2 Temporary Storage and Discharging Circuit.. o o o o o o e o o o o o o o o o o o o 4.2.3 Diode Gate and Compensating Pulse Generator 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4.2.4 Pulse Inverter, Current Amplifier and Subtracting Pulse Generator.. 4.3 Status of the Vork on t h i s Decoder o o e 4 0 3 o X AcL J US^H16n*t  0 o  o o « o o o © o « * o o o o « « o « o o o o o  4.3.2 Non-linearity Effect 4.3.3 I n s t a b i l i t y Effect' o o o o o o o o o o o o e o o  XIX  Page 4 . 4  5o  6 0  C OTIC X U S X 0 H o o o o o o o . o o o o o c o o o o o o o o o o . o o o o o o o o o o c o o  The S h i f t — R e g i s t e r  3 2  Decoderoooooooooooooooooooo.ocooo  3 4  5 d  General D e s c r i p t i o n of the Decoder...... > .. .<. 3 4  5a2  R e q u i r e m e n t s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  3 3  5 o 2 0X  R©  33  5 o 2 o 2  Synchronized  5 o2 o 3  FrEtlllXng o o o o o o e o o o o o o o o o o o o o o o o o o o o o o o o o o o o  l  P©  I  0  £L*ts 6 3 ^ o o o o o o o o o o o o o o o o e o o o o o o o o o o o o o o o o o  T i m i n g O O O O D O * O O O O « « O O O O O O O O O O  C i r c u i t s f o r the S h i f t - R e g i s t ©r  3 9  4 0  Decoder©0000*0000000  4 2  6 0 I The Repeater and the Emitter-Follower......»..,.. 4 2 6 . 2 The Slave O s c i l l a t o r and the D i f f e r e n t i a t o r . . . . . 4 4 6 o 3 The D r i v i n g Pulse Generator and the D r i v i n g Current Ge H6r8fi)Or 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 O  O  O  O  O  O  O  O  O  O  O  O  O  ©  4 6  6 . 4 Input Current Generator and the F e r r i t e - c o r e SllX jP"fc*~R© gX S "t e r o o o o o o o o o o o o o o o o o e o o o o o o o o o o o o o o o e 6 . 4 o l  The Design of the S h i f t - R e g i s t e r . ... . . ....  6 o 4 o 2  The Actual  C x r c u i * f c o o o o o o o o o o o o . o . « o o o . . « o o  4 9  4 9  63  6 . 5 The Adding C i r c u i t and the Emitter-Follower. .... 6 6 6 . 6 Ferrite-Core Counting C i r c u i t , FrequencyDivider Pulse Generator and the Framing C o n t r o l . 6 9 6 . 7 The T r a n s i s t o r Gate and the Output C i r c u i t . ..... 7 2 6<>8  F i l t e r and Equalizer  D e s i g n . . . o o o o . ° . . . o . . . . . . . .  7 4  7 . P u t t i n g the Decoder into Operation.................. 7 9 7 . 1 Adjustment of the C r i t i c a l Level of the Repeater 7 9 7 . 2 Adjustment of the Timing and Framing System..... 7 9 7 . 3 Adjustment of the Adding C i r c u i t . . . . . . . . . . . . . . . . 8 0 8•  Performance of the  S y s t e m o o o . o a . . . . a o o . . . . . . . . . . . . . .  8 . 1 S t a b i l i t y of the Timing System..................  81  81  8 . 2 L i n e a r i t y of the Goder plus Decoder............. 8 1  IV  8 o 2 o 1 Test Arrangement 8  9  o  10 o  C OnC  1\1  o 2 o 2  S X On  ite j f e r e n C  c « o o o o o  0  0  o o « o o e & o o o o e « © « o ©  Page 81  i i e S X l l " f c o * o o o o o o o o o o o o o o o 9 o o o o o o o o o o o « o o « o o o  82  o o o o » o < > © o o o o © o o o o o » o e © o o o o o o » o o o o o 6 o o  85  o o © ©  eS o  e  e a o o o o a o o o o o o o o o o o o o o o o o o o o o o o o o o e o f t o o o e  8T  LIST OF ILLUSTRATIONS  Page  Figure 2.1  Shannon and Rack D e c o d e r s . o o o o o . a o . . . . . 0 . 0 . 0 . 0 0 0  5  2.2  Decoding C i r c u i t Using Binary S h i f t - R e g i s t e r 0 .  5  2.3  Elementary Time Division Multiplex System.......  8  2.4  A Self—Txrood  8  3.1  Block Diagram of Coder Using Circulating Pulses.  11  3.2  Block Diagram of the Decoder Using Circulating •Pxil S 6 S t 0 0 0 0 0 0 e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  13  4.1  Block Diagram of the Timing Arrangement f o r the Decoder Using Circulating Pulses.... 0 . . . . . . . . . . .  16  4.2  Txmxng Waveformsoooooooooooooooooooooooooooo.oo.  16  4.3  Summing C i r c u i t and the Transistor Gate.........  18  4.4  Temporary Storage. Discharging C i r c u i t and Double Emitter—Follower... 0 0 0 . . . 0 . o . . . . . . o . . . « . '  18  R e p e a t e r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . 0 0 . 0 0 0 . . .  0 .  4.5  Diode Gate and Compensating Pulse Generator.....  21  4.6  Pulse Inverter, Current Amplifier and Subtracting Pulse G e n e r a t o r . 0 0 . o . . . . . . . . . . . . . . . .  21  4.7  Waveforms on the Summing Capacitor and the Temporary S t o r a g e . . 0 0 0 0 0 0 . o . o o o o . 0 0 0 0 . 0 0 0 . o . o o . o .  25  4.8  The Non-linearity Ef f ecto  26  o o o o . . . o o . . . o . a o o . o . . * < o  Variation of a with Respect to I . c 0 0 0 0 0 . o o o . 4.10 -Varxatxon of re with I_. c 4.9  .  27  o . . o o o o o o o o o « o  28  .  0  0  .  .  .  .  .  .  .  .  .  .  1  4.11 SxtuatXOn  O f  Htja  o o °  0  <  >  o  0  o o o o o  • '. 0 0 0 0 0 0 0 0 0 0 0 0 0  .-. . e  0  29  5.1  Block Diagram of the Successful Decoder.........  35  5.2  Waveform of the Timing  36  5.3  Block Diagram of a Line—Repeater......  S y s t e m . . » o . o o . . . . . . . o o . . .  0 . . 0 0 . . . . .  39  VI  6.1  Page The Repeater and the Emitter-Follower „ . ... ...... 4 3  6o2  The Slave O s c i l l a t o r and the D i f f e r e n t i a t o r . . . . . 4 5  6.3  Driving Pulse Generator and the Driving Current Generatoroooooooooooo-ooooooooooooooooooooooooooo 4 7  6 . 4  One-bit per Core Shif t-Registers.... . o o  6.5  Capacitor Voltage and I t s Energy Chart.......... 5 0  6 . 6  High Speed  6.7  Waveforms at the Corresponding Points of JP1 ££X1 re 6 © 6 (b)ooooooooooooooooo«oooooooooooooooo 58 The Capacitor Waveform and I t s Stored Energy Chart of Figure 6 . 7 (c)oo.oo.a.aa............... 5 9 Ferrite-Core Characteristics ( M C - 1 1 4 ) . . . . . . . . . . . 6 2  6.8 6 . 9  . . . . . .  .  Shift—Registers.......o.oo.....ooos«o  6 . 1 0 Input Current Generator and the Ferrite-Core Shift—Regxstero o . o o o o o o o o o o o o * © o o . . o o o © o . «  5 0  5 6  . © . . . •  6 4  6 . 1 1 Adding C i r c u i t and the Emitter-Follower......... 6 6 6 . 1 2 Ferrite-Core Counting C i r c u i t , Frequency Divider Pulse Generator and the Framing Control.......*. 6 8 6 . 1 3 Waveforms of the Frequency Divider Pulse Ge n e r & t o r 0 0 0 0 0 0 0 0 0 0 0 0 0  0 0 0 0 0 0 0  ooooooo«oo»oooooooo  7 0  6 . 1 4 Waveforms of the Ferrite-Core Counting C i r c u i t . . 7 0 6 . 1 5 Transistor Gate and the Output C i r c u i t . . . . . . . . . . 7 4 6 . 1 6  The Low Pass F i l t e r s .  6 . 1 7  Equalizer and  e o o . . o o o « « « o o o - o « . o . o « © o o . ' . o  Filter...............o..........o.  6 . 1 8 Curves f o r the F i l t e r a n d Equalizer Design...««.. 8 . 1 8 . 2  L i n e a r i t y Test Lxnearxty  7 5 7 5  7 8  Arrangement.......o..............  8 3  T e s t © o o . . o o o . . . o . © » « » o . . . « o . o « . • • . • • « « »  8 3  ACKNOWLEDGEMENTS Acknowledgement i s g r a t e f u l l y given to the National Research Council of Canada f o r a research assrstantship and f o r t h e i r sponsorship of t h i s p r o j e c t . The author wishes to acknowledge with gratitude the guidance of Professor P.K. Bowers, supervisor of the project.  He i s indebted to Dr. F. Noakes, grantee of the  p r o j e c t , and to the Faculty and S t a f f of the Department of E l e c t r i c a l Engineering f o r t h e i r generous assistance.  1.INTRODUCTION A complete information transmission system generally includes a transmitter, a transmission medium over whieh the information i s transmitted, and a receiver which produces at i t s output a recognizable  r e p l i c a of the input information.  In most communication work the information i s conveyed by modulating a sinusoidal signal called the c a r r i e r . a system there i s an accumulation  In such  of noise i n the  transmission medium. Therefore, i n the development of communication systems, much e f f o r t has been directed toward minimizing the effects of noise picked up i n the transmission medium. Methods of increasing the signal to noise r a t i o of the reproduced signal at the expense of increased band width i n the transmitting medium have been explored.  D i g i t a l pulse  (especially binary pulse) transmission offers attractive p o s s i b i l i t i e s f o r implementing such an exchange. Because of i t s simple c i r c u i t r y , the transmission of a binary pulse group i s becoming quite popular.  In the binary  pulse transmission, the receiver must merely recognize the absence or presence of a pulse, or the p o l a r i t y (plus or minus) of a pulse, and then decode into the o r i g i n a l quantized form to reconstruct the signal.  As long as the  noise i s limited to less than half the standard pulse height, the receiver w i l l be able to i d e n t i f y correctly the value sent and so can reconstruct the exact s i g n a l .  In a long  transmission system, each repeater can regenerate the transmitted signal exactly, thus removing any noise picked up i n  2 the transmission medium.  The quality of reproduction i s then  independent of the number of links i n the system. There are several methods of converting a continuous signal into binary form. and  another  One i s called pulse code modulation  i s called delta modulation.^"  For ~the same  bandwidthp the signal-to-noise r a t i o of the pulse code modulation system i s sometimes higher than that of delta modulation.  Besides, the exchange of the bandwidth and  signal-to-noise ratio i s much more f l e x i b l e i n PCM* than i n delta modulation. However, a pulse code modulation scheme i s rather d i f f i c u l t to b u i l d , f o r both the coder and the decoder are r e l a t i v e l y complicated.  Many types of pulse code modulation  systems have been b u i l t using vacuum tubes.^ *° ^  2 As indicated i n the ESSEX  project of the B e l l Tele-  phone Laboratory, the PCM time-division communication  has  become increasingly interesting i n recent years because of the a v a i l a b i l i t y of high-speed, solid-state devices, such as transistors and semiconductor diodes.  Thus, the development  of PCM terminal equipment using solid-state devices i s quite topical.  B.A. Hafer has b u i l t a transistorized coder using 3  circulated pulses.  This thesis i s intended to complement his  work by designing and testing a transistorized decoder.  2. PULSE CODE MODULATION SISTEMS IN GENERAL 2.1  Coding The function of the PCM coder i s to convert the  continuous analog signal into the desired binary form.  Most  coders published are of one of the following three types. (1) Scanning type'*''* The sample amplitude i s measured i n a single scanning operation by comparing i t with a set of scaled values.  The  comparison proceeds from the least s i g n i f i c a n t d i g i t to the most.  This system i s extremely f a s t , the whole coding  operation can be done i n about one microsecond.  The c i r c u i t r y  however, i s complex and usually involves special beam coding tubes.  These coders become economical only i n systems with  many channels or with wide bandwidth signals where their speed can be put to f u l l use. 6 7 (2) Subtracting type ' Amplitude  i s measured by comparing the sample with one  d i g i t value after another proceeding from the most s i g n i f i c a n t d i g i t to the l e a s t . comparison possible. speed.  The subtracting action makes the sequent This type of coder i s of intermediate  I t lends i t s e l f to the coding of a few signals of  moderate bandwidth, such as speech.  The coder b u i l t by R.Ao  Hafer i s of t h i s type. (3) Counting type** The amplitude of the sample i s measured by counting the  4  number of units contained i n i t one by one u n t i l the remainder i s less than a quantum,.  This type of coder i s of  comparatively  simple construction and i s often used i n pulse height analyzers,, These coders are the slowest of the three groups. 2.2 Decoding The PCM decoder transforms the binary signal back to i t s analog form.  Decoders can be roughly grouped into the  following two categories. 4 9 (1)Shannon-Raok decoder  9  This type of decoder i s suitable for decoding the scanning type binary coding signal only.  The decoding method  i s an impressively simple one o r i g i n a l l y proposed by C.E. Shannon.  '  In i t s basic form i t employs a pulsed resistance-  capacitor c i r c u i t as i l l u s t r a t e d i n Figure 2.1(a).  Upon  a r r i v a l of each pulse of the code, an i d e n t i c a l increment of charge i s placed upon the capacitor of the device.  The time  constant t = RC i s such that, during any single pulse i n t e r v a l , whatever charge i s on t h i s capacitor decays precisely 50$ i n amplitude.  I t follows that the charge remaining at some  chosen instant after the a r r i v a l of a complete code group consists of contributions of a l l i t s pulses, weighted i n a binary manner. Since precise timing i s required for the basic Shannon decoder, a modified decoding c i r c u i t i s shown i n Figure 2.1(b). This scheme, devised by A.J. Rack, employs a damped resonant c i r c u i t i n conjunction with the resistance-capacitance  5  +B  -IT XL 2 Code i n  >2 R  ~*  L  •^-t  Code i n  To Output Gate (a)  Figure 2.1 Code i n  1  ' !o 0%'tput Gate (b)  Shannon and Rack Decoders  i—•  B, Shiftirjg^ Pulses And  I  Output Gating Pulses 1st d i g i t Cur. Gen.  I  Summing Storage Output^ Figure 2.2  Decoding C i r c u i t Using Binary -Shift-Register  6  elements.  By this modificationj, not only the times of  application of the charges but also the time of sampling are made much less  critical.  Like i t s corresponding coder, this decoder can be made very f a s t . (2)Delay type decoder This type of decoder i s suitable for decoding any of the binary coding signals produced by various coders. The construction i s more complicated than that of the former type. Various methods of obtaining the delay have 7 The f i r s t method uses delay lines  been used.  to obtain a l l the  signal pulses at one time adding their weighted values to achieve the sample amplitude,,  This i s a fast method but delay  lines f o r slow speeds are awkward. The second method uses the loop delay p r i n c i p l e ^ analogous to the looped subtracting type coder. coder can be operated at intermediate speeds.  This kind of The f i r s t de-  coder attempted i n the work of this thesis employed, this scheme. The„third method uses a s h i f t register f o r the delay. The operating speed can be varied over wide l i m i t s .  Our  second attempt at a decoding c i r c u i t employed a ferrite—core s h i f t registero  A proposed decoding c i r c u i t using binary  s h i f t register i s shown i n Figure 2.2.  7  2.3 Multiplexing and Repeating (1) M u l t i p l e x i n g ' 1 0  1 1  Multi-channel communication systems are of two basic types! frequency-division and time-division systems.  PCM i s  especially suited to time-division multiplexing. The elementary time-division multiplex system shown i n Figure 2.3 consists of a transmission path, at each end of which i s connected a rotating switch.  The two switches  rotate i n synchronism, so that the sending and receiving apparatus of each channel are connected together for their a l l o t t e d time interval and disconnected throughout the r e mainder of each revolution of the switch.  In practice, the  rotating switch would normally be replaced by a set of gating c i r c u i t s controlled by clock pulses. A detailed arrangement of a time-division multiplex system may be found i n reference 11. (2) Repeater Technical advances i n the microwave a r t , and p a r t i c u l a r l y i n connection with waveguide transmission, have made the time d i v i s i o n multiplex pulse code modulation system with the use of regenerative repeaters a plausible means for broadband transmission over distances of thousands of miles.  Such  transmission can be successful only i f the signal can be s a t i s f a c t o r i l y retimed, i n a chain of one to a few hundred repeaters.  Figure 2.3  Elementary Time Division Multiplex System  Regeneration  Narrow B-P Filter Figure 2.4  Timing iPulse Gen. A Self-Timed Repeater  9  The essential jobs of a line-repeater are recognition, synchronizing, retiming, pulse-shaping  and power gain.  Line-  repeaters can be c l a s s i f i e d into externally timed systems and self-timed system. shown i n Figure 2.4 Synchronizing  A self-timed repeater block diagram i s  2.4. and Framing  At the receiving terminal, the sequence of code 13 groups i s passed to the decoder.  If the timing c i r c u i t  at the receiving terminal were i n perfect synchronism and frame with that at the transmitting terminal, the gate to a decoder would always open exactly at the beginning of a code group.  In this way  each code group would be correctly  decoded and distributed to i t s proper channel, 14 To obtain the desired synchronism and frame  , the  receiving timing network must be driven from the incoming pulse t r a i n . large PCM  The synchronizing and framing c i r c u i t of a  system i s rather complicated.  In our decoding  c i r c u i t , the synchronism i s obtained by driving a slave o s c i l l a t o r from the incoming pulse t r a i n and a manual framing control i s used.  3. ORGANIZATION OF A PARTICULAR PCM SYSTEM 3<>1 Arrangement of the Coder 3  The particular coder b u i l t by R . A o Hafer c i r c u l a t i n g pulses.  i s one using  I t i s simple and uses very l i t t l e power.  The block diagram of the coder i s shown i n Figure 3.1. The coder converts a continuous analog signal into a coded d i g i t a l signal consisting of groups of n binary pulses.  The mode of  action of this coder w i l l now be described. The continuous signal i s sampled by diode gate No. 1 which i s controlled by GP3+ pulse at the sampling frequency of 8 kc. I f the sample pulse amplitude i s greater than some fixed value V, the comparator pulse  generator gives a stan-  dard output pulse. When t h i s occurs, the pulse generator also subtracts V volts from the sample pulse.  The remaining  signal pulse i s then amplified by 2 and stored i n the holding c i r c u i t u n t i l diode gate No. 2 opens. t r o l l e d by GP1+ and GP3- pulses.  Diode No. 2 i s con-  The GP1+ pulse, which opens  the gate, occurs at n times the sampling frequency.  The  GP3- pulse which occurs at the sampling frequency i n h i b i t s the action of GP1+ pulse once i n n pulses.  When diode gate  No. 2 opens, the amplified c i r c u l a t i n g sample pulse i s then applied to the comparator and again compared to the voltage V. This cycle of comparing, subtracting, amplifying and storing i s repeated by the coder n times f o r every sampled signal.  Thus, a coded d i g i t a l signal of n binary d i g i t s i s  generated.  I  GP3+ I Comparator Pulse Generator  BufferAmplifier  GP1+!  GP3-  Diode Gate Subtractor  Amplifier  No. 2  GP1-  Double EmitterFollower  Figure 3.1  GP2-  Holding Circuit  EmitterFollower Gate  Block Diagram of Coder Using C i r c u l a t i n g Pulses  Code Out  3.2 Arrangement of the Similar Decoder In order to convert the coded d i g i t a l signal back to the o r i g i n a l continuous signal, the most l o g i c a l solution i s one employing a decoder using c i r c u l a t i n g pulses.  The block  diagram of such a c i r c u l a t i n g pulse decoder i s shown i n Figure 3.2. This was the f i r s t type of decoder b u i l t and i t s action w i l l now be described. When the f i r s t binary pulse arrives, i t gives a certain amount of charge to the summing c i r c u i t .  After about half of  the c i r c u l a t i n g period, the charge i n the summing c i r c u i t i s _ transferred to the temporary storage through the charge transfer gate which i s controlled by the GP2- pulse at n times the sampling frequency.  The voltage on the temporary storage  capacitor i s then applied to the diode gate through the double emitter-follower. The diode gate i s opened by the GP1+ pulse which occurs at the same frequency as that of GP2but leads by about half of the c i r c u l a t i n g period. Coincident with every nth GP1+ pulse, there i s a GP3- pulse applied to the gate to i n h i b i t the action of GP1+ pulse. When the diode gate opens, the positive signal pulse i s converted to negative one through the pulse inverter.  This  negative signal i s then applied to the current amplifier which generates a current to charge the summing c i r c u i t so that i t gives an effective amplification of exactly 2. The discharging c i r c u i t discharges the voltage of the temporary storage and i s controlled by the GP1' + pulse which  Signal in  Charge Transfer Gate  Summing Circuit  Temporary Storage  4GP2GP1' + Subtracting Pulse Generator GPJ+^_  Discharging Circuit  Double EmitterFollower  Compensating Pulse Generator  GP1+ Current Amplifier  Figure 3.2  Diode Gate  Block Diagram of the Decoder Using Circulating Pulses  GP3-  occurs just after every GP1+ pulse.  The compensating pulse  generator which i s i n i t i a t e d by a GP3+ pulse provides a zero signal pulse whose action w i l l be explained l a t e r .  The  subtracting pulse generator triggered by the GP1+ pulse, i s needed to subtract away the charge generated by the current amplifier.  The summing c i r c u i t then sums the second d i g i t  pulse and the c i r c u l a t i n g amplified f i r s t d i g i t pulse. This transferring, storing, gating, amplifying and summing process continues n-1 times f o r the n d i g i t s code. In the nth cycle, the c i r c u l a t i n g action i s inhibited by the GF3- pulse.  At this time an output can be taken either from  the summing capacitor or from the temporary storage. Therefore, after a complete sampling period, the voltage due to the f i r s t d i g i t i s 2  n - 1  times that due to the l a s t n—2  d i g i t ; that due to the second d i g i t i s likewise .2 ~ as big, etc.  times  As a r e s u l t , the maximum l e v e l of the output  for an n-digit input i s : «n—1 «n—2 ~2 „1 2 + 2 +.......+ 2 + 2  -0 „n + 2 = 2 - 1  The c i r c u i t w i l l thus convert d i g i t a l signals into corresponding analog signals. should be reasonably simple.  This kind of decoding c i r c u i t The detailed c i r c u i t r y used  w i l l be discussed i n the next section.  4. THE DECODER USING CIRCULATING PULSES 4„1 Timing Pulse Generators Our f i r s t attempt at a decoding c i r c u i t used c i r c u l a t i n g pulses.  I t was decided to use the same master clock and  frequency divider as that used i n the coding c i r c u i t . -Pour standard pulse generators were b u i l t to avoid the interaction between the timing c i r c u i t s of coder and decoder.  The  timing arrangement block diagram i s shown i n Figure 4.1. waveforms of the timing pulses are shown i n Figure  The  4.2.  The master clock i s an ordinary astable multivibrator with a r e p e t i t i o n frequency of 48 kc.  The frequency divider  i s another astable multivibrator which i s synchronized to the master clock giving a repetition frequency of 8 kc. dividing r a t i o i s 6 corresponding to a 6-digit code.  Thus the A l l the  pulse generators are conventional monostable multivibrators with a pulse width of about 2 u,s. I t can be seen from F i g . 4.2 that the PG1 arid PG3 pulses are derived from the leading edges of the waveforms of the master clock and i t s frequency divider, while the GP2 pulse i s derived from the t r a i l i n g edge of the master clock waveform.  The GP1• pulse i s again derived from the t r a i l i n g edge  of the GP1+  pulse.  The timing c i r c u i t employs standard  c i r c u i t r y arid i s not shown i n d e t a i l .  16  M aster Clock  P.G.2  Frequency Divider  P.G.I  P.G.I  Figure 4.1 Block Diagram of the Timing Arrangement for the Decoder Using C i r c u l a t i n g Pulses  Master Clock  Fres q u e n u y Divider  GP1+  GP1 • +  GP2-  GP3Figure 4.2  Timing Waveforms  4.2 Decoding C i r c u i t r y 4.2.1 The Summing C i r c u i t and the Charge Transfer Gate (Figure 4 . 3 ) After reshaping by the repeater, the incoming pulses have an amplitude  of - 6 volts and width of 2 a sec.  They are  attenuated to about one-fourth of the height by the voltage divider formed by  and  An incoming pulse therefore  sets the base voltage of transistor T^ to about -1.4 v o l t s . This gives one unit of quantized charge to the summing capacitor  Ten microseconds l a t e r , the charge on  capacitor C 2 i s transferred to the temporary storage C-j by the transistor charge transfer gate Tg which i s triggered by the GP2- pulse. Gating pulse GP2-, which i s of accurately controlled constant amplitude, pulls the base and hence the emitter of T 2 to - 6 v o l t s , thereby transferring the charge for the voltage being greater than - 6 volts C.j.  responsible  onto capacitor  At the appearance of GP1+ pulse, the summing capacitor  Cg i s charged not only by T^ but also by T^ which responds to the c i r c u l a t i n g s i g n a l .  In addition, Tg removes some  charge i n order to compensate f o r zero signal current i n T^. The maximum voltage on the summing capacitor i s arranged to be —3 v o l t s .  Therefore, the c o l l e c t o r voltage of T^ varies  from - 3 v o l t s to - 6 v o l t s .  This i s why the input signal  pulse must be divided to —1.4 volts at the base of T^. The r e s i s t o r R, i s inserted to l i m i t the excessive  -10V  GP2-  T =2N247 T ,T =2N404 D 1N497 1=  2  ?  1=  R-^ISK R =4.7K Rg=20K 2  R =100 R =3.3K C^COl^f. 4  5  C=510u.u.f. C =510u+if. T =2N1304 2  3  g  Figure 4.3 Summing C i r c u i t and the Transistor Gate -1QV  T =2N404 T =2N1304 T ,T =2N247 2  3  4  5  R =3.3K R =4.7K Rg=22K 6  ?  R =lK D =1N497 Cg=510^f. g  2  C =500^f. 4  Figure 4.4 Temporary Storage, Discharging C i r c u i t and Double Emitter-Follower  current during the transfer of charge. prevent the loading down of GP2- pulse.  i s inserted to D^ i s used to provide  the necessary d.c. restoration for the a.c. coupled input signal. 4.2o2 Temporary Storage and Discharging  Circuit  (Figure 4.4) When the charge on C 2 i s transferred to C^, the voltage of C^ i s increased correspondingly.  Just after this  event, a PG1' + pulse i s applied to the base of t r a n s i s t o r T^ through the capacitor C^. to -10 v o l t s .  This positive pulse discharges C^  The chain Rg and R^ i s used to prevent  excessive instantaneous of the PG1'+ pulse.  current i n T^ and excessive loading  The time constant of Ry and C^ i s 2.5 us  which i s small enough compared to the 21 as period, so that d.c. restoration i s not necessary. Capacitor C^ i s about the same size as C 2 , hence i t s voltage change i s approximately the same as that of C 2 . Therefore, the voltage of C^ varies between -7 v o l t s and -10 volts. The voltage on the storage capacitor C^ must be applied to the diode gate.  This requires a buffer stage with input  impedance high enough so that the droop on the C^ waveform i s held to a very small value.  The output impedance must, at  the same time, be low enough to drive the r e l a t i v e l y low impedance gate.  Two cascaded emitter-followers are used to  achieve an input impedance of about 400 kit,  4.2.3  Diode Gate and Compensating Pulse Generator (Figure 4.5)  The diode gate i s a simple unidirectional Lewis gate with i n h i b i t o r .  The gating pulse GP1+ applied through the  capacitor C^ opens the gate.  This positive pulse turns off  the normally conducting diode D^ thereby allowing the junction of the four diodes to r i s e toward 0 v o l t .  This  rise i s , however, arrested at the signal voltage when Dg starts to conduct.  The high impedance load point and the  junction point r i s e to the level set by the low impedance signal source.  The potentiometer  lower than the lowest signal voltage.  i s set at a level Hence, there i s  always a zero signal pulse applied at the base of Tg when the gate opens. Coincident with every sixth pulse of GP1+, there i s a pulse of GP3- applied through capacitor C^.  This negative  pulse prevents the junction point of the gate from r i s i n g to the signal l e v e l and hence i n h i b i t s the action of the gate. A compensating pulse applied through D^ provides the necessary zero signal pulse when the gate i s closed by GP3pulse.  This compensating pulse i s generated from the a.c.  coupled GP3+ pulse.  The compensating pulse height can be  adjusted by varying the d.c. level of the mid-point of the potentiometer  The pulse height i s simply the height of  GP3+ pulse minus the voltage difference across the normally non-conducting  diode D  A  D ,Dg,D ,D ,D = 1N497 T =2N247 R =lK 2  4  5  5  6  R =0.1M  g  T„=2N1304 6  15  R =22K  R =2K  R-^ j=2 • 2K  R^^=22K  1Q  R  13  1  = l o 8 K  6  c ,c ,c =.oin.f, 5  6  7  Figure 4.5 Diode Gate and Compensating Pulse Generator •12V f 1 I-10V f -12V  +3V R^g=18K R =4.7K D ,D ,D = 1N497 R =5K R =10K T =2N247 R =20K R =20K C =510nuf. T ,T =2N1304 R =0.1M R =10K C =500uuf. R-,16 ~=1 o 8 K T =2N404 C =0.01 iaf. R^ =2.2K Figure 4.6 Pulse Inverter, Current Amplifier and Subtracting Pufse Generator 7  g  X  6  g  22  Q  3  19  23  15  2Q  3  21  g  ?  7  g  The positive signal pulse i s then converted to a negative one by the pulse inverter T^. 4.2.4 Pulse Inverter, Current Amplifier and Subtracting Pulse Generator (Figure 4.6) The pulse inverter and the subracting device are used solely f o r the proper operation of the transistor T^. which acts as amplifier i n charging the summing capacitor C to give an over-all amplification of exactly 2.  2  In order to  reduce nonlinearity, Tj must not be operated near cutoff. Therefore, even for the zero signal a f i n i t e pulse-size i s used.  The subtracting pulse generator controlled by the  GP1+ pulse subtracts the charge generated through T^ by the zero signal pulse.  Since the charging current into C^ must  not be affected by the v a r i a t i o n of the voltage of the charged capacitor, a pnp transistor T^ i s used with a large r e s i s t o r i n series with the emitter.  This requires a  negative signal pulse to drive the current into the summing capacitor.  Thus, the pulse inverter T^ i s employed to obtain  the necessary negative signal pulse. As stated e a r l i e r , the base voltage of T^ i s set by adjusting the potentiometer R^j. so that we can get the desired negative zero signal pulse. dissipation of T^.  R^g i s used to reduce the  The negative signal pulse at the emitter  or the pulse inverter i s then coupled to the current amplifier T„ through C . ft  A.C. coupling i s chosen because of  the required d.c. level change. proyide d.c. restoration. required araplification  The diode  i s used to  R ^ i s adjusted to give the  n  The subtracting pulse generator Tg i s controlled by GP1+ pulse*  This positive pulse applied through  turns  off the normally conducting diode D^ thereby allowing diode Dg to conduct and to turn on the transistor Tg. Thus the subtracting transistor Tg takes o f f a certain amount of charge from the summing capacitor C^e  The amount of  charge taken o f f can be changed by adjusting R2Q° The summing capacitor, therefore, receives i t s charge from two signal sources. circulated signal which charges of Tj and Tg.  One i s the amplified through the combination  The other i s the new incoming d i g i t a l  signal which gives a unit quantized charge to C^o  This  summing and c i r c u l a t i n g process continues 5 times f o r the 6 d i g i t code.  In the 6th cycle, the c i r c u l a t i n g action i s  inhibited by the GP3- pulse.  At t h i s time an output can  be taken from either the summing capacitor or the temporary storage. 4.3 Status of the Vork on this Decoder 4.3.1 Adjustment The decoder mentioned above was b u i l t and tested. Before putting the c i r c u i t into operation, i t must be adjusted correctly.  The f i r s t adjustment i s made without any input signal.  i s adjusted to give the desired .5 v o l t zero  signal pulse.  The compensating pulse i s also adjusted to  .5 v o l t by varying R^3»  ** *ken adjusted to give an s  exact subtraction of the charge generated by the zero signal pulse, so that there i s no build-up of the charge on the summing capacitor or i n the temporary storage. The next adjustment i s that of the unit quantized charge generated by transistor T^. R^ i s adjusted so that the unit charge raises the voltage of  by about 50  milivolt. The l a s t adjustment i s made to the current amplifier. R^2 i s adjusted to make the over-all amplification exactly 2. If the decoder i s properly adjusted the waveforms on the summing capacitor and the temporary storage should be as shown i n Figure 4.7 f o r a series of 1st d i g i t signals. (i e 0  o  In the input signal, only the f i r s t d i g i t pulse  representing the 32nd level i s present). The kind of waveform indicated i n Figure 4.7 was observed.  But from studying the actual waveform, we found  some non-linearity and i n s t a b i l i t y effects.  T  c  2  :  f—r Figure 4»7  Waveforms on the Summing Capacitor and the•Temporary Storage  •  4.3.2 Non-linearity E f f e c t  In an ideal case, the capacitor waveform (indicated by the s o l i d pulses) f o r a series of 1st d i g i t inputs should touch the s o l i d exponentially  r i s i n g curve. These 0 1 2 3 4 six s o l i d pulses represent respectively 2 , 2 , 2 , 2 , 2 5  and 2  levels.  The non-linearity introduced i n the actual  decoding c i r c u i t i s such that the amplification for small signals i s a l i t t l e inadequate, while f o r large signals i t i s a l i t t l e more than desired.  I t i s shown i n Figure 4.8 by  dashed pulses under the dashed curve.  This effect i s  mainly due to the following two sources, (a) Non-linearity due to the v a r i a t i o n of a In ordinary t r a n s i s t o r s c o l l e c t o r current.  9  the a parameter varies with  A typical characteristic i s shown i n  Figure 4 , 9 . a  Figure 4.9  Variation of a with respect to I  Q  In the decoder c i r c u i t , almost every transistor i s operating i n the positive slope region.  A t y p i c a l operating  region i s from point A to point B as shown i n Figure 4 . 9 . This i s why the amplification for low signal level i s not adequate, while f o r high signal level i t i s more than adequate.  This non-linearity i s hard to avoid.  However, i t  can be reduced by choosing the lowest and highest operating points (A and B) as close together as possible, and near the  28  maximum <x. (b) Non-linearity due to the v a r i a t i o n of r  g  The loop gain of the c i r c u l a t i n g decoder i s obtained mainly from transistor Tj  B  Its v a r i a t i o n of a affects the  loop gain value and causes the non-linearity. Besides, the v a r i a t i o n of the emitter resistance r  once more increase  e the non-linearity e f f e c t . Typical v a r i a t i o n of the r c o l l e c t o r current I i s shown i n Figure 4.10. c  g  with  70 60 50 40 j. 30 20 10 __I  0 Fig. 4,10  Put  Since  r  Variation of r  = r • + r " e e  e  II  _  E  TH  with I  where r ' = The emitter resistance component which does not change II _ The component which changes with I or I e  c  x lO  1  where I E  T  Q  = Emitter current i n m, a. = T/ll,600  At room temperature (25° C) it  _  26  Let us consider the s i t u a t i o n of transistor T^..  Suppose the  maximum and mimimum emitter currents are respectively  and  I 2 corresponding to the maximum and minimum applied voltages @  and  As shown i n Figure 4„11, the t o t a l resistance r  from point A to point B i s s 26 II I I&  r = E + re =R + re' + r e" = B + re' + The change of r due to change of I 26  Ar = r ,  26 II  e2l  g  is: 26 |I  e2  el  Pel I | e2i I  By the r e l a t i o n :  we have: Ar =  2  6  \hl\-K2\ SR  2 6  l ^ i l - l  r i 2  1  ^ !  0 0 0 0 0 0  (a)  B  F.I Figure 4.11  Situation of T,  From equation (a) we know that i f Ar i s to have neglegihle effect, we must operate the t r a n s i s t o r T^ i n  such a condition that both V and I must be large and I , e e JL and  should be as close together as possible.  increasing I  g  However,  also increases the error of the difference of  charging and sjubtr acting on  thereby increasing the  i n s t a b i l i t y effect to be discussed i n the next section, 4.3.3 I n s t a b i l i t y E f f e c t The i n s t a b i l i t y could be seen most pronouncedly at the higher l e v e l signal of the waveform on C  2  or C^  c  For  the highest input s i g n a l , the maximum pulse height should be l e v e l 63 which i s about 3 v o l t s high. Owing to i n s t a b i l i t i e s , the maximum pulse fluctuated up and down p e r i o d i c a l l y instead of staying at the exact 63 l e v e l .  The fluctuations cover about 4 l e v e l s  (or 6$ of f u l l scale) and t h e i r period i s about 2 minutes. Since we have 3 volts available f o r the 64 l e v e l i on C  2  and C^, each l e v e l i s less than 50 m i l l i - v o l t s .  The  output of the decoder requires an accuracy of better than \ level.  As any i n i t i a l  change of C  2  voltage w i l l be amplified  32 times, the v a r i a t i o n of voltage on the summing capacitor must be less than 25/32 mv. causes C  2  Therefore, any v a r i a t i o n that  to change by as much as 1 mv i s not permissible.  The i n s t a b i l i t y of the decoder comes mainly from the following two sources: (a) I n s t a b i l i t y due to I "  C  unbalance  O  Collectors of T. , T_ and T  s  are connected i n common  to charge and discharge the summing capacitor 510 u.u.f.  Since  which i s  v a r i a t i o n must be kept to less than 1 mv  the t o t a l unbalance of reverse saturation collector current (l  c Q  ) during the 10 as half cycle should not exceeds  1 x l O " x 510 x 1 0 ~ 10 x 10" 3  =  12  0.051  ua  6  Measured values of I  for our t r a n s i s t o r s at co room temperature are of the order of 1 to 3 u,a, when the transistors are not connected to the c i r c u i t . unbalance of I  co  This d.c.  currents can of course be allowed for by  the proper adjustment of the subtracting c i r c u i t . during actual operation, I erature.! Since I  But  currents change with temp-  doubles for each increase of 10,° C for co  a germanium transistor, the I  current change of each  t r a n s i s t o r i s d i f f e r e n t from others.  This unbalance of I co  currents causes the f i n a l output l e v e l to vary, therebyincreasing or decreasing the average operating jcurrent of transistors.  Thus, the temperature of transistors varies  p e r i o d i c a l l y due to internal heating of t r a n s i s t o r s .  This  i s why the f i n a l output fluctuates p e r i o d i c a l l y . (b) The I n s t a b i l i t y due to the unbalance of the charging and subtracting action on for zero signal The subtracting device i s designed mainly for subtracting the charge generated by current generator for the zero signal pulse.  Since the charging and subtracting  actions are takenina2 us i n t e r v a l , the unbalanced error 1 x 10 ^ x 510 x lO™ ^ should not exceed — 7 — = 0.26 ua. 2 x 10~° 1  During operation, this 0.26 ua accuracy can hardly be attained. cause  A small change i n ambient temperature can easily  an unbalanced error much more than 0.26 ua.  This  error increases or decreases the f i n a l output level thereby increasing or decreasing the average operating current of transistors.  Once again, owing to the internal heating  of transistors, the f i n a l output of the decoder fluctuates up and down p e r i o d i c a l l y . 4.4 Conclusion Various measures were attempted to improve the performance of the circulating-pulse decoder. Capacitances C^ and C^ were increased to 3000 uuf thereby increasing the quantized unit charge and reducing the i n s t a b i l i t y effect due to unbalances.  The increase i n the quantized unit charg  also increases the difference of I , and I (mentioned i n el e<& 4.3.2) thus increasing the non-linearity. 0  In order to reduce the difference of I , and I „, el e2 we have also t r i e d to increase a l l the gating pulses to 4 us This arrangement improves the I  unbalance but the sub-  t r a c t i n g error l i m i t changes from 0.26 ua to 0.13 ua.  Thus,  the over-all i n s t a b i l i t y can not be improved at a l l . As mentioned e a r l i e r , attempts to improve the l i n e a r i t y by increasing I  2  and keeping I ^ and I  g 2  as close  33  together as possible merely increases errors due to current unbalances, thus increasing the i n s t a b i l i t y . Owing to the two c o n f l i c t i n g requirements, i t was decided to give up this c i r c u l a t i n g c i r c u i t and to investigate a decoder using a f e r r i t e - c o r e • s h i f t register. This proved to be more successful.  5 . THE SHIFT-REGISTER DECODER 5»1 General D e s c r i p t i o n of the Decoder The block diagram of the successful decoder i s shown i n Figure 5.1. The d i g i t a l s i g n a l passing through the prea m p l i f i e r a r r i v e s at the repeater.  The s i g n a l i s then  i d e n t i f i e d by the repeater and sent through the emitterf o l l o w e r t o the input current generator and to the oscillator.  A s e r i e s of ^0 ma current pulses i s then  generated by the input current generator and applied to the input winding of the f e r r i t e - c o r e s h i f t r e g i s t e r . The C o l p i t t s - t y p e o s c i l l a t o r i s adjusted to an o s c i l l a t i n g frequency approximately equal to the master clock frequency of the coder.  When synchronized by the  input s i g n a l i t s o s c i l l a t i n g frequency i s exactly equal to that of the master clock of the coder.  The o s c i l l a t o r  output i s d i f f e r e n t i a t e d to provide the necessary steep edges of the waveform f o r t r i g g e r i n g the d r i v i n g pulse generator. The d r i v i n g pulse generator i s t r i g g e r e d by the negative-going edge of the d i f f e r e n t i a t o r output waveform so that the s i g n a l pulse l i e s always between the 2 u.s d r i v i n g pulses.  Figure 5.2 shows the waveforms of the  various pulses used. The d r i v i n g pulse i s then applied to the d r i v i n g current generator to produce a 600 ma current pulse f o r  Repeater  Oscillator  EmitterFollower  Differmtiato:  Input Current Jenerator  Driving Pulse Generatoi  ShiftRegister  Driving Current Generator  Adding Circuit  EmitterFollower  Output Gate  Framing Control  FerriteCore Counting Device  Frequency Divider Pulse Generator  Output Circuit  Output  Figure 5.1  Block Diagram of the Successful Decoder  36  Figure 5.2 Waveform of the Timing System  37  driving the 6-core s h i f t r e g i s t e r .  In the f e r r i t e - c o r e  s h i f t register, d i g i t a l information i s "written" into the magnetic cores when the signal current pulse i s applied to i t s input winding.  After "write-in" the information i s  shifted down the line by the application of the driving pulse current.  The adding c i r c u i t then adds the pulses  stored i n the various suitably weighted cores. The added signal passes through the emitter-follower and i s applied to the output gate.  The output gate i s  controlled by the frequency divider pulse and i s used to pick out the true analog signal from n added pulses where n i s the d i g i t number of the coding system.  Finally, i n  order to make f i l t e r i n g easier and provide more output power, the analog signal pulse i s transformed into an exponentially decreasing waveform. The frequency divider pulse generator i s triggered by the positive pulse pips of the driving pulse generator. However, i t s repetition frequency i s controlled by the f e r r i t e - c o r e counting down c i r c u i t to obtain the desired frequency d i v i s i o n .  The framing control i s a monostable  pulse generator with long dead time.  By pushing a button or  other switch, the framing control can add a certain fixed amount of charge to the f e r r i t e - c o r e counting down c i r c u i t thereby advancing the frequency divider pulse one d i g i t . This kind of control enables us to make sure that the gate  38  opens for the correct one out of n d i g i t s , thus an i n t e l l i g i b l e  producing  output.  The exponentially decreasing output signal i s then passed through a properly designed f i l t e r - e q u a l i z e r combinat i o n and i s converted back to i t s o r i g i n a l continuous  form.  The detailed decoding c i r c u i t s w i l l be discussed i n the next section. 5.2 Requirements 5.2.1 Repeater The repeater i s r e a l l y a pulse comparator.  I t should  give an output when the incoming signal exceeds a certain level.  The special repeater c i r c u i t we used i n our decoder  i s as shown i n Figure 5.3. described l a t e r .  The detailed c i r c u i t w i l l be  The function of the repeater i s to eliminate  the noise associated with the incoming d i g i t a l signal.  The  c r i t i c a l l e v e l for distinguishing whether an incoming pulse i s a signal or noise can be adjusted easily to suit the height of the received signal pulses. In fact, this repeater would be the same as the many line-repeaters linking the coder and decoder i n a long transmission system.  The essential jobs of a line-repeater  are recognition, synchronizing, retiming, pulse—shaping and power gain.  Block diagram Figure 5.3 shows the parts of a  line-repeater.  The s o l i d blocks represent the devices that  have already been developed  as part of the decoder design.  We need o n l y add the r e g e n e r a t i v e  broadening and the power  a m p l i f i c a t i o n c i r c u i t s which are shown by the dashed b l o c k s .  Incoming Signal^ Repeatez  —JAmp  foflower  Output I  Figure 5.3 Block Diagram of a Line-repeater  5.2.2 Synchronized Timing The timing c i r c u i t used i n the successful s h i f t register decoder. later.  decoder i s d i f f e r e n t  from that i n the c i r c u l a t i n g  The d e t a i l e d sequence of timing w i l l be described Here we discuss only the requirement of the  synchronized timing c i r c u i t .  In the operation of a success-  f u l system, the clock pulse of the decoder must be exactly synchronized with the t r a n s m i t t i n g s i g n a l . o s c i l l a t o r was found to perform t h i s  A Colpitts  satisfactorily.  In order to avoid long gaps between pulses, code l e v e l 0 i s never used.  In a s i x d i g i t operation, the longest  duration between input pulses occurs when level 32 i s followed by level 1.  During this gap of 12 pulse periods, the  deviation of the timing wave must be less than l/2 cycle. Therefore, the maximum allowed o s c i l l a t o r frequency deviation i s 4%.  This allowed some margin f o r temperature and ageing  effects of the o s c i l l a t o r . 5.2.3 Framing In order to receive a correct signal, proper framing is essential so that the decoder w i l l recognize the groups of 6 pulses representing each sample of the signal.  The  automatic framing arrangement mentioned i n 2.4 cannot be used i n our decoding c i r c u i t because i t i s too complicated and expensive for single channel operation.  What we need  i s a simple manual framing device which can give us the correct framing sequence. The framing control can be accomplished by adding a certain amount of framing charge to the frequency dividing circuit.  In an ordinary astable frequency divider c i r c u i t ,  i t i s not easy to add the required charge to the coupling capacitor at the proper time.  Besides, only half of the  astahle period i s available for adding extra framing charge. Therefore, we designed a new frequency divider pulse generator using a f e r r i t e - c o r e counting down c i r c u i t .  This frequency  divider pulse generator not only offered us a proper place to add the framing charge but also gave us  a considerable  41  range of changing the frequency dividing r a t i o .  The  detailed c i r c u i t of the framing arrangement w i l l be discussed later.  6. CIRCUITS FOR THE SHIFT-REGISTER DECODER 6.1 The Repeater and the Emitter-Follower (Figure 6.1) The incoming binary s i g n a l passing through the prea m p l i f i e r (T^) i s applied to the repeater.  The pre-  a m p l i f i e r i s an e m i t t e r - f o l l o w e r which provides the necessary low impedance s i g n a l source.  Rg can be adjusted  to meet the c r i t i c a l d i s t i n g u i s h i n g voltage l e v e l of the repeater f o r  the incoming pulses and spaces.  The d i v i d e d  s i g n a l i s then applied to the repeater (Tg and Tg) through capacitor Cg. In the repeater, Tg i s normally on while Tg i s normally o f f . When the negative s i g n a l pulse height i s greater than the c r i t i c a l l e v e l of the repeater, the s i g n a l w i l l pass through D^ and begin to t u r n on Tg. w i l l then make a t r a n s i t i o n  The repeater  to i t s quasi-stable s t a t e .  About 1.4 u,s l a t e r , the voltage at the base of Tg decays to i t s c u t - o f f value thus making the repeater return to i t s stable s t a t e .  The repeater thus produces a reshaped output  pulse 1,5 u.s wide and independent of the size of the s i g n a l pulse. The repeater output pulse width i s mainly c o n t r o l l e d by the time constant of C„ and R . The c r i t i c a l d i s t i n g u i s h o  y  ing voltage l e v e l can be changed by varying the  potentiomete  -14V  -12V  Figure 6.1  -12V  The Repeater and the Emitter-Foilover  T 2N373  R =10K  R^ •Ry—1.8K  T ,T ,T =2N404  R =15K  R =4.7K  R =560  C =200ixu,f  D 1N497  R =4.7K  R =15K  c ,c =o.oiii,f  C =0.001uf  R 27K  R =10K  R =100K  C =200uuf  C =0.005nf  1=  2  3  4  1=  1=  2  3  4  5 K  g  9  1Q  C =350iA|if 3  12  i;L  2  5  4  6  7  4>.  44  The negative going s i g n a l pulse at the c o l l e c t o r of Tg i s coupled to the e m i t t e r - f o l l o w e r (T^) through capacitor Cg. T^ i s used mainly f o r preventing the loading of the repeater output.  The s i g n a l pulse from the e m i t t e r - f o l l o w e r i s then  coupled through  to synchronize the o s c i l l a t o r .  A divided  s i g n a l pulse i s also coupled through Cg to d r i v e the input current pulse generator. 6.2. The Slave O s c i l l a t o r and the D i f f e r e n t i a t o r (Figure 6.2) Many o s c i l l a t o r c i r c u i t s were attempted.  The most  s a t i s f a c t o r y o s c i l l a t o r f u l f i l l i n g the requirements mentioned i n 5.1.2 i s the C o l p i t t s o s c i l l a t o r (T^).  The  o s c i l l a t i n g frequency can be c a l c u l a t e d very c l o s e l y by the 15 f o l l o w i n g equation. to  2  =  1 r—r— 1 T L  C  o h 8 9 llb g  +  r  C  C  h  O s c i l l a t i o n s occur as long as  8 9 — — T 8 9 C  where, C™ =  r  T  c  C  v  C  +  T  C  8  ^  ^> h ^ ^ g  Q  9 The necessary feedback i s obtained through capacitor C-^Q  t  <&n& the o s c i l l a t i n g frequency  i s v a r i e d by changing the  value of the 2-18 mh v a r i a b l e c o i l L^. Whenever a s i g n a l arrives . through C^, the negative pulse draws a considerable current from T^ arousing the o s c i l l a t o r to s t a r t o s c i l l a t i o n s from a fixed; phase  _<•:-'.;'..  Thus, the incoming s i g n a l restores the timing d i f f e r e n c e  -12V  -18V  Synchronizing Signal From T  To Driving  4  ^ —  Pulse Generate  Figure 6.2 T T, = 2N404 5 6 D = 1N497 K  The Slave O s c i l l a t o r and the D i f f e r e n t i a t o r C  E  1 4  = 47K  R  15  to R  C  1 2  = 2d0~|i(if.  C  1 3  = 100 ujif.  17  = 2.2K  2  h  E  = 2 - 18mh  ±  1 3  = 100K  7  = 0.005af  8' 10 l ' C = 0.02uf C  C  =  0 o 0 1  9  C  ll  =  0 o 0 3 3  '  A f  J  f  4 6  between the o s c i l l a t i n g frequency and the master clock frequency of the coder.  The r e s t o r i n g a c t i o n can occur at  any time during the c y c l e . The output of the o s c i l l a t o r i s taken from the • c o l l e c t o r of Tj. and i s applied to the d i f f e r e n t i a t o r through C^2«  The d i f f e r e n t i a t o r switches from s a t u r a t i o n to cut-  o f f and back again.  I t i s designed to make the t r a n s i t i o n  time as short as p o s s i b l e g i v i n g a rather sharp edged square wave output.  i s used f o r d.c. r e s t o r a t i o n .  The  negative going edge of the output waveform of the d i f f e r e n t i a t o r i s then used to t r i g g e r the d r i v i n g pulse generator. 6 . 3 The D r i v i n g Pulse Generator and the D r i v i n g Current Generator (Figure 6 . 3 ) The d r i v i n g pulse generator (T^ and Tg) i s a standard. monostable one with a pulse width of about 2 u.s. I t i s t r i g g e r e d by the negative going edge of the d i f f e r e n t i a t o r output waveform which i s applied through C^g The time constant of the input c i r c u i t of the pulse generator i s arranged so small that no d.c. r e s t o r a t i o n i s required. Four outputs are taken out from the pulse generator: (1) The p o s i t i v e D.P.+ pulse at the c o l l e c t o r of T^ i s applied to the emitter-follower Tg through the capacitor C . ig  ( 2 ) The same D.P.+ pulse applied through C^g to charge the capacitor Cg^ of the f e r r i t e - c o r e counting c i r c u i t . p o s i t i v e pips D.P,'+ applied through C  (3)The  to t r i g g e r the  Figure 6.3  Driving Pulse Generator and Driving Current Generator  ?  8  R =22K  R =18K  c  1 3  ,o  1 4  ,c  1 8  9  1Q  R =22K  R =33K  c  1 5  ,c  1 6  ,c  1 7  D ,D = 1N497  R =470  R  C =0.01|Af  R^g=3.3K  R =2.2K  R =47/3  C =0.001uf  R =2.7K  R =47/4  C =1000uf  T ,T =2N247 T ,T =2N1304 3  4  19  20  21  22  23  24  25  26>  R =270 2?  2g  29  = =100uuf = =150ij,ulf  19  2Q  21  4>.  frequency d i v i d e r pulse generator.  (4)The negative  D.P.-  pulse applied through C^g to t r i g g e r T - ^ of the f e r r i t e core counting c i r c u i t . The emitter-follower Tg pumps i n t o the base of T ^ Q through CgQ and R^^  a large current i n order to produce the  d r i v i n g pulse f o r the cores.  R^rj i s used f o r l i m i t i n g the  i n i t i a l current of T ^ Q thus lengthening the current pulse. Diode D^ provides the necessary d.c. r e s t o r a t i o n . T - ^ Q which gives an average of 600 m.a.  current pulse consists  of two 2N 1304 N P N t r a n s i s t o r s mounted on a heat sink to increase the d i s s i p a t i o n of the combination.  R^g  provides  the necessary blocking pulse,,for the s h i f t - r e g i s t e r . As the rate of change of current during the r i s e and f a l l of the current pulse i s very large, the noise voltage induced i n the decoder c i r c u i t due to the magnetic f l u x change i s quite high.  In order to reduce t h i s noise,  the decoupling f i l t e r formed by Cg^ and R^g i s employed* The 1000 |if e l e c t r o l y t i c capacitor supplies most of the sudden burst of current, reducing the induced noise by  90$.  The heavy current pulse flows through the drive windings  to Wg which advance the stored information of  the s h i f t - r e g i s t e r .  Rgg i s chosen so that the height of the  blocking pulse i s j u s t enough to block the flow of undesired current for the duration of the s h i f t pulse.  49  6<>4 Input Current Generator and the Ferrite-core S h i f t Register 6.4.1 The design of the Shift-Register The magnetic s h i f t - r e g i s t e r s can be c l a s s i f i e d into three categories using respectively three, two or one core 16 per b i t  e  In general, the more cores per b i t used, the  easier i s the design and the higher the repetition frequency of the shift-register.. Since we have to use two-phase or three-phase s h i f t i n g pulses i n the design of two-core per b i t or threecore per b i t magnetic s h i f t - r e g i s t e r , i t was decided to design a one-core per b i t magnetic s h i f t - r e g i s t e r i n which only one s h i f t i n g current pulse i s required.  The following  two attempts have been made f o r the design of the one-core per b i t s h i f t - r e g i s t e r . (I) The F i r s t Attempt (A) General  Operations  Among the one-core per b i t s h i f t - r e g i s t e r the simplest 1f  one i s as shown i n Figure 6.4 (a).  The operation proceeds as  follows. When the driving pulse i s applied to the driving windings N , a l l the cores are reset to the state 0.  Any core that  was i n i t i a l l y i n the state 1 w i l l develop a voltage across i t s output windings  as i t resets to 0.  current through the diodes D  This voltage drives a  into the temporary-storage  capacitor C. After the decay of the driving pulse, any capacitor which has acquired a charge w i l l now discharge into  Figure 6 . 5  Capacitor Voltage and Its Energy Chart  the input winding N  c  of the next core and set this core into  state 1. If a core i s i n the state 0, i t does not charge the capacitor and hence the succeeding core w i l l be l e f t i n the state 0  o  I t i s , therefore, clear that following each  driving pulse the information stored i n each core i s transferred to the succeeding core. (B) Design consideration The voltage waveform on the capacitor C i s shown i n Figure 6.5 (a).  Therefore, the stored energy, after i t has  been charged can be represented by the energy chart shown i n Figure 6.5 (b). Since H i s the minimum mmf 18 i n ampere turns  c  required f o r a complete switching of the MC114 f e r r i t e core H and Nc i s the number of turns of input winding, hence, TJ— w IS the minimum current required during the discharging period of H the capacitor. Thus, ^ R represents the voltage drop across c the r e s i s t o r R. c  For am economic design, the choice of R i s very important. The upper l i m i t of R i s determined by the H factor | j — R. As shown in. the energy chart, the shaded area c represents the energy loss i n R. Hence, i t should not be very large compared to the energy available f o r flux H H reversal. So we have v" - ^— R ^> — R V N c  c  c  c c  and therefore, ft^^jjJH— * c There i s also a lower l i m i t of R.  Assume the  charging time for C ( i e . the switching time) i s T , the s r T energy l o s t by the capacitor through R i s : / s y2 JQ W ° Since V i s a l i n e a r l y increasing function we have, V = Kt, where O ^ t ^ , V = KT . s c s s^ V T f V ^ f Kt Therefore, -0 i 5~ 5— dt = Jo /_ S dt = ^ R c s 3R 0  DT  y  ? S  2  T s  K T  2  2  -  =  This energy loss should be kept smaller than the t o t a l 2 V T 2 stored capacitor energy £VcC„ Thus c s < iV* C 3R 2  x  The lower l i m i t of R i s  R >2Ts 3C  As indicated on the energy chart, the energy H available for flux reversal i s s(V - ^— R) C Thus, the c percentage of usable energy over the t o t a l energy supplied c  2  by the output winding AT^ i s , j A  (Yc -  =  ^V  2 c  B) C 2  2 C + c s 3R y  T  Prom the above equation we can see the two  limits  of R.  Since a higher value of R not only reduces the V T lossy term c s but also the c i r c u l a t i n g current 3R 2  generated by the input winding during the charging period, R i s designed at the higher value within i t s limits« As H , N , R, C, T , N, , N  are mutually related  53  i t i s not easy to find an optimized t h e o r e t i c a l l y or experimentally.  combination  In actual design,  H  c  can be found from the characteristic curves of the f e r r i t e core.  T and V can be estimated from the characteristic s c  curves and the dimensions  of the ferrite-core„  Thus, the  design procedures are as followss (1) Determine H  c  of the special ferrite-core used.  Estimate values of T and V and thus determine N, s c b and N approximately„ c (2) Prom the estimated values of T and V choose a s c suitable value of R within i t s two l i m i t s . (3) Estimate the amount of energy corresponding to the energy available for the flux reversal on the energy chart, thus determining the value of C. (4) Calculate current leakage loss from C and the c i r c u l a t i n g current l o s s  0  (5) Calculate the t o t a l amp-turns required.  This, with the  leakage flux loss, determines N „ a A good design can be attained by repeating the above procedure two or three times.  A five-core s h i f t register  was b u i l t using this method, with the following parameters! R = 100 ohms, C =0.03 uf, N  = 24 turns,  St  N, = 50 turns, N D  =30 turns, V C  = 5 v o l t s , and T C  = 1.2 us. S  (C) Disadvantages This kind of s h i f t - r e g i s t e r i s suitable f o r ope rating at lower repetition frequency and higher voltage levelp  since at higher voltage level the BC time constant  can be made as large as the period of one c y c l e  Thuso a  0  s l i g h t time difference T^ between the switching time of each core and the driving pulse width does not influence the operation of the register,,  For a higher frequency, the  RC time constant must be small and the match of the switching time of each core with the driving pulse width becomes very important.  Whenever T^ of any core exceeds a  certain margin the register can not be operated no matter how large the driving mmf„ 17 As pointed out by Kodis, Buhman and Woo  , the  highest frequency they attained by using vacuum tube valve was only 100 kc.  In our design the small F-394 size  f e r r i t e - c o r e were used, and operating V 5 voltso stant.  i s only around  This l i m i t s the value of B and the BC time conThe complete cycle was only 5 us corresponding to  a r e p e t i t i o n frequency of 200 kc. Due to the rather c r i t i c a l design, every component used i n the c i r c u i t must be within 5$ accuracy.  The most tedious procedure i s  winding the cores c a r e f u l l y to achieve, not only the same N , N, and N , but also approximately the same leakage. 0/  D  C  The second disadvantage i s the excessive power  55 dissipation per core,  We can use the additional diode  as shown i n Figure 6.4 (b) to prevent the c i r c u l a t i n g current flowing through N^  0  But the c i r c u l a t i n g current  flowing through N and the energy lost through leakage c still  exist. The t h i r d disadvantage  i s the large number of  turns (more than 100) per core required, leaving hardly any space f o r further output  windings.  We, therefore, turned to another version of onecore-per-bit s h i f t - r e g i s t e r which eliminates a l l the above disadvantages., (II) The Second Attempt (A) General operation A high speed s h i f t register with blocking pulses 19 was devised by Newhouse and Prywes using vacuum tube valves. The c i r c u i t arrangement i s shown i n Figure 6.6 (a). The general operation i s similar to the previous one except f o r the functions of blocking pulse and V^  0  The negative blocking pulse which i s produced by the driving current passing through B cuts off diode D  2  thus blocking the c i r c u l a t i n g current and the loss of current. i s used to prevent the building up of spurious pulses. The detailed operation and design formulas may be found in reference 19» Instead of three winding per core, we prefer the  56  Figure 606  High Speed Shift-Registers  57  two winding per core s h i f t - r e g i s t e r which i s shown i n Figure 6.6  (b)  0  By employing this c i r c u i t , we can wind  another free voltage output winding N  q  for the special  application i n the adding circuit,. The operation of Figure 6.6  (b) i s as follows.  The same winding N i s used for both input and output.  Each  of these windings i s connected i n series through diode to the storage capacitor C following the core.  The  d i r e c t i o n of the diodes i n the loop thus created changes alternately so that the capacitors can charge p o s i t i v e l y and negatively i n alternate states.  In Figure 6.6  (b),  starting from the l e f t , the odd capacitors can be charged only negatively and the even capacitors can be charged only positively. The loops created by the output windings and the capacitors are grounded i n the odd stages and are pulsed negatively i n the even stages by pulses which l a s t for the duration of the driving pulse 1^.  The effect of the pulse  i s to bias i n the reverse d i r e c t i o n the diodes D  2  between  a l l loops, rendering them nonconducting for the duration of the driving pulse.  Thus, no c i r c u l a t i n g current or  leak-off current exists during the charging period of C. A considerable v a r i a t i o n i n the switching time of the cores i s now  possible without interference of one stage with  another.  At the conclusion of the driving pulse, the  58  I  1  »  •  »  •  •  '  '  ^i,  t  0 4us 8us 12us 16us Figure 6.7 Waveforms at the Corresponding Points of F i g . 6.6(b)  capacitors C discharge through the windings N of the succeeding  stages, storing "one" i n them.  As the cores are operated i n the low voltage range, the disturbed zero output for the MC114 per turn.  core i s only 15 mv  Thus, the i n i t i a l diode resistance of  is  high enough to prevent the building up of the spurious pulse.  Therefore, the arrangement similar to  Figure 6.6  of  (a) i s omitted.  The waveforms at the corresponding points a,b,c, d,e,f of Figure 6.6  (b) i s shown i n Figure 6.8.  The  time base i s the same i n order to indicate c l e a r l y the charging, blocking and discharging sequence. We shall now  Figure 6.8  describe our design procedure.  The Capacitor Waveform and Its Stored Energy Chart of Figure 6.j. (c)  (B) Design Considerations Instead of the tedious design formulas suggested by Newhouse and Prywes, we have used the following b r i e f design consideration. As shown i n Figure 6.7 (c), the capacitor voltage changes l i n e a r l y during the discharging period.  Thus, the  right-angled triangular energy chart shown i n Figure 6.8 can again be employed. Since a l l the n discharging currents flow through the blocking resistor R, and the individual discharging current passes through the respective forward diode  resis-  tance Rp, an effective resistance of (nR + R„) i s therefore H seen by the discharging capacitor. The term | T — (nR + R^) r  represents the voltage drop developed by the discharging current flowing through R and R^.  Hence, the shaded area  represents the minimum required energy loss i n R and R^. For a six-core s h i f t register (n = 6), we have the following design steps. (1) Since f o r the adding c i r c u i t we require an output pulse as wide as possible, the switching time i s chosen at 1.3 us which gives 80 mv output per turn.(see Figure 6.9). Thus, for N = 50 turns, V (2) H  i s 4 volts.  c i s taken as 0.56 amp-turns.  Thus, the minimum c current required during the discharging of C i s 11 ma. For H a (6R + R„) of about 105 ohms, the TT - (nR + R„) voltage 0  drop i s about 1.15 volts(3) According to the energy chart of Figure 6.8 (b), the voltage V corresponding to the energy available f o r flux reversal i s then 2.85 v o l t s .  A stored energy of 0.75 erg  i s enough for a complete flux reversal of the core.  Since  there i s no other loss except the small loss due to the winding resistance, a stored energy of 0.8 erg i s sufficient.  This gives us the required capacitor size of  ° I = 0.0197 uf. 2.85^ i s used.  2  X  8  Hence, the capacitor C of 0.02 uf  (4) The required charging current f o r charging C to 4 volts • i 1 m 1.3 us i•s 0.02 — x 10" Tx 4 = 62 ma. ,Thus,,,the 1.3 x 10~° 6  £  0  m  corresponding amp-turns i s 50 x 0.062 =3.1 amp-turns. An additional 0.9 amp-turns i s required f o r switching the core i t s e l f and for supplying the small output load i n the adding  circuit.  (5) Therefore, a total of 4 amp-turns i s the minimum required driving force.  But due to the uncertain leakage  flux loss, the actual driving force used i s 5 amp-turns with a switching time of about 1.25 us. Since the driving current changes from 420 ma to 700 ma with the loading condition of the s h i f t - r e g i s t e r , a N The additional output winding N a 4 v o l t output pulse.  q  F T  of 12 turns i s given.  has 50 turns which gives  •280  dV  0  =disturbed zero output voltage  260  /  /A  0  -240 -220 -200 -180 160  1.6  140  1.4  120  1.2  -100  \  1.0  s  -80  0.8  - 60  0.6-  -40  0.4 dV  - 20  —*  1  500  ,  „  1  600  Figure 6.9  L_  / /  o  * 1  0.2  x 1  1  700 800 900 ,1000 Mil Hamper e turns  1  1100  Ferrite-Core Characteristics (MC-114)  1200  (C) Advantages The most important advantages f the blocking pulse 0  s h i f t - r e g i s t e r ares (1) Stable and non-marginal operation which i s independent of variations i n the core material and the component values. (2) A simple and r e l i a b l e design procedure i s available. The s h i f t - r e g i s t e r can adjust i t s e l f i n switching time and output voltage to cover any small error i n design consideration. (3) A means of completely blocking the transfer of energy i n a d i r e c t i o n opposite to that of the information flow. This allows high-speed  operation with comparatively  low-  power d i s s i p a t i o n i n the transfer loop. 6.4.2  The actual c i r c u i t (Figure  6.10)  The divided negative input signal pulse coming through  turns on the transistor T ^ .  Thus, a 40 ma  current flows through the input winding V^. of the s h i f t register.  The time-constant  switching transistor T ^  of the input c i r c u i t of the  i s arranged so that no d.c.  restoration i s necessary for the 48 kc pulses. Wj i s 25 turns which gives a mmf  of 1 amp-turn.  According to the characteristic curve (Figure 6.9) MC114  of the  f e r r i t e - c o r e , the switching time i s 0.7 \is for a  of 1 amp-turn.  But due to the unavoidable  leakage  flux  mmf  Output Windings to Adding C i r c u i t  -12V  Figure 6„10 Input Current Generator and the Ferrite-Core Shift-Register 11 D to D =1N497 T  = 2 N 4 0 4  5  16  R =5.6K 30  F  x  to F =F-394 6  Ferramic Cores (MC 114)  R =2?0 31  R =270 V, to W =12 turns Wg=6 turns 32  c  W^=25 turns Wgto W^ =50 turns  C =0o00iuf  W, =30 turns 13" ^14 *° ^19 5^ turns  C =0o01uf  2  o  =  6  C  22 27  t  o  c  26  = 0 o 0 2 , i f  and the small losses on W^  p  W^ and Wg,  the actual mmf  used  for switching i s only 0.8 amp-turns which gives a switching time of about 1 us. After "writing" the input signal into the f i r s t core of the s h i f t - r e g i s t e r , the driving current pulse s h i f t s the signal down the r e g i s t e r .  Whenever the signal stored i n a  core i s shifted by the driving pulse, an output appears at the output winding of the core. ^14  ^° ^19^  a r e  *  n e n  The 4 v o l t outputs  applied to the adding  circuit.  A l l the windings and the storage capacitance are the same as i n the previous design except W^ and ^^j" 0.01  uf  ^e  i s just an energy container for core F^.  provides the leakage path for the energy stored i n ^27° The combination  of C^j  and R ^  i s arranged to give a proper  termination for the register so that the operation of the register i s not interfered with by the irregular output of F^ which occurs for bad terminating conditions.  Thus, W^  i s only 6 turns which matches ^27° As shown i n Figure 6.7  ( f ) , the output pulse shape  of the s h i f t - r e g i s t e r i s not regular.  Besides, the pulse  height and width changes s l i g h t l y with the signal load of the register.  This i s due to the change of driving mmf  with  different signal load thereby changing the switching time slightly.  Therefore, we cannot depend on the exact pulse  height or size to generate a definite amount of quantized  current for use i n the adding circuito  The following adding  c i r c u i t arrangement enables us to add a l l the quantized signal currents independently of the i r r e g u l a r i t y i n the output pulse shape« 6<,5 The Adding C i r c u i t and the Emitter-Follower (Figure 6<>ll) -6V  -12V  OV  -4V  Figure 6.11 Adding C i r c u i t and the Emitter-Follower  12  R =12K  13  R_,=6o 8K  T T D R R  =2N384 =2N1304 to D =lN497 =47K =27K  1 7  33  34  2g  35  36 R =3 o 3K R g=2 o 2K R =100K 37  3  39  R =50K R. 20K 41 R„ 42^10K  R  4Q  R  1=  R  o  R =5K ' R =2K  45 46 47  43  44  Since the output pulses of the register are only about 1»2 us, a fast 2N384 transistor  i s used for T,-. As  mentioned i n 4o3o2, T^  2  must be operated i n the f l a t response  region of the a vs I  characteristic curve to eliminate the c  non-linearity and maintain I ^ and I as possible.  We , therefore, bias T^  of about 1 ma flowing through  2  a f t 2  s close together  with a constant current  into the emitter of  T^ , 2  and employ a unit quantized current of about 30 ua. Diodes D ^ D^y to D 2 2  to Dgg are normally non-conducting, while  are normally conducting  signal pulses from W^  to W^g  The 4 v o l t positive"  0  turn off diodes D ^  to  D ; 22  thus, the respective quantized currents flow through D ^ Dg 2  into the emitter of T^ „ 2  The quantized currents can be  adjusted by varying potentiometers R^g *° ^44° d i g i t output i s absent from W^, ducting and D g 2  to  D  ^  * e 1st n  w i l l be s t i l l  22  con-  non-conducting, so that the quantized 1st  d i g i t current cannot be added into T^ „ 2  The adding c i r c u i t  thus adds the existing output signal pulses only. The -4V, base voltage of T^  2  and the -6V,  output  winding reference voltage are chosen so that the adding c i r c u i t i s not affected by any zero disturbed output from W^  4  to W^g»  The quantized signal currents from T^  2  flowing  through R g give the added analog signal pulse which i s then 4  passed through the emitter-follower T ^  to the transistor  gate. In order to open the transistor gate at the proper frequency and phase, we need a frequency divider pulse generator and a framing control,  Figure 6.12  Ferrite-Core Counting Circuit, Frequency Divider Pulse Generator and the Framing Control  T ,T =2N384  ¥ =25T  a  T ,T =2N247  W =10T  R  T ,T =2N404  ¥ =8T  14  15  18  19  16  17  20  21  22  29 37= ^23 F„=F-492, ferrite-W,,.=60T ' core (MC 114) D  t  o  D  1 N 4 9 7  = 2 2 T  48  , R  49  = l o 2 K  50' 51 R^ =3 o 3K a  = : 2 2 K  2  R ,=22K K  R .,R__=100 54' 55 K  R  56  = 2 2 K  R  R  R  R  57 58 59 60  R  61  R  62  =18K  R^ =2 o 2K  C =1000 uuf  R =470K  C =250 uuf  3  64  =33K  32  C ,C =150 uuf C =0o5 uf C =0o2 uf C = 100 uuf 16  17  C  2go  33  34  lg  =330K  31  C = 1 5 0 uuf C =0o01 uf 29  35  C =200 uuf 3Q  ON CO  6.6 Ferrite-core Counting C i r c u i t , Frequency Divider Pulse Generator and the framing Control (Figure 6 . 1 2 ) The frequency divider pulse generator (T-^ and T ^ ) i s a standard monostable pulse generator which generates a pulse of 1  0  5 us width.  going pulse pips through C^y,  D . P o ' +  I t i s triggered by the p o s i t i v e of the driving pulse generator  The reference voltage of the triggering pips  i s the capacitor voltage of C^j;. When the voltage of C ^ r i s e s to - 2 V ,  a D.P.'+ pulse goes through D,,^ to the base  of T^(- thereby cutting off the normally conducting T ^ . A dividing pulse i s thus generated. i s lower than - 2 V ,  Vhen the voltage of C^^  D g i s non-conducting.  Hence, the  2  incoming pips cannot trigger the frequency divider pulse generator.  The waveforms of (a) the triggering D.P.'+  pulses (b) the base reference voltage of T^^, and (c) the frequency divider pulse generator output, are shown i n Figure 6 . 1 3 . The f e r r i t e - c o r e (F^) counting c i r c u i t i s devised to change the voltage on C ^ thereby controlling the repetition frequency of the frequency divider pulse generator.  T^j i s triggered by the negative D.P.- pulse of the  driving pulse generator through the coupling capacitor C^g° When the core Fy has been reset by ^^, the current flowing T  through W Thus, W  22  23  tends to set the core to i t s o r i g i n a l state. generates an emf i n a d i r e c t i o n which increases  the base current flowing through ^^1°  T  h  e  increasing base  gure 6c13  Waveforms of the Frequency Divider  Figure 6=14  Waveforms of the Ferrite-Core Counting C i r c u i t  current of through  boosts the collector current flowing again increasing the base current itself„  This regenerative action continues u n t i l F^ i s set by T ^ When  e  i s set, the next DoP.- pulse cannot i n i t i a t e the  regenerative action u n t i l F^. i s again reset by T ^ . T^  i s triggered by the positive pulse from the  frequency divider pulse generator through C^Q. The regenerative action similar to T ^ i s i n i t i a t e d by the t r a i l i n g edge of the dividing pulse. current passing through W Q resets F^.. 2  The resulting large At the same time  the induced emf of W ^ discharges C^^ to about -11V through D 2» 3  However, the voltage of C^^ i s set to -10V due to the  -10V voltage supply at the junction point of D^-j and D^g. Capacitor C^^ i s then charged by the D.P.+ pulse which i s coupled through  Thus, the voltage on C^^ rises step  by step. During the rise of the C.^ voltage, the frequency divider pulse generator cannot be triggered by D<,P' + p u l s e Whenever C ^ i s charged to -2V, the triggering D.P.'+ pulse passes through D,,^ and triggers the pulse generator.  The  dividing pulse F.D.+ i s thus generated by the frequency divider pulse generator.  The t r a i l i n g edge of the positive  dividing pulse then i n i t i a t e s the regenerative action of T^g which s h i f t s the state of F^ thereby discharging  C-J-J..  By means of this cycle, dividing pulses of the desired  frequency are generated.  The dividing ratio can be changed  by varying the potentiometer R(jg°  The time relationships of  (a) Voltage on capacitor  (b) Collector voltage of  (c) Collector voltage of T ^  are shown i n Figure  The framing control (T-^g and T ^ )  T^  6.14.  i s a monostable  pulse generator with a pulse width of about 0.2 sec.  This  long pulse i s i n i t i a t e d by a manual switch which connects R^  to the OV voltage supply.  This switching action turns  off T^£ thereby generating the long pulse. pulse at the collector of T ^  The negative  i s connected to C ^  i n order  to give some additional charge on C^^ f o r the framing purpose. The additional charge required i s induced by the t r a i l i n g edge of the 0.2  sec pulse.  This r i s i n g edge  allows a fixed amount of charge to pass through R^  and  into C-j^c  for the  D.J<J  i s used to set the d.c. l e v e l of C ^  i n i t i a l decay of the 0.2  sec negative pulse.  We  can,  therefore, advance the dividing pulse d i g i t by d i g i t manually. The pulse F.D.+  i s then applied to the transistor  gate. 6.7 The Transistor Gate and the Output C i r c u i t  (Figure  6d5)  Many gates have been employed for the output gating purpose.  Due to the f i n i t e signal pulse width of  the adding c i r c u i t and the large current for operating the  73  gate, the most satisfactory gate i s the transistor gate (^20 and ^21^° i s normally on while  i  s  normally o f f . When  the large F.D.+ pulse i s applied to T22 through  T2^ i s  cut off and the voltage on the emitter rises toward -4V. However, when the emitter voltage reaches the level of the base of T ^ Q , i t i s clamped by the signal on the base of ^20° Therefore,  i s charged up to the signal l e v e l through D-jg.  The signal voltage on  then discharges toward the  -18V voltage supply through R ^ and the input resistance of Tg2»  In order to retain the maximum output power, the time  constant of C^g and i t s discharging resistance Predesigned so that the "level 63" signal voltage decays exponentially to the zero signal level at the end of the sampling period. Thus, we obtain an exponentially decreasing output with the maximum possible output power. i The double emitter-follower (T22  a n < 1 T  23^ *  n e n  supplies the necessary low impedance signal to the equalizer and f i l t e r  combination.  -12V  -18V  -4V Figure 6<,15 Transistor Gate and the Output C i r c u i t T ,T oT =2N1304 13  22  23  T ,T =2N404 2()  21  D =1N497 38  R R R R  =270 =1K =10K =1M  47  65  66  67  R R C C  68  69  35  36  =33K =lo5K =Oo01uf =200uf  6 0 8 F i l t e r and Equalizer Design Since the signal i s sampled into 8 kc amplitude modulated pulses by the sampler, the maximum frequency component of our signal i s r e s t r i c t e d to 4 kc. Thus, any higher frequency component introduced by the exponentially decreasing output waveform of the decoder should be f i l t e r e d out. The f i l t e r shown i n Figure 6,16 i s designed to have a severe cut-off at 4 kc. A three-section low-pass  filter  i s employed, using one constant-K section and two m-derived  75  m-derived Section (m=0o434)  Constant K Section  m-derived Section (m=0o6224!  Figure 6016 The Low Pass F i l t e r s L =51.75 mh L =119o2 mh b  L =7404 mh  c  C =0.0115 uf a rC =0o02632 uf  C =f„=0 0265 uf e x ^ Cg =C.=0.0165 uf 1  C =0o0115 uf c 4  C =0 013 uf  a  b  o  R  h  0  r  Figure 6.17  5  Equalizer and F i l t e r  L =60 -130 mh  Ry Q=l o 2K  C =0 038 uf  L =15-60 mh  R =lo2K  C =0.043 uf  L ,L =30-130 mh  C =0 0115 uf  C =0o013 uf  C =0o0263 uf  C =Oo0165 uf  2  3  4  5  71  37  3g  o  3g  o  40  41  42  76  sections.  The constant resistance i s designed to be 1.5 K.  The values of m are 0 434 and 0.6225 respectively.. o  The frequency component of the exponentially decreasing waveform i s the Fourier transform  TC C  n  =  2TC  dt  =  e  -(a+jto)TC _ (a+ja>)K e  2n(a+3«)  -TC  where a = time constant of the waveform The magnitude of C  is,  N  Sinh HOC  n  Tt  The semi-log curve of the relative C V S R  w  i s shown i n  F i g . 6.18 (a). The actual measured f i l t e r response i s shown i n Figure 6.18 (b). Thus, we need an equalizer to compensate for the high frequency attenuation of curve (c) which i s the product of (a) and (b). The equalizer formed by B J Q »  and  i s shown i n  Figure 8.4. The transfer function of the equalizer i s , R  f(u>) =  B  71 + 3 2  7  ttL  0  + B  7  + 3 « L  1  2  Its magnitude i s ,  |f(«)U  + V  /  ( B  7  0  + B  7  U>L ) 2  / 4 - (  T  T  L  2  2  )  :  77  The r e l a t i v e magnitude jf(«)| vs w i s shown bycurve (d) i n Figure  60I80  This i s the open-circuit  transfer function of the equalizer and w i l l be  modified  when the equalizer i s connected to the f i l t e r as i n figure  6ol7»  The over-all transfer function for  the whole system should now  show a f l a t response and  sharp cut-off as i l l u s t r a t e d i n figure 6.18(e). The actual equalizer and f i l t e r combination i s shown i n Figure 6 17» 0  7.  PUTTING THE DECODEE INTO OPERATION Before putting_the decoder into operation, the  following adjustments must be made  c  7 o l Adjustment of t h e . C r i t i c a l Level of the Eepeater The c r i t i c a l l e v e l of the repeater should be adjusted to half the height of the binary signal pulses. The adjustment proceeds as followss (1) Feed the standard binary signal pulse to T^ through C^. ( 2 ) Adjust E  2  so that the pulse applied to C  2  i s just half  of the standard signal s i z e . (3) With t h i s half size standard signal applied to the repeater through C , adjust E^ so that the repeater just 2  gives an output  6  The c r i t i c a l condition i s obtained by  f i r s t setting the mid-point of B,. to OV. then decreasing i t s voltage u n t i l the repeater f i r e s . 7 . 2 Adjustment of the Timing and Framing System (1) Adjust L^ so that i t s free-running o s c i l l a t i n g  frequency  i s the same as that of the incoming signal. (2)  The frequency dividing ratio must be changed by varying  E^g to a value equal to the coding-digit n of the incoming signal. (3) Change the value of C^  2  so that the framing control  advances the dividing pulse F.D.+ d i g i t by d i g i t .  7.3 Adjustment of the Adding C i r c u i t The simplest procedure i s to adjust the levels corresponding 2  output  to input signals representing the  l e v e l , where x = 0, 1, 2, . . . n«  With such an input  ( i . e . only one pulse present i n the whole sampling period) the output at the collector of T ^ O X  representing 2 , 2 , . . . and 2  ii  i s a series of n pulses levels r e s p e c t i v e l y  0  Thus, we can adjust R^o, ^° ^44 ^° give every pulse the desired quantized height. (Note, the quantized current f o r 2° l e v e l i s around 30  ua.)  I f greater accuracy i s required, the following comparison i s recommended. (1) Make the above adjustment f i r s t . (2) Supply "level 3" signal code pulses, and record the l e v e l 3 output pulse height. and adjust R^  Then supply "level 4" pulses  to make the output pulse exactly 4/3  times  that of level 3. 3  4  (3) Likewise, compare levels 2 , 2 , 2 31 respectively.  5 with levels 7, 15,  8. PERFORMANCE OF THE SYSTEM 8ol S t a b i l i t y of the Timing System In order to re-time the incoming pulses s a t i s f a c t o r i l y the zero l e v e l signal corresponding to pulse pattern 9  000000 i s never transmittedo  Thus, we have at least one  binary pulse i n every sampling period with which to synchronize the slave o s c i l l a t o r  0  Timing s t a b i l i t y becomes more precarious as the number of d i g i t s i n the code i s increased.  However the 9  timing system constructed was stable for codes of up to 8 digitso  With a 6-digit coding signal, t h i s system has  been tested for over two hours without any i n s t a b i l i t y . The manual framing control was found quite satisfactory.  In order to advance the dividing pulse one  d i g i t at a time, the manual switching action must be completed within 0.2 sec.  A slow switching action may  advance the dividing pulse two or more d i g i t s per switching. 8.2 L i n e a r i t y of the Coder plus Decoder 8.2.1  Test Arrangement In order to test the l i n e a r i t y of the over-all  system consisting of Hafer's coder and s h i f t - r e g i s t e r decoder, the arrangement shown i n Figure 8.1 was used. The coder was f i r s t adjusted to suit the battery and temperature conditions.  The adjusting procedures  suggested by Hafer i n reference 3 were used.  82  The input signal was a saw-tooth voltage taken from an oscilloscopeo  This l i n e a r l y increasing signal i s  converted by the sampler into analog signal pulses»  The  analog signal i s then transformed to binary form by the coder.  After passing the repeater and the decoder, the  binary signal i s transformed back to i t s analog form  n  F i n a l l y , the analog signal from the output of the decoder i s passed through the equalizer and f i l t e r  combination  recovering i t s o r i g i n a l l i n e a r l y increasing form. 8.2.2 Result From the l i n e a r i t y test, some non-linearity i s observed.  This was mainly due to the coder.  Nevertheless,  t h i s system i s satisfactory for use i n telephony or similar applications.  The tested results at s i x . four  and two coding d i g i t are shown i n Figure 8.5. The non-linearity i n the coder arises from two sources.  ( l ) The change of loop gain due to temperature  change and any s l i g h t change of voltage supply.  This  e f f e c t can be seen most pronouncedly at l e v e l 16, 32 and 48 of Figure 8.5 (a). (2) The smaller value of a f o r small c i r c u l a t i n g signal. This can be seen from the slow—rising slopes of Figure 8.5 (a) just after l e v e l 0, 16, 32, 48. However, the d i g i t currents representing l e v e l 16 and 32 were i n t e n t i o n a l l y raised i n the decoder to  Figure 8 2 C  Linearity Test  compensate f o r the n o n - l i n e a r i t y i n the coder.  The  a r t i f i c i a l n o n - l i n e a r i t y of the decoder i s more pronounced i n Figure 8.5 (b). In t h i s f i g u r e  s  the i r r e g u l a r i t y i n the h o r i z o n t a l  step s i z e i s due to the coder n o n - l i n e a r i t y while the v e r t i c a l step i r r e g u l a r i t y i s due to the compensating decoder n o n - l i n e a r i t y .  9o CONCLUSION The object of t h i s work was to f i n d an economical design of a transistorized PCM decoder for transmitting speech«  The f i r s t design, using c i r c u l a t i n g pulses,  proved to have fundamental d i f f i c u l t i e s and was abandoned The second design used a ferrite-core shift-register„  0  This  s h i f t - r e g i s t e r decoder was found to be very suitable, and i t i s highly recommended for this type of applications The decoder uses only readily available design i s not c r i t i c a l .  components and the  Good l i n e a r i t y was achieved and  f a i r s t a b i l i t y against temperature change and battery voltage d r i f t o The existing c i r c u i t could be made to handle at least 3 channels of 4kc speech. high-power transistor  By employing one faster,  (such as 2G 240) and possibly  faster f e r r i t e s , the shift=register megacycle range„  can be operated i n the  Then the decoding c i r c u i t could handle  10 to 20 channelso  Further s i m p l i f i c a t i o n of the c i r c u i t r y might result from the use of multi-aperture f e r r i t e - c o r e s , and t h i s p o s s i b i l i t y would seem to be worth  investigating  0  From the result of the test on the coder plus decoder system, i t appeared that the system i s presently limited by the i n s t a b i l i t y and non-linearity Further work on this coder seems warranted.,  of the coder.  86  There i s , however, l i t t l e doubt t h a t a r e l i a b l e and r e a s o n a b l y s i m p l e PCM  system can be c o n s t r u c t e d  3 u s i n g the coder d e s i g n developed by H a f e r developed i n t h i s t h e s i s < >  and the decoder  87  10. REFERENCES 1. De Jager, P,, "Deltamodulation", P h i l i p s Research Reports, Eindhoven, Netherlands, v o l . 7, 1952. 2. Malthaner, W.A., "ESSEXs A New Concept i n Telephone Communications", B e l l Laboratories Record, February 1961. 3. Hafer, R.A., "A Coder f o r Pulse Code Modulation Using C i r c u l a t e d Pulses", M.A.Sc. Thesis,, U n i v e r s i t y of B r i t i s h Columbia, ( E l e c t r i c a l Engineering); August, 1959. 4. Meachan, L.A., Peterson, E., "Experimental Multichannel Pulse Code Modulation System of T o l l Quality", B e l l System Technical Journals v o l . 27, J u l y 1948. 5. Sears, R.W.,  "Electron Beam D e f l e c t i o n Tube f o r Pulse Code Modulation", B e l l System Technical Journals v o l . 27, J u l y 1948,  6. Goodal, V.M., "Telephony by Pulse Code Modulation", B e l l System Technical J o u r n a l , v o l . 26, J u l y 1947. 7. Fedida, S., "A System of Pulse Code Modulation", E l e c t r o n i c Engineering, v o l . 24, August 1952. 8. Block, H.S., Edson, J.O., "Pulse Code Modulation", Transactions, v o l . 66, 1947.  AoI.EoE.  9. Carbrey, R.Lo, "Decoding i n Pulse Code Modulation", B e l l Laboratories Record, v o l . 26, November 1948. 10. Flood, J.E., "Time-Division M u l t i p l e x Systems", E l e c t r o n i c Engineering, v o l . 25, January 1953. 11. K i r b y , H.D.B., "A Time-Sharing System of M u l t i p l e x " , E l e c t r o n i c Engineering, v o l . 21, 1949. 12. De Lange, 0„E., "The Timing of High-Speed Regenerative Repeaters", B e l l System Technical J o u r n a l , v o l . 37, November 1958. 13. Johanson, A.E., "Timing Control f o r PCM", B e l l Laboratories Record, v o l . 27, January 1949.  14. Manley, J»M», "Synchronization f o r the PCM Receiver"? B e l l Laboratories Record,vole 27, February 1949o 15o  Shea RoF„, Transistor C i r c u i t Engineering Wiley & Sons, I n c , 1957 = 9  John  16, Wang, A. and Woo, ¥.D. " S t a t i c Magnetic Storage and Delay L i n e " , Journal of Applied Physics, v o l . 21, S  1950,  17° Kodis, Ruhman and Woo, "Magnetic S h i f t Register Using One Core per B i t " , LR.E. Convention Record. Part 7, 1953c  l8o Sands, E.A., "Behaviour of Rectangular Hysteresis Loop Magnetic M a t e r i a l Under Current Pulse Conditions" Procedings of the LR.E,, v o L 40, October 1952c 19o Newhouse and Prywes, "High Speed S h i f t Register Using One Core per B i t " , IoR.E. Transactions, September 1956, 20. Shannon, C.E., "A Mathematical Theory of Communication" B e l l System Technical Journal , v o l e 27, J u l y , October 1948. 21. O l i v e r , B.M., P i e r c e , J,R,, Shannon, C.E., "The Philosophy of PCM", Proceedings o f the I.R.E., v o l . 36, 1948. 22. Carbrey, R.L., "Video Transmission over Telephone Cable P a i r s by Pulse Code Modulation", v o L 48, Proceedings of the IcR,E., September 1960. 23. Millman, J . and Taub, H,, Pulse and D i g i t a l C i r c u i t s , New York, McGraw-Hill, 1956. 24. Schwartz, M., Information Transmission, Modulation and Noise, New York, McGraw-Hill, 1959,  

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