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The design of a medium-scale hybrid interface Marston, Glendon Peter 1967

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THE DESIGN OP A MEDIUM-SCALE HYBRID INTERFACE by GLENDON PETER MARSTON B . A . S c , U n i v e r s i t y of B r i t i s h Columbia, 1965 A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE i n the Department of E l e c t r i c a l E n g i n e e r i n g We a c c e p t t h i s t h e s i s as co n f o r m i n g t o the s t a n d a r d s r e q u i r e d from c a n d i d a t e s f o r the degree of Master of A p p l i e d S c i e n c e Members of the Department of E l e c t r i c a l E n g i n e e r i n g THE UNIVERSITY OF BRITISH COLUMBIA May, 1967 In p r e s e n t i n g t h i s t h e s i s i n p a r t i a l f u l f i l m e n t o f the r e q u i r e m e n t s f o r an advanced d e g r e e a t the U n i v e r s i t y o f B r i t i s h C o l u m b i a , I a g r e e t h a t t h e L i b r a r y s h a l l make i t f r e e l y a v a i l a b l e f o r r e f e r e n c e and s t u d y . I f u r t h e r a g r e e t h a t p e r m i s s i o n f o r e x t e n s i v e c o p y i n g o f t h i s t h e s i s f o r s c h o l a r l y p u r p o s e s may be g r a n t e d by the Head o f my D e p a r t m e n t o r by h i s r e p r e s e n t a t i v e s I t i s u n d e r s t o o d t h a t c o p y i n g o r p u b l i c a t i o n o f t h i s t h e s i s f o r f i n a n c i a l g a i n s h a l l no t be a l l o w e d w i t h o u t my w r i t t e n p e r m i s s i o n . D e p a r t m e n t o f £ L 6 C f | < . ( C ^ L £ M 6 f K i g g f tIK\<& Ths U n i v e r s i t y o f B r i t i s h C o l u m b i a V a n c o u v e r 8 , Canada ABSTRACT The most g e n e r a l l y u s e f u l combination of analog and d i g i t a l equipment p o s s i b l e i s a hybr i d i n s t a l l a t i o n which includes a general purpose d i g i t a l computer and a general purpose analog computer, w i t h a f l e x i b l e i n t e r f a c e between the two machines. This t h e s i s contains a d e t a i l e d d e s c r i p t i o n of a hy b r i d i n t e r f a c e designed to l i n k a DEC PDP-9 d i g i t a l computer to an EAI Pace 231R-V analog computer and other equipment. Double b u f f e r i n g i s provided on d i g i t a l output channels from the PDP-9, i n c l u d i n g those s e r v i c i n g d i g i t a l - t o - a n a l o g (D/A) converters, l o a d i n g from b u f f e r r e g i s t e r s to output r e g i s t e r s can be commanded from e i t h e r the analog or the d i g i t a l s i de of the i n t e r f a c e . A s i x t e e n channel m u l t i p l e x e r w i t h a s e t t l i n g time of l e s s than two microseconds has been designed and i s employed w i t h a twelve b i t a n a l o g - t o - d i g i t a l (A/D) converter f o r high speed data t r a n s f e r s . The d i g i t a l voltmeter and s i g n a l s e l e c t o r i n the analog computer are operated together to provide a low speed 540-point multiplexer-A/D converter. The s i g n a l s e l e c t o r , mode c o n t r o l s , and servo-set potentiometers of the analog computer can be operated on command from the PDP-9. I n d i v i d u a l mode c o n t r o l of each of s i x t e e n i n t e g r a t o r s i s a l s o provided. i i TABLE OP CONTENTS Page ABSTRACT i i TABLE OP CONTENTS ........................... i i i LIST OP ILLUSTRATIONS ......... v LIST OP TABLES .............................. v i i ACKNOWLEDGEMENT v i i i 1. INTRODUCTION ............................ 1 2. PDP-9 INPUT/OUTPUT ................. . 4 2 .1 Input and Output B u f f e r s ............ 4 2 .3 The Standard Output I n t e r f a c e 9 2 .4 The Standard Input I n t e r f a c e ........ 14 2.5 De v i c e Gate F a c i l i t y 16 3. A/D CONVERSION 17 3.1 A/D Sampling C o n t r o l 17 3.2 A/D Output C o n t r o l 22 4. MULTIPLEXER 27 4.1 The Input Stage 31 4.2 A d d r e s s i n g 37 4.3 The Gate D r i v e C i r c u i t 39 4.4 The FET S w i t c h 41 5. DIGITAL-TO-ANALOG CONVERSION 47 5 .1 The Twelve B i t D/A C o n v e r t e r s 48 5.2 The Seven and Four B i t D/A Conv 5 .3 D i g i t a l By A n a l o g M u l t i p l i c a t i o n .... 50 i i i Page 6. THE INTERRUPT SYSTEM .......... . 54 6.1 Program I n t e r r u p t s 54 6.2 Automatic P r i o r i t y I n t e r r u p t s 57 6.3 P u l s e Shapers 58 7. CONTROL OF THE ANALOG COMPUTER ......... 60 7.1 Mode C o n t r o l ......... .............. 61 7.2 I n t e g r a t o r Mode C o n t r o l ............ 65 7.3 S i g n a l S e l e c t o r C o n t r o l ............ 68 7-3.1 S i g n a l S e l e c t o r Mode C o n t r o l . 68 7.3.2 S i g n a l S e l e c t o r Address 70 7.4 Servo-Set P o t e n t i o m e t e r C o n t r o l s ... 77 7.5 D i g i t a l V o l t m e t e r Readout .......... 80 7.6 P o t e n t i o m e t e r Address Ch e c k i n g 81 APPENDIX I LOGIC LEVEL SYMBOLOGY 83 APPENDIX I I GENERATION OF INITIALIZE PULSES ........................ 84 APPENDIX I I I INPUT/OUTPUT TRANSFER INSTRUCTIONS .................. 85 APPENDIX IV MONOSTABLE PULSE GENERATORS ... 88 APPENDIX V SUGGESTED SYMBOLIC ASSEMBLY LANGUAGE INSTRUCTIONS FOR HYBRID INTERFACE ...................... 89 APPENDIX VI SPECIFICATIONS FOR ANALOG DEVICES INC. OPERATIONAL AMPLIFIERS 106B APPENDIX V I I API INTERFACING MODULE ........ 93 APPENDIX V I I I CONNECTIONS TO.231R-V 94 i v LIST OF ILLUSTRATIONS F i g u r e Page 1- 1 H y b r i d I n t e r f a c e 3 2- 1 PDP-9-to-MRTL C o n v e r t e r 5 2-2 MRTL-to-PDP-9 C o n v e r t e r 5 2—3 Output B u f f e r . . 0 . 0 . 0 . 0 . »•..«•••••• 6 2-4 Input B u f f e r ...................... 8 2-5 R e g i s t e r S e l e c t o r 10 2-6 Standard Output I n t e r f a c e 11 2-7 G e n e r a t i o n of Simultaneous Update Commands ..•.«•««••••..o........... 13 2-8 Standard Input I n t e r f a c e 15 2- 9 D e v i c e F l a g F a c i l i t y C i r c u i t 16 3- 1 Sampling Frequency C o n t r o l U n i t ... 19 3-2 P u l s e G enerator f o r A/D C o n v e r t e r S t a r t C o n v e r s i o n P u l s e 20 3-3 SFC Up Counter 21 3-4 Output L e v e l C o n v e r t e r f o r A/D C o n v e r t e r 22 3- 5 B i n a r y Adder 26 4- 1 M u l t i p l e x e r 28 4-2 U n c e r t a i n t y i n Sample Value 29 4-3 M u l t i p l e x e r Input Stage 33 4-4 O c t a l Decoder 38 4-5 Gate D r i v e C i r c u i t and FET S w i t c h . 39 4-6 FET I n t e r c o n n e c t i o n i n M u l t i p l e x e r 42 4-7 M u l t i p l e x e r Output Waveform ....... 44 4-8 M u l t i p l e x e r Output Waveform ....... 44 4-9 M u l t i p l e x e r Output Waveform ....... 45 v F i g u r e Page 5-1 Twelve B i t D/A C o n v e r t e r s .„...... . 49 5- 2 D i g i t a l by Analog M u l t i p l i e r ...... 52 6- 1 I n t e r r u p t System-PI S e c t i o n ....... 55 6-2 S p e c i a l Nand Gate . . . . ...... . 56 6~"3 -Di f "f©__?©ri"fci£i~fc ox* O O O O O D » © » O O O O I > O O » . O O ' 57 6- 4 I n t e r r u p t System-API S e c t i o n ...... 58 7- 1 231R-V Mode C o n t r o l ............... 62 7-2 P u l s e G enerator ............. ..... . 64 7-3 I n t e g r a t o r Mode C o n t r o l R e l a y D r i v e r 65 7-4 L e v e l C o n v e r t e r f o r E l e c t r o n i c Mode 7-5 S i g n a l S e l e c t o r Mode C o n t r o l ...... 69 7-6 R e l a y D r i v e r ...................... 70 7-7 S i g n a l S e l e c t o r Address C o n t r o l ... 71 7-8 Tens Decoder ...................... 74 7-9 L e v e l C o n v e r t e r .................... 74 7-10 Tens C o n t r o l Network .............. 75 7-11 P u l s e G enerator ................... 77 7-12 S e r v o - s e t P o t e n t i o m e t e r C o n t r o l s .. 78 7-13 DVM Output L e v e l C o n v e r t e r ........ 80 A I I I - 1 IOT I n s t r u c t ! O10. F O X*IIlcl "fc o o o o o o o o o o o o 85 A I I I - 2 IOT I n s t r u c t i o n T i m i n g ............ 87 v i LIST OF TABLES Table Page 3-1 D e s i r e d 2's Complement Code f o r Sy m m e t r i c a l Input Range ............. 23 3-2 U n f o l d e d Output Formats ............. 24 3-3 C o n v e r s i o n of U n f o l d e d B i n a r y Code i n t o 2 ' s Complement ........ . . 25 3- 4 C o n v e r s i o n of U n f o l d e d Binar,y-'!'"Code i n t o 2 ' s Complement .... 25 4- 1 S i g n i f i c a n t E r r o r s i n " t h e A/D L i n k .. 32 7-1 231R-V Mode C o n t r o l Words .... ... 63 7-2 R e l a y S t a t e s and I n t e g r a t o r Mode .... 66 7-3 S i g n a l S e l e c t o r Addresses 73 v i i ACKNOWLEDGEMENT Acknowledgement i s g r a t e f u l l y g i v e n t o the N a t i o n a l R esearch C o u n c i l of Canada f o r f i n a n c i a l s u p p o r t r e c e i v e d under the B l o c k Term Grant A68 i n 1965-66, and f o r a S t u d e n t s h i p r e c e i v e d i n 1966-67= I would l i k e t o thank Dr. J.S. MacDonald, the s u p e r v i s o r of t h i s p r o j e c t , f o r the many v a l u a b l e s u g g e s t i o n s he has o f f e r e d , and f o r always b e i n g a v a i l a b l e t o d i s c u s s d i f f i c u l t i e s and o f f e r encouragement, no ma t t e r how busy he was. I would l i k e t o thank Dr. E.L. S i g u r d s o n f o r r e a d i n g the m a n u s c r i p t and f o r h i s u s e f u l comments. I would a l s o l i k e t o thank Dr. A.D. Moore f o r h i s a d v i c e , Mr. H. Kohne f o r h i s s u g g e s t i o n s and h i s a s s i s t a n c e i n b u i l d i n g t he i n t e r f a c e , and Mr. H. W a l t e r s , f o r h i s a s s i s t a n c e i n o r d e r i n g equipment. Thanks a re a l s o g i v e n t o my w i f e and my mother f o r t h e i r encouragement, t o Mrs. J.S. MacDonald and Mrs. M. Wein f o r t y p i n g the m a n u s c r i p t , and t o my w i f e and my c o l l e a g u e s f o r p r o o f r e a d i n g the m a n u s c r i p t . v i i i 1. INTRODUCTION When a d i g i t a l computer i s coupled t o an a n a l o g computer i n such a way t h a t a two-way exchange of d a t a and control-commands i s a l l o w e d , the r e s u l t i n g i n s t a l l a t i o n i s termed a h y b r i d computer. Many problems which are not e a s i l y s o l v e d on a n a l o g or d i g i t a l computers a l o n e a re q u i t e amenable t o s o l u t i o n on a h y b r i d machine, where the advantages of bo t h types of computation a re t o be had. On a h y b r i d computer, sampled d a t a and computer c o n t r o l l e d systems, w h i c h a r e d e s c r i b e d by b o t h d i s c r e t e and c o n t i n u o u s v a r i a b l e s , can be s t u d i e d ; p a r t i a l d i f f e r e n t i a l e q u a t i o n s can be s o l v e d u s i n g Monte C a r l o t e c h n i q u e s ; l o g i c a l o p e r a t i o n s can be performed i n a n a l o g s i m u l a t i o n s , and c o n t i n u o u s o p e r a t i o n s can be performed i n d i g i t a l s i m u l a t i o n s ; - f u n c t i o n s of two or more v a r i a b l e s can be ge n e r a t e d ; and o r d i n a r y d i f f e r e n t i a l e q u a t i o n s w i t h t r a n s p o r t d e l a y s and s i m u l t a n e o u s d i f f e r e n t i a l e q u a t i o n s w i t h w i d e l y d i f f e r e n t parameters which produce both low~ and h i g h f r e q u e n c i e s i n the s o l u t i o n can be t r e a t e d . I n s h o r t , the h y b r i d computer can be used t o advantage i n a g r e a t many a r e a s . T h i s t h e s i s d e s c r i b e s the d e s i g n of a h y b r i d i n t e r f a c e between a DEC PDP-9 d i g i t a l computer and an EAI Pace 231R-V a n a l o g computer. The PDP-9 has the b a s i c 8K of core memory, and i n c l u d e s an extended a r i t h m e t i c element and an au t o m a t i c p r i o r i t y i n t e r r u p t system. The 231R-V c o n t a i n s 24 summers, 16 i n t e g r a t o r s , 12 m u l t i p l i e r s , 50 s e r v o - s e t p o t e n t i o m e t e r s , 2 2 f u n c t i o n g e n e r a t o r s , and a memory and l o g i c (MLG-) e x p a n s i o n which i n c l u d e s 10 comparators. Both computers are w e l l s u i t e d t o o p e r a t i o n i n a h y b r i d i n s t a l l a t i o n , the PDP-9 because o f i t s f l e x i b l e i n p u t - o u t p u t (I/O) s t r u c t u r e and i t s i n t e r r u p t systems, and the 231R-V because of i t s s e r v o - s e t p o t e n t i o m e t e r s and s i g n a l s e l e c t o r and mode c o n t r o l systems which can be adapted t o respond t o commands from a d i g i t a l computer. The h y b r i d i n t e r f a c e , shown i n F i g u r e 1-1, p r o v i d e s f o r d a t a t r a n s f e r between the two computers, almost f u l l c o n t r o l o f the 231R-V by the PDP-9, and l i m i t e d c o n t r o l of the PDP-9 by the 231B.-V. The t r a n s f e r of d a t a from the d i g i t a l t o the a n a l o g s e c t i o n of the f a c i l i t y i s ac c o m p l i s h e d through a s e t of d o u b l e - b u f f e r e d D/A c o n v e r t e r s , and can be c o n t r o l l e d from e i t h e r the a n a l o g or the d i g i t a l s i d e . Data t r a n s f e r from t h e a n a l o g computer t o t h e PDP-9 i s acc o m p l i s h e d through a s i x t e e n c h a n n e l h i g h speed m u l t i p l e x e r - A / D c o n v e r t e r c o m b i n a t i o n . The A/D c o n v e r t e r i s p r o v i d e d w i t h a programmable s a m p l i n g f r e q u e n c y c o n t r o l . I n a d d i t i o n , the PDP-9 can o b t a i n low speed ac c e s s t o v i r t u a l l y e very p o i n t i n the a n a l o g computer by use of the l a t t e r ' s s i g n a l s e l e c t o r system. Complete mode c o n t r o l of the 231R-V by the PDP-9 i s p r o v i d e d . I n c l u d e d i n t h i s i s the a b i l i t y t o execute i n d i v i d u a l mode c o n t r o l over s i x t e e n i n t e -g r a t o r s . P r o v i s i o n i s a l s o made f o r s e t t i n g and c h e c k i n g the s e r v o - s e t p o t e n t i o m e t e r s i n the 231R-V. Two 4 4 0 - p o s i t i o n p a t c h p a n e l s have been employed, one f o r a n a l o g s i g n a l s and one f o r d i g i t a l s i g n a l s , t o i n c r e a s e i n t e r f a c e f l e x i b i l i t y . A n a l o g and d i g i t a l equipment i n remote l o c a t i o n s can be connected t o the i n t e r f a c e through l i n e s which t e r m i n a t e on these p a n e l s . HYBRID INTERFACE 4 2. PDP-9 INPUT/OUTPUT 2.1 Input and Output B u f f e r s T r a n s f e r s of d a t a between the PDP-9 and the h y b r i d i n t e r -f a c e occur t h r o u g h the PDP-9 I/O bus. whi c h i s connected d i r e c t l y t o the computer's a c c u m u l a t o r . Data f l o w i n g from the I/O bus i n t o the i n t e r f a c e passes t h r o u g h the output b u f f e r , w h i l e t h a t f l o w i n g onto the bus passes t h r o u g h the i n p u t b u f f e r , as shown i n F i g u r e 1-1. I n the b u f f e r s , c o n v e r s i o n from PDP-9 l o g i c l e v e l s t o M o t o r o l a r e s i s t o r - t r a n s i s t o r l o g i c (MRTL) l e v e l s i s performed, and ground i s o l a t i o n between the a n a l o g and d i g i t a l p a r t s of the h y b r i d f a c i l i t y i s o b t a i n e d . M o t o r o l a MC700P s e r i e s MRTL i n t e g r a t e d c i r c u i t s have been used f o r the d i g i t a l c i r c u i t r y i n the i n t e r f a c e . They employ r e s i s t o r - t r a n s i s t o r l o g i c , and t y p i c a l l y r e p r e s e n t a l o g i c a l "1" by a p p r o x i m a t e l y +0.1 v o l t s and a l o g i c a l "0" by a p p r o x i m a t e l y +1.5 v o l t s . A l l o w e d ranges a r e -4.00 t o +0.46 v o l t s and +0.85 t o +4.00 v o l t s r e s p e c t i v e l y . On the I/O bus, the PDP-9 r e p r e s e n t s a "1" by 0 v o l t s and a "0" by -3 v o l t s . PDP-9-to-MRTL c o n v e r t e r s l i k e the one shown i n F i g u r e 2-1 have been employed i n the output b u f f e r f o r l e v e l c o n v e r s i o n . When "V-j--^  i s 0 v o l t s , VQ-TJT i s a p p r o x i m a t e l y +2.4 v o l t s , and when V-QJ i s -3 v o l t s Vg-grji i s a p p r o x i m a t e l y -0.6 v o l t s . Thus the l e v e l c o n v e r t e r a c t s l o g i c a l l y l i k e an i n v e r t e r - i t complements. I n the i n p u t b u f f e r , c o n v e r s i o n from MRTL t o PDP-9 l e v e l s i s a c c o m p l i s h e d w i t h the c i r c u i t shown i n F i g u r e 2-2. Undamped c o l l e c t o r s a r e r e q u i r e d on a l l c i r c u i t s used f o r l o a d i n g the PDP-9 I/O bus. An MRTL l o g i c a l "1" i n p u t g i v e s a PDP-9 l o g i c a l "1" o u t p u t . 5 +3.6 u-. P R O W PDP-9 — Kj KJ Kl ^ — - ° T T 0 W R T U U o G l C 1 / 0 6 0 3 1*4,54 N4IS4 1 N4-t-4- « M .rrrERiTKce F i g u r e 2-1. PDP-9-to-MRTL C o n v e r t e r - 1 5 U; TO PDP-9 I/O BUS 15 Kft PRoM IARTL. —w w— IM4154 2M-636 F i g u r e 2-2. MRTL-to-PDP-9 C o n v e r t e r To e l i m i n a t e p o s s i b l e d e g r a d a t i o n of a n a l o g s i g n a l s due to e x c e s s i v e c u r r e n t f l o w on the a n a l o g computer's h i g h q u a l i t y ground l i n e s , i s o l a t i o n of a n a l o g and d i g i t a l computer grounds has been implemented. P u l s e t r a n s f o r m e r s a re c o n t a i n e d i n the i n p u t and output b u f f e r s , one c o i l of each b e i n g connected t o the d i g i t a l s i d e of the f a c i l i t y , and the o t h e r t o the a n a l o g s i d e . Data and commands are p u l s e d a c r o s s . A b l o c k diagram of the output b u f f e r i s g i v e n i n F i g u r e 2-3. Whenever a d a t a word i s t o be read from the I/O bus, a 400 nanosecond p u l s e i s a p p l i e d t o each of the e i g h t e e n two-- i n p u t nand g a t e s . F o r each b i t which i s a "1", a p u l s e t o FROM PDP-9 fit- D»RECTiOMM_ 16 LINES P D P - 9 - T O - M R T L . CONVERTERS 06) < > INVERTERS (18) < Z- I N P U T l^fcND " Gfvres > B u F P E R A M P L I F I E R S tr\C-i<y*p i • PU_=>£ T U F K K i S F O R l f l E R - j -18 LIMES TO REGISTERS IN-lUTeRFACE" , , RFAOOOT ie - INPUT a pou_e •—— (AC - ?_ « »? (AC 199 P Dl&>Tlv.U COMPUTEft CoWfOTeP, !*e&ivrep. (.SEE Fi&oK a-s.) F i g u r e 2-3- Output B u f f e r 7 ground appears a t the c o r r e s p o n d i n g p u l s e t r a n s f o r m e r o u t p u t . Q u i e s c e n t and "0" ou t p u t s a re D.C. l e v e l s of a p p r o x i m a t e l y +1.5 v o l t s . The secondary c o i l of each p u l s e t r a n s f o r m e r i s t i e d t o +3.6 v o l t s t h rough a 150 ohm r e s i s t o r . Without the r e s i s t o r s , q u i e s c e n t and "0" o u t p u t s would be +3.6 v o l t s and l o a d i n g on the power s u p p l y would be c o n s i d e r a b l y i n c r e a s e d . Because the PDP-9-to-MRTL c o n v e r t e r s i n t r o d u c e a l o g i c a l i n v e r s i o n , i t i s n e c e s s a r y t o i n c l u d e a s e t of i n v e r t e r s i n t he output b u f f e r t o r e s t o r e the i n i t i a l t r u t h v a l u e s . An e x p l a n a t i o n of the symbols used f o r i n d i c a t i n g p u l s e s and l o g i c a l l e v e l s i n the b l o c k diagrams i s g i v e n i n Appendix I . As many as e i g h t y i n t e r f a c e r e g i s t e r s can be connected t o the -output" b u f f e r . Only one r e g i s t e r i s l o a d e d a t a t i m e , however. The d e t j a i l s of output i n t e r f a c e r e g i s t e r c o n s t r u c t i o n and o p e r a t i o n w i l l be d i s c u s s e d i n s e c t i o n 2-3 of the t h e s i s . A b l o c k diagram" of the i n p u t b u f f e r i s g i v e n i n F i g u r e 2-4. P r o v i s i o n i s m a d e f o r l o a d i n g the c o n t e n t s of up t o t w e l v e i n t e r f a c e r e g i s t e r s onto the PDP-9 I/O bus through t h i s b u f f e r . At p r e s e n t , o n l y -four r e g i s t e r s a re connected t o the i n p u t b u f f e r , and only-one of the s e i s the f u l l eighteen, b i t s i z e . Unused i n p u t s t o the nor gates must be t i e d t o ground. The gates can be expanded t o more th a n t w e l v e i n p u t s i f the need a r i s e s . W i t h the e x c e p t i o n of the 231R-V mode c o n t r o l r e g i s t e r , a l l r e g i s t e r s connected t o the i n p u t b u f f e r a re c o n t a i n e d i n s t a n d a r d i n p u t i n t e r f a c e s ( S I I s ) , which are d e s c r i b e d i n s e c t i o n 2.4. FROM INTERFME RSCrlSTeRS I >8 U*4E<3 (3 PEC GKTE^ ) B-FPGR FHAPUF"IERS (.18) < T CotAF-OTER 1 &RoO«^ ti 1 t>\6\TkL PUL<=,e TR&NC,FORtA-RS ^ 1 CONvPoTER N\RTL-To-Pt>P-<) coNvieRxeRS 08) PDP-?j I/o 6 0 S F i g u r e 2-4. Input B u f f e r 2.2 I/O C o n t r o l To c o n t r o l the f l o w of i n f o r m a t i o n t o and from the I/O bus, i n p u t / o u t p u t t r a n s f e r i n s t r u c t i o n s a re used on the P D P-9. S i x xrf t h e e i g h t e e n b i t s i n the i n s t r u c t i o n word' s p e c i f y which i n t e r f a c e r e g i s t e r , o r d e v i c e , i s t o be i n v o l v e d i n the d a t a t r a n s f e r , and t h r e e " b i t s command the i s s u i n g of up t o t h r e e p u l s e s (IO? p u l s e s ) t o execute the i n s t r u c t i o n . A complete, d e s c r i p t i o n of i n p u t / o u t p u t t r a n s f e r i n s t r u c t i o n s i s g i v e n i n Appendix I I I . 9 Decoding of the s i x b i t r e g i s t e r s e l e c t i o n code and g a t i n g of p u l s e s t o the a p p r o p r i a t e r e g i s t e r s are done i n r e g i s t e r s e l e c t o r s l i k e the one shown i n F i g u r e 2-5. I n g e n e r a l , one s e l e c t o r i s used' T o r each r e g i s t e r connected t o the i n p u t or output b u f f e r s ' . T h e r e g i s t e r s e l e c t i o n b i t s must be passed t h r o u g h a s e o ' o f PD ?-9-1 o-MRT L c o n v e r t e r s and b u f f e r a m p l i f i e r s b e f o r e b e i n g s u p p l i e d vo the nand gates i n the s e l e c t o r s . The IOP p u l s e s are-' passed t h r o u g h a s i m i l a r s e t of c o n v e r t e r s and a m p l i f i e r s a f t e r b e i n g s h o r t e n e d from a d u r a t i o n of one m i c r o -second t o 4-00 nanoseconds i n a s e t of W64-0 P u l s e Output C o n v e r t e r s purchased from the D i g i t a l Equipment C o r p o r a t i o n . The p r i n c i p a l output p u l s e s of the r e g i s t e r s e l e c t o r s a re l a b e l l e d I0T1, I0T2, and I0T4. The f u n c t i o n of the update and s i m u l t a n e o u s " u p d a t e commands, which generate I0T4 p u l s e s , w i l l be e x p l a i n e d i n s e c t i o n 2.3 of the t h e s i s . B u f f e r a m p l i f i e r s are" needed' on the s e l e c t o r output l i n e s t o handle the heavy l o a d s encountered when d r i v i n g s e t s of r e g i s t e r c o n t r o l g a t e s . P u l s e t r a n s f o r m e r s m a i n t a i n a n a l o g - d i g i t a l ground i s o l a t i o r _ . : 2.3 " "The" Standard. Output' I n t e r f a c e """"The standard, outrput i n t e r f a c e (SOI) u n i t i s employed i n seven of the n i n e i n t e r f a c e paths c a r r y i n g d a t a from the PDP-9 (see F i g u r e ' 1-1). The s m a l l e s t can accommodate f o u r b i t s , the " l a r g e s t , e i g h t e e n . A b l o c k diagram of an e i g h t e e n b i t SOI i s g i v e n i n F i g u r e 2-6-. Each SOI c o n t a i n s two r e g i s t e r s , a b u f f e r r e g i s t e r and an output r e g i s t e r . The b u f f e r r e g i s t e r p r o v i d e s a temporary 1 0 * fcWERTER NVRTU To PDP-^ I0PI REGISTER ^EXCcTloN BvTS I0P3 - O -o -o GfcTE INSERTER - O l -o sivrE-NIC193P INMERTtR WVC189P -o K\C1%i"P N M > & K T £ ft£>t> P-eaoe^T U N E " OfcTtv. IWT'O P\>£-"5} ^peMJoOT" POL&E To T^6L.\ie wtf>0T N O R IN OUTPUT feOFFER . (f i&.S-i) . CuSet) oViV-V iN ReN>M& O M A OUT O F Pt>P-<)) BoFFeR WAPuFieft IAC199P A BuFFCR AlApuFilSR «\C199P I0P4- civre-1» NOR GKTE NVCT^P UPOKTE P U L S C TP,AM«jfoBAER e.WMiV.'TMiSOOS _ OPDKTC .. KvUTiM-VZE" M>PUCATioi^ POL.SE D\GlTM_ CotApUTER 6fcOOVib P,NALOC COMPUTER GRoOKV&~ ~> IOT I pou.se TPMSFbfeHER fcoFFEft WftPUFlEP, Js p 9 NUtWP POV.SE TRfcHSFofclAER 1^  BUFFER (WMFlEg &JFFER fW>UF\6fc KC.T99P I0T2 IOTA PULSES To INTERFACE' F i g u r e 2-5. R e g i s t e r S e l e c t o r 11 s t o r a g e l o c a t i o n f o r the next word t o he lo a d e d i n t o the output r e g i s t e r ; i t can he loa d e d w i t h o u t d i s t u r b i n g the output r e g i s t e r ' s c o n t e n t s . The b u f f e r r e g i s t e r i s composed of s e t - r e s e t f l i p f l o p s and must i n g e n e r a l be c l e a r e d b e f o r e b e i n g l o a d e d . C l e a r i n g i s ac c o m p l i s h e d w i t h a CLEAR BUFFER REGISTER command, an I0T1 p u l s e . One microsecond l a t e r , a LOAD BUFFER REGISTER command (IQT2 .pulse) can be used t o l o a d the d a t a word b e i n g \% 8iT vJoftO FRoNV I O o T P O T b o F f g f t ! v8 uv ies 9. - iviPoT >4k^D GNT£_i UB) N\CTI7 P V8 p e ^ r e R ^ OUTPUT 18 uwes TO TOT2 TOT\ IOT4 COHN\I\MD PULSES R E G I V C . T R F i g u r e 2-6. Standard Output I n t e r f a c e h e l d on-the PDP-9's I/O bus i n t o the b u f f e r r e g i s t e r t h rough the output b u f f e r d e s c r i b e d i n s e c t i o n 2.1. The nand gates i n the output b u f f e r and those i n the SOI. are s t r o b e d s i m u l t a n e o u s l y t o a c c o m p l i s h t h i s l o a d i n g . The output r e g i s t e r i s composed o f <JK f l i p f l o p s . Because d a t a i s jam t r a n s f e r r e d i n t o i t , t h i s r e g i s t e r does not have to' be c l e a r e d b e f o r e b e i n g l o a d e d w i t h a new word. C l e a r i n g does take p l a c e , however, i m m e d i a t e l y a f t e r power i s a p p l i e d t o t he PDP-9, o r , i f the PDP-9 i s a l r e a d y t u r n e d on, whenever the CAP ( c l e a r a l l f l a g s ) i n s t r u c t i o n o c c u r s or the I/O RESET key on t h e PDP-9 c o n s o l e i s depressed. A b u t t o n l a b e l l e d INITIALIZE INTERFACE has been p r o v i d e d t o produce the c l e a r i n g p u l s e i n instance's where' one does not w i s h t o d i s t u r b the PDP-9 ( d e p r e s s i n g the' I/O RESET key c l e a r s some r e g i s t e r s and t u r n s o f f some f a c i l i t i e s i n the PDP-9). The p u l s e which a c c o m p l i s h e s c l e a r i n g i s termed an INITIALIZE p u l s e . The c i r c u i t , i n which i t i s g e n e r a t e d i s g i v e n i n Appendix I I . Data' i s t r a n s f e r r e d i n t o the output r e g i s t e r from the b u f f e r r e g i s t e r w i t h a LOAD OUTPUT REGISTER command ( I 0 T 4 ) . As i s shown i n F i g u r e 2-5, t h i s command can be generated with, an IOT i n s t r u c t i o n , or w i t h an UPDATE or SIMULTANEOUS UPDATE command. I f an IOT i n s t r u c t i o n i s used, the l o a d i n g can take p l a c e one m i c r o s e c o n d • a f t e r the b u f f e r r e g i s t e r has been l o a d e d , or a t a l a t e r t i m e , as d e s i r e d . An UPDATE command can o r i g i n a t e o u t s i d e t h e i n t e r f a c e , i n a comparator of the a n a l o g computer or i n a remote l o c a t i o n , and i s s u p p l i e d from a t e r m i n a l on the 440 - h o l e d i g i t a l p a t c h p a n e l (see F i g u r e 1-1). A SIMULTANEOUS 13 UPDATE command, which, can he used t o s i m u l t a n e o u s l y update s e v e r a l SOIs i s generated w i t h the hardware shown i n F i g u r e 2-7. The s t a t u s of accu m u l a t o r h i t s 0 t o 7 i n c l u s i v e determines which of the seven SOIs w i l l be updated when the SIMULTANEOUS UPDATE p u l s e i s i s s u e d by the r e g i s t e r s e l e c t o r . The accumulator word 000000000001111111 2 w i l l cause a l l seven t o be updated, w h i l e 000000000000000011,-,, f o r example, w i l l update o n l y two. 8 ©IT \NORO FRot* POP-*) IOT2. PuuSE FRoW\ 8 U>»6S 8 u»-es ONE V.H.G To T H . " . ^ -OF EfcCVA RG&VWeR IviTcRFKCG F i g u r e 2-7. G e n e r a t i o n of Simultaneous Update Commands Most o f the SOIs are t e r m i n a t e d on the 440-hole p a t c h p a n e l f o r d i g i t a l s i g n a l s , where t h e y can be used as r e q u i r e d t o s u p p l y D/A c o n v e r t e r c o e f f i c i e n t s , m u l t i p l e x e r a d d r e s s e s , commands f o r t h e s i g n a l s e l e c t o r , i n t e g r a t o r s , and s e r v o - s e t '_. p o t e n t i o m e t e r s i n the and d i g i t a l d a t a t o r e g i s t e r s i n remote l o c a t i o n s . The use of b u f f e r r e g i s t e r s i n the SOIs o f f e r s s e v e r a l advantages. I t s i m p l i f i e s programming s i n c e computa-t i o n a l r e s u l t s which a re t o be s u p p l i e d t o the i n t e r f a c e can o f t e n be s t o r e d d i r e c t l y i n the b u f f e r r e g i s t e r s r a t h e r t h a n i n co r e . " I t a l s o a l l o w s u p d a t i n g t o be performed on command from the a n a l o g computer or a remote s o u r c e , and i t p e r m i t s s i m u l -taneous u p d a t i n g , which e l e m i n a t e s time-skew problems on the D/A c o n v e r t e r s . The IOT i n s t r u c t i o n s t o r e g i s t e r s e l e c t o r s must a t pr e s e n t be w r i t t e n i n s y m b o l i c assembly language or o'ctal code. A l i s t i n g of the mnemonics used and t h e i r c o r r e s p o n d i n g o c t a l codes i s g i v e n i n Appendix V. 2 . 4 ' The - Standard Input I n t e r f a c e D i g i t a l d a t a t o be read i n t o the PDP-9 i s handled by s t a n d a r d i n p u t i n t e r f a c e s ( S I I s ) . Each S I I c o n t a i n s a b u f f e r r e g i s t e r and two s e t s of nandl'gates, one s e t f o r l o a d i n g the b u f f e r r e g i s t e r from a p e r i p h e r a l d e v i c e , and the o t h e r f o r r e a d i n g the b u f f e r r e g i s t e r ' s c o n t e n t s onto the PDP-9's I/O bus. A t y p i c a l s t a n d a r d i n p u t i n t e r f a c e i s shown i n F i g u r e 2-8. The b u f f e r r e g i s t e r can be l o a d e d on command from the PDP-9 or w i t h a p u l s e i s s u e d by the d e v i c e which i s t o be the source of the data... The PDP-9 a l o n e i s s u e s the LOAD I/O BUS 15 F R O M OR \8 L,\*iE^ > 2-\nPoT NfM-*b GATES © O F F E R REfeWTCR WsCMP 8 - IMPUT NK^O GKTtS ^ WESTER NO<? GMe C L E A R B U F F E R R E 6 > S T E R C O M M A N D U C A D I / O B O S PULSE FRONl PfVTCH IOTI IOT4-ioTa P U U ^ E S FRO*\ RE&iVTER SELECTOR vt^PoT &oF£ER F i g u r e 2-8. Standard Input I n t e r f a c e and CLEAR I/O BUFFER REGISTER commands. A monostable p u l s e g e n e r a t o r , d e s c r i b e d i n Appendix IV, must be i n s e r t e d i n the I0T2 l i n e of the r e g i s t e r s e l e c t o r ( a t p o i n t A i n F i g u r e 2-5) to,produce the one microsecond p u l s e which i s r e q u i r e d f o r l o a d i n g i n f o r m a t i o n onto the I/O bus and f o r s t r o b i n g the PDP-9's read r e q u e s t line."'' The b u f f e r r e g i s t e r i s n o r m a l l y c l e a r e d one microsecond a f t e r i t s c o n t e n t s have been r e a d out, by an I0T4 p u l s e g e n e r a t e d w i t h an I0P4 from the PDP-9. The r e g i s t e r i s a l s o c l e a r e d whenever an INITIALIZE p u l s e i s generated (which 16 i n t u r n g e n e r a t e s an I 0 T 4 ) . 2.5 D e v i c e F l a g F a c i l i t y When d e a l i n g w i t h an e x t e r n a l d e v i c e connected t o a d i g i t a l computer, i t i s o f t e n c o n v e n i e n t t o perform a b r a n c h i n g o p e r a t i o n i n the program^based on the s t a t u s of a f l a g a s s o c i a t e d w i t h t h a t d e v i c e . The I / O s k i p f a c i l i t y on the PDP-9 a l l o w s one t o do t h i s and the I / O read s t a t u s f a c i l i t y a l l o w s one to l o a d the f l a g s i n t o the ac c u m u l a t o r . To enable i n t e r f a c e u s e r s t o employ these two f e a t u r e s of the PDP-9, a d e v i c e f l a g f a c i l i t y c a p able of h a n d l i n g t h r e e f l a g s has been d e s i g n e d . Each f l a g i s connected, on the d i g i t a l p a t c h p a n e l , t o a c i r c u i t l i k e t h a t shown i n F i g u r e 2-9- The f l a g s a r e l o c a t e d i n remote d e v i c e s and can be c l e a r e d , but not s e t , by the PDP-9. P u l s e t r a n s f o r m e r s a r e employed t o m a i n t a i n ground i s o l a t i o n . T O F\-KG> T o ItiPOT O F PM>-<) TO Vo <}-O F Pt>V^  (_©VT vS,»fc, O R n ) C L - E K S . F L A G C o ( v w M ) CovweRTCP T R W i F . T O - P d V - 1 ) & O F F & R AMPLIFIER G A T E woe* q— 0 — B U F F E R f\fvpup<e{? H W W GATe 0— - T R ^ F . I I | ^ ^ ^ p k C_ON\POTf R _GR_oojJ\i | IOT4-IOT I F R O M RSSBTeR VYlVTo'b OF CF(?oN\ TH&ATM P K T C H p^ueu) READ VTKTu^ (.FfeotV\ PbP-<}) F i g u r e 2-9. D e v i c e F l a g F a c i l i t y C i r c u i t r A/D CONVERSION A Model 5516 A n a l o g - t o - D i g i t a l C o n v e r t e r manufactured by R a d i a t i o n , I n c . has been i n c l u d e d i n the h y b r i d i n t e r f a c e . The i n s t r u m e n t has a twenty microsecond c o n v e r s i o n time and i n -c l u d e s a sample and h o l d u n i t w i t h an a p e r t u r e w i d t h of l e s s than 100 nanoseconds. The a n a l o g i n p u t v o l t a g e range i s +5.120 v o l t s , and t h e output i s 12 b i t s i n u n f o l d e d b i n a r y code, a "1" b e i n g -6 t o -10 v o l t s , and a "0", 0 t o -.2 v o l t s . V i s u a l readout i s p r o v i d e d , and a c o n v e r s i o n complete l e v e l i s a v a i l a b l e . The a n a l o g s i g n a l t o be opera t e d on i s f e d t o the A/D c o n v e r t e r t h r o u g h a s i x t e e n c h a n n e l m u l t i p l e x e r which w i l l a c c e p t a f u l l s c a l e i n p u t " o f +100 v o l t s , +10 v o l t s o r +1. v o l t on any ch a n n e l and produce the + 5.120 v o l t range the c o n v e r t e r r e q u i r e s . The m u l t i p l e x e r , which w i l l be d e s c r i b e d i n d e t a i l i n Chapter 4, employs - an o p e r a t i o n a l a m p l i f i e r i n t h e i n v e r t i n g mode i n each c h a n n e l , thus the p o l a r i t y of the a n a l o g s i g n a l s u p p l i e d t o the A/D c o n v e r t e r i s always o p p o s i t e t o t h a t of the i n p u t s i g n a l . D i g i t a l hardware i s used t o c o n v e r t the u n f o l d e d b i n a r y output of t h e A/D c o n v e r t e r i n t o 2 ! s complement format and to c o r r e c t f o r t h e s i g n i n v e r s i o n which occurs i n the m u l t i p l e x e r . 3.1 A/D Sampling C o n t r o l The A/D c o n v e r t e r samples the a n a l o g i n p u t s i g n a l and performs a c o n v e r s i o n each time i t r e c e i v e s a START CONVERSION command, p r o v i d e d t h a t such commands are a t l e a s t twenty m i c r o -seconds a p a r t . The commands can o r i g i n a t e i n any one o f f o u r 18 d i f f e r e n t l o c a t i o n s : i n the PDP -9 , under d i r e c t program c o n t r o l , w i t h the ADSC "(A/D s t a r t c o n v e r s i o n ) i n s t r u c t i o n ; i n the 231R-V w i t h the change of s t a t e of a comparator; i n a remote source w i t h the change of s t a t e of a comparator or f l a g ; or i n the A/D s a m p l i n g f r e q u e n c y c o n t r o l u n i t (SFC) when i t i s e n a b l e d , w i t h the .-'passing o f a c e r t a i n i n t e r v a l of t i m e . P u l s e s from t h e f i r s t t h r e e l o c a t i o n s mentioned are mixed i n the output stage of t h e SFC, w h e r e i n the p u l s e r e q u i r e d f o r t r i g g e r i n g the A/D c o n v e r t e r i s formed. The -SFC i t s e l f i s used t o generate t h e command p u l s e s i n cases where d i g i t a l d a t a samples a r e r e q u i r e d a t r e g u l a r i n t e r v a l s . I t r e l i e v e s i t h e programmer of t h e burden of remember-i n g when t o command the A/D c o n v e r t e r t o p e r f o r m a c o n v e r s i o n , and p r o v i d e s time r e s o l u t i o n t o w i t h i n +1/2 m i c r o second. The i n t e r v a l , t o the n e a r e s t m i c r o s e c o n d , which i s t o e l a p s e between the t a k i n g o f c o n s e c u t i v e d a t a samples i s l o a d e d i n t o a r e g i s t e r i n the SFC from the PDP - 9 , and the SFC commences o p e r a t i o n upon r e c e i v i n g an ENABLE SFC command. I n t e r v a l s from 2 microseconds t o .262143 seconds can be accommodated. The s h o r t e s t p r a c t i c a b l e i n t e r v a l f o r u s e e w i t h the A/D c o n v e r t e r employed i s 21 m i c r o s e c o n d s , however. A b l o c k diagram of the s a m p l i n g f r e q u e n c y c o n t r o l u n i t i s g i v e n i n F i g u r e 3-1. The SFC i n t e r v a l r e g i s t e r i s composed of s e t - r e s e t f l i p f l o p s and must be c l e a r e d w i t h a CLEAR SFC REGISTER command b e f o r e b e i n g l o a d e d . The SFC i n t e r v a l i s s p e c i f i e d w i t h an e i g h t e e n b i t b i n a r y i n t e g e r , i n m i c r o s e c o n d s , and i s r e a d from t h e a c c u m u l a t o r of t h e PDP-9 i n t o the i n t e r v a l 19 IS BIT WORD FRON\ P&P-9 I O O T P U ^ BUFFER (8 \_\m<a LOAD SFC REGISTER ^cnvi p i6 CLEAR SFC g£G\STER BoPFes AH*uF\ER - IOT I ve 2-IMPOT NKNQ GATES PRESET %UFFEfe MPL\F\6R «<\C79<»P % L\»ES O P COOWTER SoonS PULSE GSM. \HCfcEN£»T COUNTER CwFFeC q Mb AmPLvFvee. GKT€ S>Oe.f\$. ^ 66H. Nbfe GATE f» - I0T4 PULSE pop-g To tAlttu F U P FLOP fftcie^p ENAfeig SFC O'ShBLg SFC \ N V £ R T E e < j -<AC1©P COVNEfcS\.bri4  V>vJLSE Tt> PuLSE £1 MOST oft GENERATOR GATC FRotA REGISTER SELECTOR FPCHA - PUP-<) CLoCK NOR 6IV.TE loTe" N\0£4P START IM.T88P (M>SC iNVrROCT^OM) START  I0T4. FRo« -fteGi<pTER SELECTOR (*2) Cov»\tee"»voN ("5B\R-V ofc REtAoTE" SouR&e J FfcoM DvGlTKL PATCH PANEL F i g u r e 3-1. Sampling Frequency C o n t r o l U n i t 20 r e g i s t e r w i t h a LOAD' SFC REGISTER command. With a PRESET COUNTER command, \ which can f o l l o w i n one microsecond i f d e s i r e d , the up cou n t e r i s p r e s e t t o the complement of t h e SEC i n t e r v a l i n t e g e r . Then p u l s e s from the 1 mHz. c l o c k i n the PDP-9 are gated i n t o the c o u n t e r , which c o n t i n u e s c o u n t i n g i n a normal f a s h i o n u n t i l the t r a n s i t i o n from 1 1 1 1 . . . 1 ^ t o 0000...00^ i s made. The change i n s t a t e of the c o u n t e r ' s most s i g n i f i c a n t h i t s i g n i f i e s 1 t h a t the d e s i r e d count"has been reached, and i s used t o generate a p u l s e which commands the 'A/D c o n v e r t e r t o s t a r t a c o n v e r s i o n , and which b l a n k s out" t h e PDP-9 c l o c k p u l s e w h i l e i t p r e s e t s t he co u n t e r t o s t a r t "the count f o r the next i n t e r v a l . The START CONVERSION p u l s e s a re i s s u e d a t r e g u l a r i n t e r v a l s u n t i l a DISABLE SFC cGnmnand i s g i v e n by the PDP-9. The d e t a i l s :<of . - c o n s t r u c t i o n of the 500 and 600 nanosecond monostable p u l s e g e n e r a t o r s a re g i v e n i n Appendix IV. The p u l s e FRbNi KVRTL. _ -H W— To A/o CoMMEKTER ^Wv. $L v ia* +3.fe v. F i g u r e 3-2. P u l s e Generator f o r A/D C o n v e r t e r S t a r t C o n v e r s i o n P u l s e 21 g e n e r a t o r which forms the START CONVERSION p u l s e f o r the A/TJ c o n v e r t e r i s shown i n F i g u r e 3-2. The output p u l s e has a r i s e time of l e s s than 100 nanoseconds. The up c o u n t e r i s c o n s t r u c t e d w i t h M o t o r o l a MC826P JK f l i p f l o p s , which have b o t h p r e s e t (PS) and p r e c l e a r (PC) t e r m i n a l s . When the c o u n t e r i s l o a d e d from the SFC i n t e r v a l r e g i s t e r , i t i s l o a d e d t h r o u g h these t e r m i n a l s . The co n n e c t i o n s a r e made such t h a t the c o u n t e r i s load e d w i t h the complement of the number c o n t a i n e d i n the i n t e r v a l r e g i s t e r , as r e q u i r e d . The " d e t a i l s of the c o u n t e r d e s i g n a re g i v e n i n F i g u r e 3-3. The l o g i c l e v e l s shown are f o r the case when the 18 B»T F K o t A Bnro BIT 17 GfVTE GATE 6M€ GKT£ »*CReiAGHT-To se>oriS. GENERATOR F i g u r e 3-3. SFC Up Counter 22 i n t e r v a l r e g i s t e r c o n t a i n s the number 100... 01 and a PRESET COUNTER command l o a d s the c o u n t e r w i t h O i l . . . 1 0 . 3.2 A/D Output C o n t r o l Immediately upon c o m p l e t i o n of a c o n v e r s i o n , the " c o n v e r s i o n complete" l e v e l on the A/D c o n v e r t e r changes from 0 v o l t s t o a p p r o x i m a t e l y -8 v o l t s . T h i s change i s used t o generate a 500 nanosecond p u l s e which l o a d s the t w e l v e b i t A/D c o n v e r t e r output i n t o the b u f f e r r e g i s t e r of a s t a n d a r d i n p u t i n t e r f a c e ( S I I ) and n o t i f i e s the PDP-9 t h r o u g h the a u t o m a t i c p r i o r i t y i n t e r r u p t system t h a t s e r v i c i n g of the S I I i s r e q u i r e d . The time which e l a p s e s between t h e . p l a c i n g and g r a n t i n g o f the r e q u e s t f o r / s e r v i c e depends on the p r i o r i t y l e v e l of t h e c u r r e n t program and on the p a r t i c u l a r i n s t r u c t i o n w hich i s b e i n g executed a t the time the r e q u e s t i s made. Under the most i d e a l c o n d i t i o n s , the c o n t e n t s o f the S I I r e g i s t e r can be l o a d e d i n t o the PDP-9 w i t h i n f i v e m i croseconds. The o p e r a t i o n of t h e i n t e r r u p t system i s d i s c u s s e d i n d e t a i l i n Chapter 6. l e v e l c o n v e r t e r s l i k e the one.shown i n E i g u r e 3-4 have - i s * -av. 5.6 ksi. W — K J — W -A7 D 2 2 fcfl. CONVERTER / V W H 2 N ^ B OOTPOT ^ To EMITTERS R E N T I N G \» V-ENIEV. CO*WERTCRE F i g u r e 3-4. Output L e v e l C o n v e r t e r f o r A/D C o n v e r t e r / 23 been employed t o c o n v e r t the output l e v e l s of the A/D c o n v e r t e r t o MRTL l e v e l s . D i g i t a l complementation i s i n t r o d u c e d , thus an A/D "1" becomes an MRTL "0", and an A/D "0" becomes an MRTL "1". Two's complement a r i t h m e t i c has been s e l e c t e d f o r the d i g i t a l r e p r e s e n t a t i o n of a n a l o g s i g n a l s because of the absence of an ambiguous ze r o i n t h i s n o t a t i o n . Table 3-1 shows the d e s i r e d 2's complement code f o r a s y m m e t r i c a l i n p u t range. Note t h a t the word 1 0 0 . . . d e n o t e s minus f u l l s c a l e minus one l e a s t s i g n i f i c a n t b i t (LSB), and i s t h e r e f o r e o u t s i d e of t h e s y m m e t r i c a l i n p u t range + f u l l s c a l e . Table 3-1. D e s i r e d 2's Complement Code f o r S y m m e t r i c a l Input Range ANALOG INPUT 2'S COMPLEMENT ' CODE + P u l l S c a l e O i l . . 11 (+2047) 0 000 . , . 00 (0) - F u l l S c a l e 100 . , . 01 (-2047) - F u l l S c a l e -1LSB 100 . . . 00 (-2048) Depending on the s e t t i n g s o f the r e f e r e n c e s u p p l i e s i n the A/D c o n v e r t e r , two d i f f e r e n t u n f o l d e d output formats s h o u l d be 24 a v a i l a b l e . The one used by R a d i a t i o n , I n c . (the m a n u f a c t u r e r ) t o a c h i e v e sign-magnitude output format i s shown i n Table 3-2(a), C o n v e r s i o n from t h i s format t o 2's complement form i s d i f f i c u l t . A more c o n v e n i e n t u n f o l d e d format f o r our purposes i s shown i n Table 3~2(b). "The two form a t s d i f f e r o n l y i n a one LSB d i s p l a c e -ment, hence i t s h o u l d be p o s s i b l e t o a d j u s t the r e f e r e n c e s u p p l i e s t o a c h i e v e e i t h e r one. Table 3-2. U n f o l d e d Output Formats ANALOG INPUT UNFOLDED BINARY CODE ANALOG INPUT UNFOLDED BINARY CODE +5.120 v. 111 . , . 11 +5.120 v. 111 ... 10 0 v. 100 . . . 00' 0 v. O i l ... 11 -5.120 v. 000 .. . 01 -5.120 v. 000 ... 00 (a) (b) The s t e p s r e q u i r e d t o c o n v e r t the format of Table 3-2(b) i n t o 2's complement form a r e shown i n Table 3-3• These s t e p s take i n t o account the a n a l o g i n v e r s i o n which o c c u r s i n the m u l t i -p l e x e r and the d i g i t a l complementation which t a k e s p l a c e i n the l e v e l c o n v e r t e r s on the A/D c o n v e r t e r o u t p u t . 25 Table 3-3. C o n v e r s i o n of U n f o l d e d B i n a r y Code i n t o 2's Complement INPUT TO MULTIPLEXER INPUT TO A/D CONVERTER OUTPUT OF A/D CONVERTER OUTPUT OF LEVEL CONVERTERS COMPLEMENT MOST SIGNI-FICANT BIT + F u l l S c a l e -5.120 v. 000 ... 00 111 ... 11 O i l . . 11 t 2047 0 0 v. O i l ... 11 100 ... 00 000 . .. 0 0 1 • t 2047 - P u l l S c a l e +5.120 v. 111 ... 10 000 ... 01 100 . . 01* D e l i v e r y has not been made on the A/D c o n v e r t e r , hence i t i s i m p o s s i b l e t o a s c e r t a i n whether or not the r e f e r e n c e s u p p l i e s i n the A/D c o n v e r t e r a re s u f f i c i e n t l y a d j u s t a b l e t o r e a l i z e the format of Table 3-2(b). I f t h i s format i s not a t t a i n a b l e , the more c o m p l i c a t e d c o n v e r s i o n procedure o u t l i n e d i n Table 3-4 can be a p p l i e d t o the format of Table 3-2(a). Table 3-4. C o n v e r s i o n of U n f o l d e d B i n a r y Code i n t o 2's Complement INPUT TO MULTIPLEXER INPUT TO A/D CONVERTER OUTPUT OF A/D CONVERTER OUTPUT OF LEVEL CONVERTERS COMPL. MOST SIG. BIT ADD 1 + F u l l S c a l e 0 - F u l l S c a l e -5.120 v. 0 v. +5.120 v. 000 ... 01 100 ... 00 111 ... 11 111 ... 10 O i l ... 11 000 ... 00 O i l ... 10 111 ... 11 100 ... 00 O i l ... 11 000 ... 00 100 ... 01 26 Implementation of the scheme of Table 3-2(b) r e q u i r e s o n l y the complementing of the most s i g n i f i c a n t b i t . The procedure o u t l i n e d i n Table 3-4 r e q u i r e s complementing of the most s i g n i -f i c a n t b i t and a d d i t i o n of 1 w i t h a b i n a r y adder. The adder i s shown i n F i g u r e 3-5. The i n p u t word 10... 00 has been used as an example. «,lGNVFlCkVfT-B\T \»4 r P+l G*\T£ GKTg CAftfcV N M D G « T 6 IMNIERTER 6NT6 ho &W6 LEAST ^IGKHFICANT - o • • r-O G*T€ rAo<ST GATE L-o| GNTe Mow SvGmFiCfctfT F i g u r e 3-5. B i n a r y Adder 27 4. THE MULTIPLEXER To allow"analog signals from more than one source to conveniently be"fed to the A/D converter, a sixteen channel analog7 data multiplexer has been designed and built for use in the hybrid interface-.- -The-multiplexer i s , in effect, a very high speed digitally-controlled six-teen-position electronic switch. It employs f i e l d effect- transistors (PETs) for switching, and performs voltage scaling and impedance buffering with operational amplifiers.--A block diagram of the multiplexer is given in Figure 4-1. .Initially, sixteen channels w i l l be provided. Up to forty-eight mcjre channels-oan be added as the need arises. Multi-plexer, channels-oan be selected in any sequence desired, with the six bit address word•(two octal digits) coming from the PDP-9 or from a remote di g i t a l source. The time required for settling to within 1 mv. of signal voltage is approximately 1.3 microseconds'.- -The f u l l " scale-input voltage on any multiplexer channel can be +100 volts > +10 volts, or +1 volt. Inputs from the 231R-V are +100 volts, but those from- other analog equipment are generally in the lower voltage ranges. The three input terminals for each of the sixteen channels are located on the 440-hole patch panel for analog signals, as shown in Figure 1-1, adjacent to sets of lines from the laboratories and the 231R-V. The capacitance between neighbouring terminals of the t lev. Z t IV. SATE i • • S*T£ 8 6 O C T A L oecoDCfc in T i T GATS' l b O C T A L otaooi® Dl&rtAL PNTGM PM1L 1 I 1 Figure 4-1. Multiplexer 29 p a t c h p a n e l i s a maximum of 2.5 p f . , and between any t e r m i n a l and i t s e i g h t n e a r e s t n e i g h bours i t i s a p p r o x i m a t e l y 13 p f . To e l i m i n a t e c r o s s t a l k and o t h e r e r r o r s i n t r o d u c e d by t h i s c a p a c i t a n c e the e i g h t n e a r e s t n e i g h bours of each m u l t i p l e x e r i n p u t t e r m i n a l have been t i e d t o ground. S h i e l d e d l e a d s can be used on the p a t c h p a n e l but s h o u l d not be needed i f i n p u t s are s u p p l i e d from low impedance s o u r c e s . An e x a m i n a t i o n of frequency-dependent system e r r o r s i n d i c a t e d t h a t the m u l t i p l e x e r s h o u l d be designed t o handle a n a l o g s i g n a l s c o n t a i n i n g f r e q u e n c i e s no h i g h e r t h a n 20kHz. The sample and h o l d u n i t which samples the m u l t i p l e x e r output and h o l d s the sample w h i l e the A/D c o n v e r t e r performs, a c o n v e r s i o n i n t r o d u c e s an e r r o r , or u n c e r t a i n t y , i n the sampled s i g n a l . There i s a f i n i t e a p e r t u r e t i m e , or s a m p l i n g i n t e r v a l , and one cannot say when w i t h i n the i n t e r v a l the sample was tak e n . F i g u r e 4—2 i l l u s t r a t e s the con c e p t . I f we have an a n a l o g s i g n a l d e s c r i b e d by the e q u a t i o n e = E s i n w t , t h e n the maximum r a t e of change of v o l t a g e w i t h r e s p e c t t o time o c c u r s e e = E=>in tot F i g u r e 4-2. U n c e r t a i n t y i n Sample V a l u e 30 when the s i g n a l is. passing through zero, and i s given by the equation || = Ew cos (0* + nl80° ) , n = l , 2, . . . j Thus, i n a time At, the voltage w i l l change by Ae < EwAt, and i f At i s the aperture time of the sample and hold u n i t , we have an e r r o r , or u n c e r t a i n t y , of Ae v o l t s i n our sampled s i g n a l . Expressed as a percentage of peak amplitude, t h i s e r r o r i s given as e(#) = lOOwAt . The sample and hold u n i t i n the R a d i a t i o n Model 5516 A/D converte has an aperture time of 100 nanoseconds. Table 4-1 l i s t s the e r r o r t h i s aperture introduces f o r various s i g n a l frequencies. I t i s of i n t e r e s t to note that s t a t e - o f - t h e - a r t sample and hold u n i t s have 50 nanosecond apertures, thus they too introduce 0 s i g n i f i c a n t e r r o r s at high frequencies. Two a d d i t i o n a l f a c t o r s a l s o i n d i c a t e that a 20kHz.frequenc l i m i t f o r the m u l t i p l e x e r i s reasonable. Operational a m p l i f i e r s w i t h the high gain and wide bandwidth required f o r handling frequencies s i g n i f i c a n t l y above 20kHz. cost more than twice as much as the a m p l i f i e r s which have been employed. And the 231R-V analog computer, which i s the p r i n c i p a l piece of analog equipment to be used with-the i n t e r f a c e i s not a high frequency machine. I t s o p e r a t i o n a l a m p l i f i e r s , introduce a phase s h i f t of 34° at 20kHz. and have an .upper Jdbr" point of 34 kHz. 31 4•1 The Input Stage The input stage of a t y p i c a l m u l t i p l e x e r channel i s d e t a i l e d i n Figure 4-3. The p r i n c i p a l component i s the AD106B operational, a m p l i f i e r , which was chosen f o r i t s high gain, good frequency response, and low cost. I t i s the c h i e f source of e r r o r i n the m u l t i p l e x e r , hut the e r r o r s i t introduces are small compared to those introduced by other parts of the a n a l o g - d i g i t a l l i n k , as i s shown i n Table 4-1. The AD106B can be replaced with the more c o s t l y AD110B i f improved frequency response becomes necessary. The s p e c i f i c a t i o n s f o r both a m p l i f i e r s are given i n Appendix VI. To obtain the best performance i t has been necessary, to employ the o p e r a t i o n a l a m p l i f i e r s i n the i n v e r t i n g mode-.• The d i g i t a l hardware at the A/D converter output used to cancel t h i s i n v e r s i o n has been described i n Chapter 3• Metal f i l m r e s i s t o r s with a tolerance of ±lfo and a temperature c o e f f i c i e n t of l e s s than 50 ppm //°C. have been employed with the o p e r a t i o n a l a m p l i f i e r s . To obtain D.C. closed loop gains of .0512, .512, and 5.120 accurate to w i t h i n .01$, a Bourns model 3257 commercial wirewound TRIMIT potentiometer has been i n s e r t e d i n s e r i e s with each input r e s i s t o r . Each trimmer has a maximum r e s i s t a n c e equal to 2$ of the r e s i s t a n c e of the metal f i l m r e s i s t o r t o which i t : i s attached. To obtain rough trimming i n the feedback loop before s e t t i n g up the input potentiometer, a Bourns model 3067 trimmer i s used. 32 Table 4-1. S i g n i f i c a n t Err.ors i n the A/D L i n k MULTIPLEXER INPUT VOLTAGE RANGE ANALOG SIGNAL FREQUENCY SAMPLE AND HOLD APERTURE ERROR (% OF PEAK SIGNAL AMPLITUDE) AD106B . OPERATIONAL AMPLIFIER ERROR (% OF PEAK SIGNAL AMPLITUDE) D.C. .0004% 100 Hz. .006% .0004% + 100 v. 1 kHz. .063% .002% 10 kHz. o63% .139% 20 kHz. 1.26% . 347% D.C. .0006% 100 Hz. .006% .0006% + 10 7 . 1 kHz. .063% .003% 10 kHz. .63% ....193% 20 kHz. 1.26% .487% D.C. .0024% 100 Hz. .006% .0024% + 1 V . 1 kHz. .063% .011% 10 kHz. <.63% .754% 20 kHz. 1.26% 1.89% 33 iioov. D-FRotA P M W P N E L ±wv.< t ~ l v. o-220 PT K>pP. OTo - A W - — 1.5* To lopf. toppf. O lb -AAAA— uot.pT: 0T B OFPSST CORRECT, loveSl COMPEUSKUoN : - w -I5v. . l»HlS4 PROTECTS OuTPOT TO F i g u r e 4-3. M u l t i p l e x e r Input Stage 34 I n d e t e r m i n i n g the magnitude -of the i n p u t and feedback r e s i s t o r s t o be used, two major c o n d i t i o n s had t o be s a t i s f i e d : the c u r r e n t drawn from any source had t o be as s m a l l as p o s s i b l e i n o r d e r t o m i n i m i z e l o a d i n g problems, and the r e s i s t o r s had t o be s m a l l enough t o pre v e n t the oc c u r r e n c e of problems due t o v o l t a g e and c u r r e n t o f f s e t s a s s o c i a t e d w i t h the o p e r a t i o n a l a m p l i n ' f i e r . V a l u e s of l m f i , 1Q0 kn , and 10 ka were chosen f o r the +100 v o l t , +10 v o l t and +1 v o l t i n p u t s r e s p e c t i v e l y . These g i v e worst case 'loads of +10Q |j.a. a t D.C, which s h o u l d s a t i s f y the low l o a d i n g r e q u i r e m e n t . I n i t i a l v o l t a g e and c u r r e n t o f f s e t s are compensated f o r by using, p o t e n t i o m e t e r s as i n d i c a t e d i n F i g u r e 4-3>"hut changes i n thes e o f f s e t s w i t h changes i n temperature a re dependent on the s i z e . o f the i n p u t and feedback r e s i s t o r s . F o r a c i r c u i t c o n t a i n i n g an o p e r a t i o n a l a m p l i f i e r w i t h an i n p u t r e s i s t o r R^ . and feedback r e s i s t o r R^, the temperature c o e f f i c i e n t r e f e r r e d t o the source v o l t a g e S V , i s g i v e n s by AV Ae R.+R„ i R. S _ O S _ . . 1 - f O S 1 AT AT R f A T Ae where os i s the change i n o f f s e t v o l t a g e w i t h temperature and AT ^ o s i s the change i n o f f s e t c u r r e n t w i t h temperature. I n the AT AD106B, over t h e temperature range -25°C t o +86°C, ^ e o s AT i s a maximum average of + 10uv./°Cand A ^ o s i s a maximum AT average of +.7na/°C . W i t h the r e s i s t o r v a l u e s chosen, the e r r o r , as a percentage of f u l l s c a l e , on any m u l t i p l e x e r c h a n n e l , w i t h 35 a d e v i a t i o n o f +10° C. from room, temperature s h o u l d he l e s s than .009%. The s i z e o f the i n p u t r e s i s t o r s a l s o had t o he compared t o the d i f f e r e n t i a l i n p u t impedance o f the o p e r a t i o n a l a m p l i f i e r t o ensure the r e s i s t o r s would not he so l a r g e as t o degrade the a m p l i f i e r ' s performance. C o n s i d e r an o p e r a t i o n a l a m p l i f i e r w i t h a d i f f e r e n t i a l i n p u t impedance Z-j-^ and open l o o p g a i n A connected i n the i n v e r t i n g c o n f i g u r a t i o n w i t h i n p u t impedance Z^ and feedback impedance Z^. I f Z^ « Z-j-^, then the e r r o r i n h e r e n t i n the c i r c u i t i s g i v e n by £ ( % ) = 100 A'P where 1 + Z f z. 1 But when Z ^ i s comparable t o Z - ^ , we must account f o r the f a c t t h a t Z-J-J-J. i s . "in p a r a l l e l w i t h Z ^ i n the feedback v o l t a g e d i v i d e r , and r e p l a c e B w i t h p' - _ L !••+ Z f where Z c Z — Z . Z -r •» Tc x IN Z i + Z I N S i n c e |3<' i s l e s s t h a n B, the e r r o r i s g r e a t e r than i n the p r e v i o u s 3 6 case. The d e g r a d a t i o n of performance i s not g r e a t when the c l o s e d l o o p g a i n of the c i r c u i t i s l e s s t h a n u n i t y , however, and the r e s i s t o r s have been chosen so the o n l y case i n which Z ^ i s not much l e s s t h a n Z J J - i n v o l v e s a c l o s e d l o o p g a i n of .0512. When a m u l t i p l e x e r c h a n n e l i s t u r n e d o f f , i t s i n p u t stage d r i v e s a l o a d impedance of a p p r o x i m a t e l y l l k f i t o -22 v o l t s (see F i g u r e 4-5). When the cha n n e l i s t u r n e d on, the l o a d impedance becomes a p p r o x i m a t e l y 200 p f . j l m f l t o ground. I t was found e x p e r i m e n t a l l y t h a t the b e s t m u l t i p l e x e r performance c o u l d be o b t a i n e d when a 220 p f . c a p a c i t o r was i n s e r t e d a c r o s s the feedback r e s i s t o r and a b i p o l a r e m i t t e r f o l l o w e r was i n c l u d e d i n the feedback l o o p . The c a p a c i t o r h e l p e d t o make the c i r c u i t l e s s s e n s i t i v e t o p i c k u p and t o decrease s w i t c h i n g t i m e s , w h i l e the e m i t t e r f o l l o w e r , a c t i n g as an impedance b u f f e r , improved s t a b i l i t y by d e c r e a s i n g the e f f e c t s of l o a d c a p a c i t a n c e on the o p e r a t i o n a l a m p l i f i e r s . S i n c e a c a p a c i t o r a c r o s s the feedback r e s i s t o r reduces feedback impedance a t h i g h f r e q u e n c i e s , c a p a c i t o r s had t o be added a c r o s s a l l the i n p u t r e s i s t o r s i n o r d e r t o m a i n t a i n the d e s i r e d g a i n s of .0512, .512, and 5.12 f o r a l l f r e q u e n c i e s from D.C. t o 20kHz. T e m p e r a t u r e - s t a b l e c a p a c i t o r s w i t h trimmers have been employed. W i t h the a d d i t i o n of the c a p a c i t o r s , worst case i n p u t c u r r e n t s t o the m u l t i p l e x e r i n c r e a s e t o + 225 ua. a t 20kHz. 37 To p r o t e c t the o p e r a t i o n a l a m p l i f i e r s a g a i n s t the damage they c o u l d s u f f e r i f a 100 v o l t l i n e were a c c i d e n t a l l y connected t o a +1 v o l t i n p u t , two 1K4-154 d i o d e s have been i n s e r t e d between the a m p l i f i e r i n p u t and ground. These d i o d e s prevent the v o l t a g e from r i s i n g above .8 v o l t s i n magnitude. 4•2 A d d r e s s i n g " To address a m u l t i p l e x e r c h a n n e l , a s i x b i t word i s s u p p l i e d t o t h e m u l t i p l e x e r address t e r m i n a l s on the d i g i t a l p a t c h p a n e l . T h i s word w i l l i n g e n e r a l be o b t a i n e d from t h e output r e g i s t e r of the s i x b i t s t a n d a r d output i n t e r f a c e (SOI) shown o p p o s i t e the m u l t i p l e x e r i n F i g u r e 1-1, but may a l t e r n a t i v e l y be o b t a i n e d from a remote s o u r c e . The output r e g i s t e r i n the SOI, which i s the m u l t i p l e x e r address r e g i s t e r , can be updated w i t h any of t h r e e IOT i n s t r u c t i o n s , o r w i t h an update pul.se from the p a t c h p a n e l . The i n s t r u c t i o n MUAL l o a d s the address r e g i s t e r from the SOI b u f f e r r e g i s t e r ; MUALD l o a d s t h e b u f f e r r e g i s t e r from the PDP-9's a c c u m u l a t o r , and then l o a d s the address r e g i s t e r from the b u f f e r , and MUSC l o a d s the address r e g i s t e r from, t h e b u f f e r and two microseconds l a t e r p u l s e s the A/D c o n v e r t e r t o s t a r t a c o n v e r s i o n . A complete l i s t i n g of i n t e r f a c e i n s t r u c t i o n s and t h e i r o c t a l codes i s g i v e n i n Appendix V. The address word i s composed of two o c t a l d i g i t s ; the f i r s t s e l e c t s a group of e i g h t c h a n n e l s , and t h e second, a p a r t i c u l a r c h a n n e l w i t h i n the group. Only two groups of e i g h t w i l l be i n s t a l l e d i n i t i a l l y , but up t o s i x more groups can e a s i l y be 38 added as t h e y are needed. The f l o w o f d a t a and command s i g n a l s i s i n d i c a t e d i n F i g u r e 4-1. I n s e l e c t i n g a group of c h a n n e l s , one of the two FET s w i t c h e s i n rank A i s t u r n e d on, and i n s e l e c t i n g the c h a n n e l w i t h i n the group two s w i t c h e s i n rank B are t u r n e d on, one i n each group. Grouping s i m p l i f i e s address d e c o d i n g and h e l p s t o reduce c r o s s t a l k and leaka g e problems a s s o c i a t e d w i t h the FETs. Each o c t a l number i n the a d d r e s s word i s f e d t o an o c t a l decoder. A b l o c k diagram of a decoder i s g i v e n i n F i g u r e 4-4. OCTM. INPUT FRoNV P&TCH INVESTED - wo GKTE Nltl88P -or BUFFER I*C"WP O I -o 4 -OL F i g u r e 4-4. O c t a l Decoder 39 The l o g i c l e v e l s shown are those which would, he pr e s e n t i f the o c t a l i n p u t were a "5" ( l O l g ) . A b i n a r y "1" a t t h e i n p u t i s r e p r e s e n t e d by a p o s i t i v e v o l t a g e l e v e l , and a "0" by a ground l e v e l , as i s the case a t the output t e r m i n a l s of t h e SOI t o which the decoder may be connected. A p o s i t i v e l e v e l a t a decoder output causes the connected gate d r i v e c i r c u i t t o t u r n i t s PETs on. Only one of the e i g h t o u t p u t s i s p o s i t i v e a t a time. 4.3 The Gate D r i v e C i r c u i t A schematic of a gate d r i v e c i r c u i t connected t o an FET s w i t c h i s g i v e n i n F i g u r e 4-5. Amelco 2N4091 N-channel j u n c t i o n f i e l d e f f e c t t r a n s i s t o r s have been employed. When the g a t e - s o u r c e v o l t a g e , V g . g , of one of thes e d e v i c e s i s more negative:) t h a n -10 v o l t s , t h e r e s i s t a n c e between source and d r a i n a t FRotA f E T SvMlTCU SOURCE t>ei\\N < < •ZZ* +15/. 6uFFEt? M A P U F l E R OF OCTAL DECODER IN400I Iv^OOl -A/WV-IF ftBo^e Per beg Fit.vi) CONNECT ftWOTHeC ^er SWITCH + 1 5 / +15/. F i g u r e 4-5. Gate D r i v e C i r c u i t and FET S w i t c h 40 room temperature "is 10 1 1 ohms, and the FET i s " o f f " . As g a t e -source v o l t a g e approaches z e r o , the r e s i s t a n c e d e c r e a s e s , u n t i l , f o r "V^g = 0, i t i s l e s s t h a n 3 0 A . At t h i s p o i n t the FET. i s "on". The a n a l o g s i g n a l s on the source and d r a i n t e r m i n a l s of the FETs come from m u l t i p l e x e r i n p u t s t a g e s , and w i l l not exceed +5.12 v o l t s . T h i s determines minimum v a l u e s f o r the v o l t a g e s w hich must he a p p l i e d a t p o i n t A i n F i g u r e 4-5 t o operat e the FET as,,a s w i t c h . To t u r n the FET on, the 1N914 diode connected t o the gate t e r m i n a l must he r e v e r s e b i a s e d so the v o l t a g e a t the gate can f o l l o w t h a t a t the so u r c e , s a t i s f y i n g the c o n d i t i o n VQ.g= 0. A v o l t a g e more p o s i t i v e t h a n +5.12 v o l t s w i l l s u f f i c e . To t u r n the FET o f f , the gate must be h e l d more n e g a t i v e t h a n -15.12 v o l t s . A l l o w i n g f o r a f o r w a r d v o l t a g e drop of 1 v o l t a c r o s s the d i o d e , p o i n t A must he h e l d more n e g a t i v e t h a n -16.12 v o l t s . The gate d r i v e c i r c u i t i n F i g u r e 4-5 meets the above r e q u i r e m e n t s , s u p p l y i n g +14.8 v o l t s t o t u r n FETs on and a n e g a t i v e v o l t a g e between -19.2 and -17-5 v o l t s , depending on the number of FETs i t i s d r i v i n g and the v o l t a g e s a t the source t e r m i -n a l s , t o t u r n FETs o f f . Each gate d r i v e c i r c u i t i s d r i v e n by an MRTL b u f f e r a m p l i f i e r and draws no c u r r e n t when the p o s i t i v e i n p u t l e v e l i s s u p p l i e d and l e s s t h a n 1 ma. when the ground l e v e l i s s u p p l i e d . The t r a n s i s t o r s a r e s a t u r a t e d to,''produce the +14.8 v o l t output and cut o f f t o produce the n e g a t i v e o u t p u t . S i n c e o n l y one m u l t i p l e x e r c h a n n e l i s on a t a t i m e , and t h e r e f o r e o n l y two gate d r i v e c i r c u i t s a r e p r o d u c i n g +14.8 v o l t s a t a t i m e , 41 demands on the +15 v o l t and -22 v o l t power s u p p l i e s are kept t o a minimum. R i s e and f a l l t i mes of 7 nanoseconds and 80 nanoseconds r e s p e c t i v e l y have been o b t a i n e d w i t h unloaded gate d r i v e c i r c u i t s . 4.4 The FET S w i t c h Some of the p r o p e r t i e s o f the FET s w i t c h have been d i s c u s s e d above. However, D.C. leak a g e c u r r e n t , v o l t a g e d i v i d e r e r r o r , s w i t c h i n g speed, and c r o s s t a l k have not y e t been mentioned. At a temperature of 25°C. the s o u r c e - d r a i n l e a k a g e c u r r e n t of a 2N4091 f i e l d e f f e c t t r a n s i s t o r w i t h V D S = 10 v o l t s i s a p p r o x i m a t e l y .1 nanoamper.es. I n the m u l t i p l e x e r the FETs are i n t e r c o n n e c t e d as shown i n F i g u r e 4-6. I f the addressed c h a n n e l , c h a n n e l 2 i n t h i s example, i s a t -5.12 v o l t s and a l l o t h e r channels are a t +5.12 v o l t s we have the worst case f o r D.C. le a k a g e and the c u r r e n t s w i l l f l o w as i n d i c a t e d . The e r r o r s i g n a l , r e f e r r e d t o the v o l t a g e source f o r c h a n n e l 2, i s l e s s t h a n 27 n a n o v o l t s , which i s n e g l i g i b l e . The l e a k a g e c u r r e n t i n c r e a s e s w i t h temperature t o become a p p r o x i m a t e l y 200 nanoamperes f o r each FET a t 150°C. I n t h i s case, the e r r o r s i g n a l i s l e s s t h a n 49 m i c r o v o l t s , s t i l l n e g l i g i b l e . The i n p u t impedance o f the A/D c o n v e r t e r the m u l t i p l e x e r i s d r i v i n g i s 1 megohm shunted by a c a p a c i t a n c e of 100 p f . The m u l t i p l e x e r a c t s l i k e a source w i t h an impedance of l e s s t h a n 60 ohms, s i n c e the output s i g n a l i s s u p p l i e d t h rough two FETs from an AD106B o p e r a t i o n a l a m p l i f i e r , and the -M-on" r e s i s t a n c e of each FET i s l e s s t h a n 30 ohms w h i l e the output impedance of the o p e r a t i o n a l a m p l i f i e r i s much l e s s t h a n 1 ohm. Thus, at :ure 4-6 PET I n t e r c o n n e c t i o n i n M u l t i p l e x e r 4 3 D.C. the " v o l t a g e d i v i d e r " e r r o r i n t r o d u c e d i n the m u l t i p l e x e r i s l e s s t h a n .006% of s i g n a l a m p l i t u d e . T h i s e r r o r i n c r e a s e s l i n e a r l y w i t h f r e q u e n c y , . t o r e a c h .075% a t 20kHz . I t i s always n e g l i g i b l e i n comparison t o o t h e r system e r r o r s . The s w i t c h i n g speed of the m u l t i p l e x e r depends c h i e f l y on the c a p a c i t a n c e s and r e s i s t a n c e s i n the FETs and on the e x t e r n a l r e s i s t o r R^g between the gate and source t e r m i n a l s i n the s w i t c h . When an FET c h a n n e l i s t u r n e d on, the 9: p'f. i n p u t c a p a c i t a n c e between gate and source must d i s c h a r g e t h r o u g h R^g t o g i v e the c o n d i t i o n V^g = 0 . T h i s i n d i c a t e s t h a t R^g s h o u l d be chosen as s m a l l as p o s s i b l e . However, i f R^g i s made too s m a l l , the l o a d i n g on the gate d r i v e c i r c u i t ran become p r o h i b i t i v e . A s a t i s f a c t o r y v a l u e was found t o be 10 k i l o h m s , which g i v e s an RC time c o n s t a n t of 90 nanoseconds. An FET "on" r e s i s t a n c e of a p p r o x i m a t e l y 60- ohms s h o u l d be reached w i t h i n 150 t o 220 nanoseconds, depending on the s o u r c e v o l t a g e i n v o l v e d . D r a i n -gate c a p a c i t a n c e s t o t a l l i n g a p p r o x i m a t e l y 100 pf must be charged, as must the A/D c o n v e r t e r i n p u t c a p a c i t a n c e . F i g u r e 4-7 i s a photograph of the output v o l t a g e when the m u l t i p l e x e r i s s w i t c h i n g from -5 t o +5 v o l t s , and F i g u r e 4 - 8 shows the waveform o b t a i n e d i n s w i t c h i n g from +5 t o -5 v o l t s . The time s c a l e s are 200 n a n o s e c o n d s / d i v i s i o n . F i g u r e 4 - 9 shows the same output a t a time s c a l e of 100 m i c r o s e c o n d s / d i v i s i o n . P e r f e c t e x p o n e n t i a l curves are not observed, s i n c e w h i l e one FET i s t u r n i n g on, a n other i s t u r n i n g o f f , and more t h a n one t i m e c o n s t a n t i s c o n t r i b u t i n g t o each, c u r v e . However, o v e r a l l RC time c o n s t a n t s of l e s s t h a n 120 nanoseconds are i n d i c a t e d . I f 44 Zoc 400 600 8eo looo iSoo >AOO (too VBOO TIME" (Nf\Wo5G"Co»oDS) F i g u r e 4-7. M u l t i p l e x e r Output Waveform O 200 ftOC 600 6'0 1000 >20O (*40 vtoo 1600 TIME (NftViCaECoNttSj F i g u r e 4-8. M u l t i p l e x e r Output Waveform 45 VOLTk&E F i g u r e 4-9- M u l t i p l e x e r Output Waveform 200 nanoseconds i s a l l o w e d f o r the n o n - e x p o n e n t i a l l e a d i n g edge of the curv e , and then 9.2 time c o n s t a n t s are a l l o w e d f o r the output v o l t a g e t o s e t t l e t o w i t h i n .01% of the v o l t a g e on the addressed c h a n n e l , the m u l t i p l e x e r s e t t l i n g time i s 1.3 m i c r o -seconds . T r a n s i e n t s a t t r i b u t a b l e t o the f a c t t h a t the i n p u t stage o p e r a t i o n a l a m p l i f i e r s a re s u b j e c t e d t o sudden changes i n l o a d i n g have been observed. The t r a n s i e n t s peak a t a p p r o x i m a t e l y 300 mv. above the s i g n a l v o l t a g e , and w i t h i n 1 microsecond have decayed t o l e s s t h a n 1 mv. S i n c e o n e - h a l f of the l e a s t s i g n i f i c a n t b i t i n the A/D c o n v e r t e r i s 1.25 mv., and a t l e a s t 2 m i c r o -seconds i s a l l o w e d f o r the m u l t i p l e x e r t o s e t t l e b e f o r e the A/D c o n v e r t e r s t a r t s a c o n v e r s i o n , these t r a n s i e n t s can be i g n o r e d . 46 C r o s s t a l k " i n t h e m u l t i p l e x e r i s dependent c h i e f l y upon the s o u r c e - d r a i n c a p a c i t a n c e , Cg-^, of the FETs which are " o f f " and the s o u r c e - d r a i n r e s i s t a n c e s of those which a r e "on". From the s p e c i f i c a t i o n s f o r the 2N4091 FET, one can c a l c u l a t e t h a t Cg-^ w i l l he a p p r o x i m a t e l y 3 p f . S o u r c e - d r a i n "on" r e s i s t a n c e i s l e s s t h a n 30 ohms." I n the worst 20Hkz. s i g n a l , 10.24 v o l t s peak-to-peak", i s p r e s e n t on every c h a n n e l hut the addressed one, and a l l the 20kHz. s i g n a l s are i n phase. C r o s s -t a l k i s c a l c u l a t e d t o d e v e l o p an e r r o r s i g n a l o f 1.04 mv., peak-to-peak. F o r each a d d i t i o n a l group of e i g h t c h a n nels i n s t a l l e d , .12 mv. w i l l he .added. Measurements on a p r o t o t y p e of the m u l t i p l e x e r i n d i c a t e t h a t these c a l c u l a t i o n s are v a l i d . C r o s s t a l k s h o u l d n o t , t h e r e f o r e , he a problem. 47 5. DIG-ITAL-TO-ANALOG- CONVERSION E i g h t channels of d i g i t a l - t o - a n a l o g (D/A) c o n v e r s i o n are i n c l u d e d i n the i n t e r f a c e - two w i t h an a c c u r a c y of twe l v e h i t s , f o u r w i t h seven h i t s , and two w i t h f o u r h i t s . The d i g i t a l numbers t o be c o n v e r t e d a re h e l d i n output r e g i s t e r s o f s t a n d a r d output i n t e r f a c e s (SOIs) which are connected t o the D/A c o n v e r t e r s through the d i g i t a l p a t c h p a n e l . The double b u f f e r i n g and the sim u l t a n e o u s and e x t e r n a l u p d a t i n g f e a t u r e s of the SOIs are e s p e c i a l l y u s e f u l i n t h i s a p p l i c a t i o n . A l l e i g h t D/A c o n v e r t e r s a c c e p t a 2's complement d i g i t a l i n p u t and produce an a n a l o g output of,+ 10 v o l t s f u l l s c a l e from an o p e r a t i o n a l a m p l i f i e r . The output impedance i s l e s s t h a n .004 ohms, and a maximum c u r r e n t o f + 20 ma. can be d e l i v e r e d . Where + 100 v o l t s i s r e q u i r e d , an a m p l i f i e r i n the 231R-V w i t h a g a i n of t e n nrusi: be used. The o u t p u t s of the D/A c o n v e r t e r s t e r m i n a t e on the 440 - h o l e p a t c h p a n e l f o r a n a l o g s i g n a l s . By p a t c h i n g the output of a D/A c o n v e r t e r t o more t h a n one p o i n t i n the a n a l o g computer, one can use the c o n v e r t e r t o maximum advantage i n a h y b r i d problem. When the computer i s i n the POTSET mode, the c o n v e r t e r can be" used t o s u p p l y c o e f f i c i e n t s f o r s e t t i n g s e r v o - s e t p o t e n t i o m e t e r s ; when the computer i s i n the INITIAL CONDITION mode, the c o n v e r t e r can s u p p l y an i n i t i a l c o n d i t i o n v o l t a g e t o an i n t e g r a t o r ; and when the computer i s i n the OPERATE mode, the c o n v e r t e r can s u p p l y a problem parameter. The output of a D/A c o n v e r t e r can be m u l t i p l e x e d so t h a t i t can be s u p p l i e d t o any of 48 s e v e r a l a d d r e s s a b l e p o i n t s . No m u l t i p l e x e r s have been i n c l u d e d i n the h y b r i d i n t e r f a c e f o r t h i s purpose, but they can be added q u i t e e a s i l y i f t h e y are needed. 5.1 The Twelve B i t D/A C o n v e r t e r s -Modules manufactured by the D i g i t a l Equipment C o r p o r a t i o n (DEC)-have been employed i n the t w e l v e b i t D/A c o n v e r t e r s . Each c o n v e r t e r c o n t a i n s one #A601, two #A604, and two #605 D i g i t a l -A n a l o g C o n v e r t e r Modules. One #A704 P r e c i s i o n R e f e r e n c e Supply (-10 v o l t s ) i s used. S p e c i f i c a t i o n s f o r t h e s e modules and i n s t r u c t i o n s f o r t h e i r i n t e r c o n n e c t i o n are g i v e n i n the D i g i t a l 2 L o g i c Handbook . The DEC modules r e q u i r e d i g i t a l l e v e l s of 0 and -3 v o l t s , thus l e v e l c o n v e r t e r s must be employed so the d i g i t a " l i n p u t word can be s u p p l i e d from an SOI, which produces . MRTL l e v e l s . The c o n v e r t e r s are s i m i l a r t o the one used w i t h the PDP-9 and shown i n F i g u r e 2-2, but i n c l u d e a 6.8kft. r e s i s t o r from the c o l l e c t o r of the 2N3638 t r a n s i s t o r t o the -15 v o l t s u p p l y , and a diode clamp t o ensure t h a t the c o l l e c t o r v o l t a g e does not exceed -3 v o l t s when the t r a n s i s t o r i s cut o f f . A" b l o c k diagram of a t w e l v e b i t D/A c o n v e r t e r i s g i v e n i n F i g u r e 5-1- To t r a n s f o r m the 2's complement i n p u t from the SOI i n t o t h e magnitude-only format r e q u i r e d by the DEC modules, the most s i g n i f i c a n t b i t (the s i g n b i t ) must be complemented. A "1" a t the SOI output i s r e p r e s e n t e d by a p o s i t i v e l e v e l , but ground l e v e l s are r e q u i r e d f o r a s s e r t i o n a t the i n p u t s t o the l e v e l c o n v e r t e r s . The two r e q u i r e m e n t s are met by complementing a l l but t h e most s i g n i f i c a n t b i t i n b u f f e r a m p l i f i e r s . To o b t a i n the b i p o l a r output of + 10 v o l t s , o p e r a t i o n a l 49 - l o \J. f$eF6<?. IOICA 6003. TWE\_\JE fcvT 2 "3 COIAPLENIE^T OU T P U T FROIA S O T Jill 0 0 12 U*i€S Dec / 47hJl O U T P U T : O T o -10 V. T o MAPUFvERlKi T O PROVIDE PcrrEvjnortETeft COEFFICIENTS -IS/. +15/ OTo 2oWl 6oo^n-100 K«. O O T P O T : @ T o ftuKcoG. ^PKTC«PKNE>_ O N E ONV-Y G€QOlPe0 Foft l ift toMvjeeTees -15* F i g u r e 5-1. Twelve B i t D/A Co n v e r t e r 50 a m p l i f i e r s a re used. An AD106B a m p l i f i e r c o n v e r t s the -10 v o l t p r e c i s i o n r e f e r e n c e i n t o a +5 v o l t r e f e r e n c e which i s added t o the 0 t o -10 v o l t output of the DEC modules i n an AD110B o p e r a t i o n a l a m p l i f i e r w i t h a g a i n of two. M e t a l f i l m r e s i s t o r s and t r i m m i n g p o t e n t i o m e t e r s s i m i l a r t o those used i n the m u l t i p l e x e r i n p u t stage (see s e c t i o n 2.4) are employed. The DEC p o r t i o n of the c o n v e r t e r "has an output impedance of 1000 ohms + .1% w h i l e the AD106B a m p l i f i e r has an output impedance of l e s s t h a n .004 ohms. Thus, a 9k XI r e s i s t o r i s used on one i n p u t t o the AD110B, and a 10kft r e s i s t o r i s used on the o t h e r . V o l t a g e l e v e l s i n the range 0 t o +100 v o l t s a re r e q u i r e d f o r s e t t i n g the s e r v o - s e t p o t e n t i o m e t e r s i n the a n a l o g computer. To produce v o l t a g e s i n t h i s range, the 0 t o -10 v o l t output of the DEC modules i n one of the tw e l v e h i t D/A c o n v e r t e r s i s f e d thr o u g h an o p e r a t i o n a l a m p l i f i e r i n the 231R-V which has a g a i n of t e n and i n v e r t s . An AD106B a m p l i f i e r o p e r a t i n g i n the non-i n v e r t i n g • mode i s used as an impedance b u f f e r s i n c e the i n p u t r e s i s t o r on the computer a m p l i f i e r cannot be a d j u s t e d t o compensate f o r the l a r g e output impedance of the DEC modules, and w i t h o u t impedance b u f f e r i n g , i n t o l e r a b l e e r r o r s would be i n t r o d u c e d . 5.2 The Seven and Eour B i t D/A C o n v e r t e r s . The seven and f o u r b i t D/A c o n v e r t e r s are b e i n g designed as p a r t of another p r o j e c t , but w i l l become a permanent p a r t of the h y b r i d i n t e r f a c e . They w i l l a c c e p t 2's complement d i g i t a l i n p u t s and produce a n a l o g o u t p u t s i n the range + 10 v o l t s . 5.3 D i g i t a l By A n a l o g M u l t i p l i c a t i o n A f o u r quadrant d i g i t a l by a n a l o g m u l t i p l i e r was designed 51 f o r the h y b r i d i n t e r f a c e . Some of these m u l t i p l i e r s may be i n c o r p o r a t e d i n t o the i n t e r f a c e i n the f u t u r e . The m u l t i p l i e r c i r c u i t i s g i v e n i n F i g u r e 5 - 2 . An R-2R l a d d e r network i s used, as i n a c o n v e n t i o n a l D/A c o n v e r t e r , but i n s t e a d of f i x e d r e f e r e n c e v o l t a g e s , v o l t a g e s p r o p o r t i o n a l t o the a n a l o g s i g n a l are s w i t c h e d onto the l a d d e r arms. D e p l e t i o n mode f i e l d e f f e c t t r a n s i s t o r s h a v i n g an "on" r e s i s t a n c e of l e s s than 30 ohms are employed as s w i t c h e s . The FET r e s i s t a n c e i s s m a l l compared t o the l a d d e r arm r e s i s t a n c e of 20k f l , and can be compensated f o r by u s i n g t r i m m i n g p o t e n t i o m e t e r s and a l a d d e r whose h i g h r e s i s t a n c e arms are 2R-x ohms, where x = 30. I f a c c u r a c i e s of the or d e r of twe l v e b i t s are r e q u i r e d , temperature s t a b l e r e s i s t o r s must be used. The d i g i t a l i n p u t t o the m u l t i p l i e r i s s u p p l i e d from an MRTL r e g i s t e r i n 2's complement format. The gate d r i v e c i r c u i t s a re s i m i l a r t o those used i n the m u l t i p l e x e r and shown i n F i g u r e 4-7. The a n a l o g s i g n a l , i s s u p p l i e d t h r o u g h o p e r a t i o n a l a m p l i f i e r s f o r t h r e e r e a s o n s : t o e l i m i n a t e the p o s s i b i l i t y of o v e r l o a d i n g the s i g n a l source; t o p r o v i d e an e f f e c t i v e d r i v i n g p o i n t impedance of l e s s t h a n one ohm so e r r o r v o l t a g e s due t o c u r r e n t s from the g a t e - s o u r c e : r e s i s t o r s , RQQ, of " o f f " FETs w i l l i n a l l cases be- i n s i g n i f i c a n t l y s m a l l ; and t o p r o v i d e the which i s needed. A n a l o g s i g n a l s i n the range + 10 v o l t s can be handled d i r e c t l y , but s i g n a l s o u t s i d e t h i s range must be s c a l e d down i n the i n p u t a m p l i f i e r and s c a l e d back up i n the output a m p l i f i e r . The output a m p l i f i e r i s operated i n the n o n - i n v e r t i n g 52 lOtcn. GfvTE DP-V\J6 FU>P Co6FFlC\et^T TRilA SR-x - A / W -• • • F i g u r e 5-2. D i g i t a l by An a l o g M u l t i p l i e r c o n f i g u r a t i o n i n order' t o o b t a i n a v e r y h i g h i n p u t impedance s i n c e i t i s d r i v e n by the l a d d e r , which i s a r a t h e r h i g h impedance s o u r c e . The f r e q u e n c y range of the m u l t i p l i e r depends upon the o p e r a t i o n a l a m p l i f i e r s which are used. The AD106B p r o v i d e s s a t i s f a c t o r y performance from D.C. t o 20kHz. 54 6. THE INTERRUPT SYSTEM •The.'interrupt system p r o v i d e s a method of c o n t r o l l i n g the PDP-9 from the h y b r i d i n t e r f a c e t h r ough the computer's a u t o m a t i c p r i o r i t y i n t e r r u p t (API) and program i n t e r r u p t ( P I ) f a c i l i t i e s . An event such as the changing of s t a t e of a f l i p f l o p or a com-p a r a t o r can be used t o s e t a f l a g i n the i n t e r r u p t system and cause t h e PDP-9 t o s t o p whatever i t i s d o i n g and execute a s p e c i f i e d s e r v i c i n g s u b r o u t i n e , t o r e t u r n t o the i n t e r r u p t e d job a t a l a t e r t ime. Three of the seven l i n e s i n the i n t e r r u p t system a re f o r i n i t i a t i n g a u t o m a t i c p r i o r i t y i n t e r r u p t s and f o u r are f o r program i n t e r r u p t s . The APIs have p r i o r i t y over the P i s and are ranked w i t h r e s p e c t t o one another f o r p r i o r i t y . They are p a r t i c u l a r l y u s e f u l i n programs o p e r a t i n g i n r e a l time environments. Except when a program of e q u a l or h i g h e r p r i o r i t y i s b e i n g executed, an i n t e r r u p t r e q u e s t i s g r a n t e d by the PDP-9 upon c o m p l e t i o n of the c u r r e n t i n s t r u c t i o n u n l e s s t h a t i n s t r u c t i o n i s an IOT or XCT, i n which case the r e q u e s t i s g r a n t e d upon c o m p l e t i o n of the i n s t r u c t i o n f o l l o w i n g the c u r r e n t i n s t r u c t i o n . I n t e r r u p t s from API l i n e s a r e s e r v i c e d more q u i c k l y t h a n those from PI l i n e s because w i t h the API f a c i l i t y one does not have to conduct -a f l a g s e a r c h t o determine which d e v i c e r e q u e s t e d the i n t e r r u p t . Complete d e s c r i p t i o n s o f the API and P I f a c i l i t i e s and t h e i r " a p p l i c a t i o n s can be found i n the PDP-9.User Handbook. 6.1 Program I n t e r r u p t s The p a r t of the i n t e r r u p t system which handles program 55 i n t e r r u p t s i s shown i n b l o c k diagram form i n F i g u r e 6-1. Each PI f l a g i s s e t w i t h a p u l s e from a d i f f e r e n t i a t o r and c l e a r e d To POP-<» PROGRM<\ \KYTERRUPT I KVRTV.-TO-Pt>P-<* CoiviEgfeR I To POP-") I/o e>os i . < L 4 UNES N\RTL-To- PDP-9 CONVERTERS NOR T IsWeRTERS s p e c i f G ^ E S (4) ReM> PI FiAGS ( . S E T - R C S E T FUKP F L O P ^ ) n S E T RESET D \ E Re wT \ ATO RS 4- LINES PoS\T\vlE - G O I N G L E M 6 U CUI\NG>€S> F R O N \ I N P U T T e R W i N f c L S O K i D(G\T\L t r TOT 2 I0T4 C L E & P PI FL*GS PuLSES - FfeOtA R E G I S T E R S E L E C T O R NOR. 6&res IUM&RTERS D l G n A L CotAPOTER SROUNO ^NfM-OG. COMPUTER GftouNO (4-) IWI-IUP' WC189P F i g u r e 6-1. I n t e r r u p t System-PI S e c t i o n w i t h the PI FLAGS READ command which reads i t onto the I/O bus of the PDP-9. The f l a g s can a l s o be c l e a r e d w i t h a PI FLAGS CLEAR command, which i s i s s u e d whenever the PDP-9 i s t u r n e d on, or w i t h the IOT i n s t r u c t i o n PIFC. The r e g i s t e r s e l e c t o r which s u p p l i e s the commands i s s i m i l a r t o the s e l e c t o r s used w i t h s t a n d a r d i n p u t i n t e r - f a c e s , but needs no p u l s e t r a n s f o r m e r s s i n c e the e n t i r e system of F i g u r e 6-1 i s t i e d t o d i g i t a l ground. Whenever a f l a g i s s e t and a w a i t i n g s e r v i c i n g a ground l e v e l i s a p p l i e d t o t h e program i n t e r r u p t t e r m i n a l of the PDP-9. by the D i g i t a l Equipment C o r p o r a t i o n i n t h e i r F l i p C h i p Modules, a l l o w the s i m u l t a n e o u s s a m p l i n g and r e s e t t i n g of the PI f l a g s . The c i r c u i t i s g i v e n i n F i g u r e 6-2. Each gate has a p u l s e i n p u t and a l e v e l i n p u t , and p r o v i d e s a d e l a y i n the l e v e l l i n e . I f t h e l e v e l has been at ground f o r a t l e a s t one microsecond b e f o r e the a p p l i c a t i o n of a one microsecond p u l s e , the p u l s e i s t r a n s -m i t t e d by the gate i r r e s p e c t i v e of what happens at the l e v e l i n p u t a f t e r the p u l s e has begun. S p e c i a l nand g a t e s , a d a p t a t i o n s of a c i r c u i t employed P U L S E IKSPOT I N P U T P u u s e OuTPuT F i g u r e 6-2. S p e c i a l Nand Gate I n p u t s from the d i g i t a l p a t c h p a n e l pass t h r o u g h d i f f e r e n t i a t o r s which p r o v i d e ground i s o l a t i o n ( a t D.C.) and generate f l a g - s e t t i n g p u l s e s from the l e v e l changes of f l i p f l o p s or comparators. The d i f f e r e n t i a t o r c i r c u i t i s shown i n F i g u r e 6-3. The d i o d e s p r o t e c t the f l i p f l o p s ( f l a g s ) from FRoiA OV&VTKL -P A T C H P A N E L 500 pf. A T~0 P I F t KG TER.N4MM. F i g u r e 6-3. D i f f e r e n t i a t o r damage i n the event t h a t p u l s e s or l e v e l changes of more than f o u r v o l t s magnitude are d e l i v e r e d t o the i n p u t t e r m i n a l . A p o s i t i v e - g o i n g l e v e l change of two t o f o u r v o l t s w i t h a r i s e time of l e s s t h a n 500 nanoseconds i s r e q u i r e d t o s e t a f l a g . 6.2 Automatic P r i o r i t y I n t e r r u p t s A u t omatic p r i o r i t y i n t e r r u p t s are handled by the system shown i n F i g u r e 6-4. The d i f f e r e n t i a t o r s and f l a g s are s i m i l a r t o those used i n the program i n t e r r u p t system. However, the ' methods of s e r v i c i n g and r e s e t t i n g the f l a g s are d i f f e r e n t . The API f l a g s are not r e a d onto the PDP-9's I/O bus l i k e the PI f l a g s , but r a t h e r a re s u p p l i e d t o API I n t e r f a c i n g Modules, d e s c r i b e d i n Appendix V I I . When an i n t e r r u p t r e q u e s t i s granted, 58 To P u P - c * A P I Te-RMK^vJS API MODULES < "i L I N E S f\PI F L A G S i > "bET OvFFEfeewTlAToR'i 3 UNES . cLgf\e POSVTWJE - G O l ^ G L-tMEL. OmN6E<i FRot* It^ PoT TERMINALS ON O16TAL PKTCU PAMEL F i g u r e 6 - 4 . I n t e r r u p t System - API S e c t i o n _ the a p p r o p r i a t e i n t e r f a c i n g module i s s u e s a p u l s e t o r e s e t ( o r c l e a r ) the API f l a g . The modules a l l i s s u e a f l a g - c l e a r i n g p u l s e when the PDP-9 i s t u r n e d on. One of the API l i n e s i s n o r m a l l y used t o s e r v i c e the A/D c o n v e r t e r i n the h y b r i d i n t e r f a c e . 6.3 P u l s e Shapers The outputs of the comparators on the 231R-V have a r i s e time of more t h a n 500 nanoseconds, and thus cannot be used d i r e c t l y "to s e t the f l a g s i n the i n t e r r u p t system. The t e n comparator outputs a r e t h e r e f o r e passed through p u l s e shapers b e f o r e b e i n g s u p p l i e d t o the d i g i t a l p a t c h p a n e l . The pu l s e s h a p i n g c i r c u i t i s g i v e n i n F i g u r e 6-5. 59 3/JKJI C O M P A R A T O R 33K5L To OvGvTAu P A T C U PAMEL +3.6 F i g u r e 6-5. P u l s e Shaper 60 7. CONTROL OF THE ANALOG- COMPUTER Most of the o p e r a t i o n s n o r m a l l y c a r r i e d out by means o f pushbuttons on the a n a l o g computer c o n s o l e can be performed through the h y b r i d i n t e r f a c e on command from the PDP -9 . The mode df the a n a l o g computer can be c o n t r o l l e d and sensed, and the mode of each i n t e g r a t o r -can be c o n t r o l l e d i n d e p e n d e n t l y . The s t e p p i n g s w i t c h e s i n . the s i g n a l s e l e c t o r system can be operat e d by l o a d i n g an e i g h t e e n b i t SOI w i t h the d e s i r e d s e l e c t o r a d d r e s s , and the output of the d i g i t a l v o l t m e t e r (DVM), which corresponds t o the v o l t a g e a t the p o i n t addressed, can be read i n t o the PDP -9 . A d d r e s s i n g and s e t t i n g of the f i f t y s e r v o - s e t p o t e n t i o m e t e r s i n the 231R-V i s a l s o a l l o w e d . I f the d e s i r e d p o t e n t i o m e t e r s e t t i n g i s not reached w i t h i n f o u r seconds, the servo motor i s disengaged and a d i a g n o s t i c message can be p r i n t e d on the PDP-9's t e l e t y p e . The d i f f e r e n c e between the d e s i r e d p o t e n t i o m e t e r s e t t i n g and the a c t u a l s e t t i n g can be found. One can a l s o check t h a t the d e s i r e d p o t e n t i o m e t e r address has been reached. To p l a c e t h e a n a l o g computer under c o n t r o l of the PDP -9 , the DVM s w i t c h on the a n a l o g c o n s o l e must be p l a c e d i n the REMOTE p o s i t i o n . Most s w i t c h i n g and c o n t r o l f u n c t i o n s i n the 231R-V are performed w i t h r e l a y s and s t e p p i n g s w i t c h e s which r e q u i r e 90 v o l t s D.C. f o r o p e r a t i o n . When the DVM s w i t c h i s a t REMOTE, the 90 v o l t s i s s u p p l i e d t o the s o l i d s t a t e s w i t c h e s i n the h y b r i d i n t e r f a c e which send c o n t r o l s i g n a l s t o 231R-V r e l a y s . When the s w i t c h i s not a t REMOTE, c o n t r o l of the 231R-V through the i n t e r f a c e i s l o s t except f o r the e l e c t r o n i c s w i t c h i n g of 6 1 of i n t e g r a t o r modes. 7.1 Mode C o n t r o l The Pace 231R-V a n a l o g computer has s i x b a s i c modes of o p e r a t i o n : OPERATE (OP), HOLD (H), INITIAL CONDITION ( I C ) , POT SET ( P S ) , STATIC TEST (ST) ahd RATE TEST (RT). I t can be made to operate i n any one of these modes on command from t h e PDP-9, and i t s mode can be sensed. The p o r t i o n of the h y b r i d i n t e r f a c e which p r o v i d e s the mode c o n t r o l i s shown i n b l o c k diagram form i n F i g u r e 7-1. To change the a n a l o g computer's mode, the accumulator of the PDP-9 must f i r s t be lo a d e d w i t h the a p p r o p r i a t e t h r e e b i t word (see Table 7-1). T h i s word i s gated i n t o a s e t of s i x d e c o d i n g nand gates and jam t r a n s f e r r e d i n t o the i n t e r f a c e : mode r e g i s t e r w i t h an ANALOG MODE UPDATE command. The mode r e g i s t e r c o n s i s t s of s i x JK f l i p f l o p s , one f o r each a n a l o g computer mode. When a new word i s lo a d e d i n t o t he r e g i s t e r , one and o n l y one f l i p f l o p changes to the ^ 1 " s t a t e . W ith t h i s change of s t a t e , the p u l s e g e n e r a t o r connected t o t h i s f l i p f l o p produces a p u l s e t o +90 v o l t s which i s a p p l i e d t o a mode bus bar i n the 231R-V t o execute the mode change. The -analog computer cannot be i n two or more modes s i m u l t a n e o u s l y . The de c o d i n g nand gates through which the mode r e g i s t e r i s l o a d e d ensure t h a t o n l y one mode a t a time can be re q u e s t e d . When the i n t e r f a c e i s i n i t i a l i z e d or an ANALOG MODE CLEAR command i s i s s u e d the POT SET mode f l i p f l o p i n the mode r e g i s t e r i s s e t t o the "1" ; s t a t e and thus the a n a l o g computer i s put t o the POT SET mode. 62 1 6lT \MOR0 F R O M P O P ~9 I O U T P U T B U F F E R I I 3 LITE'S 6uFF£R AMPLIFIERS ^ N\cT39P B u F F E t ? A t A p u F i e R S ^ I f f v C W P D E C O D E S VNPOT) I 1 INVERTER*. «1 MODE R E G I S T E R <.T<) A N A L O G M O P E O P P A VN)\T\KL-\££ O R P o u s e GENERATORS 1 I NPUT t A ^ D G.ATE9 lo * N M Q 6 I 0 T 4 <woi>e CHAM6E Pov-ses TO a^ie - v / IADPE BUS B A R S V/IA R.Pa-T2 £ GAT VMORO TO POP - 9 VIA I N P U T B U F F E R COMNvftHDS F R O M REGISTER SELECTORS L F i g u r e 7-1. 231E-V Mode C o n t r o l Table 7-1. 231R-V Mode C o n t r o l Words 63 MODE WORD OP 111 1C 101 H 110 PS 000 RT O i l ST 010 To sense the mode of the 231R-V, the c o n t e n t s o f the mode r e g i s t e r a r e load e d i n t o the PDP -9's accumulator through the i n p u t b u f f e r w i t h an ANALOG MODE READ command. The mode can th e n be determined by t h e PDP -9 w i t h a d i g i t a l s u b r o u t i n e s i m i l a r to - a f l a g s e a r c h . Commands from the PDP -9 t o the mode c o n t r o l p o r t i o n of the i n t e r f a c e are d e l i v e r e d t h r ough a r e g i s t e r s e l e c t o r s i m i l a r t o those employed w i t h s t a n d a r d i n p u t i n t e r f a c e s ( i . e . i n c l u d i n g the one microsecond p u l s e g e n e r a t o r , the INITIALIZE p u l s e input,'' and the c o n n e c t i o n t o the PDP - 9 's read r e q u e s t t e r m i n a l ) . D u r i n g e x e c u t i o n o f a f o u r microsecond IOT i n s t r u c t i o n , IOP p u l s e s can be i s s u e d - a t one microsecond i n t e r v a l s from the PDP -9 i n the ord e r I0P1, I0P2, I0P4 (see Appendix I I I ) . I t i s f o r b i d d e n t o e i t h e r l o a d a r e g i s t e r from or read a r e g i s t e r onto the I/O bus 64 of the PDP-9 w i t h a command generated w i t h an I0P1 p u l s e . S i n c e we w i s h t o he a b l e t o l o a d and r e a d , u s i n g one r e g i s t e r s e l e c t o r , and the two o p e r a t i o n s cannot be c a r r i e d out s i m u l t a n e o u s l y , we use I0P2 t o generate the ANALOG MODE UPDATE command which l o a d s the mode r e g i s t e r , and I0P4 t o generate the one microsecond ANALOG MODE READ command which reads the r e g i s t e r c o n t e n t s i n t o the PDP-9. U s i n g t h i s sequence, we can perform a q u i c k check on the mociie c o n t r o l c i r c u i t r y i n the i n t e r f a c e by examining the mode r e g i s t e r ' s c o n t e n t s i m m e d i a t e l y a f t e r l o a d i n g i t . We can generate ANALOG MODE CLEAR commands w i t h I0P1 p u l s e s . To ac c o m p l i s h the above t a s k s u s i n g the s t a n d a r d r e g i s t e r s e l e c t o r p r i n t e d c i r c u i t (shown i n F i g u r e 2-5), i t i s n e c e s s a r y t o a p p l y the PDP-9's I0P1 p u l s e t o the t e r m i n a l which n o r m a l l y r e c e i v e s I0P2, t o a p p l y I0P2 t o the t e r m i n a l which n o r m a l l y r e c e i v e s I0P4, and t o a p p l y I0P4 t o the t e r m i n a l which n o r m a l l y r e c e i v e s I0P1. The c i r c u i t used f o r g e n e r a t i o n of the 90 v o l t p u l s e s f o r +3L&V. +9ov. (SUPPLIED ONLY wv\e»4 I 0\lNv SVNVTCH isi^RENiOTE" | po-SVrvosO Nvooe ReG>v<=>TE<r Fnp FLOP (KV1NLO& T RE LAV F i g u r e 7-2. P u l s e Generator 65 a p p l i c a t i o n t o the computer's mode bus b a r s i s shown i n F i g u r e 7-2. A p o s i t i v e s t e p a p p l i e d t o the i n p u t s a t u r a t e s T-^ , c u t s o f f T^, and s a t u r a t e s T^, p r o d u c i n g a 60 ms. p u l s e from ground to +90 v o l t s ( a p p r o x i m a t e l y ) . The c i r c u i t i s an improvement on one employed by E l e c t r o n i c A s s o c i a t e s , I n c . f o r s i m i l a r purposes.^" The mode bus ba r s i n the 231R-V are a c c e s s i b l e t h rough c o n n e c t o r RP2-J2 on the back of the c o n s o l e . The'pin c o n n e c t i o n s a re l i s t e d i n Appendix V I I I . 7.2 I n t e g r a t o r Mode C o n t r o l To p r o v i d e f l e x i b i l i t y f o r h y b r i d o p e r a t i o n s and t o a l l o w the use of i n t e g r a t o r s as t r a c k and h o l d a m p l i f i e r s , i n d i v i d u a l i n t e g r a t o r mode c o n t r o l i s p r o v i d e d t h r o u g h the i n t e r f a c e . The mode of each of the s i x t e e n i n t e g r a t o r s i n the a n a l o g computer can be determined by the s t a t e of a p a r t i c u l a r f l i p f l o p i n an SOI output r e g i s t e r . Both Telay and e l e c t r o n i c mode s w i t c h i n g are employed i n the 231R-V,the former f o r i n t e g r a t o r time c o n s t a n t s of .1 seconds or more and the l a t t e r f o r time c o n s t a n t s of .01 seconds or l e s s . Each i n t e g r a t o r has a s s o c i a t e d w i t h i t two mode r e l a y s , KI and K2, whose c o i l s a r e t e r m i n a t e d on the 3450 h o l e p r e p a t c h p a n e l , and an e l e c t r o n i c s w i t c h i n g system whose i n p u t t e r m i n a l s are l o c a t e d on the M1G p a t c h p a n e l ^ . When r e l a y s w i t c h i n g i s b e i n g employed, the i n t e g r a t o r mode corresponds t o the r e l a y s t a t e s as i n d i c a t e d i n Table 1-2. To e n e r g i z e a r e l a y , a p u l s e t o a p p r o x i m a t e l y +90 v o l t s , d e c a y i n g t o a s u s t a i n i n g l e v e l of +25 v o l t s i s r e q u i r e d . A f l o a t i n g or ground l e v e l i n p u t r e l e a s e s the r e l a y . When i n d i v i d u a l i n t e g r a t o r 66 Table 7-2. R e l a y S t a t e s and I n t e g r a t o r Mode MODE RELAY KI RELAY K2 OP Re l e a s e d R e l e a s e d H Re l e a s e d E n e r g i z e d IC E n e r g i z e d E n e r g i z e d mode c o n t r o l i s not r e q u i r e d , a gre y b o t t l e p l u g . i n s e r t e d i n the p r e p a t c h " p a n e l s u p p l i e s these c o n t r o l v o l t a g e s from the mode bus b a r s . F o r i n d i v i d u a l c o n t r o l , however, the c o n t r o l v o l t a g e s are s u p p l i e d from c i r c u i t s l i k e t h a t i n F i g u r e 7-3. The i n t e g r a t o r mode c o n t r o l p o r t i o n of the i n t e r f a c e c o n t a i n s s i x t e e n of these F R o w Sol OOTPOT RE6 VVVER -±r B l \ R - \ / G R O U N D usov.) TtRiAvviivCtoN P R C P K V C H F i g u r e 7-3. I n t e g r a t o r Mode C o n t r o l R e l a y D r i v e r 67 c i r c u i t s . Each i s d r i v e n from an SOI f l i p f l o p ( b u f f e r e d ) , and d e l i v e r s I t s qutput s i g n a l t o an IN TRUNK t e r m i n a t i o n on the p r e -pa t c h p a n e l , from which i t can be patched t o a mode c o n t r o l r e l a y . A p p l i c a t i o n of an SOI "0" i n p u t , or ground l e v e l , c u t s o f f T l , s a t u r a t e s T2, and produces a s t e p from ground t o +86 v o l t s a t the outp u t . The 10 \if. c a p a c i t o r t h e n charges through the 5 * 6 k l l r e s i s t o r and the v o l t a g e a t the c i r c u i t output drops t o +25 v o l t s , which i s s u f f i c i e n t t o h o l d a r e l a y i n . When an SOI "1", or p o s i t i v e l e v e l , i s a p p l i e d T l i s s a t u r a t e d , T2 i s cut o f f , and the c i r c u i t 'Output i s a ground l e v e l , which r e l e a s e s the r e l a y which i s a t t a c h e d . The c i r c u i t can be m o d i f i e d t o d r i v e up t o f o u r r e l a y s a t a time by a d d i n g the 1N3000 62 v o l t zener diode as i n d i c a t e d . 0 and +5 v o l t s . To a l l o w c o n t r o l of t h i s system from a st a n d a r d output i n t e r f a c e , a s e t o f s i x t e e n c i r c u i t s l i k e the one shown i n F i g u r e 7-4 have been employed. Each a c c e p t s MRTL l e v e l i n p u t s C o n t r o l v o l t a g e s f o r t h e e l e c t r o n i c s w i t c h i n g system a re Sol A M A -F i g u r e 7-4. L e v e l C o n v e r t e r f o r E l e c t r o n i c Mode S w i t c h i n g 68 and. produces 0 and +5 v o l t o u t p u t s . An SOI "1" i n p u t produces a 0 v o l t output; and puts the i n t e g r a t o r i n the OPEEATE mode, w h i l e an SOI -"-0" produces a +5 v o l t output and puts the i n t e g r a t o r i n the INITIAL CONDITION mode. The l e v e l c o n v e r t e r s are t e r m i n a t e d on the MLG- p a t c h p a n e l f o r c o n n e c t i o n t o the e l e c t r o n i c s w i t c h i n g system. 7.3 S i g n a l S e l e c t o r C o n t r o l The s i g n a l s e l e c t o r system i n the a n a l o g computer i s a group o f s t e p p i n g s w i t c h e s and r e l a y s t h rough which output t e r m i n a l s on the 3450-hole p r e p a t c h p a n e l can he s e l e c t e d f o r readout and s e r v o - s e t p o t e n t i o m e t e r s can be s e l e c t e d f o r s e t t i n g . A t o t a l of 540 p o i n t s i n the computer, i n c l u d i n g the o u t p u t s of a l l o p e r a t i o n a l a m p l i f i e r s , e l e c t r o n i c m u l t i p l i e r s , and poten-t i o m e t e r s can be s e l e c t e d , and the v o l t a g e a t the s e l e c t e d p o i n t can be d i s p l a y e d - on the d i g i t a l v o l t m e t e r . 7.3-1 S i g n a l S e l e c t o r Mode C o n t r o l Three -modes o f s i g n a l s e l e c t o r o p e r a t i o n a re d e f i n e d : READOUT, ATTENUATOR CHECK, and ATTENUATOR SET. The ATTENUATOR SET mode i s en t e r e d when a s e r v o - s e t p o t e n t i o m e t e r i s t o be set,'' and the ATTENUATOR CHECK mode i s e n t e r e d when the s e t t i n g , or c o e f f i c i e n t , of a s e r v o - s e t p o t e n t i o m e t e r i s t o be checked. At a l l o t h e r t i m e s , the s i g n a l s e l e c t o r must be operated i n the READOUT mode. 7 The s i g n a l s e l e c t o r mode c o n t r o l p o r t i o n of the i n t e r f a c e i s shown i n F i g u r e 7-5 i n the READOUT mode. I t i s c o n t r o l l e d from the PDP-9 through the f o u r b i t SOI i n d i c a t e d i n F i g u r e 1-1, and i s o p e r a b l e o n l y when the DVM s w i t c h i s i n the REMOTE 69 R E A D O U T SOI JESTED. NtlWP KvttB'JP A N M D i s N E f c T E R - o A T T E N U A T O R CHECK GATE N\C12AP O NVIEBTER N\cne<)P REuAy ATTENUATOR SET &KTE *WEfcTEfc ORwlEp. -> TO COvmECToR RP2.-J& ON e^vR-v T o SERvlO-SET POT. CONTROLS F i g u r e 7-5. S i g n a l S e l e c t o r Mode C o n t r o l p o s i t i o n . To cause the s i g n a l s e l e c t o r t o e n t e r a mode, approx-i m a t e l y 90 v o l t s must he a p p l i e d t o the a p p r o p r i a t e r e l a y i n the 231R-V. The r e l a y d r i v e r on each mode l i n e produces outputs of +88 v o l t s "or 0 v o l t s , as r e q u i r e d . The c i r c u i t i s g i v e n i n F i g u r e 7-6. To p l a c e the s i g n a l s e l e c t o r i n the READOUT mode, the SOI i s l o a d e d w i t h OOOO2. The word 0001^ p l a c e s the..'..selector i n the ATTENUATOR-SET mode, and 0010 2 p l a c e s i t i n the ATTENUATOR CHECK mode. When the i n t e r f a c e i s i n i t i a l i z e d , the SOI i s c l e a r e d t o 0000^ and the READOUT mode i s e n t e r e d . 70 v g c w . ( s o P P u v e U ONLY VWHEN) 'fe£N\0TE" POSVTVONi) I A P T L " U N I T 8.2. kSt -AAAA TO REUKS F i g u r e 7-6. R e l a y D r i v e r 7 . 3 - 2 S i g n a l S e l e c t o r Address C o n t r o l The s i g n a l s e l e c t o r address c o n t r o l i n the h y b r i d i n t e r f a c e a c c e p t s a n " e i g h t e e n b i t address word from an SOI and causes t h e s i g n a l s e l e c t o r t o s t e p t o the s p e c i f i e d p o s i t i o n . The ^address c o n s i s t s o f t h r e e s i x b i t c h a r a c t e r s i n T e l e t y p e Q code. The f i r s t c h a r a c t e r i s a l e t t e r which i n d i c a t e s the group of out p u t s s e l e c t e d - f o r example,A f o r a m p l i f i e r s , or M f o r m u l t i p l i e r s - and the r e m a i n i n g two c h a r a c t e r s are d e c i m a l d i g i t s which s p e c i f y a p a r t i c u l a r output w i t h i n the group. The T e l e t y p e code i s used because t h i s i s the code i n which t e x t i s s t o r e d i n the PDP-9. Three s i x b i t c h a r a c t e r s are s t o r e d i n one memory l o c a t i o n , so a s i n g l e i n s t r u c t i o n can be used t o l o a d t h e accumulator w i t h the d e s i r e d a d d r e s s . The word can be used as r e c e i v e d from the t e l e t y p e , w i t h o u t m o d i f i c a t i o n . The address format of one l e t t e r f o l l o w e d by two d e c i m a l d i g i t s conforms w i t h the format employed i n the a n a l o g computer. 71 A b l a c k diagram of the s i g n a l s e l e c t o r address c o n t r o l i s g i v e n i n "Figure 7-7. When an address i s l o a d e d i n t o the SOI output r e g i s t e r , each of the decoders produces ground l e v e l >6 BIT vJoEO FROM PbP-<} STP^bfvRb OOTPOT INTERFACE I8UU6S IOT4 POLSE FRoWV feEfel^TER .SELECTOR. i fc HUNDREDS (.LETTER?.) CODER M>t>RE*S REACHED FRON\ VTEWMUG S*J\TO\ES M)bRS<iS ON REACHES (.CovwfcCToR LRefcCHeo LEVEL. CONVERTERS (.QNvTS) LEV/EL. CONVERTERS IreuS) LEVEL CONVERTERS 1 TEtfS bECODER P,\)bRE^ > DEVREO 10 UN\TS D E C O D E R ADDR6% O E S \ P t D \0 C O N T R O L NETWORK (.VAWtoPfifc) I I I I r - * - n i REL(V< 1 ] ^Rvs lER j I i AA 10 MJOREIS "SET FLiP FixP OESvPEu CONTROL NETWORK (TE>4S) I A LA C O N T R O L NETWORK (ONVTS^ R E L M DRvVER 1 ' T O RELMS A R E L A V D R V J E R A. R E L I W ORWJER To 1 Ho^aeeos VToP R E L M 1 TO.-'.,. TENS RELKV R E L K V DRWJER Tevft STOP R E U K V 1 To C O N N E C T O R NVTlb ON &^\R-V ' To ' UNVTS STOP REA-Kf NOR G M E IMmhUlE PUL-aE 6EHERMofi .SERVO STAT09 C O N N E C T O R N\3T) A. DRvlER To T M > D R € « SET R E L I W V>V£>\TNL PATCV* PANEL . 1 To CONwECToR >ATV7 ON Z ^ R - V F i g u r e 7-7. S i g n a l S e l e c t o r Address C o n t r o l 72 o u t p u t s on two of i t s l i n e s . These are a p p l i e d t o the a p p r o p r i a t e c o n t r o l network. The IOT p u l s e which l o a d s the SOI r e g i s t e r s e t s the ADDRESS SET f l i p f l o p , and i f the DVM s w i t c h on the a n a l o g c o n s o l e i s i n the REMOTE p o s i t i o n as r e q u i r e d f o r h y b r i d o p e r a t i o n , the r e l a y d r i v e r connected t o t h i s f l i p f l o p a p p l i e s power t o the motors of the s i g n a l s e l e c t o r s t e p p i n g s w i t c h e s . There are t h r e e groups of s w i t c h e s , one group f o r each c h a r a c t e r i n the a d d r e s s . I n each group, t h e r e i s one w i p e r arm t o which +90 v o l t s i s a p p l i e d . As the group of s w i t c h e s s t e p s around i t s c y c l e , t h i s arm touches i n t u r n , one c o n t a c t c o r r e s p o n d i n g t o each p o s s i b l e v a l u e of the c h a r a c t e r . Each s e t of c o n t a c t s i s connected through l e v e l c o n v e r t e r s t o a c o n t r o l network as shown i n F i g u r e 7-7. When a group of s w i t c h e s reaches the d e s i r e d p o s i t i o n , the a s s o c i a t e d c o n t r o l network a c t s t h r o u g h i t s r e l a y d r i v e r t o c l o s e a s t o p r e l a y which'removes power from the s t e p p i n g s w i t c h motors. When a l l t h r e e "groups have reached the d e s i r e d p o s i t i o n s , the ADDRESS SET f l i p f l o p i s r e s e t t o the q u i e s c e n t s t a t e . The s t e p p i n g s w i t c h e s do not move, a g a i n u n t i l a new s i g n a l s e l e c t o r , address i s r e q u e s t e d . Table 7-3 l i s t s the o c t a l e q u i v a l e n t s of the l e t t e r s and numb-e r s used:in s p e c i f y i n g a d d r e s s e s . F i g u r e 7-8 i s a b l o c k diagram of the t e n s decoder ( d e c o d i n g , as an example, the number " 5 " ) . The u n i t s decoder i s i d e n t i c a l , and the hundreds ( l e t t e r s ) decoder i s c o n s t r u c t e d on the same p r i n c i p l e . F i g u r e 7-9 shows one of the l e v e l c o n v e r t e r s used t o s c a l e the +90 v o l t s o b t a i n e d from the s i g n a l s e l e c t o r c o n t a c t s down t o +2.6 v o l t s f o r use w i t h MRTL l o g i c modules i n the c o n t r o l networks. I n p u t s from Table 7-3. S i g n a l S e l e c t o r Addresses 73 231R-V O c t a l E q u i v a l e n t of T e l e t y p e Code R 22 M 15 F 06 C 03 A 01 T 24 P 20 Q 21 0 60 l 61 2 62 3 63 4 64 5 65 6 66 7 67 8 70 9 71 the s t e p p i n g s w i t c h e s a re +90 v o l t s f o r a s s e r t i o n , f l o a t i n g o t h e r w i s e . Outputs are ground f o r a s s e r t i o n , and a p o s i t i v e l e v e l o t h e r w i s e . 74 CODE FRoNv S o l -OOTPOT RE&V5TEt SECOVJV> O C T K L -cn&iT INvlefcTER tviVERTER INVERTER F I R S T O C T K L , DlGvT INVERTER AND GME" IWH6BP G A T E A N D GATlf A N b GATE AN\> G A T E A N D 5 < G K T E ANX> 6 ATE AND G A T E r INVERTED O y\ AND G A T E , o INVERTED ANt> GAT£ I ° r SECOND O C T A L UIG.IT TO • CONTROL NETWORK FIRST OCTAL DIGIT F i g u r e 7-8. Tens Decoder FRotA S T E P P IMG _ SNITCH OM 53IR-V (^CONNECTOR OR — F L O A T M G INVERTER I*LI69P -O To CONTROL NETV4GRVC (Fvk.VIo) F i g u r e 7-9. L e v e l C o n v e r t e r 75 The "tens c o n t r o l network i s shown i n F i g u r e 7-10. The output t o the te n s s t o p r e l a y d r i v e r i s a ground l e v e l when the d e s i r e d t e n s a d d r e s s , r e c e i v e d from the tens decoder, and the a c t u a l t e n s a d d r e s s , r e c e i v e d from the s t e p p i n g s w i t c h e s through the l e v e l c o n v e r t e r s , c o i n c i d e . C o i n c i d e n c e i s sensed w i t h the t h r e e - i n p u t nand g a t e s . The l o g i c l e v e l s d e p i c t e d i n F i g u r e 7-10 are those which would he p r e s e n t i f the s i g n a l s e l e c t o r were s t a t i o n a r y a t a p o i n t whose tens address d i g i t i s a " 5 " . The b i - q u i n a r y tens output i s r e q u i r e d f o r the o p e r a t i o n of c o n t r o l r e l a y s i n the a n a l o g computer. The "b i - q u i n a r y nor gate produces a ground l e v e l output i f the tens d i g i t i s g r e a t e r " ADDRESS REACHED" " (pRoM UEVJEL CObWERTefcS) MAND SATE NANb GfcTE GKTE NAvlt) GATE Nf\uu GATE N A N O G A T E GATE NA»V) GAT6 I [_ MAN& I r GATE G A T E 0 1 1 3 4 5 6 1 6 7 r — , ' D E S I R E D ADDRESS FROM TENS DECODER NOR 3j_GAT£ MIEPTSR — , N\C78<$P / NoR GfcTE iNVEergR NOP. Z<q GATE NCR GATE ^Cissp To RELAV DRVMER FoR TENS STop L RELKY ToREUVY D R N E R FoR fel-QOlN. F i g u r e 7-10. Tens C o n t r o l Network 76 t h a n f o u r , and e n e r g i z e s the r e l a y s through the r e l a y d r i v e r . A s i m i l a r b i - q u i n a r y output i s r e q u i r e d f o r the hundreds d i g i t i f the a n a l o g computer c o n t a i n s the d i g i t a l d iode f u n c t i o n g e n e r a t o r (DDFG) expansi o n . We do not a t p r e s e n t have t h i s e x p a n s i o n . c o n t r o l ( F i g u r e 7 - 7 ) are i d e n t i c a l t o those used i n the s i g n a l s e l e c t o r mode c o n t r o l . The c i r c u i t i s g i v e n i n F i g u r e 7 - 6 . The SIGNAL SELECTOR STATUS l e v e l on the a n a l o g computer s i t s a t +90 v o l t s when., the s i g n a l s e l e c t o r i s s t a t i o n a r y , and : f l o a t s when the s e l e c t o r i s moving. The change which o c c u r s I n t h i s l e v e l when the d e s i r e d address i s reached i s used t o generate a p u l s e t o r e s e t the ADDRESS SET f l i p f l o p i n the s i g n a l s e l e c t o r address c o n t r o l ( F i g u r e 7 - 7 ) . The l e v e l c o n v e r t e r and d i f f e r e n t i a t ; o r used t o generate the p u l s e are shown i n F i g u r e The r e l a y d r i v e r s employed i n the s i g n a l s e l e c t o r address 7-11. S»6uKL SELECTOR STWuS (.CONNECTOR T o NOR F i g u r e 7-11. P u l s e Generator 77 The ADDRESS SET f l i p f l o p output i s a v a i l a b l e on the d i g i t a l p a t c h panel,, where i t can be patched i n t o the d e v i c e f l a g f a c i l i t y or the i n t e r r u p t system so the PDP-9 can t e l l when the d e s i r e d address has been reached. 7.4 S e r v o - s e t P o t e n t i o m e t e r C o n t r o l s To s e t a s e r v o - s e t p o t e n t i o m e t e r , the f o l l o w i n g sequence of o p e r a t i o n s must be executed: 1. P l a c e the a n a l o g computer i n the POT SET mode. 2. Load the a p p r o p r i a t e D/A c o n v e r t e r w i t h the d e s i r e d p o t e n t i o m e t e r c o e f f i c i e n t . 3. Command the s i g n a l s e l e c t o r t o s t e p t o the address of the p o t e n t i o m e t e r which i s t o be s e t . 4. P l a c e the s i g n a l s e l e c t o r i n the ATTENUATOR SET mode. C o n t r o l of the s e r v o - s e t p o t e n t i o m e t e r s i n the 231R-V i s p r o v i d e d t h r o u g h the system shown i n F i g u r e 7-12. The command p u l s e which p l a c e s the s i g n a l s e l e c t o r i n the ATTENUATOR SET mode i s used to- s e t the SERVO ON f l i p f l o p and t o t r i g g e r the f o u r second monostable m u l t i v i b r a t o r (see Appendix IV f o r monostable d e s i g n d e t a i l s ) . Two r e l a y d r i v e r s a r e connected t o the f l i p f l o p t o operate the analog, computer's SERVO CONNECT and SERVO DISCONNECT r e l a y s . When the f l i p f l o p i s s e t , the SERVO CONNECT r e l a y s a re energized., the SERVO DISCONNECT r e l a y s a r e d e - e n e r g i z e d , and the ser v o motor i s engaged t o s e t the addressed p o t e n t i o m e t e r . The SERVO STATUS l e v e l from the 231R-V f l o a t s w h i l e the s e t t i n g i s i n p r o g r e s s , and goes t o +90 v o l t s when the s e t t i n g has been completed. N o r m a l l y , a s e t t i n g i s completed i n a p p r o x i m a t e l y two seconds, and t h e change which then o c c u r s i n the SERVO STATUS l e v e l i s used t o generate a p u l s e which r e s e t s 78 the SERVO ON f l i p f l o p and t e r m i n a t e s the o p e r a t i o n . The p u l s e g e n e r a t o r c i r c u i t i s g i v e n i n F i g u r e 7-11. FRotA (COHWECTOQ Rf*-Ti>) $TATO<3 PULSE IOT* POLSE FRotA REGISTER SELECTOR USED To L O M ) 4BlT ^.or ( s i & . S E L . NVoDE^  FRoH| ~~ SI&NI^L SELECTOR NvoOE CONTROL (.FVG .1-1) INSERTER N\C"I8<)P N\ODE L E A / E L GKTE 4 S E C o w O tACiaaP IvWERTER 3-K\t169P RELI^ ORwlER O v k l T N -P M C H PI\HEL To 1 To 1 SEISxJO SEfev/O CowweCT OlSCortNECT ReUWS RetMS , 1 To CoMsveCToR R P 5 - T E 0H23IP. -V I TO 1 I -"TO I " S»IAOLTA e^oOS tHGlTAL OVDKTt" \NPUT WvrcM OF REGvSTER PfV^EL SELECTOR OSES To LoKt) 4. <&\T SOI CSIS.SEL. t^OOE) F i g u r e 7-12. S e r v o - s e t P o t e n t i o m e t e r C o n t r o l s Four seconds a f t e r the s t a r t of a p o t e n t i o m e t e r - s e t t i n g c y c l e , the output of the monostable m u l t i v i b r a t o r r e t u r n s t o i t s 79 q u i e s c e n t ground l e v e l (see Appendix 17 f o r d e s i g n d e t a i l s ) . I f the p o t e n t i o m e t e r has not been s e t , the SER70 STATUS i n p u t i s s t i l l f l o a t i n g , and the l e v e l c o n v e r t e r , -which i s s i m p l y a v o l t a g e d i v i d e r w i t h one end grounded, s u p p l i e s a ground l e v e l t o the two-input nand gate. Thus the SER70 ON f l i p f l o p i s r e s e t and the serv o motor i s disengaged. The p u l s e which r e s e t s the f l i p f l o p i n t h i s i n s t a n c e i s a v a i l a b l e on the d i g i t a l p a t c h p a n e l where i t can be patched i n t o the i n t e r r u p t system. On r e c e i v i n g the i n t e r r u p t r e q u e s t the PDP -9 can type out a message t o i n f o r m the u s e r that; d i f f i c u l t y has been encountered. The p u l s e which r e s e t s the SER70 ON f l i p f l o p a l s o i s used t o c l e a r the;'output r e g i s t e r of t h e f o u r b i t SOI which c o n t a i n s the s i g n a l s e l e c t o r mode i n f o r m a t i o n so the mode i s r e t u r n e d t o READOUT (see s e c t i o n 7.3.1). T h i s ensures t h a t the programmer cannot a c c i d e n t a l l y l e a v e the s i g n a l s e l e c t o r i n the ATTENUATOR SET mode when h i s p o t e n t i o m e t e r s e t t i n g o p e r a t i o n s are completed. - I f the computer i s p l a c e d i n the OPERATE mode w h i l e the s i g n a l s e l e c t o r i s s t i l l i n the ATTENUATOR SET mode, erroneous output v o l t a g e s a re o b t a i n e d from the p o t e n t i o m e t e r s . The SERVO ON f l i p f l o p output i s a v a i l a b l e on t h e d i g i t a l p a t c h p a n e l where i t can be patched i n t o the d e v i c e f l a g f a c i l i t y or t he i n t e r r u p t system t p p r o v i d e the PDP -9 w i t h a way f o r d e t e r m i n i n g when the s e t t i n g o p e r a t i o n has been completed. As was mentioned i n Chapter 5, the output o f a t w e l v e b i t D/A c o n v e r t e r "must be f e d through an o p e r a t i o n a l a m p l i f i e r i n the a n a l o g computer t o produce the D.C. l e v e l i n the 0 t o +100 v o l t range needed f o r s e t t i n g a p o t e n t i o m e t e r . The a m p l i f i e r must be 80 i n the OPERATE mode when the r e s t of the computer i s i n the POT SET mode, and i t s output-must be s u p p l i e d t o t e r m i n a l RP2-J2-0 on the 231R-V console" through a r e l a y which breaks the c o n n e c t i o n whenever the DVM s w i t c h i s not i n the REMOTE p o s i t i o n . 7.5 D i g i t a l V o l t m e t e r Readout The a n a l o g computer's d i g i t a l v o l t m e t e r (DVM) and s i g n a l s e l e c t o r system o p e r a t e - t o g e t h e r t o p r o v i d e a low speed 540 p o i n t m u l t i p l e x e r - A / D c o n v e r t e r which can be v e r y u s e f u l d u r i n g the set-up and check-out of h y b r i d problems. When s e r v o - s e t p o t e n t i o m e t e r s a re b e i n g s e t , f o r example, the a c t u a l s e t t i n g a t t a i n e d can be read from the - DVM. The output v o l t a g e s of o p e r a t i o n a l a m p l i f i e r s can a l s o be monitored t o check f o r d r i f t . The output' of the "DVM can be read i n t o the PDP-9 th r o u g h a s t a n d a r d i n p u t i n t e r f a c e (see F i g u r e .1—1). To match l o g i c l e v e l s , the l e v e l conve^ter'•"'sho"wn-•-in"• F i g u r e 7-13 must be employed i n each c o n n e c t i n g l i n e : ; The' "converter a c c e p t s the DVM out p u t s of -12 and +2 v o l t s (-12 v o l t s "for a s s e r t i o n ) and produces MRTL l e v e l vV\A F i g u r e 7-13- DVM-Output L e v e l C o n v e r t e r 81 o u t p u t s . The d i g i t a l word i s e i g h t e e n b i t s l o n g , c o n s i s t i n g of f o u r b i n a r y - c o d e d - d e c i m a l d i g i t s (8421), :& s i g n b i t , and a "hundreds" b i t , and i n d i c a t e s the v o l t a g e a t the p o i n t addressed t o the n e a r e s t 10 mv. The i n p u t v o l t a g e range of the DVM i s +120 v o l t s . The DVM r e q u i r e s a maximum of t e n m i l l i s e c o n d s t o perform an A/D c o n v e r s i o n . I t s output s h o u l d be f r o z e n w i t h a DVM LOCK command b e f o r e b e i n g r e a d . i n t o the PDP-9. The command i s i s s u e d from a r e g i s t e r s e l e c t o r t o the c i r c u i t shown i n F i g u r e 7-14, i - I S 7. V-OCK 1 \M4>54 ifJ4tS4 F i g u r e 7-14. DVM Lock C i r c u i t and r e s u l t s i n a l o c k i n g i n t e r v a l of 100 microseconds. The monostable m u l t i v i b r a t o r i s d e s c r i b e d i n Appendix IV. 7.6 P o t e n t i o m e t e r Address Ch e c k i n g I t i s p o s s i b l e f o r the a n a l o g computer's s i g n a l s e l e c t o r system t o i n d i c a t e t h a t a se-rvo-set p o t e n t i o m e t e r address has been reached when c e r t a i n s t e p p i n g s w i t c h e s a s s o c i a t e d w i t h the poten-t i o m e t e r s have not reached the c o r r e c t p o s i t i o n ( t h i s s h o u l d not occur i f the computer i s o p e r a t i n g p r o p e r l y ) . P r o v i s i o n has been made i n the h y b r i d i n t e r f a c e f o r c h e c k i n g t h a t the d e s i r e d p o t e n t i o m e t e r address has been reached. The a c t u a l a d d r e s s , c o n s i s t i n g of a "P" or "Q" and two b i n a r y coded d e c i m a l d i g i t s i s a v a i l a b l e from c o n n e c t o r MJ17 on the 231R-V c o n s o l e . The output i s +90 v o l t s f o r a s s e r t i o n , f l o a t i n g o t h e r w i s e . A s e t of l e v e l c o n v e r t e r s i d e n t i c a l t o the one i n F i g u r e 7-9 i s used t o s u p p l y the i n f o r m a t i o n t o an S I I (see F i g u r e l - l ) . APPENDIX I LOGIC LEVEL SYMBOLOGY t h M o t o r o l a MC700P S e r i e s MRTL I n t e g r a t e d C i r c u i t s : SYMBOL MEANING o Ground L e v e l For A s s e r t i o n • P o s i t i v e L e v e l F o r A s s e r t i o n • P u l s e t o P o s i t i v e L e v e l f o r A s s e r t i o n > P u l s e t o Ground L e v e l f o r A s s e r t i o n >• Nonstandard S i g n a l t h PDP-9: SYMBOL MEANING o Ground L e v e l F o r A s s e r t i o n • N e g a t i v e L e v e l F o r A s s e r t i o n • Standard N e g a t i v e P u l s e -t> Standard P u l s e t o Ground ( P o s i t i v e P u l s e ) 84 APPENDIX I I GENERATION OP INITIALIZE PULSE: I/o POWER, CLEAR PULSE isSoEft 8V PDP-9 WHESh (A) POVMER TORfSEb oti (6) CAF INSTRUCTS OCCURS Ct) I/O RESET KeV DEPRESSED POP-^ -To W\RT1_ NOR B o F F E R GATE —^ MAPUFlEP I/O SVMCV\. p o v . s e ^IIAUE. CLOCK FRotw PDP-9) rf\PTU CONWEVTER " vKUTlAUZE INTERFACE" POSHBOTTOKi. BUFFER AWvPUFVER yv\CB9P INITIALIZE PULSES TO REGISTER SELECTORS AHO OTHER EQOVPmENT DVGVTKL SvDE OF V M T E P . F K C E P O L S E 1 TRKVJSF. 1 Puv-SE TRWN&F. c "(NITIALIZE PULSES To SOT OOTPOT REGVSTERS KSVD OTHER EQOVPNVEHT ON ANALC6 S lDE OF It-vTECFK-E I D I G I T A L ! A N A L O G C O M P U T E R CONVPOTER 85 APPENDIX I I I " INPUT/OUTPUT TRANSFER INSTRUCTIONS In p u t / o u t p u t t r a n s f e r (IOT) i n s t r u c t i o n s i n i t i a t e t r a n s -m i s s i o n of s i g n a l s v i a the I/O bus t o c o n t r o l p e r i p h e r a l d e v i c e s , sense t h e i r s t a t u s , and e f f e c t i n f o r m a t i o n t r a n s f e r s between them and the p r o c e s s o r . A PDP-9 IOT i n s t r u c t i o n c o n t a i n s the f o l l o w i n g i n f o r m a t i o n ( F i g u r e A I I I - l ) : oPei?i\-cioK) cope io S E L E C T I O N CLEAfe A t AT EveNT TvtAE I Ge*»eRAT« 1ST \i\)eWT o 1 2 3 4 S 6 7 B 9 10 it \Z 13 \4 \5 It \1 J UsJOSED l_ \_ •=>ei-6CTio>a vopA^puise IOPI POIAE T(AE 1- T>MC I F i g u r e A I I I - I . IOT I n s t r u c t i o n Format 1. An o p e r a t i o n code of 70g. 2. An 8 - b i t d e v i c e s e l e c t i o n code t o d i s c r i m i n a t e among up t o 256 p e r i p h e r a l d e v i c e s ( s e l e c t i o n l o g i c i n a d e v i c e ' s I/O bus i n t e r f a c e responds o n l y t o i t s p r e -a s s i g n e d code). I n normal p r a c t i c e , b i t s 6 through 11 perform the p r i m a r y d e v i c e d i s c r i m i n a t i o n among up t o 64 d e v i c e s w i t h b i t s 12 and 13 coded t o s e l e c t an o p e r a t i o n a l mode or s u b d e v i c e . 86 3. A command code ( b i t s 14 through 17) capable of b e i n g microprogrammed t o c l e a r the AC and i s s u e up to t h r e e p u l s e s v i a the I/O bus. The f o u r machine c y c l e s r e q u i r e d t o execute an IOT i n s t r u c t i o n c o n s i s t of the IOT f e t c h from core memory (memory i s not a c c e s s e d t h e r e a f t e r u n t i l c o m p l e t i o n of the IOT), and t h r e e s e q u e n t i a l c y c l e s of 1.0 usee d u r a t i o n each, d e s i g n a t e d event times 1, 2, and 4 ( F i g u r e A I I I - 2 ) . B i t s 14 and 17 can be coded t o i n i t i a t e c l e a r i n g of the AC and g e n e r a t i o n of an IOPI p u l s e r e s p e c t i v e l y , d u r i n g event time 1. B i t s 16 and 15 can be coded t o i n i t i a t e g e n e r a t i o n of I0P2 and I0P4 p u l s e s d u r i n g event time 2 and 4, r e s p e c t i v e l y . IOT s k i p i n s t r u c t i o n s a re m i c r o -programmed t o produce an IOPI p u l s e f o r t e s t i n g a d e v i c e s t a t u s f l a g . I0P2 p u l s e s a re n o r m a l l y used t o e f f e c t programmed t r a n s f e r s of i n f o r m a t i o n from a d e v i c e t o the p r o c e s s o r . Because the AC s e r v e s as the d a t a r e g i s t e r f o r both " i n " and "out" t r a n s f e r s , the " c l e a r AC" m i c r o i n s t r u c t i o n ( b i t 14) i s u s u a l l y microprogrammed w i t h the I0P2 m i c r o i n s t r u c t i o n ; t h i s c o m b i n a t i o n e f f e c t s c l e a r i n g the AC d u r i n g event time 1 p r i o r t o s t r o b i n g the i n f o r m a t i o n i n t o the AC by the I0P2 p u l s e d u r i n g event time 2. I0P4 p u l s e s are n o r m a l l y used t o e f f e c t programmed t r a n s f e r s o f i n f o r m a t i o n from the AC t o a s e l e c t e d d e v i c e . These c o n v e n t i o n s do n o t , however, p r e c l u d e use of the IOP p u l s e s t o e f f e c t o t h e r e x t e r n a l f u n c t i o n s i f the f o l l o w i n g r e s t r i c t i o n s are observed. The u s u a l use of IOPs. i s : IOPI - n o r m a l l y used i n an I/O s k i p i n s t r u c t i o n t o t e s t a d e v i c e f l a g . May be used as a command p u l s e but not t o i n i t i a t e e i t h e r a " l o a d " or 87 " r e a d " from a d e v i c e . I0P2 - u s u a l l y used t o t r a n s f e r d a t a from the d e v i c e t o the computer, or t o c l e a r a r e g i s -t e r . May not be used t o determine a " s k i p " c o n d i t i o n . I0P4 - u s u a l l y used t o t r a n s f e r d a t a from the computer t o the d e v i c e . May not be used t o determine a " s k i p " c o n d i t i o n . F E T C H E V E N T T » E I EVENT Tv|AE t EMENT TtH\6 4. NEXT F E T 0 4 IOT vNVV"fcOCT\c&J I I IOPI I \.o p%*c. —*+*— l.o p«t I -*4*— 1.0 P$EC ioP4 F i g u r e A l l 1 - 2 . IOT I n s t r u c t i o n Timing The f o l l o w i n g a r e the IOT i n s t r u c t i o n s f o r the t h r e e p e r i p h e r a l s i n c l u d e d as s t a n d a r d I/O d e v i c e s i n the b a s i c PDP-9. IOT's f o r the o p t i o n a l p e r i p h e r a l s a r e i n c l u d e d w i t h t h e i r d e s c r i p t i o n s . 88 APPENDIX IV MONOSTABLE PULSE GENERATORS The monostable m u l t i v i b r a t o r p u l s e g e n e r a t o r s were each b u i l t by a d d i n g components t o a , p a i r of MC724P two-input nand U g a t e s . The c i r c u i t i s as shown i n F i g u r e AIV-1. The heavy l i n e s i n d i c a t e components added t o the MC724P. t I I -ISv/. C o S E O T o Te\GG»E<? "Soo n S . iwouoSTK'SL . e OML .V ) F i g u r e AIV-1 Monostable P u l s e Generator C i r c u i t T able AIV-1 PULSE GENERATOR PARAMETERS DURATION OF PULSE R C 500 nsec. 600 nsec. 1 'usee. 100 usee. 2 s e c . 3.6. kil 4.4 kn 7.8 kn 14.5 kn 29 kn 200 p f . 200 p f . 200 p f . 1000 p f . " 100 uf . 89 APPENDIX V SUGGESTED SYMBOLIC ASSEMBLY LANGUAGE INSTRUCTIONS FOR HYBRID INTERFACE - see t a b l e i n PDP-9 User's Handbook f o r l i s t i n g of a l r e a d y a s s i g n e d codes. (P. 13-3)• MNEMONIC OCTAL CODE APPLICATION ADC: ADRB ADSC SFCL SFCE SFCD MUSC 701116 701204 701302 701304 701202 701205 Read A/D B u f f e r Reg. S t a r t C o n v e r s i o n Load SFC Reg. SFC Enable SFC D i s a b l e Update M u l t i p l e x e r and S t a r t Conv. MULTIPLEXER: MUBL MUAL MUALD 701403 701404 701407 STANDARD OUTPUT INTERFACES BRAL 703003 ORAL 703004 ORALD 703007 BRBL 703103 ORBL 703104 ORBLD 703107 BRCL 703203 ORCL 703204 ORCLD 703207 BRDL 703403 ORDL 703404 ORDLD 703407 D/A CONVERTERS: DABAL 703003 DAAL 703004 DAALD 703007 DABBL 703103 DABL 703104 DABLD 703107 DABCL 703203 DACL 703204 DACLD 703207 MUX B u f f e r Reg. Load MUX Address Reg. Load MUX Address Reg. Load D i r e c t B u f f e r Reg. #A Load Output Reg. #A Load Output Reg. #A Load D i r e c t Output Reg. #B Load Output Reg. #B Load Output Reg. #B Load D i r e c t Output Reg. #C Load Output Reg. #C Load Output Reg. #C Load D i r e c t Output Reg. #D Load Output Reg. #D Load Output Reg. #D Load D i r e c t D/A B u f f e r #A Load D/A #A Load D/A #A Load D i r e c t D/A B u f f e r #B Load D/A #B Load D/A #B Load D i r e c t D/A B u f f e r #C Load D/A #C Load D/A #C Load D i r e c t 90 SIMULTANEOUS UPDATING: Su 703502 INTEGRATOR MODE CONTROL: IMBL IMCRL POTSET: PCBL POTSET POTAD SIGNAL SELECTOR: SSABL SSAL DAS MODE CONTROL: DMBL DMU 231R-V MODE CONTROL: AMC AMU AMR . 703403 703404 703203 703204 705117 703603 703604 701603 701604 701501 701502 701514 STANDARD INPUT INTERFACE: INBRIL 705001 1NBRIR 705016 DIGITAL VOLTMETER: DVMBL 705001 DVMBR 705016 Simultaneous Update I n t e g r a t o r Mode B u f f e r Load I n t e g r a t o r Mode C o n t r o l Reg. Load Po t . C o e f f . B u f f e r Load P o t . S e t . Read A c t u a l P o t . Address S i g n a l S e i . Address B u f f e r Load S i g n a l S e i . Address Load DAS Mode B u f f e r Load DAS Mode Update A n a l o g Mode C l e a r (To P o t s e t ) A n a l o g Mode Update Anal o g Mode Read Input B u f f e r Reg. 1 Load Input B u f f e r Reg. 1 Read DVM B u f f e r Load DVM B u f f e r Read PROGRAM INTERRUPT FLAGS: PIFR PIFC 705212 705204 Read P I F l a g s , Then C l e a r C l e a r P I F l a g s APPENDIX VI J SPECIFICATIONS FOR ANALOG DEVICES INC. OPERATIONAL AMPLIFIERS 106B AND HOB SPECIFICATIONS ( t y p i c a l a t Model 106 A/B/C Model 110 A/B/C 25 C u n l e s s noted) H i g h Gain 5ma Wideband Output F a s t Slew Rate OPEN LOOP GAIN DC, r a t e d l o a d , min. DC, 1OK .ft l o a d , min. RATED OUTPUT, min. 250,000 +10V a t 5ma 50,000 + 10V a t 20ma INPUT VOLTAGE OFFSET I n i t i a l O f f s e t , e x t . t r i m pot Avg. v s . temp., max., Model A (-25 t o +85°C) Model B Model C v s . s u p p l y v o l t a g e v s . time INPUT CURRENT OFFSET (each i n p u t ) I n i t i a l o f f s e t , 25°C, max. Avg. v s . temp., (-25 t o 85 C) max. v s . s u p p l y v o l t a g e INPUT CURRENT OFFSET ( d i f f e r e n t i a l ) I n i t i a l o f f s e t , 25 C Avg. v s . temp., (-25 t o 85 C) INPUT IMPEDANCE Between i n p u t s Common mode + 50K.O. +20uV/°C ±10nV/°C ± 5iiV/°C ±20\iV/% +50^iV/day (0, +) 50na +0.7 na/°C +0.5na/^ +5na +0.2na/°C 1 MA 100 MA 100k i l ±20uV/°C +10uV/°C + 5u.V/°C + 40^iV/^ + 50^iV/day (0, +) 30na +0.5na/°C +0.5na/^ +5na +0.2na/°C 1 Ma N.A. INPUT VOLTAGE AND NOISE Max. v o l t a g e between i n p u t s Max. common mode v o l t a g e Common mode r e j e c t i o n V o l t a g e n o i s e , t o 50kHz, rms POWER SUPPLY V o l t a g e , r a t e d s p e c i f i c a t i o n V o l t a g e , d e r a t e d s p e c i f i c - .• a t i o n C u r r e n t , q u i e s c e n t TEMPERATURE RANGE O p e r a t i n g Storage 1 +15V +10V 10,000 4uV +15V +(10 t o 16)V 8ma -40 t o +85 C -55 t o +125°C +15V N.A. N.A. 4(iV +15V +(10 t o 16)V 8ma -40 t o +85 C -55 t o +125°C 'Add l o a d and f e e d back c u r r e n t t o o b t a i n power s u p p l y d r a i n . FREQUENCY RESPONSE U n i t y g a i n , s m a l l s i g n a l 2MHz 20MHz F u l l power re s p o n s e , min. 20kHz 1MHz S l e w i n g r a t e , min. l<,2V/ji,sec 100V/|i. Overload r e c o v e r y 1msec 100|j,se 93 APPENDIX V I I API INTERFACING MODULE (EQUIVALENT OF DEC MODULE W104) \ Tb-|*B\i_ F R o r t PDP-<j. movtATeS * VS E.HA%LEt> AUD REQUEST CAW b E roNie - 0 » — o 1 — • BoFFee . p o p - q -To -KvRTU CoMVtepTQJ IV^KCAttS C^ewEST FOR WTteRuPT HAS O O T P u T To U E * T NvoboLE OV^ SAN\E P R v o f t 1 ^ uEwE\_ , ( S H o w U i n ©5 S T A T E ) o RQ (eeooevr VNTEfcfoVT) To Pt>P-9 wnTlAv-UE \HTEREKE VvVTERRoPT s y s - r e * FLNi O R OESVCE F(-A& C L E N R FLAG, n \ R T U - T o -ROP-5 C o u \ / E K t E R s ( — o A W R E S S PDP-q \ /o \Z T o v"7) WTiAuZE APPENDIX V I I I 94 CONNECTOR MJ16: TERMINAL FUNCTION MJ16-1 Hundreds Address Stop R e l a y -2 Hundreds Address Reached - R -3 - M -4 - F -5 - C -6 - A -7 - T -8 I' - P -9 Hundreds Address Reached - Q -12 Tens Address Stop R e l a y -13 Tens Address Reached - 0 -14 - 1 -15 - 2 -16 - 3 -17 - 4 -18 - 5 -19 - 6 -20 - 7 -21 - 8 -22 Tens Address Reached - 9 -23 U n i t s Address Stop R e l a y --24 U n i t s Address Reached - 0 -25 - 1 -26 - 2 -27 - 3 -28 - 4 -29 - 5 -30 - 6 -31 - 7 -32 - 8 -33 U n i t s Address Reached - 9 -34 B i --Quinary Input (Tens) CONNECTOR MJ17: TERMINAL FUNCTION -4 +90v i n From MJ17-24 -13 A c t u a l P o t . Address Reached - P -14 - Q -15 — Tens BCD1 -16 — Tens BCD2 -17 - Tens BCD4 •. -18 — Tens BCD8 -19 — U n i t s BCD1 -20 - U n i t s BCD2 -21 > - U n i t s BCD4 -22 A c t u a l P o t . Address Reached - U n i t s BCD8 -24 S u p p l i e s +90v When DVM S w i t c h i n "Remote" P o s i t i o n -25 Address Set R e l a y (In) -37 Servo S t a t u s (Out) -39 S i g n a l S e l e c t o r S t a t u s (Out) CONNECTOR RP2-J2: 95 TERMINAL FUNCTION -0 An a l o g Input - C o e f f i c i e n t F o r S e t t i n g Servo-Set P o t e n t i o m e t e r s ~ 3 Mode Bus R.T. -4 P.S. -5 S.T. -6 i . e . -7 H. -8 Mode Bus OP. -20 S u p p l i e s +90v When DVM S w i t c h i n "Remote" P o s i t i o n -21 A t t e n u a t o r Set Mode -22 A t t e n u a t o r Check Mode - 2 3 Readout Mode 96 REFERENCES 1. PDP-9 User Handbook, D i g i t a l Equipment C o r p o r a t i o n , Maynard, Mass., P. 13-6. 2. The D i g i t a l L o g i c Handbook (1966-67), D i g i t a l Equipment C o r p o r a t i o n , Maynard, Mass,, pp. 145-147. 3. PDP-9 User Handbook, op. c i t . , pp. 3-6, 3-12 t o 3-13, 9-6 t o 9-16, 13-10. 14-2. 4. MLG System (Memory and L o g i c U n i t 14.138 and E x p a n s i o n  Groups), V o l . I , E l e c t r o n i c A s s o c i a t e s I n c . , Long Branch, New J e r s e y , d rawing B05U3405. 5. 231R Computer Console Model 3.080. V o l . I , E l e c t r o n i c A s s o c i a t e s I n c . , Long Branch, New J e r s e y , pp. 23, 53-6. MLG System (Memory and L o g i c U n i t 14.138 and E x p a n s i o n  Groups K op. c i t . , p. 6, 7. D i g i t a l A t t e n u a t o r System 2.152 Thru 2.156, E l e c t r o n i c A s s o c i a t e s I n c . , Long Branch, New J e r s e y , p. 9. 8. PDP-9 User Handbook, op. c i t . , p. A2-4. 

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