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UBC Theses and Dissertations

Interactive adjustment of digital controller parameters using a minicomputer. Koritz, Anne L. 1972

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INTERACTIVE ADJUSTMENT OF DIGITAL CONTROLLER PARAMETERS USING A MINICOMPUTER. by ANNE L. KORITZ B.Sc. (Hon.), University of British Columbia, 1970 A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in the Department of E l e c t r i c a l Engineering We accept this thesis as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA May, 1972 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the Head of my Department or by his representatives. tt is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department of S.b-cthCc*^ i ^ ^ X ^ ^ ^ t ^ The University of British Columbia Vancouver 8, Canada Date / * 7£-ABSTRACT A simple display-interactive system for process control using a small computer i s presented which i s based on conventional d i g i t a l f i l t e r design methods and accuracy considerations. The system permits gain, lead, and lag-lead compensation of a two-real-pole plant with position offset. The program, written for the PDP-12, allows the user much f l e x i b i l i t y in sampling and displaying the step, responses and choosing the compensator parameters. There i s also provision for evaluating the system performance (peak time, maximum overshoot, and position offset). This f l e x i b i l i t y i s provided by organization of the program into large subroutine packages, e.g. graphic display, fixed-point two-decimal-place and double-precision (24-bit) fractional arithmetic routines, compensator difference equations, etc. Discussed are theoretical and practical aspects of the system design and implementation, sources of error, overall structure of the program, including a general flowchart, experimental results, the limits imposed on the program by the computing f a c i l i t i e s used, and some suggestions concerning possible extensions of the system. TABLE OF CONTENTS Page ABSTRACT ; i i TABLE OF CONTENTS i i i LIST OF ILLUSTRATIONS v ACKNOWLEDGEMENT , v i 1. INTRODUCTION 1 2. SYSTEM DESIGN: THEORETICAL CONSIDERATIONS 4 2.1 Description of the System 4 2.2 Compensator Difference Equations 6 2.2.1 Lead Network 6 2.2.2 Lag-Lead Network 6 2.3 Analysis of System Behaviour 9 2.3.1 Uncompensated System •• 9 2.3.2 Lead-Compensated System. 12 2.3.3 Lag-Lead-Compensated System 14 2.3.4 A Typical Example 14, 3. SYSTEM DESIGN: PRACTICAL CONSIDERATIONS 19 3.1 System Configuration 19 3.2 Analogue Computer Setup 21 3.3 Generation of Timing Pulses and Step Input Signal 23 3.4 Sources of Error 26 3.4.1 The Hardware. 26 3.4.2 The Digital F i l t e r i n g Process 29 4. THE SOFTWARE 32 4.1 Program Structure and Operation 32 4.2 General Flowchart 39 Page 4.3 Difference-Equation Subroutines 47 4.4 Difference-Equation Flowcharts 48 5. EXPERIMENTAL RESULTS AND CONCLUSIONS 51 REFERENCES 57 LIST OF ILLUSTRATIONS Figure Page 2.1 General System Diagram 5 2.2a Lead Network 8 2.2b Lag-Lead Network . 8 2.3 Uncompensated System 11 2.4 Lead-Compensated System 13 2.5 Lag-Lead Compensated System 15 2.6 Theoretically Predicted System Step Responses . 18 3.1 Actual System Implementation 20 3.2 Analogue Simulation of 0.01c" = 3e(t) - 0.15c'(t) - 0.50c(t) with e(t) = 0.5v - c ( t ) . . . . 22 3.3a Actual Transfer Function of PDP-12 D/A Converter 24 3.3b Desired Transfer Function for D/A Converter 24 3.4 Op-amp Scaling Network for D/A Converter Output 25 3.5 Circuitry for Timing Pulses and Step Input Signal 27 3.6 Timing Diagram 28 5.1a Scope Photo of Uncompensated System Response 52 5.1b Scope Photo of Gain-Compensated System Response 52 5.1c Scope Photo of Lead-Compensated System Response 53 5.Id Scope Photo of Lag-Lead-Compensated System Response 53 ACKNOWLEDGEMENT I wish to thank the National Research Council for financial support in the form of a postgraduate scholarship. I would also like to thank my supervisor, Dr. E. V. Bohn, for his ideas and suggestions and reading of the manuscript, Dr. J. S. MacDonald for reading the manuscript and offering further suggestions, and Dr. M. P. Beddoes for use of the PDP-12 computer. I am also grateful to Miss Linda Morris for typing the thesis, Mr. Dave Holmes for his assistance with the hardware, Mr. Al MacKenzie for preparing the f i n a l drawings, and Mr. Herb Black for photographic work. 1 1. INTRODUCTION With the increasingly wide use of d i g i t a l communication and feed-back control systems, d i g i t a l f i l t e r networks have become important as a low-cost, versatile means of signal processing. Advances in integrated ci r c u i t technology, particularly large-scale integration techniques, have made this feasible. White and Mitsutomi (11.) have summarized the situation as follows: "The advent of large-scale integration has made the implementation of d i g i t a l f i l t e r s directly into hardware economically reasonable... MOS-LSI chips, in conjunction with read-only memory, are capable of per-forming any d i g i t a l computing function, including linear or nonlinear, fixed parameter, and time-varying types. The read-only memory stores scaling coefficients when multipliers or entire f i l t e r sections are time-shared". The v e r s a t i l i t y of such f i l t e r s makes i t relatively easy to realize adaptive d i g i t a l control elements. Because of their low cost, alternative practical realizations of adaptive d i g i t a l f i l t e r s can be achieved by use of programmed minicomputers. There are several methods of d i g i t a l f i l t e r design, which depend on the desired f i l t e r characteristic and the signal to be processed. Basic design principles of d i g i t a l f i l t e r s are given in (1.), (3.), (7.), and (10.). A f u l l discussion of accuracy, s t a b i l i t y , word-length require-ments and hardware implementation i s given in (10.). For low-frequency applications such as industrial process controls, d i g i t a l controllers are very versatile; analogue networks in the low-frequency range are limited by size and complexity as well as many other problems. A discussion of direct d i g i t a l control (DDC) applications and their advantages over conventional analogue control methods i s given in 2 (6.)' One obvious advantage i s the use of time-shared computer control, incorporating such things as start-up, shutdown, emergency operation or adaptive tuning of controller parameters. In particular, linear d i g i t a l control and the use of propor-tional-integral-derivative (PID) d i g i t a l controllers to improve system response is discussed in (6.). The optimum-tuning problem for DDC systems i s more complicated than the same problem for analogue PID control, because the DDC algorithm has more adjustable parameters than the equivalent analogue control system. This f l e x i b i l i t y , however, gives rise to the possibility for on-line adaptive tuning of a d i g i t a l PID controller. Such adaptive tuning requires the introduction of some acceptable performance index which i s optimized and a method for assessing system performance. A computer-based interactive system with graphical display seems ideal for performing the required operations. In this thesis, the emphasis is on developing a simple display-interactive system, with variable user-specified compensator parameters, using a minicomputer. This could be part" of a more general system incorporating, for example, process identification and adaptive tuning of compensator parameters to optimize some performance index. This thesis considers the problem of implementing a d i g i t a l lag-lead compensator for a typical simplified process model by means of a small computer. The program controls sampling and displaying of the response of an analogue computer to a step input, evaluation of the system performance, and allows the user to choose compensator parameters within specified limits. The performance c r i t e r i a are peak time,, maximum overshoot and position offset of the step response. The overall program structure i s simple, consisting of several 3 large blocks of subroutines, and allows the user much f l e x i b i l i t y in determining the manner of sampling, compensation and display of the response. The subroutine packages are as independent as possible, thus making i t relatively easy for the user to modify them. Most important is the tradeoff between program f l e x i b i l i t y and complexity. The system developed in this thesis makes f u l l use of modest f a c i l i t i e s to provide the user with a simple-to-use way of studying a system response and observing the effects of compensation. Due to the modular structure of the program, however, i t is capable of being extended to a more elaborate system with a more sophisticated d i g i t a l computer. The main use of the system described in this thesis would be to simulate the d i g i t a l control of a process model and study the effects of varying compensator parameters. The process i t s e l f , and the corres-ponding compensators, would have time constants and sampling frequency scaled by an appropriate factor for analogue simulation, e.g. 1 sec in the simulated system might correspond to 100 sec in the actual system. In actual applications where speed, efficiency and time-sharing of the d i g i t a l f i l t e r i n g process i s important, i t may be desirable to implement the d i g i t a l f i l t e r directly in hardware, with the computer f i l l i n g the appropriate word locations in a memory for the multiplier coefficients. If the equipment i s not available, however, and the computational delay of a compensator subroutine is very small compared to the sampling period, the minicomputer can be programmed to realize the d i g i t a l f i l t e r , as i s done in this case. 2. SYSTEM DESIGN: THEORETICAL CONSIDERATIONS 2.1 Description of the System Fig. 2.1 represents the system under consideration, where the d i g i t a l controller ^ ( z ) is to be realized by a small computer. In this particular case, G p(s) is a two-pole plant with position error: G (s) = 7 — ^ — 7 r (2.1) p (s + p,)(s + p ) G £(s), the continuous controller to be d i g i t a l l y simulated, may take the following forms: G c(s) = k c (gain) (2.2) G (s) = -I + v (lead) (2.3) c s + aw (s + w j (s + w„) G (s) = T — — -.—T7—v s (lag-lead) (2.4) c (s + w 1/a 1)(s + a 2 w2^ Since the performance c r i t e r i a here are just those of the step response, the parameters of G c(s) are chosen according to the principles of root-locus compensation. Once these parameters are known, and the sampling period T is fixed, the coefficients of the difference equation corresponding to D c(z) can be found. The basic design problem is to represent D^(z) in such a way that i t s response to a step input sequence should be the same as the sampled step response of G c(s). (Other design problems have to do with the choice of T, the manner in which sampling is done, the form of the difference equation, and actual hardware/software considerations which w i l l be discussed later.) Fig. 2.1 General System Diagram There are several ways of designing the d i g i t a l f i l t e r to correspond to G c(s), but the most appropriate method here i s the standard (or impulse-invariant) z-transform, which works well for low frequencies and preserves the impulse response. The transform pair for one real pole is (2.5) s + p , , T s -1 r 1 - exp(-pT)z In the following section, the difference equations for D^(z) are derived using the standard z-transform. 2.2 Compensator Difference Equations 2.2.1 Lead Network (illustrated in Fig. 2.2a) = D (z) = ( i - a - i ) z p - ± - 2 - . i % ( 1 - r V f A 1 + (^) -4—1 E(z) c Ls + aw sj (_ a s a s + awj = (1 - z"1) > 1 - z- 1 a 1 - e ^ V 1 J 1 - A Z .j « , o , . 1 -awT . a - 1 where A = — e + -awT -1 o a a 1 - e z e (nT) = e(nT) - A e[(n - 1)T] + e" a w Te [(n - 1)T] (2.6) C O c 2.2.2 Lag-lead Network (illustrated in Fig. 2.2b) E c(z) D (z) = (1 - z - 1) Z c r 5 + W l m S + W2 V s + w 1/a 1 ' s + a2w2 s = (1 - z"1) Z s s + w j7a^ s + a 2 w 2 where c o = a i / a 2 c, = a l " 1 W2 ~ W l ^ a l 1 a 2 w2 ~ w i / a i a 2 a2 ~ 1 W2 ~ W ] / a 2 2 a 2 w2 - w 1/a 1a 2 _ -1 , _ -1 Then D (z) = c - c. —*-=r. + c c • o 1 -w1T/a1 _ x 2 - a 2 W 2 T -1 1 - e z 1 - e z , E .(z) . -1 If D l ( z ) ° 1 " Z c l v J E(z) -w^T^ ^ 1 - e z a n d n , , A E c 2 ( z ) 1 - z" 1 D„(z) c2K ' E(z) _ a 2 w 2 T -1 ' 1 - e z D (z) = c - c nD (z) + c 0D 0(z) c o 1 c l 2 cZ which corresponds to the difference equations -w Ta e .(nT) = e(nT) - e[(n - 1)T] + e e , [ (n- - 1)T] c l ci. -a w T e c 2(nT) = e(nT) - e[(n - 1)T] + e e c 2 ^ n ~ ^ e (nT) = c e(nT) - c.e .(nT) + c„e (nT) (2.7) C O 1 c l I cl Fig. 2.2a Lead Network I - e -sT e(nT) (s+w^ (s+w2) ( s + w ^ a ^ (s+a2w2) 0 i in e c(nT) Fig. 2.2B Lag-Lead Network 9 2.3 Analysis of System Behaviour Difference equations which describe the controller and plant provide a method for studying the effects of compensator parameters and sampling frequency on the system's response to a step input. A short summary of the development of these equations is given for the uncom-pensated, lead-compensated, and lag-lead-compensated systems, together with a typical example with response curves. The choice of sampling period T in an actual sampled-data feedback control system i s based on considerations such as the sampling theorem, s t a b i l i t y , allowable ripple content, possible hidden oscillations in the response, etc. These questions are discussed in detail in Toil (7.). For system involving an interactive graphics display, the response c(t) should be sampled at a faster rate than the error signal e(t) so that an accurate display and evaluation of transient response characteristics (e.g. peak time, maximum overshoot) can be obtained, and also that the effect of varying the sampling period T may be evaluated. Since this could not be conveniently accomplished with the equipment available (i.e. error samples had to be converted to response samples for the display), the same sampling period T was used for both purposes. 2.3.1 Uncompensated System (illustrated in Fig. 2.3) Let the open-loop continuous transfer function be , _ -sT G r ( s ) = G p ( s ) ' T h e n G r(z) = (1 - z"1) Z[G p(s)/s] = (1 - z"1) Z K O s s + p 1 s + p 2 J 10 where K = K o P l P 2 K, = K 1 P 1(P 2 ~ P]_) K 2 P 2(P 2 - P l ) so that ....... -1 , -1 G (z) = K — K. 1 " Z_ + K 1 - 2 or where r o 1 -p T _± 2 -p2T ^ 1 - e z 1 - e z , -1 , -z G (z) = V "• b2 r =1 ^2 1 - b„z + b.z 3 4 -P9T -P,T -p T -p T b = K,(l + e ) - K (e + e ) + K_(l + e ) 1 1 o 2 -P2T -(p +p )T -p T b„ = K,e - K e • + K.e 2 1 o 2 " P l T + "P 2 T b^ = e + e (2.9) -(P1+P2)r b. = e T 4 The difference equation for the response is then c(nT) = b i e [ ( n - 1)T] - b 2e[(n - 2)T] + b 3c[(n - 1)T] - b 4c[(n - 2)T] (2.10) with the i n i t i a l values being c(0) = 0, e(0) = R q ; c(nT) = e(nT) = 0 for n < 0 C(t) -Ro«(t) Zero-order hold Plant G (s) P Fig. 2.3 Uncompensated System In this system, the main effect of increasing T i s to increase the maximum overshoot. (Tou (7., p. 330) gives an expression for maximum overshoot in terms of z-plane pole-zero plot parameters and the sampling time T; assuming a fixed pole-zero configuration, the overshoot i s seen to increase with T.) In the example which follows, however, T i s small enough so that the overshoot i s only slightly more than i t would .be for the continuous system. To evaluate the compensated-system responses, one need only change the variable e (error signal) to e^compensator output) and append the difference equations for the error signal and the compensator output. This i s shown below for lead and lag-lead cases. 2.3.2 Lead-compensated System (illustrated in Fig. 2.4) Response: c(nT) = b^e [(n - 1)T] - lys [(n - 2)T] + b 3c[(n - 1)T] - b 4c[(n Error signal: e(nT) = R q - c(nT) Compensator output: e (nT) = e(nT) - A e[(n - 1)T] + e~ a w Te [(n - 1)T] C O c The i n i t i a l values are c(0) = 0; e(0) = R ; e.(0) = R o <- o c(nT) = e(nT) = e (nT) = 0 for n < 0 c - 2)T] (2.11) r(t) -Rou(t) T e(nT) i . -sT 1 - e s + w CO s + aw Zero-order hold Lead G (s) c Zero-order hold Plant G (s) P c(t) Fig. 2.4 Lead-compensated System 14 2.3.3 Lag-lead Compensated System (illustrated in Fig. 2.5) Response: c(nT) = b ^ K n - 1)T] - b ^ t d i - 2)T] + b 3c[(n - 1)T] - b^cKn - 2)T] (2.12) Error signal: e(nT) = R q - c(nT) Compensator Output: -w T/a e ,(nT) = e(nT) - e[(n - 1)T] + e e - [(n - 1)T] c± c± -a„w„T e c 2(nT) = e(nT) - e[(n - 1)T] + e e c 2 ^ n " D T1 e (nT) = ce(nT) - c.e (nT) + c„e 9(nT) c o 1 c l 2 c2 The i n i t i a l values are c(0) = 0 e(0) = R e . (0-) = R e „(0) = R e (0) = R o c l o c2 o c o c(nT) = e(nT) = e .(nT) = e „(nT) = e (nT) = 0 for n < 0. c i c2 c 2.3.4 A Typical Example The difference equations 2.10, 2.11, and 2.12 were programmed on the IBM 360/67 to yield a typical set of responses, following the conventions of root-locus compensation. The uncompensated system was chosen to have k = 300, p^ = 5, p 2 = 10, and R q = 0.5 v. In a l l cases, the sampling time T was 0.01 sec. These values can be considered typical for an analogue computer simulation of an actual process, which might have time constants 10 or 100 times as long as the ones used in the simulation. For example, i f the actual system poles are p| = kp^ and p 2 = ^P 2» t^ i e compensator zeros are w^  = kw^  and w2 = kw2> and the sampling period i s T' = T/k, Zero-order hold Lag-Lead G (s) c Zero-order hold Plant G (s) P Fig. 2.5 Lag-lead Compensated System i t can be seen from root-locus plots that K' = K K , and that a l l coeffi cients in the difference equations remain the same. Thus the analysis of system behaviour obtained from the simulated system can be applied t the actual system; the analogue system simply represents the actual system scaled in time by a factor of k (where k might, for example, be 0.1 or 0.01). The following performance c r i t e r i a were applied: t (peak time) P M (maximum overshoot) o e (position offset) ss t (time for the response to reach 98% of the fi n a l value) The plots in Fig. 2.6 show the responses. Curve I: Uncompensated System t =0.18 sec P M = 29.5% o e = 0.072 v ss t =0.59 sec s Curve II: Lead Compensated System (w2 = 10.5, a = 2) t =0.19 sec P M = 9.8% o e = 0.125 v ss t =0.29 sec s Curve III: Lag-lead Compensated System (a) (w^  = 1, a^ - A, w2 = 10.5, a 2 = 2) t = 0.21 sec P e = 0.039 v ss t =0.80 sec s Curve IV: Lag-lead Compensated System (b) (w = 4, a.. =.4, w_ = 10.5, rt\ J- J-a2 = 2 ) t = 0.21 sec P M = 7.7% o e = 0.039 v ss t = 0.43 sec s These plots i l l u s t r a t e the problem of compensating a system whose response has both too much overshoot and position offset. For this system, the lead a-factor serves to decrease overshoot and the lag a-factor to decrease offset; as seen from comparing curves III and IV, i t is desirable to put the lag zero f a i r l y close to the system pole p^ so that the response reaches i t s f i n a l value quickly. Compensator pole-zero distribution has l i t t l e effect on peak time; to decrease peak time, the open-loop gain must be increased. In the actual system involving an analgoue and d i g i t a l computer the compensator parameters are chosen to those of curves II and IV. (Uncompensated system parameters and sampling time are also the same.) As w i l l be seen, the experimental results agree closely with the theore-t i c a l l y predicted responses of this example. U n c o m p e n s a t e d 3. SYSTEM DESIGN: PRACTICAL CONSIDERATIONS 3.1 System Configuration The system described in Chapter 2 i s implemented in the form of Fig. 3.1, using a PDP-12 computer as the d i g i t a l compensator and a Donner analogue computer to simulate the continuous plant. The A/D and D/A are controlled by PDP-12 instructions, and the timing pulses for the sampling and the input step signal are generated by external logic which w i l l be detailed later. Additional external hardware scales the D/A output to the appropriate range for Donner input. F u l l use is made of the PDP-12 to build a rather general user/ display-interactive system for sampling and displaying signals with feedback and compensation capabilities. The user communicates with the program by means of various text displays, some of which ask the user to specify parameters such as number of samples, A/D input channel, the table in which the sampled data is to be stored, etc. There are also keyboard commands to control program flow, data displays, sampling, compensation, specification of compensator parameters, and system per-formance evaluations. Any user-specified parameter may be easily changed via a particular text display, and many provisions are made to ensure that user-specified parameters are entered properly. These capabilities make the system quite flexible, practical and easy to use in a wide variety of situations. The actual d i g i t a l compensation is handled by a set of difference-equation subroutines which simply update the particular expressions (derived in the previous chapter) once for each new A/D value of the error signal e(nT). The binary number corresponding to PDP-12 A/D j e(t) 10 bits t I Sampler/ Quantizer Compensator Difference Equation e c(nT) Digital Compensator D/A bits I e (t) • c Hold Analogue Computer Plant c(t) Fig. 3 . 1 Actual System Implementation M O e^(nT) i s then D/A converted and scaled by an external op-amp network, and the op-amp output i s used as the input to the analogue computer. The compensator pre-calculation routines which set up a pointer to the selected difference equation and calculate the appropriate parameters are f u l l y described in Chapter 4. The following sections include descriptions and diagrams for the analgoue system and D/A output scaling network, logic for timing pulses and step input signal, and a discussion of sources of error in the hardware and the d i g i t a l f i l t e r i n g process. 3.2 Analogue Computer Setup Fig. 3.2 illustrates the analogue implementation of G (s) = K/(s + P l ) ( s + p 2) = C(s)/E(s), The differential equation i s c"(t) = Ke(t) - ( P ; L + p 2)c'(t) - P ; L p 2 c ( t ) , (3.1) where e(t) = R - c(t). o Choosing K = 300, p± = 5, p 2 = 10, and R q = 0.5 v, then scaling the equation for analogue layout: 0.01c"(t) = 3e(t) - 0.15c'(t) - 0.50c(t); e(t) = 0.5 - c(t) . (3.2) These values are chosen to give a sufficiently fast-responding system to allow sampling to take place in a few seconds. The choice of 0.5 v for R q is motivated by: (1) the requirement that no amplifier overload at any time: (2) the convenience of sampling R q directly with the PDP-12's A/D, which has an input range of only ±1 v. (The A/D value of R q is used in a routine which converts the error samples to response samples so that the system response c(nT) = - e(nT), rather than the error signal e(nT), is displayed.) The simulation of Eq. 3.2 is shown in Fig. 3.2. It should be mentioned here that R q i s actually a square wave varying between 0 and 0.5 v with a period of 16 sec; thus the analogue response occurs on both positive- and negative-going edges, but the timing logic ensures that only the positive response is sampled (subject to a restriction on the total sampling time to be discussed in section 3.3). The 9-bit D/A output of the PDP-12 is actually an auxiliary scope drive which has the transfer characteristic shownin Fig. 3.3a. For input to the Donner, however, the voltage must be scaled the same as the A/D, between -1 and 1 v, the only difference being 512 levels instead of 1024, as shown in Fig. 3.3b. (The A/D has 10-bit accuracy, the D/A 9-bits.) For this purpose, an op-amp which adds +3 v to the D/A output, inverts and attenuates by 1/3 is used. This network i s illustrated in Fig. 3.4. The pots are adjusted u n t i l the desired transfer characteristic is reached. 3.3 Generation of Timing Pulses arid Step Input Signal The sampling of the analogue error signal i s controlled by a pulse train which is synchronized with the positive-going edge of the step signal; also present is a sync pulse which i s used by the PDP-12 to in i t i a t e sampling at the proper time. These pulses, including the input signal i t s e l f , are a l l derived from a 100 Hz square wave, as illu s t r a t e d in the circuit diagram (Fig. 3.5). The waveforms are shown in the timing out Fig. 3.3b Desired Transfer Function for D/A Converter Fig. 3.4 Op. Amp Scaling Network for D/A Converter Output diagram (Fig. 3.6). RTL logic modules are used for the frequency divide and the one-shots. The f/1600 network i s made up of four J-K fl i p f l o p s and two f/10 modules, the output of which is synchronized with the 100 Hz square wave but is not exactly symmetrical (see Fig. 3.6). The one-shots are made up of two NOR gates and one R-C module each. Their 10-psec (approx.) pulse width allows the PDP-12 program enough time to detect the high or low level on the sense line. The attenuator is used to bring the high level of R q close to 0.5 v, and the zero adjust i s necessary because the low level of R must be exactly 0 v. o 1 The 6.4-sec width of the poisitive part of R q restricts the total sampling time to less than 6.4 sec. For the analogue system chosen, however, this i s far longer than the system settling time, which is less than 1 sec. The 6.-4 sec simply allows the user to vary the analogue parameters and sample over a longer period of time i f desired. 3.4 Sources of Error For the system under investigation, the measured responses can be expected to differ from the theoretically predicted ones by at least several percent. This section examines those parts of the system which contribute to the error. 3.4.1 The Hardware Resistor and capacitor values in the Donner may diffe r from specifications by up to 10 percent, causing, for instance, a xlO amplifier to have an actual gain of 11. There i s also 5-10 mv of 60-cycle ripple ? +3.6v 560Q 100 Hz Microdot Function Generator Frequency Divide f/1600 Attenuator and zero adjust R to o A/D Channel 11 -R to o Donner A8 input Sync pulses to Sense Line 1 of PDP-12 One-shot No. 1 Sampling pulses to Sense Line 2 of PDP-12 Fig. 3.5 Circuitry for timing pulses and step input signal v l Fig. 3.6 Timing Diagram on the op-amp outputs, some of which shows up in the response, p a r t i -culary in the overshoot calculation. There is also some d r i f t in the D/A scaling offset (the addition of +3 v to the op-amp input), so that the pot must be read-justed occasionally. As seen from response photographs in Fig. 5.1 a-d, the response does not always start exactly from zero. This problem, however, affects only the position-offset calculation and can be taken into account on observation of the response. 3.4.2 The Digital Filtering Process There are three possible sources of error inherent in any d i g i t a l f i l t e r : quantization error, computational (truncation and/or roundoff) error, and inaccuracy of d i g i t a l f i l t e r pole positions. These are associated with input data, computational data, and multiplier coefficient word lengths respectively. White (9., 10.) gives a detailed discussion of word length requirements and a quantitative analysis of their associated errors. Some of his results are used here to account for d i g i t a l - f i l t e r i n g errors in this system. Since the arithmetic accuracy required in this system is only to two decimal places, A/D quantization error can be neglected. Quanti-~2 -2(C+1) zation error, for an A/D with C bits plus sign, is e = 2 /3, which for C = 9 in this case is negligible. Truncation or roundoff error in finite-precision arithmetic may be analysed in the same fashion as A/D conversion noise. The d i g i t a l f i l t e r computations amplify quantization noise by a factor depending on the f i l t e r pole positions. This "noise gain" for a first-order f i l t e r i s 2 """DT 1/(1 - k ) for a pole at k = e , and for a lag pole at p = 1, and T = 0.01, the factor is 50, which is s t i l l negligible for the small amount of quantization error in the system. The actual roundoff noise has a mean-squared value of 2 /3, where M i s the number of computa-tional data bits (9 in this case.) The number of data b i t s , N, for coefficient multipliers, depends on the desired percent accuracy in locating the d i g i t a l f i l t e r poles, the position of the corresponding analogue poles (p), and the sampling period T according to the expression N > H + N 2 (3.3) where = -log^pTe , N 2 = -(1 - log 2Ap/p). N 2 is determined by desired pole accuracy, and depends on analogue pole position and sampling frequency; the higher the sampling frequency and the smaller the analogue pole, the higher the value of N^. For 0.1% accuracy, N 2 = 8.95. For 1% accuracy, N 2 = 5.64. If the same values for the lag and lead poles are used as chosen for the theoretical example of Section 2.3.4, = 6.64 for the lag pole and 2.54 for the lead pole. The d i g i t a l compensator poles are calculated in the program by two sets of arithmetic routines: (1) 2-decimal-place fixed point multiply, divide, and subtract which have a roundoff error of at most 0.005: (2) 24-bit multiply and exponential subroutines which use the results of the 2-place routines and round off the result to 12 bits, thus having an accuracy of at least 1% according to the formula described above. (These routines are detailed in the next chapter.) Thus the error i n pole positions, contributed to by both sets of routines, is no more than 2%. From this analysis i t i s clear that any discrepancy between experimental and theoretical results w i l l be caused mainly by inaccuracies inherent in the hardware. The only other source of error, and much smaller one, is in the location of the d i g i t a l compensator poles. 4. THE SOFTWARE 4.1 Program Structure and Operation This user/display-interactive program, written mostly in PAL III (PDP-8) assembler code*, is designed to allow the user as much ease and freedom as possible in studying the response of a system in a real-time situation. Since i t s structure is based on the "modular" i d e a — different classes of operations being grouped into subroutine packages— i t has the capability of being extended to include more sophisticated operations, given a d i g i t a l computer with more features than the PDP-12. The program can be greatly modified (including translation into a different assembler code) without i t s basic structure being changed. The limitations imposed by the computer used in this system w i l l be more fu l l y discussed in Chapter 5. The program is organized into groups of subroutines as follows: (1) Display routines for a. Horizontal marked scale with dashed line for R (shows number of samples) b. vertical marked scale (shows voltages) c. text buffers d. data which has been stored in a table (shown as a voltage-vs-samples curve) (2) Sample-and-store routines for a. sampling only b. sampling followed by D/A output *The A/D, display, sense line, and sense switch instructions are in LINC code. PDP-12 programs can combine LINC and PDP-8 code. 33 c. sampling, followed by a compensation subroutine, followed by D/A (3) Keyboard service (on interrupt) for a. user-input mode b. command mode c. compensator-parameter input mode (4) Compensator difference-equation subroutines for a. gain b. lead c. lag-lead (5) System performance evaluation - calculations for a. peak time b. maximum overshoot c. position offset (6) Arithmetic routines for a. 2-decimal-place fixed-point multiply, divide, and subtract b. 24-bit-fraction fixed-point multiply with 24-bit result c. 2-decimal to 24-bit fraction conversion d. 24-bit fixed-point exponential expansion (calculation of 6 Z ( - l ) n x n/n! = 1 - e" X, accurate to 0.1% for 0 £ x < 1) n=l e. 24-bit to 12-bit fraction roundoff (7) Compensator pre-calculation routines for coefficient multipliers in the difference equations (8) Miscellaneous (located throughout the program) routines for a. i n i t i a l i z i n g for keyboard input, sampling, difference equations, scale displays, etc. b. packing bytes (in 6-bit ASCII) in a display text buffer c. checking that compensator parameters are within a predetermined range d. conversion of error samples to response samples prior to data display The operation of the program can best be illustrated by following through the steps involved in an actual example by means of the general flowchart of the next section. The example used is the same system whose theoretically predicted results are plotted in Chapter 2, and the actual results taken from scope photographs, are shown in Chapter 5 The steps are described as the user would go through the program,as follows 1. The i n i t i a l user-input display appears: DISPLAY-INTERACTIVE SAMPLING, FEEDBACK AND COMPENSATION PROGRAM PLEASE SPECIFY IN OCTAL: 1. NO. OF SAMPLES= ? 2. "NO. OF SCALE MARKS= ? 3. X-AXIS POSITION=? 4. SENSE LINE= ? 5. PULSE LEVEL=? 6. A/D CHANNEL=? 7. SAMPLING PERIOD MULTIPLE= ? . PLEASE TYPE IN ALL DATA BEFORE ENTERING "K" COMMAND The-various parameters are f u l l y explained in the user write-up. 2. Suppose the user wishes to take 100 samples at 100Hz sampling frequency, and place the horizontal axis at the bottom of the scope, with scale marks at 20, 40, 60, 80, and 100. The sampling pulses on sense line 2 w i l l be high-to-low, and the error signal w i l l be sampled on A/D channel 14. He w i l l type, in order, 144, 5, 423, 2, 1, 14, 1. These numbers w i l l be echoed on the display. 3. The user types K, and the keyboard commands display appears: KEYBOARD COMMANDS: (N=OCTAL DIGIT) PROGRAM CONTROL: -> RESTART AND CLEAR R RESTART S SAMPLE F SAMPLE WITH FEEDBACK C SAMPLE WITH COMPENSATION P ENTER COMPENSATOR PARAMETERS EN EVALUATE AND DISPLAY CRITERIA FOR TABLE N DISPLAY: K KEYBOARD COMMANDS D MARKED SCALE DN DATA TABLE N DN,M DATA TABLES N AND M D AND E COMMANDS MUST BE TERMINATED BY A CARRIAGE RETURN. 4. The user now wishes to observe the uncompensated system respons He types F-, and the display requests a table address for data storage: DATA STORE ADDRESS= ? Assuming the data w i l l be stored in Table 0 , he types 0 i . ( i = carriag return). The program now i n i t i a l i z e s in preparation for sampling; the D/A output is set to 0 (value of the error signal for t < 0). At this point, the analogue computer must be on RESET so that system response is i n i t i a l l y 0, and sense switch 1 must be reset. The program w i l l now wait in a loop u n t i l sense switch 1 is set: this allows the user time to make the necessary off-line adjustments, namely setting the analgoue to COMPUTE and making sure that the D/A scaling network output is zero, readjusting the pot i f necessary. When the user i s ready to begin sampling, he sets sense switch 1, and the program continues. Fir s t i t waits for the sync pulse on sense line 1, and then i t sets the D/A to R q (value of error signal at t = 0) and jumps to the sample-and-store routine, where i t waits for the f i r s t sampling pulse to occur on sense line 2. The sample is taken, stored, and D/A converted; then the D/A converter output is scaled to the ±1 v range for input to the analogue computer. (It is shifted right once on D/A conversion since the D/A has one less b i t than the A/D). The program then waits for the next sampling pulse, and so on. (It should be noted here that in general sampling only occurs every N pulses, where N is the sampling period multiple specified before; in this way, sampling may be done at 50 Hz, 33 Hz, 25 Hz, etc.) The interrupt i s off during this process; however, i t need not be i f a fast high~pr£>rity device can be allowed to interrupt the sampling. 5. When the run is completed, the message SAMPLING COMPLETE appears on the display. It is good practice at this point to reset the analogue and sense switch 1 in preparation for a subsequent sampling run. 6. To simply display the response, the user may type D0 j), . However, i f he wishes to display the response together with i t s performance evaluation, he types E0 it . The error samples, stored in Table 0, are converted to response samples, stored in a temporary table for display (leaving Table 0 unchanged), and the performance c r i t e r i a are calculated; the resulting numbers are then converted to 6-bit ASCII and packed in the "performance display" text buffer. The response curve, together with the marked axes and performance calculation, appears on the scope. (Result is shown in Fig. 5.1a). 7. Suppose the user next wishes to observe the effect of using gain compensation with k =' 1.5. He types P, and the compensator-options dis-play appears: COMPENSATION: 1. GAIN 2. LEAD 3. LAG-LEAD PLEASE REPLY BY TYPING 1, 2, OR 3. 8. He then types 1 to specify gain, and the display responds with GAIN KC= . ; 0 < .KC * 1.5 9. He enters, for example, the value 1.50 and then types G, at which point the program calculates the multiplier coefficient and sets the compensator-subroutine pointer for the gain difference equation. The program then returns to the keyboard commands display. 10. The user types C, and a table address is requested to which he responds by typing 1 i. to store the data in Table 1. He then makes off-line adjustments and sets sense switch 1. 11. The sampling is done as before, except that the error samples e(nT) are routed through the difference equation e £(nT) = k^e(nT), and the compensator output results e^CnT) are input to the analogue via the D/A and scaling network. 12. When the "sampling complete" message appears, the user types E l to evaluate and display the gain-compensated response. (Result in Fig. 5.1b). 13. To observe lead compensation effect, the user types P, followed by a 2, causing LEAD ZERO W = _ _. 10 < W $ 15 LEAD A-FACTOR A = _. 1 < A <: 5 to appear. He enters, for example, the values 10.50 and 2.00 and types G. After the multiplier coefficients have been calculated, the program returns to display the keyboard commands, and the user types C, followed by 2 J. , and the rest of the procedure follows as before. The command E2 ), causes the lead-compensated response curve and performance evaluation to appear on the scope. (Result i n Fig. 5.1c). 14. For a lag-lead compensated response, the user types P, followed by a 3, causing LAG ZERO Wl = 2 < Wl <c 4.5 LAG A-FACTOR Al = 1 < Al $ 5 LEAD ZERO W2 = 10 < W2 •< 15 LEAD A-FACTOR A2 = 1 < A2 ? 5 to appear. The rest of the procedure is the same as for lead response, except that data i s stored in Table 3, and the lag-lead subroutine i s used. The E3 ). command causes the lag-lead compensated response and performance evaluation to be displayed. (Result in Fig. 5.Id.) At almost any time, the user may change input or compensator parameters with the * command, which i s not included in the general flowchart because i t is part of the keyboard service routine. Not used in this example were the S, D ) , and Dn,m I commands. The S command is meant for sampling only (no D/A involved), since the program can also be used generally for sampling and display of signals. (Sense line 1 is l e f t unconnected and sense switch 1 i s l e f t set for this purpose.) D ^ simply displays the marked axes alone, and Dn,m J. allows two data tables to be displayed at once, one on each scope channel. For general sampling purposes, the x-axis should be positioned in the middle of the scope; the R q line w i l l not appear, and the convert-for-display subroutine allows the samples to be displayed as originally taken. program use may be found in the user write-up, and complete documentation accompanies the program l i s t i n g . The compensator difference-equation subroutines are discussed and flowcharted in sections 4.3 and 4.4. A more detailed explanation of parameters, commands, and 4.2 General Flowchart 39 Clear out user-input data locations Put zero in core and "?" in user-input display text buffer locations I n i t i a l i z e 1. Reset flags and pointers 2. Sample RD 3. Enable half-size display characters 4. Set data input mode for keyboard service routine I n i t i a l input data| display Jser enters data User types i n : 1. No. of samples 2. No. of scale marks 3 . x-axis position 4. sense line 5. pulse level 6. A/D channel 7. sampling period multiple Any command except K, R, or w i l l be ignored as an error (? typed) at this time. K i s only accepted when a l l data has been entered. 1. Build sample and sense-line instructions from user data 2. Set up display scale parameters 3 . Set command mode for keyboard 4. Go to keyboard commands display 40 User [types commandB Display l i s t of a l l keyboard commands; any command may be typed at this point. n R? Restart program with user-input data locations cleared. Restart program without disturbing user-input data locations. K? Return to keyboard commands display. S? n F? 4 h -Sample signal on specified A/D channel; store samples in specified table. Sample signal on specified A/D; Output to D/A; also store samples. C? Sample signal on specified A/D; store samples; go to compensation subroutine; output result to D/A. 41 Set compensator-input mode for keyboard service routine; enter compensator-options display routine. Display marked axes with dashed line for RQ (unless x-axis is in the middle of the scope). Display: (1) marked axes with R line (2) data in Table n as curve Display: (1) marked axes with R line (2) data in Table n ° (3) data in Table m Evaluate, for sampled data in Table n, the system performance; display data | and performance figures on marked axes I with R Q Not a valid command; ignored as error (? typed). Return to key-board commands display. 42 o 4A Specify table and i n i t i a l i z e system Get sample and store in table Same as 4, except that sample i s output to D/A after i t i s taken and stored. Same as 4, except that sample i s input to the compensator difference-equation subroutine, then output the result to D/A, after the sample i s taken and stored. 43 I Samples may be stored in any one of I eight tables (0-7); each table has room for 127 samples. 1. Interrupt off. 2. Set D/A to zero 3. Make sure analogue is on RESET, and sense switch 1 (SNS 1) is reset. User may make off-line adjustments here: 1. Put analogue on COMPUTE 2. Check that D/A scaling network output i s zero 3. When ready to continue, set SNS 1 Wait for sync pulse before starting to sample I n i t i a l value of error signal Pulse counter is -N i n i t i a l l y , where the user-specified sampling period i s N x 0.01 sec Wait for the specified high (or.low) level to appear on the specified sense line 44 Sample on specified A/D N pulses are counted between each sample to get the specified sampling period Store in specified table 1. Set compensator-input mode for keyboard service routine 2. Reset flags and pointers User must now type 1, 2, or 3 to specify type of compensation User I types number D 45 Gain compensation — Lead compensation Lag-lead compensation y B j Same as 7A, except lead comp. display and pre-calculation © 7Q ) Same as Ik, except lag-lead comp. display and pre-calculation \z Arithmetic routines are used here to calculate the multiplier coefficient (s) for the difference equation. User w i l l usually type C at this point. 46 Convert errorl samples to response E samples Convert error samples to response samples Evalual system perf on :e nance Display horizontal marked scale Same as 9, except that scales and Table n are displayed on scope channel 1, then scales and Table m displayed on channel 2. 47 4.3 Difference-Equation Subroutines These subroutines mechanize the difference equations 4.1, 4.2, 4.3, which were detailed in Chapter 2. The multiplier coefficients have been previously calculated and are in a 2-word format, integer and 12-bit fraction (or fraction only in the case of coefficients always less than 1). For 100 Hz sampling frequency, the computational delays intro-duced by the routines are negligible. The maximum time taken by the routines i s about 58 usee for gain, 122 for lead, and 357 for lag-lead. •The actual time taken depends on the sign of the error sample, and in the gain case, whether or not k^ is less than 1. The difference equations contain a subroutine which does a two's complement multiply of an integer by a 12-bit fraction with integer result (rounded o f f ) . The fraction i s assumed positive, and is therefore unsigned. This 37-usec routine, together with signed integer multiplies in the main part of the difference-equation routines, take up most of the computation time. (The integer-fraction multiply routine i s indicated by a box with extra bars in the flowchart.) The equations, which are detailed in the flowcharts of section 4.4 are: Gain: e (n) = k e(n) (4.1) c c Lead: e (n) = e(n) - A e(n-l) + e~ a w Te (n-1) (4.2) c o c -w1T/a1 Lag-lead: e n(n) = e(n) - e(n-l) + e e ..(n-1) (4.3) c l c l ~ a2 W2 T e c 2(n) = e(n) - e(n-l) + e e c 2 ( n - l ) e (n) = c e(n) - c.e (n) + c e „(n) c o 1 c l 2 c2 A Q , C 2 and the poles are always less than 1 and are represented by a 12-bit fraction word only. Return 49 Lag-Lead Compute e(n)-e(n-l) and store -wlT/al e x e n(n-l) c l Add e(n)-e(n-l) Store as £ c l ( n ) -a2w2T x e 0(n-l) c2 Add e(n)-e(n-l) c Q(int) x e(n) Store Negate and f 50 e(n) - e(n-l) for next iteration 5. EXPERIMENTAL RESULTS AND CONCLUSIONS The results of a typical run are shown i n the photograp in Fig. 5.1a-d. A l l parameters are the same as in the example used throughout this paper. Analogue system: K = 300 P l = 5 p 2 = 10 Theoretically predicted curve in Fig. 2.6 (I). Gain compensation: k =1.5 c Lead compensation: w = 10.5 a = 2 . Theoretically predicted curve in Fig. 2.6 (II). Lag-lead compensation: w^  = 4 a i = 4 w2 = 10-5 , a2 = 2 Theoretically predicted curve in Fig. 2.6 (IV). .Sampling period T = 0.01 sec. 52 P E R K • UERSHDD7s,30. 3X. 8 i »-•s:o <KS *ia so • 1 0 W Fig. 5.1a Scope Photo - Uncompensated System Response P ERK T I ME = !.•=: nUERSHDQT=:33. SS. 3| O F F S E T * © . © 5 2 U 8 4-K « 4 » 80 :L,;:":i Fig. 5.1b Scope Photo - Gain-Compensated System Response PERK TIHEaJLti P U ERSHDQTailE. Z» OFFSET"®©. 132 u 4 0 rf© 8 © - l ^ 1 3 Fig. 5.1c Scope Photo - Lead-Compensated System Response PERK TIHEa.22 D U E R S H D a 7 a i 0 . 2^ D F F S E T a © . 04<£ U B _ -J i _ j —I — 4 0 <£0 80 -10° Fig. 5.Id Scope Photo - Lag-lead-Compensated System Response These results differ from the theoretically predicted ones of section 2.3.4 by about 10%, and can be accounted for (see section 3.4) by the inaccuracies inherent in the hardware. For instance, a five or ten percent variation in Donner RC components would cause the overshoot and peak time to be slightly off, and d r i f t in the D/A scaling offset would affect the measured position offset. Thus the system i s accurate enough for purposes of studying the effects of compensation on a system response. The program could be made more sophisticated i f implemented on a computer with features such as: (1) several accumulator registers: (2) a real-time clock: (3) a storage scope: (4) hardware floating-point processor and: (5) up to 16K of core. For example, 8 or 16 accumulators would make the program much more efficient (the present version takes up 7K of the available 8K on the PDP-12). A real-time clock would allow sampling to occur on an interrupt basis, thus leaving the processor free to do other tasks, instead of waiting for a sampling pulse to occur on a sense line. A storage scope would also be useful for this purpose, since the refresher scope necessitates the program spending almost a l l i t s time in display routines; there is also no flic k e r problem with a storage scope. A hardware floating-point processor would not only simplify the arithmetic routines and make them much more general, but would shorten the time required in the compensation sub-routines. A computer with microprogramming capability could also be used for this purpose. For more general types of compensation than the ones used here, this i s essential. Another desirable feature would be A/D and D/A channels which can accept a ±5 v or ±10 v input range, so that small amounts of ripple would not be a problem. It i s also preferable for the D/A to have as many levels as the A/D and for i t s output to be scaled in the same range, thus eliminating the need for an op-amp scaling network which can introduce offset errors. The PDP-12 can be considered about minimal for this type of system, since i t has enough (8K) core, several A/D channels, one D/A channel, a scope with character-generating capability, some means by which external pulse levels can be detected (the sense lines), and hard-ware multiply, divide and shift instructions (Extended Arithmetic Element). However, i t has none of the additional features mentioned above, and the program is as general as can be allowed by the present f a c i l i t i e s . Some additional things which could be done on a machine with the proper features are root-locus plots, Bode plots, time responses (theoretically calculated), and optimal control. One might like to make state variable measurements, calculate a performance index, and automa-t i c a l l y adjust compensator parameters for an optimal response, perhaps with the capability of changing the expression for the performance index i t s e l f ; also included could be matrix-inversion methods and possibly special methods for time-varying and nonlinear systems. To do this, one would require a rather powerful minicomputer, most l i k e l y one with at least 16K of core, a storage scope, hardware floating-point, several accumulators and probably a very fast cycle time. With the advances being made in minicomputers and their peripherals, however, this could be accomplished. In an actual system i t might be desirable to implement the di g i t a l f i l t e r in hardware as suggested by White and Mitsutomi (11.) in conjunction with a read-write memory for the multiplier coefficients. The computer could determine which d i g i t a l f i l t e r sections are to be used, and f i l l the corresponding coefficient locations in the memory. The f i l t e r could then be treated as an I/O device, which would result in a tremendous gain in speed, particularly for a complicated f i l t e r requiring time-sharing and multi-precision accuracy. In systems where speed i s important, i t would be desirable to implement the d i g i t a l f i l t in this way, provided the hardware can be made as flexible as software. 57 REFERENCES 1. Merkel, R., "Applying Digital F i l t e r i n g on Line", Control Engineering, v. 17, no. 1, January 1970, pp. 92-95. 2. Proakis, J. G., "Adaptive Digital F i l t e r s for Equalization of Telephone Channels", IEEE Trans, on Audio and Electroacoustics, v. AU-18, no. 2, June 1970, pp. 195-200. 3. Rader, C. and Gold, B., "Digital F i l t e r Design Techniques in the Frequency Domain", Proc. IEEE., v. 55, no. 2, February 1967, pp. 149-171. 4. Roberts, P. D., "Self-Adjustable Orthogonal Digital F i l t e r s for System Identification and Optimization", Proc. Institution of E l e c t r i c a l Engineers, v. 114, May 1967, pp. 666-670. 5. Stevenson, J. W., "Servo Compensation with Digital F i l t e r s " , Control  Engineering, v. 18, no. 11, November 1971, pp. 71-75. 6. Takahashi, Y., Rabins, M. J., Auslander, D. M., Control, Ch: 11. Reading, Mass.: Addison-Wesley, 1970. 7. Tou, J. T., Digital and Sampled Data Control Systems, New York: McGraw-Hill, 1958. 8. White, S. A., "Designing a Comb F i l t e r into a Digital Servo Controller", Report X8-1879/501, September 1968, Autonetics Div., North American Rockwell Corp., Anaheim, Calif. 9. White, S. A,, "Coefficient-Word-Length Requirement for Accurate Pole Location for Digital F i l t e r s " , Report X8-2129/501, October 1968, Autonetics Division, Anaheim, Calif. 10. White, S. A., "Design and Implementation of Recursive Digital F i l t e r s " , Report No. X9-359/501, April 1969, Autonetics Div., North American Rockwell Corp., Anaheim, Calif. 11. White, S. A. and Mitsutomi, T., "The IC Digital F i l t e r : A Low-Cost Signal Processing Tool", Control Engineering, v. 17, no. 6, June 1970, pp. 58-68. 


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