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Design of sub-mW RF CMOS low-noise amplifiers Ho, Derek 2007

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Design of Sub-mW RF C M O S Low-Noise Amplifiers by D E R E K H O B . A . Sc., The University of British Columbia, 2005 A THESIS S U B M I T T E D IN P A R T I A L F U L F I L L M E N T OF T H E R E Q U I R E M E N T S F O R T H E D E G R E E O F M A S T E R OF A P P L I E D S C I E N C E in T H E F A C U L T Y OF G R A D U A T E S T U D I E S (Electrical and Computer Engineering) T H E U N I V E R S I T Y OF B R I T I S H C O L U M B I A March 2007 © Derek Ho, 2007 Abstract The quest for low power, low cost, and highly integrated transceivers has gained substantial momentum due to the explosion of wireless applications such as personal area networks and wireless sensor networks. This dissertation presents a comprehensive study and a design methodology for power-efficient C M O S radio-frequency (RF) low-noise amplifiers (LNAs) . To demonstrate the design methodology, a sub-mW fully integrated narrow-band source degenerated cascode R F L N A is designed and simulated in a standard 90nm C M O S process to operate in the 2.4GHz band. The L N A achieves a voltage gain of 22.7dB, noise figure (NF) of 2.8dB, 3 r d-order intercept point (IIP3) of +5.14dBm, and l d B compression point ( P l d B ) o f - 1 0 d B m , while consuming 943 oW from a I V supply. The main contributions of this work include: i) the introduction of a design methodology for power-efficient sub-mW source degenerated L N A s ; ii) the collection of design graphs to facilitate the exploration of tradeoffs between L N A performance and power consumption; and i i i) the use of an alternative analysis to find the dependency of gain, noise, and linearity on biasing conditions. i i Table of Contents A B S T R A C T ii T A B L E O F C O N T E N T S iii L I S T O F T A B L E S v L I S T O F F I G U R E S vi A C K N O W L E D G M E N T S vii C H A P T E R 1. I N T R O D U C T I O N 1 MOTIVATION 1 RESEARCH OBJECTIVE 2 THESIS ORGANIZATION 3 C H A P T E R 2. B A C K G R O U N D 5 TWO-PORT NETWORKS 5 IMPEDANCE MATCHING 6 SCATTERING PARAMETERS 7 LINEARITY 9 Harmonic Distortion 9 Intermodulation 11 1 dB Compression Point , 13 3rd Order Intercept Point 13 STABILITY 14 NOISE IN TWO-PORT SYSTEMS 15 C H A P T E R 3. C M O S L N A F U N D A M E N T A L S 19 NOISE SOURCES IN CMOS 19 Thermal Noise 19 Induced Gate Noise 20 Distributed Gate Noise 22 INTRINSIC MOSFET TWO-PORT NOISE PARAMETERS 23 INDUCTIVE SOURCE DEGENERATION 24 Input Impedance Match ; 25 Circuit Transconductance 26 CIRCUIT TOPOLOGIES 27 PERFORMANCE OF THE CASCODE AMPLIFIER 29 Voltage and Power Gain 30 Noise 30 Linearity .' 31 INDUCTOR DESIGN 33 Physical Dimensions 33 Inductor Figures of Merit 34 Inductor Modeling 36 C H A P T E R 4. D E S I G N I N G F O R P O W E R - E F F I C I E N T O P E R A T I O N 37 DEVICE BIASING 37 Terminal I-V Characteristics 38 Gain and Transconductance 40 TRANSISTOR SIZING 44 STEP-BY-STEP LNA DESIGN METHODOLOGY 46 i i i CHAPTER 5. DESIGN OF A POWER-EFFICIENT LNA AND SIMULATION RESULTS 52 CIRCUIT TOPOLOGY AND IMPEDANCE MATCHING 52 POWER-EFFICIENT LNA DESIGN 53 Gain 54 Noise 56 Linearity 58 SIMULATION RESULTS 59 PERFORMANCE SUMMARY 62 CHAPTER 6. CONCLUSIONS AND FUTURE WORKS 64 CONCLUSION 64 FUTURE WORK 65 REFERENCES 67 iv List of Tables Table 1 Summary of L N A component values 59 Table 2 Summary of L N A performance 61 Table 3 Comparison of CMOS low-power LNAs 62 v List of Figures Chapter 2 Figure 2.1 Two-port network diagram 5 Figure 2.2 A system with a source driving a load.. 6 Figure 2.3 S parameter representation of a two-port network 7 Figure 2.5 Frequency locations of distortion terms 12 Figure 2.4 Noise modeling, (a) Noisy two-port, (b) Input-referred noise model 15 Chapter 3 Figure 3.1 MOSFET small-signal model with thermal noise 19 Figure 3.2 Induced gate noise model, (a) Frequency dependent, (b) Frequency independent.... 21 Figure 3.3 Inductive source degeneration 25 Figure 3.4 Narrow-band topologies, (a) Common-source, (b) Cascode 27 Figure 3.5 VEP3 of a 40nm nFET vs. VGS for different VDS (VTH = 0.23V) [22] 32 Figure 3.6 The layout of a square spiral inductor 33 Figure 3.7 Pi-model of inductor 36 Chapter 4 Figure 4.1 ID vs. VGS for a 90nm nFET (VDS= IV) 38 Figure 4.2 ID vs. VDS for a 90nm nFET (W/L = 20 (im/O.lirm, VDS= IV)...., 39 Figure 4.3 fT vs. VGS for a 90nm nFET (Vos= IV) ' 40 Figure 4.4 gm vs. VGS for a 90nm nFET (VDS= IV) 41 Figure 4.5 gmIID vs. VGS for a 90nm nFET (VDS= IV). 42 Figure 4.6 r0 (=l/gds) vs. VDS for a 90nm nFET (VDS= IV).. 43 Figure 4.7 Intrinsic gain gm r0 (= gjgds) vs. VGS for a 90nm nFET (VDS= IV) 44 Figure 4.8 NF vs. Woi cascode and common-source amplifiers. ; 45 Figure 4.9 Cascode amplifier, (a) Schematic, (b) Simplified small-signal model for input matching analysis 46 Chapter 5 Figure 5.1 Schematic of a cascode amplifier 52 Figure 5.2 ID of a cascode L N A . (a) ID vs. VGS (1^=^=2 5 urn), (b) ID vs. W (FGS=0.4V).' 54 Figure 5.3 Voltage gain of a cascode L N A . (a) A v vs. VGS, (b) A v . vs. W. 55 Figure 5.4 NF of a cascode LNA. (a) NF vs. VGS, and (b) NF vs. W 56 Figure 5.5 Noise contribution of the signal source and L N A components 57 Figure 5.6 IIP3 vs. VGS of the cascode L N A '. 58 Figure 5.7 PldB vs. VGS of the cascode L N A 58 Figure 5.8 7t-model of a 5nil spiral inductor '. 59 Figure 5.9 Gain and NF of the proposed L N A 60 Figure 5.10 S\ \ of the proposed L N A 61 Figure 5.11 Graphical illustration comparing recently published LNAs and this work 62 vi Acknowledgments This work 1 could not have been completed without the help of many people and I would like to take this opportunity to express my appreciation to them. I would like to start by thanking my graduate advisor, Professor Shahriar Mirabbasi for his guidance and for always making decisions based on what is best for my education. This, has led to not only a productive but also an enjoyable experience. I would like to thank Dr. Andre Ivanov for supervising my undergraduate research in the System-on-Chip lab, where I cultivated my early interest in VLSIc i rcu i t s . I would also like to thank Professor Resve Saleh and Professor Steve Wil ton for reading this dissertation and serving as committee: members in my thesis defense. I could not imagine where I would be without the help of Roberto Rosales and Kar im Al l id ina . They deserve special recognition for having the patience to explain to me any question that I threw at them. I probably would have gone insane without the companions at the S O C lab to listen to all my problems and give me advice (even though some advice was insane too). Y o u know who you are: Usman Ahmed, Shirley A u , Nathalie Chan, Melody Chang, Scott Chin, 1 This research is funded by Natural Science and Engineering Research Council of Canada ( N S E R C ) . C A D tools are provided by Canadian Microelectronics Corporation ( C M C ) Microsystems. v i i David Chiu, Rod Foist, Ami t Kedia, Sohaib Majzoub, Xiongfei Meng, Dipanjan Sengupta, and Howard Yang. I am sure I would be a different person without the influence of Wilson Fung and Jennifer L i . Being friends for more than a decade, Wilson and I grew up together. His commitment to doing good work has become my role model. Having a technical discussion with him is nothing less than inspiring. Jennifer and I have gone through both ups and downs. Her love is indispensable to my general well-being. Last but not least, I would like to thank my sister for putting up with me for as long as she has existed. I 'd also like to express my deepest gratitude to my parents for their unconditional love. They have made tremendous sacrifices to give me the best upbringing a child can possibly receive. Derek Ho Vancouver, B C v i i i Chapter 1 Introduction Motivation The design of low-power wireless transceivers has gained substantial significance due to the explosion of wireless applications such as personal area networks and wireless sensor networks. These applications demand for small, low-cost, and low-power wireless transceivers which require a high level of integration with a minimal amount of off-chip components. The first active block in most wireless receivers is the low-noise amplifier (LNA). The LNA needs to amplify the signal without adding a large amount of noise and distortion while consuming minimal power. RF circuits have traditionally been implemented in compound semiconductor technologies such as Gallium Arsenide (GaAs) or Silicon Germanium (SiGe). Since the CMOS technology is employed for the digital transceiver back-end, it is attractive to implement the RF front-end also in CMOS, with the goal to integrate all parts of the receiver on a single chip to reduce cost and time to market. In the recent past, numerous CMOS RF circuits have been presented and have demonstrated good performance [l]-[4]. 1 The design of a power-efficient L N A in C M O S is particularly challenging due to a number of reasons: 1) The performance such as gain and bandwidth of a metal-oxide-semiconductor field-effect transistor ( M O S F E T ) is poor when biased at the small drain current necessary for power-efficient operation. 2) The choice of circuit topologies is limited due to the reduction of M O S F E T output resistance and supply voltage as C M O S technology scales. 3) On-chip passive elements have poor quality factor, limited range of values, and large area consumption. 4) Conventional power-constrained noise optimization techniques [5] often lead to subthreshold operation when power consumption is restricted to l m W or below. Research Objective The objective of this thesis is to develop a narrow-band R F C M O S L N A design technique suitable for the prevalent inductively degenerated L N A architecture. This work aims to achieve the following targets: 1) Devise a methodology that leads to a power-efficient L N A design. 2) Explore the tradeoffs between L N A performance and power consumption. 3) Find a circuit topology capable of low-voltage low-power operation. 4) Demonstrate a high performance design with on-chip \ow-Q passive components in a deep submicron technology. 2 In devising the design methodology, a major goal is to review, coordinate, and exploit several device-level properties proposed in the recent literature: 1) Device transit frequency fr and unity power gain frequency fMAX depend strongly on drain current density, which is mainly controlled by the gate-source voltage [6]. 2) The M O S F E T has a large transconductance per unit drain current gm/Io in weak inversion and progressively degrades towards strong inversion [7]. 3) The M O S F E T minimum noise figure improves as gate length decreases [6], [8]. 4) M O S F E T linearity improves as drain current density increases with a significant peaking in the moderate inversion region [9], [10]. A s part of the overall objective, a 2 .4GHz L N A is designed and simulated in a 90nm C M O S technology with sub-mW power consumption using the proposed design methodology. The simulation results demonstrate the applicability of the methodology to the design of narrow-band R F front-ends needed for many low-power applications. Thesis Organization In this thesis, an L N A design methodology is devised and. documented. Chapter 2 presents background information about two-port networks that is fundamental to the design of L N A s and other R F circuits. Chapter 3 focuses on the design of C M O S L N A s . Chapter 4 discusses the design of transistor biasing conditions for power-efficient amplifiers. This chapter concludes with a step-by-step design procedure. Chapter 5 3 details the application of the proposed methodology to the design of a sub-mW L N A . Simulation results are presented at the end of this chapter. Finally, Chapter 6 draws some conclusions and suggests future works. 4 Chapter 2 Background To simplify the design and analysis of analog circuits, it is useful to abstract circuit blocks into two-port networks. This chapter begins with a discussion of parameters that are used to characterize two-port networks. Then, performance measures of the two-port network such as gain, noise, linearity, and stability that are important in the design of L N A s are presented. Two-Port Networks A two-port network is shown in Fig . 2.1. There are usually two quantities, namely, voltage and current associated to each port. A t low frequencies, two common representations that characterizes the network are the impedance matrix (Z parameters) and the admittance matrix ( Y parameters) [11], [12]. 12 O O + + Port 1 Vl Two-Port Network Port 2 O Figure 2.1 Two-port network diagram. 5 The impedance and admittance matrices are defined by (2.1) and (2.2), respectively. ~zu 7 7 _ Z y21 7 z , 2 2 _ ' l X ^1 J2_ X Y I22J _V 2 . (2.1) (2.2) Z parameters and Y parameters are particularly useful at low frequencies because they can be readily measured by applying either a test current or voltage to the input port and connecting the output port either as a short or open circuit. For example, from (2.1) vi can be expressed as v, =Zuil+Zui2. (2.3) If the output port is open circuited, ii becomes zero, and Z\ \ can be calculated to be Impedance Matching A system with a signal source driving a load is depicted in Fig . 2.2 where Zs and Zi are the source and load impedances, respectively. Zs — Rs + jXs Vs (o^ ) ZL = RL +JXL Source Load Figure 2.2 A system with a source driving a load. 6 There are two types of impedance matching [13]. The first type of impedance matching concerns with minimizing signal reflection from the load back to the source. When Zs = ZL, there is no reflection. This is important for the design of the receiver front-end as the frequency response of the antenna filter that precedes the L N A deviates from its normal operation i f there are reflections from the L N A back to the filter. The second type of matching concerns with maximum power transfer from the source to the load. Hence it is often referred to as power matching. Power matching occurs when the load impedance is the complex conjugate of the source impedance. When the source and load impedances are real as in a typical 50Q R F system, the conditions for power matching and impedance matching are equal. Scattering Parameters A t R F and microwave frequencies, Z and Y parameters become very difficult to measure due to the need for broadband short and open circuits [14], A s a result, a different representation of the two-port network is needed at these frequencies. A popular representation is the scattering, or S, parameters. Instead of relying on ports being open and short circuited, S parameters have the advantage that they can be measured by matching the source and load impedances to a reference impedance Z0. A n S parameter representation of a two-port network is shown in Fig. 2.3. Figure 2.3 S parameter representation of a two-port network. 7 The notion of the S parameter representation is to measure the normalized incident voltage wave a, entering the system at port i, as well as the corresponding reflected voltage wave 6, leaving port i. The normalized incident and reflected voltage waves a, and bi are related to the terminal voltage and current at port i by the following equations: v, +ZJ, a, = I O I (2.4) Vl -Zoii (2.5) where Z0 is assumed real as it is usually equal to 50£X The network of Fig. 2.3 can be express, in matrix form, as (2.6). i r.s\. K.:\\„.~\ (2.6) where S\\, Sn, 521, 522 are the scattering parameters. By expanding the scattering matrix, the following equations can be written: V 512 a, A . _52i 522_ a2 5,, =• a , = 0 5n — l-\ 521 -52 2 - • a ,=0 o , = 0 a ,=0 (2.7) (2.8) (2.9) (2.10) where 5i i is interpreted as the ratio of the reflected voltage wave to the incident voltage wave at port 1 with the output port properly terminated. The condition for a port being 8 properly terminated is that the impedance looking into the port must match the characteristic impedance of the transmission line attached to it. Definitions for the rest of the S parameters can be interpreted analogously. Linearity Linearity is a key requirement in the design of an L N A because the L N A must be able to maintain linear operation in the presence of a large interfering signal and when the input is driven by a large signal [14]. Intermodulation linearity, characterized by the input-referred 3 r d-order intermodulation intercept point (IIP3), is crucial to prevent the intermodulation tones created by a large interfering signal from corrupting the signal o f interest. Large-signal linearity, characterized by the input-referred l d B voltage compression point (P ldB) , is important as it determines the maximum input level that can be amplified linearly, i.e. the upper bound of the dynamic range of the L N A . Harmonic Distortion The input Vi and output V0 of a two-port network can be related by a power series [15]: K =aiVi+a2Vi2 +aiVi3 +... (2.11) where a\, « 2 , « 3 are constants. If the input is driven by a sinusoidal signal as follows, ^)=F,cos(tfv) (2.12) where V\ and a>\ are the amplitude and frequency, respectively, then the output is equal to a V2 V0(t)=a1Vi cos(ft>,f)+ 2 1 [cos(2ftv)+l] a V' 2 ( 2 , 1 3 ) + 3 1 [cos(3fty) + 3cos(ay )] + ••• 9 The first term in (2.13) is the linear term, and is the ideal output i f the two-port network is completely linear. Other terms in (2.13) are due to non-linearities, and they cause a D C shift as well as distortion at frequencies 2co\, 3co\, and higher harmonics, which result in either gain compression or gain expansion. It can also be observed from equation (2.13) that distortion is present in any signal level. To quantify the amount of harmonic distortion, the following definitions are used: Amplitude ,„ H D i = 1 ?5L o\ 4) Amplitude Amplitude,,, HD,= ^ - (2.15) Amplitude where (2.14) represents the fractional second harmonic distortion, and (2.15) represents the third fractional harmonic distortion. Higher order fractional harmonic distortion definitions can be written in the same fashion. The above definitions for the second and third order fractional harmonic distortion can be written in terms of the coefficients of the power series and the input signal by examining (2.13). HD2=-^V, (2.16) 2a, HD3 (2.17) 4a, 10 Intermodulation Harmonic distortion, introduced previously, is the result of non-linearities due to a single sinusoidal input. It is quite possible in practice that two or more sinusoidal signals are applied to the input of a two-port, for example, the first signal representing the input and others representing large in-band interferences at the input of an L N A . When this occurs, another non-linearity called intermodulation results. To see the effects of both harmonic distortion and intermodulation, assume that the input signal is now equal to The output can be expanded in a power series and (2.18) can be substituted into (2.11). The linear first term can be expressed as Vj (t) = Vx cos(<y^) + V2 cos{co2t) (2.18) \vx cos(coxt) + V2 cos(ft>2?)] (2.19) The second term is given by V2 V 2 = ^ _ L _ [cos(2^, t) +1] + f^2_L_ [cos(2co2t)+1] (2.20) + a2VxV2 [cos(ty, + co2 )t + 003(0), - co2 )t] Expanding the third term gives [cos(3<»,;)+ 3cos(a>,?)] + 3 ^ 2 [cos(3&>2f) + 3cos(a>2t)] + — a 3 F, V2 [2 cos(coxt) + cos(2<£>2 + cox )t + cos(2&>2 - cox )t] + — aiVx2V2[2cos(a)2t)+ cos(2&>, + a>2)t + cos(2&>, - « 2 ) ^ ] (2.21) 11 It can be observed from (2.20) and (2.21) that harmonic distortion terms are produced as i f each sine wave is applied separately. However, second order intermodulation terms are also produced at (a>\ + 0)2) and (a>\ - C02), and third order intermodulation terms are produced at (2a>\ ± CO2), and (2a>2 ± co\). Fig . 2.5 shows the distortion terms in the frequency spectrum [12]. V0 F F 4 4 IM2 4 IM3 4 IM, 1M3 4 HD2' 4 HD2 4 IM3 IM3 4 4 HD3 4 HD3 4 frfx 2frf2 Af2 2/2-/, 2/, 2f2 J/ , 3f2 f fv.fi 2Mf2 2fy-fs Figure 2.5 Frequency locations of distortion terms; The following two equations define fractional intermodulation: Amplitude ^ IM2 = Amplitude (2.22) Amplitude (2a± a>2),(2<u2±<a]) Amplitude 0)\ ,0)2 (2.23) Using the definitions in (2.22) and (2.23), the fractional intermodulation terms are IM2 =f^Vl a , (2.24) IM3=3-^V> 3 4a, 1 (2.25) 12 where it is assumed that V\ = V2. From Fig. 2.5, it is apparent that the 3 r d-order intermodulation distortion IMi signals are close to the signal of interest F, which makes the filtering out of IM3 signals difficult when recovering the signal of interest. Therefore minimizing intermodulation distortion is a key objective in many R F circuit designs. 1 dB Compression Point It is mentioned previously that the 3 r d-order term in the power series can either cause gain compression or gain expansion. If we assume that the sign between a\ and az are different, then gain compression occurs. P l d B is a measure of the power of the input signal such that it causes the 3 r d-order non-linearity to reduce gain by 1 dB from the ideal value. It can be expressed as: 20 log 1 + ^ l F , 2 v 4 a i j = -\dB (2.26) Solving for V\ in (2.26) gives p - \ -r-\dB ^ 3 r d Order Intercept Point VoTT (2.27) Another measure for the 3 r d-order non-linearity in a two-port network is the 3 r d-order intercept point. Since the 3 r d-order non-linearity is proportional to the input signal cubed, while the fundamental is increasing only linearly with the input signal, there is a point at which the amplitudes of the fundamental and that of the 3 r d-order intermodulation product meet. The input signal at which this occurs is defined as the input-referred 3 r d -13 order intercept point (IIP3), and is equal to when 7 M 3 equals 1. Solving for V\ using (2.25), the following equation for IIP3 is obtained. IIP3 = J-3 (2.28) Stability A critical requirement of a two-port network is that it must not produce an output with oscillatory behavior. The stability of a two-port network can be determined from its S-parameters and the load and source impedances. The Rollet stability factor, K, is often used for verifying stability [16]. Unconditional stability is satisfied under the following two conditions: K > 1 (2.29) A < 1 (2.30) where „ 1-15',, I2 - | 5 „ I2 +1 A I2 K = — ! — ^ 1 — - (2.31) 2 | Sl2S2i A — S^S22 iS|2iS*2j (2.32) However, K alone is usually good enough to test for stability since most transistors are either unconditionally stable, satisfying (2.29) and (2.30), or conditionally stable with K< 1 and |A| < 1 [14]. 14 Noise in Two-Port Systems In order to design a circuit for low noise, it is useful to determine the condition under which noise can be minimized. This condition is then used in Chapter 3 to relate noise performance to C M O S design parameters. For the analysis of noise in two-port systems, consider a noisy two-port network driven by a noisy source as shown in Fig. 2.5(a). (a) Ys Noiseless Two -Port -O (b) Figure 2.4 Noise modeling, (a) Noisy two-port, (b) Input-referred noise model. The noise factor of a two-port network is defined as F = .SNRIN P. n,output SNR (2.33) OUT n,source where P„,output is the noise power outputted by the two-port and Pn,source is the noise presented at the input of the two-port. A n ideal noiseless two-port network contributes no noise; hence the noise factor is equal to one. Noise figure N F , which is noise factor 15 expressed in decibel, often used to specify noise performance and has an ideally value of OdB. To simplify analysis, the noise of a two-port network can be modeled as a noise voltage and a noise current at the input as shown in Fig. 2.5(b). The signal source is represented by a current source is in parallel with and an admittance Ys to simplify derivation. In this case, the noise factor can be expressed as [13]: i , 2 + F = -in+Ysvn . 2 (2.34) In the derivation of (2.34), the assumption has been made that the noise from the source is not correlated to the noise from the two-port. However, since the exact nature of the source of the two-port is not known, the above assumption about correlation may not be reasonable. Therefore, the following definition for i„ is needed: K =ic+i„ (2.35) where ic is the portion of i„ that is correlated with v„, while /„ is the part of i„ that is uncorrected with v„. The current ic is equal to Ycvn,where Yc is known as the correlation admittance and is given by Yc=— (2.36) 16 Equation (2.34) contains independent noise sources, each of which may be treated as thermal noise produced by an equivalent resistance or conductance: R n ^ ^ ~ (2-37) " 4kTAf Gu=-±— (2.38) " AkTAf Gs=-^— (2.39) 4kTAf where k is Boltzmann's constant (about 1.38 x 10-23 J /K) , T is the absolute temperature in kelvins, and A / i s the noise bandwidth in hertz. Using (2.36) - (2.39), the noise factor can be expressed purely in terms of impedances and admittances: r u G u + [ ( G c + G s Y + ( B c + B s f y R n To optimize for noise in a circuit, the minimum noise factor can be solved for by first taking the derivative of (2.40) with respect to the source conductance and susceptance and setting them to zero. The results for the optimal source conductance and susceptance are stated below. Bs,opl=~Bc (2.41) Gs,opt=jf- + Gc2 (2.42) Substituting (2.41) and (2.42) into (2.40) gives the following results for the minimum noise factor. Fmin=l + 2Rn(Gs,op,+Gc) (2.43) 17 The noise factor can then be expressed in terms of F m i n and the source admittances by The above analysis shows that a source impedance optimized for a minimum noise factor exists, but this source impedance is often not the same as the impedance that achieves maximum power transfer. In (2.44), the ratio R„/Gs appears as a multiplier in front of the second term. For a fixed source conductance, Rn represents the sensitivity of the noise factor as Gs and Bs departs from their optimal values. A large R„ implies a high sensitivity, which obligates the design to stay close to optimal noise matching. A s discussed subsequently, operation at low bias currents is associated with large Rn, mainly due to small device transconductance gm. This is an example o f the difficulty in achieving high performance at low power consumption. (2.44) 18 Chapter 3 CMOS LNA Fundamentals This chapter describes the theories and considerations useful to the implementation of an L N A in the CMOS technology. Noise Sources in CMOS Before beginning an analysis of how to design for low noise, the origins of the noise should be identified and understood. This section discusses several important noise sources in CMOS transistors. Thermal Noise J Cgs —, ~1 + Vgs Cgd [)gmVgS Q >  V ° 1 Figure 3.1 MOSFET small-signal model with thermal noise. Thermal noise is due to the random thermal motion of the carriers in the channel [17]. It is commonly referred to as a white noise source because its power spectral density holds a constant value up to very high frequencies (over 1 THz) [13], Thermal noise can be 19 modeled as a current source across the drain and source of a transistor, as depicted in Fig. 3.1 [12], and has a power spectral density of A / where k is Boltzmann's constant, T is the absolute temperature, y is a bias dependent process parameter, and gdso is the zero-Vps drain-source conductance, and has the following definition: a = -^=- (3.2) SdsO where gm is the transconductance and a is typically in the range between 0 and 1. Equation (3.1) is a general equation that can be used in both the linear and saturation regions of operation simply by using different values for y. For long channel transistors, y = 2/3 in the saturation region, and y = 1 in the linear region. For short channel transistors, hot carrier effects may cause y to be as high as 2 or 3 [18]. Induced Gate Noise Induced gate noise is a high frequency noise source that is caused by the non-quasi static effects influencing the power spectral density of the drain current [17]. Thermal noise in the channel couples through the oxide capacitance to the gate terminal, causing a gate noise current to flow. This noise source is normally not included in standard noise analysis because at low frequencies it is negligible. However, it can dominate at R F 20 frequencies [13]. Induced gate noise, with its circuit model shown in Fig. 3.2(a), has a power spectral density given by / 2 co2C 2 s =4kTS- g s 5g (3.3) dsO where co is the frequency, Cgs is the gate-source capacitance, and d is a process parameter equal to 4/3 in long channel devices [17]. Since the thermal channel noise and induced gate noise stem from the same physical phenomenon, it can be assumed that the relation S = 2y continues to hold for short channel devices [13]. G o S o (a) Va G o Q V W c, S o . + v gs (b) Figure 3.2 Induced gate noise model, (a) Frequency dependent, (b) Frequency independent. The power spectral density of (3.3) is frequency dependent. An equivalent frequency independent noise model is to express the induced gate noise as a voltage in series with the gate capacitance, as shown in Fig. 3.2(b). If a high quality factor Q is assumed, then 21 the models shown in Fig. 3.2(a) and (b) are equivalent, and (3.4) gives the power spectral density. 2 ' ^ - = 4kTdre (3-4) A / Equation (3.4) shows the interesting result that the gate noise is equal to the noise of rg, a resistor placed at the gate, scaled with the constant S. A s discussed previously, gate noise and drain noise are partially correlated due to the fact that they are from the same source. The correlation coefficient c can be expressed as in (3.5): c -2 . 2 (3.5) The theoretical value for c is -0.395/ for long channel devices [17]. Precise measurements of c are difficult to carry out, but the best published measurements reveal that its magnitude stays within a factor of 2 of this theoretical value, even for devices with drawn channel lengths as small as 0.13pm [13]. Distributed Gate Noise The distributed gate resistance of the C M O S transistor also contributes to the noise figure of an L N A . This noise source is modeled as a resistor at the gate and has a noise power spectral density equal to 2 = 4kTR (3.6) Af 22 where Rg is the gate resistance, and is given by In (3.7), Z ^ i s the sheet resistance of the gate material, n is the number of fingers, and the factor 1/3 results from the assumption that each finger is only contacted at only one end. If both ends are contacted, then the factor reduces to 1/12. Intrinsic MOSFET Two-port Noise Parameters In chapter 2, the expression for the noise factor is derived, herein reproduced as (3.8) for convenience. Viewing the M O S F E T as a two-port network, with the gate and source forming a port and the drain and source forming another, it is useful to express F m j n , Rn, Gs>oph and BSt0pt in terms of M O S F E T device parameters [13]: (3.8) (3.9) R„ = TSdo (3.10) g, m (3.11) (3.12) 23 This completes the noise analysis that relates the noise factor with design variables gm, co, Cgs, and gdo- Examining (3.9) - (3.12), Wcan also be related to the four noise parameters, which permits noise consideration in transistor sizing. F i n i n no width dependence (3.13) Rn acl/W (3.14) (3.15) (3.16) Aside from.the classical noise matching ( C N M ) presented above, a number of C M O S L N A design optimization techniques are also well established such as simultaneous noise and input matching (SNIM), power-constrained simultaneous noise and input matching (PCSNIM) , and power-constrained noise optimization (PCNO) . A good overview of these techniques is presented in [5]. Inductive Source Degeneration A n L N A must provide an input matching to a typically 50Q element such as a band-select filter or an antenna. In a fully integrated receiver, L N A output matching is often not required as it is connected to the next on-chip stage in the receive chain. To minimize the number of off-chip components, an L N A should implement the elements required for input matching on chip. One popular approach is to use inductive degeneration. 24 Input Impedance Match Input impedance matching by inductive source degeneration is popular, as matching to the signal source does not introduce additional noise (as in the case of using a shunt input resistor) and does not restrict the value of gm (as in the case of the common-gate configuration). Rs -vw _nmr\_ lout ^7 Figure 3.3 Inductive source degeneration. The circuit shown in Fig. 3.3 has an input impedance equal to Z,.„ (a>) = jco{Ls + Ls)+—!— + J ss zs (3.17) where ideal inductors and capacitors have been assumed. From (3.17), in order to achieve an input impedance match, the following condition must be satisfied: R = ^ n L ^ x L C (3.18) where coj- gmlCgs is the transit frequency of the transistor. Once Ls is chosen based on gain, linearity and input matching requirements, Lg can then be chosen such that Lg, Ls, and Cgs resonate at a>o. In other words, the following condition for Lg must hold: 1 co0 = (3.19) 25 Circuit Transconductance Transconductance is important for gain. To find the transconductance Gm of the circuit shown in Fig. 3.3, first note that the input matching network forms a series R L C tank. The Q of the tank is 1 Qin f \ R + g m s (On c c (3.20) gs gs J where COQ is the resonant frequency defined in (3.19). A t resonance, the voltage across the capacitor is equal to (3.21) and the short circuit output current is equal to Ku, = gmvgs (3.22) where gmis the transconductance of the device. Using (3.20) - (3.22), the overall circuit transconductance can be solved for, and is given by the following equations: g„ R + g m s C C gs gs J (3.23) (3.24) It can be observed from (3.24) that Gm is dependent on C M O S process technology through the transit frequency. 26 Circuit Topologies The key specifications for characterizing the performance o f an integrated L N A are gain, noise, linearity, power consumption, stability, and input matching. These specifications depend on the circuit topology. Topologies such as common-source, common-gate, cascode, and distributed amplifiers have been used for different performance requirements. Compared to the common-source configuration, common-gate is more suitable for wide-band operation, but suffers from relatively high N F [19]. Distributed amplifiers are also capable of wide-band operation, but they suffer from relatively high power consumption [20]. (a) (b) Figure 3.4 Narrow-band topologies, (a) Common-source, (b) Cascode. For narrow-band operation, which is the focus of this work, the common-source and cascode amplifiers are the most suitable. In the common-source configuration, as shown in Fig. 3.4(a), the signal is applied to the gate and the output is taken from the drain. The cascode amplifier is a common-gate amplifier stacked on top of a common-source 27 amplifier, as shown in Fig. 3.4(b). The cascode amplifier consists of an input transistor M i and a cascode transistor M2 with a gate bias voltage VB. Compared to the cascode amplifier, the common-source amplifier suffers from the following shortcomings: 1) Poor isolation between input and output, due to the gate-to-drain parasitic capacitance Cgd, increases the chance of instability significantly. 2) As CMOS technology scales, the MOSFET output resistance r0 decreases, causing noticeable performance degradation. For a common-source amplifier, r0 appears in parallel with the load impedance in small-signal operation, which reduces the output impedance, and lowers the gain of the LNA. A possible solution is to increase the gate length L , which results in a degradation of NF. To alleviate the shortcomings of the common-source topology, the cascode topology is often used. The addition of the cascode device reduces the effect of the Cgd of M\ by presenting a low impedance node at the drain of M\, improving stability. The cascode device also performs impedance transformation so that the output impedance of the amplifier is improved by a factor approximately equal to the intrinsic gain of the cascode device. The load inductor, Ld, is designed to resonate at the operating frequency with the output node capacitance. The input and output tanks can be aligned to provide a narrowband gain, but can also be offset from each other to provide a broader and flatter frequency 28 response. One shortcoming of the cascode topology is that the extra transistor consumes voltage headroom. A s a result, the load should not consume a large voltage headroom. A n inductive load Ld, as opposed to a resistive load, is preferred. A n inductive load has the added benefit o f increasing the gain by resonating with the capacitances associated with the output node and also improving frequency selectivity. Since on-chip inductors have a limited range of values, the capacitor Cm o f Fig . 3.4(b) can be added between the gate and source terminals of M\ so that the values of Lg and Ls are reduced to permit on-chip implementation. Reducing the inductor value also improves Q, which reduces input losses and improves L N A noise figure. Adding Cm has another advantage of providing an extra degree of freedom for choosing the gate width W o f M\, which decouples impedance matching requirements from power consumption. A drawback of adding extra gate-to-source capacitance is the degradation of fy o f M\. However, as discussed subsequently, at operating frequencies well below fr, this trade-off is reasonable. It is also interesting to note that adding Cm does not degrade distortion performance [10]. Performance of the Cascode Amplifier Since the cascode amplifier depicted in Fig. 3.4(a) is a robust topology for narrow-band applications, a detailed study of its gain, noise, and linearity performance is provided in this section. 29 Voltage and Power Gain Assuming the L N A is input matched, the voltage gain and power gain can be expressed as (3.25) and (3.26), respectively [17]. 2R. (3.25) Gr = R. (3.26) where RL is the resistance at the output due to the finite Q of Ld and the finite output resistance of the transistor, and RS is the impedance of the signal source. Noise The noise factor F of the L N A can be expressed as [ 1 ] K, a KcoT j (3.27) F can be expressed in a more intuitive form i f power/impedance matching is assumed at the input (which is often the case). The derivation is done in [21], and the result is repeated below: F « l + ^ a yCOr j gMRs+T + aS(\-\c\2) 5gMRS (3.28) where the portion of the gate noise that is correlated with the drain noise has been neglected. In (3.28), the second term is the contribution from the channel drain noise, and the last term is the contribution from the uncorrected portion of the gate noise. It can be 30 observed that as COT increases (for example with improving technology), the drain noise contribution becomes less significant i f the operating frequency is kept constant. Linearity A purely sinusoidal input signal can produce a distorted output signal with higher-order harmonics due to the nonlinearity of the M O S F E T . These harmonics are mainly induced by higher-order derivatives of the current-voltage {ID-VGS) characteristics. A n important figure of merit for linearity is the 3 r d-order harmonic intercept voltage VIP3 , which is the extrapolated input voltage amplitude at which the 1 s t- and 3 r d-order output amplitudes are equal. The input-referred VIP3 can be expressed as [9]: For linearity, VIP3 is used as a key design parameter and its value is representative of the input signal amplitude that the system can process with reasonably low distortion. It can be obtained by taking the third derivative of the ID-VGS characteristics in respect to Fas-Figure 3.5 gives the VIP3 as a function of gate bias Vcs under different values of drain bias VDS [22]. A sharp peak is observed near the threshold voltage as gate bias is varied, which reflects the so called "sweet spot" of gate biases for high M O S F E T linearity [9]. This is because, during the transition from subthreshold to strong inversion, the increase of gm with Vcs is at its highest, and the 2 n d-order nonlinearity coefficient gm2 reaches its peak, while the 3 r d-order nonlinearity coefficient gmz becomes zero. (3.29) 31 10 t-Q -j I i J l i i i i i I 0.0 0.2 0.4 0.6 0.8 1.0 Vgs (V) Figure 3.5 VIP3 of a 40nm nFET vs. Vos for different VDS (VTH = 0.23V) [22]. A t the system level, the input 3 r d-order intermodulation point (IIP3) of the cascode amplifier can be written as [22] IIP3[dbm] = IIP3in [dBm] - 20 log 1 0 1 (3.30) The first term in (3.30) is the intrinsic IIP3 of the device, and arises from the fact that short channel C M O S transistors exhibit velocity saturation, which gradually linearizes the ideal quadratic relationship of the long channel drain current equation. The second term results from the extra voltage boost across the Cgs due to the series resonance tank, which increases gain but degrades IIP3. This outlines a tradeoff between gain and linearity. 32 Inductor Design Inductors are widely used in RF circuitry to resonate with capacitors and to provide impedance transformations. The design of on-chip inductors is important as the inductor may dominate the frequency selectivity of a RF circuit and consumes a large area. The frequency selectivity of an inductor, characterized by the quality factor Q, is a major design parameter to be optimized. As evident in the following subsections, there is a tradeoff between Q, practical inductance values, and inductor area. Physical Dimensions On-chip inductors can be implemented in different shapes such as squares, octagons, and circles. The layout of a square spiral inductor is depicted in Fig. 3.6. I m 7 •. b-Figure 3.6 The layout of a square spiral inductor. 33 Although it may seem counterintuitive, the Q depends very little on the shape [13]. Instead, it mainly depends on the following parameters: N The number of turns in the spiral D The inductor's inner radius (For a square spiral, D is the shortest distance between the center and the inner side of the spiral) W The width of the wire S The spacing between two wires T The thickness of the wire. Once the metal layer is chosen, T is fixed. Inductor Figures of Merit In this section, three common figures of merit used to describe the characteristics of an inductor are discussed: inductance, quality factor, and self-resonant frequency. A. Inductance The calculation of the inductance of a structure is based upon the self-inductance of a conductor, and the mutual inductance between two conductors [23]. The total inductance of a spiral structure is equal to the sum of all o f the self-inductances of the wire segments and the positive and negative mutual inductances between the wire segments. Two segments have a positive mutual inductance i f the direction of current flow in them is the same and a negative mutual inductance i f the direction of current flow in them opposes each other. Inductance calculation is often complicated and is best performed by a computer simulation program such as ASITIC [24]. 34 B. Quality Factor The quality factor Q is a measure of the amount of energy loss in a circuit component or network and has implications on their frequency selectivity. It is defined as Q = l n Energy _ stored = _ g J L Energy _ dissipated BW where a>o and BW are the resonant frequency and bandwidth, respectively, of the component or network. A n ideal inductor has a Q of infinity. When the loss is significant (caused by for example interconnect resistance, substrate loss, and the skin effect), the peaking of a signal at resonance degrades, which in turn lowers the amplifier gain. The degradation of the frequency selectivity, which results in a large BW may be undesirable as, for example, an L N A should ideally reject out-of-band signals while only amplifying the signal of interest. The quality factor can be improved by adding a patterned ground shield between the inductor and the substrate to reduce capacitive coupling [25]. C. Self-Resonant Frequency The self-resonant frequency is the frequency at which the inductor resonates with its own parasitic capacitance. Below the self-resonant frequency, the inductor behaves like an inductor, at the self-resonant frequency the inductor behaves like a resistor, and above the self-resonant frequency, the inductor behaves like a capacitor. In general, a physically larger inductor tends to have a lower self-resonant frequency [13]. Therefore, the requirement that the inductor operates at most at half its self-resonant frequency places a limit to the size of the inductor. 35 Inductor Modeling Inductors can be modeled with an electromagnetic field solver tool such as A S I T I C . A frequency-dependent n model as shown in Fig. 3.7 can be used for narrow-band applications. R models the resistance of the interconnect, L models the inductance, Cs and Rs respectively model the capacitance and resistance from the inductor metal to the substrate. R L O o CS2 Figure 3.7 Pi-model of inductor. 36 Chapter 4 Designing for Power-Efficient Operation The main objective of this work is to create a design methodology for power-efficient L N A s that can operate at sub-mW power consumption levels. This chapter describes device biasing and sizing, the two fundamental design steps, and presents a step-by-step design procedure. The following discussion is illustrated with a collection of graphs that relate device characteristics such as transconductance and power consumption to circuit design parameters such as gate voltage VQS and gate width W. These graphs offer perspectives to explore the design space particularly useful for selecting the biasing condition for the amplifier, which is the first step of the proposed design procedure. Data from the graphs has been obtained from SpectreRF simulations using a commercial 90nm process design kit. Device Biasing Since circuit performance is strongly tied to device biasing and that proper biasing involves knowledge of device characteristics, it is important to incorporate the knowledge of the device from the beginning of the design cycle to minimize parameter tuning at the end. 37 Terminal / - V Characteristics 30 —•-20/0.1 25 40/0.1 -A-40/0.2 20 < Q 10 + 5 0 0 0.2 0.4 0.6 0.8 V G S (V) Figure 4.1 ID vs. Vcs for a 90nrn nFET (Vos = IV) . Figure 4.1 shows the drain current of a 90nm n M O S F E T as a function of its gate voltage for three transistor sizes, specified in units of micrometers. In this process, the threshold voltage VTH is around 0.35V. A l l results thereafter are based on such an n M O S F E T . It is apparent that deep submicron effects such as velocity saturation occur at Vcs > 0.6V, rendering the ID-VGS curve more linear as opposed to quadratic. This suggests that linearity of a circuit can be improved with a strong gate bias voltage. Also evident from Fig. 4.1 is that ID is proportional to the transistor width W for a given length L. However, according to the square law, transistor sizes 20/0.1 and 40/0.2 should have the same current, which is not the case for this 90nm nFET. Wi th the aid of this graph, the designer can evaluate the extent of the deviation of the 1-V relationship from the classical model. 38 VDS [V] Figure 4.2 ID vs. VDS for a 90nm nFET (W/L = 20 pm/0.1 um, VDS= I V ) . The ability for a transistor to function as a robust current source is crucial to amplifier design. F ig . 4.2 shows the drain current characteristics of a 90nm nFET. For a given Vcs, ID is plotted as a function of VDs- This plot explicitly reveals channel length modulation, evident by the dependency of ID on VDS when the transistor operates in saturation. Channel length modulation manifests itself as non-linearity and gain reduction at the circuit level. If the power consumption of a M O S F E T is indicated by the product of ID and VDS, then a set of constant power contours, which is also depicted in Fig. 4.2, can be plotted in the ID-VDS design space. The plot shows three power levels at 0.1, 0.5, and l m W , with the lower left corner representing a region of lower power consumption. The intersection of power contours and ID-VDS curves provides different combinations of Vcs, VDS, and ID, which in turn facilitates the choice of power-constrained bias selection. 39 Gain and Transconductance 250 i A - A A A A V G S [V] Figure 4.3 /rvs. PGS for a 90nm nFET (P£>,s = IV). The cut-off frequency fr, also called transit frequency, has been widely used as a measure of operating frequency of the device. It is defined as the frequency at which the current gain of the device is equal to unity and is given by fr = 8n 2x(Cgs+Cgd) (4.1) Figure 4.3 illustrates fr as a function of Vcs for different transistor sizes. The curves for transistor sizes 20/0.1 and 40/0.1 overlap, indicating that fr for a fixed L is not a function of W. It can be inferred from (4.1) that the increase in transconductance gm that results from increasing W is offset by the increase in parasitic capacitances. Also evident from Fig. 4.3 is that fr is relatively low at a low Vcs, which is necessary for power-efficient operation, and since a high fr is necessary for a low noise figure, a tradeoff is needed between noise and power. Also, fr is degraded when the device operates in the subthreshold region and when non-minimum L is used. 40 0.4 0.6 VGS [V] Figure 4.4 gm vs. Vcs for a 90nm nFET (VDS= I V ) . The transconductance gm of a device is important to amplifier design as the gain of an amplifier is the product of its transconductance and output resistance. F ig . 4.4 depicts gm as a function of Vcs- gm is obtained by differentiating the D C drain current ID with respect to Vcs- gm increases rapidly with Vcs until it saturates at a Vcs well above VTH-To relate device performance with power consumption, it is useful to define transconductance efficiency gjlo [7]. Fig. 4.5 shows gm/Io as a function of Vcs-41 35 0 H , , - , , 1 0 0.2 0.4 0.6 0.8 1 V G S (V) Figure 4.5 gjlo vs. Vcs for a 90nm nFET (Vos = I V ) . A s can be seen, gjlo is, to the first order, invariant across transistor sizes, indicated by the overlapping of the curves for the Z,=0.1um cases and that gjlo is insensitive to W when the device is turned on. The fact that gm/Io is independent from transistor size is significant as this removes transistor size from the power efficiency optimization equation, leaving Vcs as the primary variable to be considered. This means that circuit design that optimizes transconductance efficiency can be broken down into two sequential steps: first determining bias condition for maximum efficiency, then sizing transistors based on the absolute power requirement. A s shown in Fig . 4.5, to exploit the high gm/Io, it is ideal to bias the transistor in the subthreshold region. However, as previously shown in Fig . 4 . 3 , / r i n this region may be insufficient. A good compromise is to operate in moderate inversion. 42 10 1 4- • —, , r— , 0 0.2 0.4 0.6 0.8 1 VGS[V] Figure 4.6 r0 (=l/gds) vs. VDS for a 90nm nFET (VDS= I V ) . A s mentioned previously, an amplifier's gain is a function of the amplifier's output resistance, which in turn is a function of the device's output resistance r0. r0 can be expressed as \lgds, where gjs is the drain-to-source conductance. If r0 is small, the fact that it appears in parallel with the amplifier's load can significantly reduce the output resistance of the amplifier, hence degrading its gain. For the older technologies, r0 has been high enough that it can be ignored. A s devices move to deep submicron, r0 decreases due to channel length modulation, with a small value in the order of hundreds of ohms for practical choices of VQS- A S can be seen from Fig. 4.6, rQ is a strong function of Vcs, W, and L. Also , a large W, often required for noise matching at the input stage, degrades r0 substantially. This posts a challenge for L N A design and is often overcome by an increase in power consumption. 43 100 0 0.2 0.4 0.6 0.8 1 VGS (V) Figure 4.7 Intrinsic gain gm r0 (= gjgds) vs. VGS for a 90nm nFET (VDS= I V ) . To evaluate the ability of a device to provide gain, the intrinsic gain gjgds is plotted as a function of Vcs in Fig . 4.7. The intrinsic gain represents the theoretical maximum gain achievable by a single transistor. Curves for L-0.1 urn overlap each other. A s shown in Fig. 4.7, gmlgds improves significantly as L increases. However, using non-minimum L is often not a good practice in designing L N A s as it degrades the noise performance. This outlines a tradeoff between gain and noise performance. If gain is compromised to achieve low noise, then multiple gain stages may be required. This adds power consumption into the gain-noise tradeoff. Transistor Sizing The biasing condition, which corresponds to a particular Vcs, determines the drain current density ID/W. Once IQ/W is found, transistor sizing can be performed based on the current density and the drain current allowed by the power specification. Since the objective is to 44 design for low noise, the dependency of noise on W is examined. F ig . 4.8 shows the N F of a cascode and a common-source L N A for different gate widths. Figure 4.8 N F vs. W of cascode and common-source amplifiers. A s can be seen, N F decreases as W increase, which suggests a tradeoff between N F and power consumption. Also , N F is significant for small W, indicating that low noise is fundamentally difficult to achieve for low-power circuits. Figure 4.8 reveals an interesting limitation of conventional power-constrained noise optimization methods proposed to target low-power design. This technique is based on first finding an optimal gate width, then biasing the device with the amount of drain current allowed by the power constraint [13]. In sub-mW designs, the large optimal gate width combined with a small drain current often force the device to be biased in the subthreshold region. When subthreshold operation is inadequate, such as insufficient 45 frequency response, the technique is no longer applicable. A n effective noise optimization technique for the ultra-low-power design space is needed. Step-by-step LNA Design Methodology A step-by step design methodology for power-efficient inductively degenerated common-source or cascode L N A s is proposed. The cascode L N A is depicted in Fig . 4.9. The key difference between the proposed methodology and the conventional ones [1] [5] is that it starts from device biasing instead of device noise characteristics. Beginning the design procedure with device biasing has the advantage that all of gain, noise, linearity, and power are taken into consideration at the start of the design, instead of optimizing for noise while later possibly resorting to compromising other aspects severely. Also , it is important to note that the primary objective of the proposed design methodology is to reduce power consumption. The performance of the L N A , especially noise, is inevitably suboptimal. (a) (b) Figure 4.9 Cascode amplifier, (a) Schematic, (b) Simplified small-signal model for input matching analysis. 46 Stepl: Choosing the bias VGS Since power consumption is the focus of this design methodology, the first step exploits the notion of transconductance efficiency gjlo- A s Vcs increases, gjlo reduces but gm (and also ff) improves. This suggests that there is an optimal value of VGS for a given application. Ideally, VGS should be chosen to be a low value to maximize gmlh, which leads to a power-efficient circuit. But the lower bound of VGS is governed by designing for sufficient gm, which translates proportionally to amplifier gain, and sufficient fT, which provides enough bandwidth for the amplifier operating frequency. VGS can also determine noise performance in three ways. First, since biasing for higher fj leads to lower device N F , VGS should ideally be large. Second, there exists a characteristic current density of 0.15mA/um that yields minimum device N F [6]. Having a lower device N F in turn lowers the overall amplifier N F . Since the characteristic current density corresponds to strong inversion, Vcs should ideally be large. Third, as often seen in sub-m W designs, the width of the input transistor is often made small to satisfy the power requirement. But this small W is often not optimal for noise matching. B y lowering VGS, although reducing/^and deviating from the characteristic current density, W can be made larger to further approach an optimal noise match. Therefore, an optimal Vcs exists and its selection is nontrivial. 47 VQS can also determine linearity performance. The fact that the device exhibits superb VIP3 linearity performance when biased in moderate inversion gives the designer more incentive to choose Vcs from a narrow range that corresponds to moderate inversion. Since gm and fr fall dramatically as Vcs enters the subthreshold values, having Vcs slightly above VTH is often a good choice for R F operations (frequency roughly below 10GHz). For operation at a higher frequency, a higher Vcs is often needed to achieve an fr close to the maximum achievable by the technology. A s can be seen from the above discussion, all o f gain, noise, and linearity are simultaneously affected by biasing, reflecting the interdependent nature of analog circuit design. Step 2: Calculate ID Calculate the drain current ID from the target power consumption (excluding biasing circuits) PDC and target supply voltage VDD, namely ID = PDC / VDD-Step 3: Transistor Sizing The widths of the transistors W can then be readily calculated from the drain current ID obtained in Step 2 with the aid of (4.2), the expression for ID o f a short-channel device, where vsat ~ 10 7cm/s is the saturation velocity and Ec is the critical field (Ec ~ 6 x l 0 4 V / c m for electrons and 24x10 4 V / c m for holes). In L N A design, non-minimum L is rarely chosen as a small L is critical for providing a low N F and gain at RF . 48 ^Vcs VTH) (l + AVDS) (4.2) ox Step 4: Determine gm Transconductance gm can be obtained by taking the partial derivative of ID with respect to VGS for (4.2) or by running a D C simulation. Step 5: Determine Gate Capacitance Cgs Decide whether or not additional gate-to-source capacitance Cm is beneficial. If the circuit is designed to operate at high frequency, Cgs should be minimized to improve fT. If the circuit is designed for operation at relatively low frequency, the lower resonance frequency of the circuit requires larger combined inductance and capacitance. Since large on-chip inductors cost significant area and cannot be made with high Q in current standard technologies, it is easier to add capacitance. Step 6: Impedance matching Inductive degeneration is used for input matching. Fig . 4.9(b) is a simplified small-signal model showing the components for matching, where Cgs\ denotes the gate-source capacitance of M\. The input impedance of the L N A Zin can be expressed as 1 + jco(Ls +L ) + (4.3) jcoC C 49 where gm is the small-signal transconductance, Cgs = Cm \\ Cgs\ is the effective capacitance between the gate and source and co is the operating frequency. Since Zin is to be matched 50 to the source impedance, which is typically 50Q. in an R F system, the real and imagery parts of Z,„ can be expressed as follows: = RS= 5 0 Q (4.4) 3m{ZJ 1 + cu(Ls+Lg) = 0 cuC (4.5) Examining (4.4), given gm is determined by Vcs and W, Ls and Cgs can be designed. It is better to design Ls first as the gain and linearity of the amplifier is dependent on it. A larger Ls adds more source degeneration and reduces the gain but improves the linearity [10]. Another practical reason is that inductors that are suitable for on-chip implementation have a smaller range of values. Since gm is known from Step 4, once Ls is found, Cgs can be readily calculated. Then Lg can be calculated from (4.5). Step 7: Designing the Load Ld and CUme Ld, Ctune, and the parasitic capacitance at the drain of the cascode device should resonate at the frequency of operation. Ctune is often implemented using a bank of capacitors to provide variable capacitance for channel tuning and calibration for process variation. Ld is often chosen to be as large as possible for on-chip implementation as a large Ld improves gain. Step 7 concludes the design methodology. The performance and yield of the design may be further optimized by using C A D tools such as a design optimizer or a yield optimizer. 51 Chapter 5 Design of a Power-efficient LNA and Simulation Results To demonstrate the application of the design methodology described in Chapter 4, an L N A is designed and simulated in a commercial 90nm C M O S technology to operate at the 2 .4GHz band. This chapter presents the design rationale and the corresponding simulation results. Circuit Topology and Impedance Matching To alleviate the shortcomings of the common-source topology as discussed in Chapter 3, the cascode topology as discussed previously is used, hereby reproduced as Fig. 5.1 for convenience. C •o RF, lime out Figure 5.1 Schematic of a cascode amplifier. 52 The cascode amplifier consists of an input transistor M\ and a cascode transistor M2 with a gate bias voltage VB. Since the cascode amplifier consists of two stacked transistors, the load should not consume a large voltage headroom. A n inductive load Ld, as opposed to a resistive load, is preferred. A n inductive load has the added benefit o f boosting the gain by resonating with the capacitances associated with the output node. Inductive degeneration is used for input matching. Power-Efficient LNA Design The biasing of the transistors has strong implications on L N A performance such as gain, noise, and linearity. When a short-channel M O S F E T is biased in saturation, ID can be expressed by (4.2), herein reproduced as (5.1) below: (Vr< -Vr„)2 ID-WvsatC0X K <* T"> d + WDS) (5.1) I ' C S TH ) + where vsat ~ 10 7cm/s is the saturation velocity and Ec is the critical field (Ec ~ 6x10 4 V / c m for electrons and 24x10 4 V / c m for holes). A s shown by (5.1), when L is kept to its minimum, Vcs and W are key design parameters that directly link to power consumption. The drain current of a 90nm cascode L N A is plotted in Fig. 5.2 to quantify the sensitivity of power consumption to Vcs and (supply voltage = I V ) . F ig . 5.2(a) depicts the drain current of a cascode L N A with both transistors sized to 25p.m. The threshold voltage of the technology used is around 0.4V. In the typical analog design space for this technology (i.e., Vcs in the range of 0.4V to 0.7V), power consumption increases 6.4x whereas, in Fig. 5.2(b) a change of W from lOum to 40um (Vcs held constant at 0.4V) leads to a power increase of 4.2x. It is interesting to note that, given a drain-to-source voltage, the 53 performance of the M O S F E T is strongly tied to the drain current density IrJW, which is mainly controlled by VGS- The following subsections describe the sensitivity of gain, noise, and linearity to Vcs and W. (a) (b) Figure 5.2 ID o f a cascode L N A . (a) ID vs. VCS (^,=0^=25 um), (b) ID vs. W(VGS=0AV). Gain In conventional R F and microwave design approaches [26], [27], primarily developed for high-speed bipolar circuits, fr is an indispensable design parameter. For C M O S technologies, there is a characteristic current density associated with operating in strong inversion that yields an optimal fr [6]. For the 90nm C M O S technology used in this work, VGS ~ 0.7V is required to reach the optimal value. 54 18 0.3 0.4 0.5 0.6 0.7 10 15 20 25 30 35 40 VGS [V] W[[im] (a) (b) Figure 5.3 Voltage gain of a cascode L N A . (a) A v vs. VGS, (b) A v . vs. W. Figure 5.3(a) shows the simulated voltage gain Av of the cascode amplifier depicted in Fig. 5.1 at 2.4GHz. While sweeping VGS, VB is also modified such that the ratio VGSJVGSI, hence gm\/gm2, is relatively constant. It may seem counterintuitive that Av only increases slightly as VGS changes from 0.4V to 0.7V, which corresponds to roughly doubling/rand gm\. The reason lies in the fact that the operating frequency is sufficiently low compared to the maximum fr o f the technology and therefore the benefits of increasing/^ are not as pronounced. This suggests that the use of fr as a design tool may have less influence in modern R F design. In addition, as VGS increases, ID also increases, which reduces the overall output impedance of the cascode structure. Since gain is the product of output impedance and transconductance, the reduction of output impedance partially counteracts the effects of increasing gm\ on the overall gain. For comparison, F ig . 5.3(b) shows moderate increase in A v as the widths of both transistors are increased. 55 Noise / [GHz] (a) 1 1.5 2 2.5 3 3.5 / [GHz] (b) Figure 5.4 N F of a cascode L N A . (a) N F vs. Vcs, and (b) N F vs. W . A s discussed in Chapter 4, there is currently no robust noise optimization technique specifically developed for the sub-mW regime. In the absence of such a technique, an alternative design approach is to use the knowledge gained in Chapter 4 to establish an initial biasing point and determine the sensitivity of N F with respect to Vcs and W. For this purpose, a 90nm cascode L N A is simulated. Fig. 5.4(a) shows N F as Vcs of M\ is 56 swept from 0.3V to 0.7V (W = 25pm). VB is adjusted accordingly as mentioned earlier. A s can be seen from Fig . 5.4(a), N F is inadequate when operating in the subthreshold region (VGS = 0.3V). For a change of Vcs from 0.4V to 0.7V, N F is reduced by 0.6dB at the expense of a 6.4x increase in the power consumption. Fig. 5.4(b) shows N F as the width of both transistors are changed simultaneously from 10pm to 40pm (VGS = 0.4V), which results in a 3.4dB N F improvement at the expense of 4.2x the power consumption. This suggests that increasing Wis a more effective method for reducing N F . It is also instructive to use the SpectreRF simulator to obtain a noise summary that shows the noise contribution of components. F ig . 5.5 depicts the R F signal source and the L N A with the inductor models explicitly shown. The noise contributions from inductor parasitic resistances are significant, suggesting high-C? inductors are highly desirable. -Top 5 Noise Contributors : 1 (9.2%) 2 (8.6%) 3 (8.2%) 4 (7.3%) 5 (5.5%) 'tune o (52%) 5 R Figure 5.5 Noise contribution of the signal source and L N A components. 57 Linearity A s discussed in Chapter 2, there are two types of linearity performance for an L N A , which are characterized by the input-referred 3 r d-order intermodulation intercept point (IIP3) and the input-referred l d B voltage compression point (P ldB) . 8 -4 -I , , , , , 1 0.4 0.45 0.5 0.55 0.6 0.65 0.7 V G S M Figure 5.6 IIP3 vs. VGS of the cascode L N A . Figure 5.7 PldB vs. VGS of the cascode L N A . Figure 5.6 and Fig. 5.7, respectively, show the IIP3 and P l d B of the cascode L N A with 25pm transistors. Since linearity is a function of gain, Fig. 5.6 and Fig. 5.7 also show the 58 linearity of the L N A with gate widths adjusted to maintain a constant gain across Vcs- VB is adjusted accordingly as mentioned earlier. Two observations can be made. First, IIP3 can be exploited in amplifier design. Second, the IIP3 and P l d B of the L N A degrade as Vcs increases. This is an interesting observation since previous analysis and measurements reveal that the M O S F E T IIP3 performance improves as Vcs increases [9], [10]. Lastly, it has been reported that linearity of a M O S F E T in moderate inversion is not well studied [9] and that the IIP3 peaking for a C M O S short-channel transistor may not be easily applicable for R F L N A designs [10]. This is due to the fact that source degeneration tends to improve the overall linearity but dampen the peak. Simulation Results The cascode L N A has been simulated using the BSIM3v3 model provided for the ST Microelectronics 90nm C M O S process. On-chip inductors are modeled and designed using the A S I T I C electromagnetic field solver. Fig. 5.8 depicts the 7i-model for a 5nH spiral inductor used as Lg and Ld in Fig. 5.1, implemented using the thick metal layer of a 90nm technology. This inductor has a Q o f 7.3. To further improve Q, two metal layers can be used to reduce the series resistance of the inductor. Ls is modeled similarly. of the L N A is indeed the highest in moderate inversion, suggesting that the VIP3 peak O 4.96nH 4.59C2 o Figure 5.8 7t-model of a 5nH spiral inductor. 59 In this design, Cm and Ctune are assumed to be implemented using h igh-g metal-insulator-metal ( M I M ) capacitors. The widths of both transistors are sized equally. Vcs is chosen to be 0.4V, slightly above the threshold voltage to exploit the high gjlp in moderate inversion. Table 1 is a summary of component values. T A B L E 1 S U M M A R Y O F L N A C O M P O N E N T V A L U E S VDD (V) 1 Ls = Ld (nH) 5 Ls (nH) 2 C„( fF) 480 Ctune (fF) 720 Wx/Lx (um) 25/0.1 W2/L2 (um) 25/0.1 Vin,DC(V) 0.4 VB(V) 0.9 Figure 5.9 shows the voltage gain Av and N F of the L N A . The voltage gain is 22.7dB in the 2 .4GHz band with a 3dB bandwidth of around 300MHz. / [GHz] Figure 5.9 Gain and N F of the proposed L N A . 60 As.depicted in Fig . 5.10, an S\\ o f -14 .7dB provides a good input impedance matching to 50Q. N F is 2.8dB which is acceptable for short-range applications. IIP3 and P l d B are +5.14dBm and - l O d B m , respectively. Table 2 summarizes the performance of the L N A . The circuit consumes 943 u W from a I V supply. o -25 H —-, •——i : — i : 1 1.5 2 2.5 3 3.5 / [ G H z ] Figure 5.10 Si i o f the proposed L N A . T A B L E 2 S U M M A R Y O F L N A P E R F O R M A N C E Gain (dB) 22.7 . N F (dB) 2.8 Sn (dB) -14.7 IIP3 (dBm) 5.14 P l d B (dBm) -10 i>Dc(uW) 943 / c ( G H z ) 2.4 Gate L (pm) 0.09 61 Performance Summary Table 3 shows a performance comparison between the proposed L N A and low-power C M O S L N A s from recent literature. The performance comparison is further illustrated on the gain-power design space as in Fig. 5.11. T A B L E 3 C O M P A R I S O N O F C M O S L O W - P O W E R L N A S This work [3]'- # [ 2 8 f [if [29]" [30]* [31] J ' # [32 f [33 f Gain (dB) 22.7 13.6 13* 12 9.2* 11.5 10.1 12.8 19 N F (dB) 2.8 4.6 3.6 1.8 3.6 3.4 2.9 1.4 2.8 5 „ ( d B ) -14.7 - 5 <-10 -18 -10 -14 -10.1 - -14.5 IIP3 (dBm) 5.14 7.2 -10 -3 -7.25 - +4 +13.3 -PldB (dBm) -10 -0.2 - — -15.8 -8 - 7 - -PDC (mW) 0.94 0.26 0.72 0.9 1 4 11.7 14.4 15 /c (GHz) 2.4 1 0-0.96 2.4 5.5 5.7 2.4 2.0 2.4 Gate L (um) 0.09 0.18 0,13 0.18 0.09 0.18 0.18 0.18 0.18 * Power gain, 1 Subthreshold design, 2 U W B design, 3 Dual-banc design, # Measurement 30 i 25-DO 20-T3, C 15-' r o O 10-5 -0 -< 1mW > 1 mW 0 Best T h i - Th 1 1 l i b I 1 o 9 [33] , '( '5 r o o i i n c [-3] ' 0 5 [32] , ' 0 6 # J?]' ' 0 5 [311. ' 0 5 # [ZO j , uo •T30], ' B )6 • [29 ] , ' 04 Worse 1 2 3 4 5 Noise Figure (dB) Figure 5.11 Graphical illustration comparing recently published L N A s and this work. 62 A direct comparison of L N A s listed in Table 3 is a challenge as most L N A s have specifications that are tailored to work with the specific radio architecture and application. A n attempt is made to compare the proposed L N A to comparable low-power, relatively narrow-band L N A s . There are several aspects to note in this comparison. First, the proposed work is based on simulation results and the others are based on measurements. When a chip is fabricated, its performance tends to degrade due to unaccounted parasitics and the assumptions made during circuit design. Second, not all the L N A s compared operate at the same frequency. Typically, more power is required to provide gain at a higher frequency, for example, the L N A s in [3] and [28] have lower power consumption. Third, all L N A s use the cascode topology or its variants, except for the ones in [3] and [28]. The L N A in [3] uses a common-source topology, which exploits the relatively high M O S F E T output resistance in 0.18um C M O S . This L N A design may have difficulty delivering gain when ported to the 90nm technology. Also , the fact that it is targeted for lower frequency operation enables a subthreshold design, giving it an advantage in transconductance efficiency over other L N A s . The L N A in [28] uses the common-gate topology as it needs to provide a large bandwidth for the targeted ultra-wideband application. Since this design and the dual-band L N A in [31] need to cover a greater bandwidth, a higher power consumption and a lower gain is inevitable. Fourth, the L N A in [32] employs an extra transistor for post-linearization, which results in larger power consumption but the best linearity in the comparison. From Fig . 5.11, it can be seen that the L N A designed based on the proposed approach demonstrates a competitive gain and noise figure amongst low-power L N A s . 63 Chapter 6 Conclusions and Future Works Conclusion In this thesis, a design methodology for low-power C M O S R F inductively degenerated L N A s has been introduced. The design approach presented in this dissertation differs from existing techniques in that it begins with determining how device biasing affects gain, noise, linearity, and power consumption of the amplifier to ensure a well-rounded design. Design plots have been used to help the circuit designer in understanding the fundamental characteristics of the M O S F E T in preparation to applying the design methodology. To demonstrate the technique, a fully integrated R F C M O S L N A is design and simulated. This 2 .4GHz 90nm cascode L N A achieves a voltage gain of 22.7dB, N F of 2.8dB, IIP3 of+5.14dBm, and P l d B o f - l O d B m , while consuming 943uW from a I V supply. This study has revealed that for designs that operate well below fr, a balanced design can be achieved by biasing the device just above the threshold voltage to exploit the high gm/Io- This achieves low power consumption while avoiding the performance degradation associated with the subthreshold region. This observation is significant as many R F circuits for applications operating in the low-GHz range implemented in a modern C M O S technology can be designed based on the proposed technique. 64 Future Work Although this work has provided solutions to the challenges of power-efficient design, it has also uncovered many interesting topics worthy of further investigation. They often require a deeper understanding and characterization of the device and are listed as follows: 1) Conventional power-constrained noise optimization methods proposed to target low-power design have their limits. The techniques is based on first finding an optimal gate width, then biasing the device with the amount of drain current allowed by the power constraint. In sub-mW designs, the large optimal gate width combined with a small drain current often force the device to be biased in the subthreshold region. When subthreshold operation is inadequate, such as insufficient frequency response, the technique is no longer applicable. A n effective noise optimization technique for the ultra-low-power design space is needed. 2) The proposed design methodology has been devised with a focus of maximizing transconductance efficiency, which translates to power-efficient amplifier designs. Although current low-power applications tend to have a more relaxed noise requirement, it is worthwhile to incorporate noise formulation into the transconductance efficiency framework so that the establishment of biasing condition can include a quantitative noise analysis. 65 3) The effectiveness of the proposed design methodology has thus far been verified with SpectreRF simulations. Sil icon implementation is the next logical step to confirm simulation results. 4) There is only a narrow range of biasing conditions that can exploit the high M O S F E T linearity performance in moderate inversion. This narrow range demands for accurate biasing circuits; therefore, conventional L N A designs have not exploited this effect. Biasing circuits with improved accuracy may make the use of the high M O S F E T linearity performance possible and reliable. 5) On-chip inductors are area intensive and do not scale well with technology. They are of low quality factor and contribute substantially to the noise figure of the amplifier. Improved on-chip implementation is needed. 6) Process variation is expected to increase as C M O S technology scales. Advanced layout techniques and robust calibration schemes for mitigating process variation is needed. There is much work to be done in the area of low power, deep submicron C M O S L N A design. The landscape of analog circuit design is rapidly changing as technology scales to quantum levels, opening the designer to a new world of challenges and possibilities. 66 References [I] D.Shaeffer and T. Lee, " A 1.5V, 1.5 G H z C M O S low noise amplifier," IEEE J. Solid State Circuits, vol . 32, M a y 1997. [2] T . - K . Nguyen, S.-K. Han, and S.-G. Lee, "Ultra-low-power 2 .4GHz image-rejection low-noise amplifier," Electronics Letters, vol . 41, no. 15, July 2005. [3] D . B . G . Perumana, S. Chakraborty, C . - H . Lee, and J. Laskar, " A fully monolithic 260-uW, 1-GHz subthreshold low noise amplifier," IEEE Microwave and Wireless Components Letters, vol . 15, no. 6, Jun 2005. [4] W . Kluge, F. Poegel, H . Roller, M . Lange, T. Ferchland, L . Dathe, and D . Eggert, " A fully integrated 2.4-GHz I E E E 802.15.4-compliant transceiver for ZigBee™ applications," IEEE J. Solid-State Circuits, vol . 41, no. 12, Dec 2006. [5] T . - K . Nguyen, C. H . K i m , G . J. Ihm, M . S. Yang, and S.-G. Lee, " C M O S Low-noise amplifier design optimization techniques," IEEE Trans, on Microwave Theory and Techniques, vol . 52, no. 5, May 2004. [6] T. O. Dickson, K . Yau , T. Chalvatzis, A . M . Mangan, E . Laskin, R. Beerkens, P. Westergaard, M . Tazlauanu, M - T Yang, and S. P. Voinigescu, "The invariance of characteristic current densities in nanoscale M O S F E T s and its impact on algorithmic design methodologies and design porting of Si(Ge) ( B i ) C M O S high-speed building blocks," IEEE J. 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