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Design of sub-mW RF CMOS low-noise amplifiers Ho, Derek 2007

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Design o f Sub-mW R F C M O S Low-Noise Amplifiers by DEREK HO B . A . Sc., The University o f British Columbia, 2005  A THESIS SUBMITTED IN P A R T I A L F U L F I L L M E N T OF THE REQUIREMENTS FOR THE D E G R E E OF M A S T E R OF APPLIED  SCIENCE  in  T H E F A C U L T Y OF G R A D U A T E STUDIES  (Electrical and Computer Engineering)  T H E UNIVERSITY OF BRITISH C O L U M B I A March 2007 © Derek Ho, 2007  Abstract The quest for low power, low cost, and highly integrated transceivers has gained substantial momentum due to the explosion o f wireless applications such as personal area networks and wireless sensor networks. This dissertation presents a comprehensive study and a design methodology for power-efficient C M O S radio-frequency (RF) low-noise amplifiers ( L N A s ) .  To demonstrate the design methodology, a sub-mW fully integrated narrow-band source degenerated cascode R F L N A is designed and simulated in a standard 90nm C M O S process to operate in the 2.4GHz band. The L N A achieves a voltage gain o f 22.7dB, noise figure (NF) o f 2.8dB, 3 -order intercept point (IIP3) o f +5.14dBm, and l d B rd  compression point ( P l d B ) o f - 1 0 d B m , while consuming 943 o W from a I V supply.  The main contributions o f this work include: i) the introduction o f a design methodology for power-efficient sub-mW source degenerated L N A s ; ii) the collection o f design graphs to facilitate the  exploration o f tradeoffs  between  L N A performance  and  power  consumption; and iii) the use o f an alternative analysis to find the dependency o f gain, noise, and linearity on biasing conditions.  ii  Table of Contents ABSTRACT  ii  TABLE OF CONTENTS  iii  LIST O F T A B L E S  v  LIST O F FIGURES  vi  ACKNOWLEDGMENTS  vii  C H A P T E R 1. I N T R O D U C T I O N  1  MOTIVATION  1  RESEARCH OBJECTIVE  2  THESIS ORGANIZATION  3  C H A P T E R 2. B A C K G R O U N D  5  TWO-PORT NETWORKS  5  IMPEDANCE MATCHING  6  SCATTERING PARAMETERS  7  LINEARITY  9  Harmonic Distortion Intermodulation 1 dB Compression Point 3 Order Intercept Point  9 11 13 13  ,  rd  STABILITY  14  NOISE IN TWO-PORT SYSTEMS  15  C H A P T E R 3. C M O S L N A F U N D A M E N T A L S  19  NOISE SOURCES IN CMOS  19  Thermal Noise Induced Gate Noise Distributed Gate Noise  19 20 22  INTRINSIC MOSFET TWO-PORT NOISE PARAMETERS  23  INDUCTIVE SOURCE DEGENERATION  24  Input Impedance Match Circuit Transconductance  ;  25 26  CIRCUIT TOPOLOGIES  27  PERFORMANCE OF THE CASCODE AMPLIFIER  29  Voltage and Power Gain Noise Linearity .'  30 30 31  INDUCTOR DESIGN  33  Physical Dimensions Inductor Figures of Merit Inductor Modeling  33 34 36  C H A P T E R 4. D E S I G N I N G F O R P O W E R - E F F I C I E N T O P E R A T I O N DEVICE BIASING  37 37  Terminal I-V Characteristics Gain and Transconductance  38 40  TRANSISTOR SIZING  44  STEP-BY-STEP LNA DESIGN METHODOLOGY  46  iii  CHAPTER 5. DESIGN OF A POWER-EFFICIENT LNA AND SIMULATION RESULTS  52  CIRCUIT TOPOLOGY AND IMPEDANCE MATCHING  52  POWER-EFFICIENT LNA DESIGN  53  Gain Noise Linearity  54 56 58  SIMULATION RESULTS  59  PERFORMANCE SUMMARY  62  CHAPTER 6. CONCLUSIONS AND FUTURE WORKS  64  CONCLUSION  64  FUTURE WORK  65  REFERENCES  67  iv  List of Tables Table 1 Summary of L N A component values Table 2 Summary of L N A performance Table 3 Comparison of C M O S low-power LNAs  v  59 61 62  List of Figures Chapter 2 Figure Figure Figure Figure Figure  2.1 2.2 2.3 2.5 2.4  Two-port network diagram A system with a source driving a load.. S parameter representation of a two-port network Frequency locations of distortion terms Noise modeling, (a) Noisy two-port, (b) Input-referred noise model  5 6 7 12 15  M O S F E T small-signal model with thermal noise Induced gate noise model, (a) Frequency dependent, (b) Frequency independent.... Inductive source degeneration Narrow-band topologies, (a) Common-source, (b) Cascode VEP3 of a 40nm nFET vs. V for different V (V = 0.23V) [22] The layout of a square spiral inductor Pi-model of inductor  19 21 25 27 32 33 36  I vs. V for a 90nm nFET (V = IV) I vs. V for a 90nm nFET (W/L = 20 (im/O.lirm, V = IV)...., f vs. V for a 90nm nFET (V = IV) ' g vs. V for a 90nm nFET (V = IV) g II vs. V for a 90nm nFET (V = IV). r (=l/g ) vs. V for a 90nm nFET (V = I V ) . . Intrinsic gain g r (= gjgds) vs. V for a 90nm nFET (V = IV) N F vs. Woi cascode and common-source amplifiers. ; Cascode amplifier, (a) Schematic, (b) Simplified small-signal model for input matching analysis  38 39 40 41 42 43 44 45  Schematic of a cascode amplifier I of a cascode L N A . (a) I vs. V (1^=^=2 5 urn), (b) I vs. W (F =0.4V).' Voltage gain of a cascode L N A . (a) A vs. V , (b) A . vs. W. N F of a cascode L N A . (a) N F vs. V , and (b) N F vs. W Noise contribution of the signal source and L N A components IIP3 vs. V of the cascode L N A '. PldB vs. V of the cascode L N A 7t-model of a 5nil spiral inductor '. Gain and N F of the proposed L N A S\ \ of the proposed L N A Graphical illustration comparing recently published L N A s and this work  52 54 55 56 57 58 58 59 60 61 62  Chapter 3 Figure Figure Figure Figure Figure Figure Figure  3.1 3.2 3.3 3.4 3.5 3.6 3.7  GS  DS  TH  Chapter 4 Figure Figure Figure Figure Figure Figure Figure Figure Figure  4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9  D  GS  D  DS  DS  T  DS  GS  m  m  0  os  GS  D  DS  GS  DS  ds  DS  m  DS  0  GS  DS  46  Chapter 5 Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure  5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11  D  D  GS  D  v  GS  GS  GS  vi  GS  v  GS  Acknowledgments This work could not have been completed without the help o f many people and I would 1  like to take this opportunity to express my appreciation to them.  I would like to start by thanking m y graduate advisor, Professor Shahriar Mirabbasi for his guidance and for always making decisions based on what is best for m y education. This, has led to not only a productive but also an enjoyable experience. I would like to thank Dr. Andre Ivanov for supervising m y undergraduate research in the System-onChip lab, where I cultivated m y early interest i n V L S I c i r c u i t s . I would also like to thank Professor Resve Saleh and Professor Steve W i l t o n for reading this dissertation and serving as committee: members i n m y thesis defense.  I could not imagine where I would be without the help o f Roberto Rosales and K a r i m Allidina. They deserve special recognition for having the patience to explain to me any question that I threw at them.  I probably would have gone insane without the companions at the S O C lab to listen to all m y problems and give me advice (even though some advice was insane too). Y o u know who you are: Usman Ahmed, Shirley A u , Nathalie Chan, M e l o d y Chang, Scott Chin,  This research is funded by Natural Science and Engineering Research Council o f Canada ( N S E R C ) . C A D tools are provided by Canadian Microelectronics Corporation ( C M C ) Microsystems. 1  vii  David Chiu, R o d Foist, A m i t Kedia, Sohaib Majzoub, Xiongfei Meng, Dipanjan Sengupta, and Howard Yang.  I am sure I would be a different person without the influence o f W i l s o n Fung and Jennifer L i . Being friends  for more than a decade, W i l s o n and I grew up together. His  commitment to doing good work has become m y role model. Having a technical discussion with him is nothing less than inspiring. Jennifer and I have gone through both ups and downs. Her love is indispensable to m y general well-being.  Last but not least, I would like to thank m y sister for putting up with me for as long as she has existed. I'd also like to express m y deepest gratitude to m y parents for their unconditional love. They have made tremendous sacrifices to give me the best upbringing a child can possibly receive.  Derek H o Vancouver, B C  viii  Chapter 1 Introduction  Motivation The design of low-power wireless transceivers has gained substantial significance due to the explosion of wireless applications such as personal area networks and wireless sensor networks. These applications demand for small, low-cost, and low-power wireless transceivers which require a high level of integration with a minimal amount of off-chip components. The first active block in most wireless receivers is the low-noise amplifier (LNA). The LNA needs to amplify the signal without adding a large amount of noise and distortion while consuming minimal power.  RF circuits have traditionally been implemented in compound semiconductor technologies such as Gallium Arsenide (GaAs) or Silicon Germanium (SiGe). Since the CMOS technology is employed for the digital transceiver back-end, it is attractive to implement the RF front-end also in CMOS, with the goal to integrate all parts of the receiver on a single chip to reduce cost and time to market. In the recent past, numerous CMOS RF circuits have been presented and have demonstrated good performance [l]-[4].  1  The design o f a power-efficient L N A in C M O S is particularly challenging due to a number o f reasons: 1) The performance such as gain and bandwidth o f a metal-oxide-semiconductor field-effect transistor ( M O S F E T ) is poor when biased at the small drain current necessary for power-efficient operation. 2) The choice o f circuit topologies is limited due to the reduction o f M O S F E T output resistance and supply voltage as C M O S technology scales. 3) On-chip passive elements have poor quality factor, limited range o f values, and large area consumption. 4) Conventional power-constrained noise optimization techniques [5] often lead to subthreshold operation when power consumption is restricted to l m W or below.  Research Objective The objective o f this thesis is to develop a narrow-band R F C M O S L N A design technique suitable for the prevalent inductively degenerated L N A architecture. This work aims to achieve the following targets:  1) Devise a methodology that leads to a power-efficient L N A design. 2) Explore the tradeoffs between L N A performance and power consumption. 3) Find a circuit topology capable o f low-voltage low-power operation. 4) Demonstrate a high performance design with on-chip \ow-Q passive components i n a deep submicron technology.  2  In devising the design methodology, a major goal is to review, coordinate, and exploit several device-level properties proposed in the recent literature:  1) Device transit frequency fr and unity power gain frequency fMAX depend strongly on drain current density, which is mainly controlled by the gate-source voltage [6]. 2) The M O S F E T has a large transconductance per unit drain current g /Io in weak m  inversion and progressively degrades towards strong inversion [7]. 3) The M O S F E T minimum noise figure improves as gate length decreases [6], [8]. 4)  MOSFET  linearity improves as drain current density increases  with a  significant peaking i n the moderate inversion region [9], [10].  A s part o f the overall objective, a 2 . 4 G H z L N A is designed and simulated in a 90nm CMOS  technology with sub-mW power consumption using the proposed  design  methodology. The simulation results demonstrate the applicability o f the methodology to the design o f narrow-band R F front-ends needed for many low-power applications.  Thesis Organization In this thesis, an L N A design methodology is devised and. documented. Chapter 2 presents background information about two-port networks that is fundamental to the design o f L N A s and other R F circuits. Chapter 3 focuses on the design o f C M O S L N A s . Chapter 4 discusses the design o f transistor biasing conditions for power-efficient amplifiers. This chapter concludes with a step-by-step design procedure. Chapter 5  3  details the application o f the proposed methodology to the design o f a sub-mW L N A . Simulation results are presented at the end o f this chapter. Finally, Chapter 6 draws some conclusions and suggests future works.  4  Chapter 2 Background  To simplify the design and analysis o f analog circuits, it is useful to abstract circuit blocks into two-port networks. This chapter begins with a discussion o f parameters that are used to characterize two-port networks. Then, performance measures o f the two-port network such as gain, noise, linearity, and stability that are important in the design o f L N A s are presented.  Two-Port Networks A two-port network is shown i n F i g . 2.1. There are usually two quantities, namely, voltage and current  associated to each port. A t low frequencies,  two common  representations that characterizes the network are the impedance matrix (Z parameters) and the admittance matrix ( Y parameters) [11], [12].  12  O  Port 1  +  Vl  Two-Port Network  +  O  Port 2 O  Figure 2.1  Two-port network diagram.  5  The impedance and admittance matrices are defined by (2.1) and (2.2), respectively. ~z  7  7  7  u  (2.1)  _ 21  z,  'l  X  ^1  J2_  X  Zy  2 2  Y  _  (2.2)  _ 2. V  22J  I  Z parameters and Y parameters are particularly useful at low frequencies because they can be readily measured by applying either a test current or voltage to the input port and connecting the output port either as a short or open circuit. For example, from (2.1) vi can be expressed as v, =Z i +Z i . u l  (2.3)  u 2  If the output port is open circuited, ii becomes zero, and Z\ \ can be calculated to be  Impedance Matching A system with a signal source driving a load is depicted in Fig. 2.2 where Zs and Zi are the source and load impedances, respectively.  Zs — Rs + jXs V  s  Z = R +JX L  L  (o^)  Source  Load  Figure 2.2 A system with a source driving a load.  6  L  There are two types o f impedance matching [13]. The first type o f impedance matching concerns with minimizing signal reflection from the load back to the source. When Zs = ZL, there is no reflection. This is important for the design o f the receiver front-end as the frequency response o f the antenna filter that precedes the L N A deviates from its normal operation i f there are reflections from the L N A back to the filter. The second type of matching concerns with maximum power transfer from the source to the load. Hence it is often referred to as power matching. Power matching occurs when the load impedance is the complex conjugate o f the source impedance. When the source and load impedances are real as in a typical 50Q R F system, the conditions for power matching and impedance matching are equal.  Scattering Parameters A t R F and microwave frequencies, Z and Y parameters become very difficult to measure due to the need for broadband short and open circuits [14], A s a result, a different representation o f the two-port network is needed at these frequencies. A popular representation is the scattering, or S, parameters. Instead o f relying on ports being open and short circuited, S parameters have the advantage that they can be measured by matching the source and load impedances to a reference impedance Z . A n S parameter 0  representation o f a two-port network is shown in Fig. 2.3.  Figure 2.3  S parameter representation o f a two-port network. 7  The notion of the S parameter representation is to measure the normalized incident voltage wave a, entering the system at port i, as well as the corresponding reflected voltage wave 6, leaving port i. The normalized incident and reflected voltage waves a, and bi are related to the terminal voltage and current at port i by the following equations: a, =  v,I  +ZJ,  l  - oi  O I  V  (2.4)  i  Z  (2.5)  where Z is assumed real as it is usually equal to 50£X The network of Fig. 2.3 can be 0  express, in matrix form, as (2.6).  Vi A.  r.s\.  5  _5 i  5 _  12  22  2  a, a  K.:\\„.~\  (2.6)  2  where S\\, Sn, 521, 522 are the scattering parameters. By expanding the scattering matrix, the following equations can be written: 5,, =•  (2.7) a,=0  5n — -\  (2.8)  l  a,=0  5  21  -  (2.9) o,=0  5  22  -•  (2.10) a,=0  where 5i i is interpreted as the ratio of the reflected voltage wave to the incident voltage wave at port 1 with the output port properly terminated. The condition for a port being  8  properly terminated is that the impedance looking into the port must match the characteristic impedance o f the transmission line attached to it. Definitions for the rest o f the S parameters can be interpreted analogously.  Linearity Linearity is a key requirement i n the design o f an L N A because the L N A must be able to maintain linear operation i n the presence o f a large interfering signal and when the input is driven b y a large signal [14]. Intermodulation linearity, characterized b y the inputreferred  3 -order intermodulation intercept point (IIP3), is crucial to prevent the rd  intermodulation tones created b y a large interfering signal from corrupting the signal o f interest.  Large-signal linearity, characterized  by the input-referred  l d B voltage  compression point ( P l d B ) , is important as it determines the maximum input level that can be amplified linearly, i.e. the upper bound o f the dynamic range o f the L N A .  Harmonic Distortion The input Vi and output V o f a two-port network can be related by a power series [15]: 0  K =a V +a V i  i  2  2 i  +a V i  3 i  +...  (2.11)  where a\, « 2 , « 3 are constants. If the input is driven by a sinusoidal signal as follows,  ^)=F,cos(tfv)  (2.12)  where V\ and a>\ are the amplitude and frequency, respectively, then the output is equal to a V  2  V (t)=a V cos(ft>,f)+ [cos(2ftv)+l] a V' + [cos(3fty) + 3cos(ay )] + ••• 2  0  1  1  i  2  3  1  9  ( 2 , 1 3 )  The first term i n (2.13) is the linear term, and is the ideal output i f the two-port network is completely linear. Other terms in (2.13) are due to non-linearities, and they cause a D C shift as well as distortion at frequencies 2co\, 3co\, and higher harmonics, which result in either gain compression or gain expansion. It can also be observed from equation (2.13) that distortion is present in any signal level.  To quantify the amount o f harmonic distortion, the following definitions are used: Amplitude ,„ H  D  i  1  =  Amplitude  ?5L  Amplitude,,, ^Amplitude  HD,=  o\ 4)  (2.15)  where (2.14) represents the fractional second harmonic distortion, and (2.15) represents the third fractional harmonic distortion. Higher order fractional harmonic distortion definitions can be written i n the same fashion.  The above definitions for the second and third order fractional harmonic distortion can be written in terms o f the coefficients o f the power series and the input signal by examining (2.13).  HD =-^V, 2a,  (2.16)  HD  (2.17)  2  3  4a,  10  Intermodulation Harmonic distortion, introduced previously, is the result o f non-linearities due to a single sinusoidal input. It is quite possible i n practice that two or more sinusoidal signals are applied to the input o f a two-port, for example, the first signal representing the input and others representing large in-band interferences at the input o f an L N A . When this occurs, another non-linearity called intermodulation results. To see the effects o f both harmonic distortion and intermodulation, assume that the input signal is now equal to V (t) = V cos(<y^) + V cos{co t) j  x  2  (2.18)  2  The output can be expanded in a power series and (2.18) can be substituted into (2.11). The linear first term can be expressed as \v cos(co t) + V cos(ft> ?)] x  x  2  (2.19)  2  The second term is given by  V  V  2  2  = ^ _ L _ [cos(2^, t) +1] + f^2_L_ [cos(2co t)+1] 2  (2.20)  + a V V [cos(ty, + co )t + 003(0), - co )t] 2  x  2  2  2  Expanding the third term gives  [cos(3<»,;)+ 3cos(a>,?)] +  3  ^  [cos(3&> f) + 3cos(a> t)]  2  2  2  (2.21) + — a F , V [2 cos(co t) + cos(2<£> + co )t + cos(2&> - co )t] 3  2  x  + — a V V [2cos(a) t)+ 2  i  x  2  2  2  x  2  x  cos(2&>, + a> )t + cos(2&>, - « ) ^ ] 2  11  2  It can be observed from (2.20) and (2.21) that harmonic distortion terms are produced as i f each sine wave is applied separately. However, second order intermodulation terms are also produced at (a>\ + 0)2) and (a>\ - C02), and third order intermodulation terms are produced at (2a>\ ± CO2), and (2a>2 ± co\). F i g . 2.5 shows the distortion terms i n the frequency spectrum [12].  V  F F  0  4 4 IM,  IM  2  4  4  2  4  1M  IM  3  4  HD  HD ' 3  4  2  IM IM 3  44  HD  HD  3  4  frfx  2f f r  2  2/2-/,  Af  2  2/, 2f fv.fi  3  4  3  J/, 3f 2Mf 2fy-f  2  2  2  f  s  Figure 2.5 Frequency locations o f distortion terms;  The following two equations define fractional intermodulation:  IM  2  Amplitude  =  ^  (2.22)  Amplitude  Amplitude ( a>),(2<u±<a) 2a±  2  2  ]  Amplitude  (2.23)  0)\ ,0)  2  Using the definitions i n (2.22) and (2.23), the fractional intermodulation terms are  =f^V  IM  2  l  a,  IM = -^V> 4a, 3  3  3  1  12  (2.24)  (2.25)  where it is assumed that V\ = V2. From F i g . 2.5, it is apparent that the  3 -order rd  intermodulation distortion IMi signals are close to the signal o f interest F, which makes the filtering out o f IM3 signals difficult when recovering the signal o f interest. Therefore minimizing intermodulation distortion is a key objective i n many R F circuit designs.  1 dB Compression Point It is mentioned previously that the 3 -order term in the power series can either cause gain rd  compression or gain expansion. If we assume that the sign between a\ and az are different, then gain compression occurs. P l d B is a measure o f the power o f the input signal such that it causes the 3 -order non-linearity to reduce gain by 1 d B from the ideal value. It rd  can be expressed as:  20 log 1 + ^ l F , = -\dB v i j  (2.26)  2  4  a  Solving for V\ in (2.26) gives  p  -\dB  r  3  rd  - \ ^  VoTT  (2.27)  Order Intercept Point  Another measure for the 3 -order non-linearity in a two-port network is the 3 -order rd  rd  intercept point. Since the 3 -order non-linearity is proportional to the input signal cubed, rd  while the fundamental is increasing only linearly with the input signal, there is a point at which the amplitudes o f the fundamental  and that o f the 3 -order intermodulation rd  product meet. The input signal at which this occurs is defined as the input-referred 3 rd  13  order intercept point (IIP3), and is equal to when 7 M equals 1. Solving for V\ using (2.25), 3  the following equation for IIP3 is obtained.  IIP3 = J3  (2.28)  Stability A critical requirement o f a two-port network is that it must not produce an output with oscillatory behavior. The stability o f a two-port network can be determined from its Sparameters and the load and source impedances. The Rollet stability factor, K, is often used for verifying stability [16]. Unconditional stability is satisfied under the following two conditions:  K >1  (2.29)  A <1  (2.30)  where „  1-15',, I - | 5 „ I +1 A I 2  2  K = — ! — ^2 | S S l2  A — S^S  22  1  2  —-  (2.31)  2i  iS|2iS*2j  (2.32)  However, K alone is usually good enough to test for stability since most transistors are either unconditionally stable, satisfying (2.29) and (2.30), or conditionally stable with K< 1 and |A| < 1 [14].  14  Noise in Two-Port Systems In order to design a circuit for l o w noise, it is useful to determine the condition under which noise can be minimized. This condition is then used i n Chapter 3 to relate noise performance to C M O S design parameters. For the analysis o f noise i n two-port systems, consider a noisy two-port network driven by a noisy source as shown i n Fig. 2.5(a).  (a)  Noiseless Two -Port  Ys  -O (b) Figure 2.4 Noise modeling, (a) Noisy two-port, (b) Input-referred noise model.  The noise factor o f a two-port network is defined as  F  =  .SNR  IN  SNR  P.  n,output  OUT  (2.33)  n,source  where P„,output is the noise power outputted b y the two-port and P ,source is the noise n  presented at the input o f the two-port. A n ideal noiseless two-port network contributes no noise; hence the noise factor is equal to one. Noise figure N F , which is noise factor  15  expressed in decibel, often used to specify noise performance and has an ideally value o f OdB.  To simplify analysis, the noise o f a two-port network can be modeled as a noise voltage and a noise current at the input as shown in Fig. 2.5(b). The signal source is represented by a current source i i n parallel with and an admittance Y to simplify derivation. In this s  s  case, the noise factor can be expressed as [13]:  i,  F =-  2  + i +Y v n  s  n  (2.34)  .2  In the derivation o f (2.34), the assumption has been made that the noise from the source is not correlated to the noise from the two-port. However, since the exact nature o f the source o f the two-port is not known, the above assumption about correlation may not be reasonable. Therefore, the following definition for i„ is needed: K =i +i„  (2.35)  c  where i is the portion o f i„ that is correlated with v„, while /„ is the part o f i„ that is c  uncorrected with v„. The current i is equal to Y v ,where c  c  n  Y is known as the correlation c  admittance and is given by  Y =—  (2.36)  c  16  Equation (2.34) contains independent noise sources, each o f which may be treated as thermal noise produced by an equivalent resistance or conductance:  R  "  ^ ^ ~  n  (2-37)  4kTAf  G =-±— u  "  (2.38)  AkTAf  G =-^— s  (2.39)  4kTAf  where k is Boltzmann's constant (about 1.38 x 10-23 J / K ) , T is the absolute temperature in kelvins, and A / i s the noise bandwidth in hertz. Using (2.36) - (2.39), the noise factor can be expressed purely in terms o f impedances and admittances:  r  u  G  u  +  [ ( G  c  +  G Y s  +  ( B  c  +  B f y R s  n  To optimize for noise in a circuit, the minimum noise factor can be solved for by first taking the derivative o f (2.40) with respect to the source conductance and susceptance and setting them to zero. The results for the optimal source conductance and susceptance are stated below. B , =~B s opl  (2.41)  c  G , =jf-  +G  s opt  2 c  (2.42)  Substituting (2.41) and (2.42) into (2.40) gives the following results for the minimum noise factor. F n=l mi  + 2R (G , ,+G ) n  s op  17  c  (2.43)  The noise factor can then be expressed in terms o f F i and the source admittances by m  n  (2.44)  The above analysis shows that a source impedance optimized for a minimum noise factor exists, but this source impedance is often not the same as the impedance that achieves maximum power transfer. In (2.44), the ratio R„/G  s  appears as a multiplier in front o f the  second term. For a fixed source conductance, R represents the sensitivity o f the noise n  factor as G and B departs from their optimal values. A large R„ implies a high sensitivity, s  s  which obligates the design to stay close to optimal noise matching. A s discussed subsequently, operation at low bias currents is associated with large R , mainly due to n  small device transconductance g . This is an example o f the difficulty in achieving high m  performance at low power consumption.  18  Chapter 3 CMOS LNA Fundamentals  This chapter describes the theories and considerations useful to the implementation of an L N A in the C M O S technology.  Noise Sources in CMOS Before beginning an analysis of how to design for low noise, the origins of the noise should be identified and understood. This section discusses several important noise sources in CMOS transistors.  Thermal Noise J  Cgs —,  + gs  V  gd  C  [)gmVg  S  >  V  °  1  ~1  Figure 3.1  Q  MOSFET small-signal model with thermal noise.  Thermal noise is due to the random thermal motion of the carriers in the channel [17]. It is commonly referred to as a white noise source because its power spectral density holds a constant value up to very high frequencies (over 1 THz) [13], Thermal noise can be  19  modeled as a current source across the drain and source o f a transistor, as depicted in Fig. 3.1 [12], and has a power spectral density o f  A/  where k is Boltzmann's constant, T is the absolute temperature, y is a bias dependent process parameter, and gd o is the zero-Vps drain-source conductance, and has the s  following definition:  a = -^=-  (3.2)  SdsO  where g  m  is the transconductance and a is typically in the range between 0 and 1.  Equation (3.1) is a general equation that can be used i n both the linear and saturation regions o f operation simply by using different values for y. For long channel transistors, y = 2/3 in the saturation region, and y = 1 in the linear region. For short channel transistors, hot carrier effects may cause y to be as high as 2 or 3 [18].  Induced Gate Noise Induced gate noise is a high frequency noise source that is caused by the non-quasi static effects influencing the power spectral density o f the drain current [17]. Thermal noise in the channel couples through the oxide capacitance to the gate terminal, causing a gate noise current to flow. This noise source is normally not included in standard noise analysis because at low frequencies it is negligible. However, it can dominate at R F  20  frequencies [13]. Induced gate noise, with its circuit model shown in Fig. 3.2(a), has a power spectral density given by /  2 s  co C 2  =4kTS-  2  (3.3)  g s  5g dsO  where co is the frequency, C is the gate-source capacitance, and d is a process parameter gs  equal to 4/3 in long channel devices [17]. Since the thermal channel noise and induced gate noise stem from the same physical phenomenon, it can be assumed that the relation S = 2y continues to hold for short channel devices [13].  G  o  S  o  (a) Va  G o  Q  VW  c,  S o  . + v gs  (b) Figure 3.2 Induced gate noise model, (a) Frequency dependent, (b) Frequency independent.  The power spectral density of (3.3) is frequency dependent. An equivalent frequency independent noise model is to express the induced gate noise as a voltage in series with the gate capacitance, as shown in Fig. 3.2(b). If a high quality factor Q is assumed, then  21  the models shown i n Fig. 3.2(a) and (b) are equivalent, and (3.4) gives the power spectral density. 2'  ^ - = 4kTdr  (3-4)  e  A/  Equation (3.4) shows the interesting result that the gate noise is equal to the noise o f r , a g  resistor placed at the gate, scaled with the constant S.  A s discussed previously, gate noise and drain noise are partially correlated due to the fact that they are from the same source. The correlation coefficient c can be expressed as in (3.5):  c -  (3.5)  2 . 2  The theoretical  value  for c is -0.395/  for long channel  devices  [17]. Precise  measurements o f c are difficult to carry out, but the best published measurements reveal that its magnitude stays within a factor o f 2 o f this theoretical value, even for devices with drawn channel lengths as small as 0.13pm [13].  Distributed Gate Noise The distributed gate resistance o f the C M O S transistor also contributes to the noise figure of an L N A . This noise source is modeled as a resistor at the gate and has a noise power spectral density equal to 2  Af  = 4kTR  22  (3.6)  where R is the gate resistance, and is given by g  In (3.7), Z ^ i s the sheet resistance o f the gate material, n is the number o f fingers, and the factor 1/3 results from the assumption that each finger is only contacted at only one end. If both ends are contacted, then the factor reduces to 1/12.  Intrinsic MOSFET Two-port Noise Parameters In chapter 2, the expression for the noise factor is derived, herein reproduced as (3.8) for convenience.  (3.8)  V i e w i n g the M O S F E T as a two-port network, with the gate and source forming a port and the drain and source forming another, it is useful to express F j , R , G m  n  n  s>oph  and  B  St0pt  in terms o f M O S F E T device parameters [13]:  (3.9)  R„ =  TSdo  (3.10)  g,m  (3.11)  (3.12)  23  This completes the noise analysis that relates the noise factor with design variables g , co, m  C , and gdo- Examining (3.9) - (3.12), Wcan also be related to the four noise parameters, gs  which permits noise consideration in transistor sizing.  F  i n i n  no width dependence R  n  acl/W  (3.13) (3.14) (3.15) (3.16)  Aside from.the classical noise matching ( C N M ) presented above, a number o f C M O S L N A design optimization techniques are also well established such as simultaneous noise and input matching ( S N I M ) , power-constrained simultaneous noise and input matching ( P C S N I M ) , and power-constrained noise optimization ( P C N O ) . A good overview o f these techniques is presented in [5].  Inductive Source Degeneration A n L N A must provide an input matching to a typically 50Q element such as a bandselect filter or an antenna. In a fully integrated receiver, L N A output matching is often not required as it is connected to the next on-chip stage in the receive chain. To minimize the number o f off-chip components, an L N A should implement the elements required for input matching on chip. One popular approach is to use inductive degeneration.  24  Input Impedance Match Input impedance matching by inductive source degeneration is popular, as matching to the signal source does not introduce additional noise (as i n the case o f using a shunt input resistor) and does not restrict the value o f g  m  (as i n the case o f the common-gate  configuration).  lout  R -vw s  _nmr\_  ^7 Figure 3.3  Inductive source degeneration.  The circuit shown in Fig. 3.3 has an input impedance equal to  Z,.„ (a>) = jco{L  s  + L )+—!—  +  s  ss  J  (3.17) zs  where ideal inductors and capacitors have been assumed. From (3.17), i n order to achieve an input impedance match, the following condition must be satisfied:  R  =  ^ n  L  ^  x  (3.18)  L  C  where coj- gmlC  gs  is the transit frequency o f the transistor. Once L is chosen based on s  gain, linearity and input matching requirements, L can then be chosen such that L , L , g  g  s  and C resonate at a>o. In other words, the following condition for L must hold: gs  g  co =  1  0  25  (3.19)  Circuit Transconductance Transconductance is important for gain. To find the transconductance G  m  o f the circuit  shown i n F i g . 3.3, first note that the input matching network forms a series R L C tank. The Q o f the tank is 1 Qin  f  \  (On R +  g  m  s  c  (3.20)  gs  cgs  J  where COQ is the resonant frequency defined in (3.19). A t resonance, the voltage across the capacitor is equal to (3.21)  and the short circuit output current is equal to Ku,  =  (3.22)  g s v  m g  where g is the transconductance o f the device. Using (3.20) - (3.22), the overall circuit m  transconductance can be solved for, and is given by the following equations:  g„ R +  g  m  C  s  C  (3.23) gs  gs J  (3.24)  It can be observed from (3.24) that G  m  is dependent on C M O S process technology  through the transit frequency.  26  Circuit Topologies The key specifications for characterizing the performance o f an integrated L N A are gain, noise, linearity, power consumption, stability, and input matching. These specifications depend on the circuit topology. Topologies such as common-source, cascode,  and  distributed  amplifiers  have  been  used  for  different  common-gate, performance  requirements. Compared to the common-source configuration, common-gate is more suitable for wide-band operation, but suffers from relatively high N F [19]. Distributed amplifiers are also capable o f wide-band operation, but they suffer from relatively high power consumption [20].  (a) Figure 3.4  (b)  Narrow-band topologies, (a) Common-source, (b) Cascode.  For narrow-band operation, which is the focus o f this work, the common-source and cascode amplifiers are the most suitable. In the common-source configuration, as shown in Fig. 3.4(a), the signal is applied to the gate and the output is taken from the drain. The cascode amplifier is a common-gate amplifier stacked on top o f a common-source  27  amplifier, as shown in Fig. 3.4(b). The cascode amplifier consists of an input transistor M i and a cascode transistor M2 with a gate bias voltage V . Compared to the cascode B  amplifier, the common-source amplifier suffers from the following shortcomings:  1) Poor isolation between input and output, due to the gate-to-drain parasitic capacitance C d, increases the chance of instability significantly. g  2) As CMOS technology scales, the MOSFET output resistance r decreases, causing 0  noticeable performance degradation. For a common-source amplifier, r appears in 0  parallel with the load impedance in small-signal operation, which reduces the output impedance, and lowers the gain of the LNA. A possible solution is to increase the gate length L , which results in a degradation of NF.  To alleviate the shortcomings of the common-source topology, the cascode topology is often used. The addition of the cascode device reduces the effect of the C d of M\ by g  presenting a low impedance node at the drain of M\, improving stability. The cascode device also performs impedance transformation so that the output impedance of the amplifier is improved by a factor approximately equal to the intrinsic gain of the cascode device.  The load inductor, Ld, is designed to resonate at the operating frequency with the output node capacitance. The input and output tanks can be aligned to provide a narrowband gain, but can also be offset from each other to provide a broader and flatter frequency  28  response. One shortcoming o f the cascode topology is that the extra transistor consumes voltage headroom. A s a result, the load should not consume a large voltage headroom. A n inductive load Ld, as opposed to a resistive load, is preferred. A n inductive load has the added benefit o f increasing the gain by resonating with the capacitances associated with the output node and also improving frequency selectivity.  Since on-chip inductors have a limited range o f values, the capacitor C  m  o f Fig. 3.4(b)  can be added between the gate and source terminals o f M\ so that the values o f L and L g  s  are reduced to permit on-chip implementation. Reducing the inductor value also improves Q, which reduces input losses and improves L N A noise figure. A d d i n g C  m  has another  advantage o f providing an extra degree o f freedom for choosing the gate width W o f M\, which decouples  impedance matching requirements  from power consumption. A  drawback o f adding extra gate-to-source capacitance is the degradation o f fy o f M\. However, as discussed subsequently, at operating frequencies well below fr, this trade-off is reasonable. It is also interesting to note that adding C  m  does not degrade distortion  performance [10].  Performance of the Cascode Amplifier Since the cascode amplifier depicted in F i g . 3.4(a) is a robust topology for narrow-band applications, a detailed study o f its gain, noise, and linearity performance is provided in this section.  29  Voltage and Power Gain Assuming the L N A is input matched, the voltage gain and power gain can be expressed as (3.25) and (3.26), respectively [17].  (3.25)  2R.  G  =  r  (3.26)  R.  where RL is the resistance at the output due to the finite Q o f Ld and the finite output resistance o f the transistor, and R is the impedance o f the signal source. S  Noise The noise factor F o f the L N A can be expressed as [ 1 ]  K,  (3.27)  a  co j  K  T  F can be expressed in a more intuitive form i f power/impedance matching is assumed at the input (which is often the case). The derivation is done i n [21], and the result is repeated below: aS(\-\c\ ) 2  F«l + ^ a yCO  r  j  +  g R +T M  s  (3.28)  5g R M  S  where the portion o f the gate noise that is correlated with the drain noise has been neglected. In (3.28), the second term is the contribution from the channel drain noise, and the last term is the contribution from the uncorrected portion o f the gate noise. It can be  30  observed that as COT increases (for example with improving technology), the drain noise contribution becomes less significant i f the operating frequency is kept constant.  Linearity A purely sinusoidal input signal can produce a distorted output signal with higher-order harmonics due to the nonlinearity o f the M O S F E T . These harmonics are mainly induced by higher-order derivatives o f the current-voltage  {ID-VGS)  characteristics. A n important  figure o f merit for linearity is the 3 -order harmonic intercept voltage V I P 3 , which is the rd  extrapolated input voltage amplitude at which the 1 - and 3 -order output amplitudes are st  rd  equal. The input-referred VIP3 can be expressed as [9]:  (3.29)  For linearity, V I P 3 is used as a key design parameter and its value is representative o f the input signal amplitude that the system can process with reasonably low distortion. It can be obtained by taking the third derivative o f the  ID-VGS  characteristics i n respect to Fas-  Figure 3.5 gives the V I P 3 as a function o f gate bias Vcs under different values o f drain bias VDS [22]. A sharp peak is observed near the threshold voltage as gate bias is varied, which reflects the so called "sweet spot" o f gate biases for high M O S F E T linearity [9]. This is because, during the transition from subthreshold to strong inversion, the increase of g  with Vcs is at its highest, and the 2 -order nonlinearity coefficient g 2 reaches its nd  m  m  peak, while the 3 -order nonlinearity coefficient g z becomes zero. rd  m  31  10 t-  Q -j I  0.0  i  J  0.2  i  l  0.4  i  i  i  i  0.8  0.6  I  1.0  Vgs (V) Figure 3.5  VIP3 o f a 40nm n F E T vs. V  os  for different V  DS  (V  TH  = 0.23V) [22].  A t the system level, the input 3 -order intermodulation point (IIP3) o f the cascode rd  amplifier can be written as [22] IIP3[dbm] = IIP3  in  [dBm] - 20 l o g  1 10  (3.30)  The first term i n (3.30) is the intrinsic IIP3 o f the device, and arises from the fact that short channel C M O S transistors exhibit velocity saturation, which gradually linearizes the ideal quadratic relationship o f the long channel drain current equation. The second term results from the extra voltage boost across the C due to the series resonance tank, gs  which increases gain but degrades IIP3. This outlines a tradeoff between gain and linearity.  32  Inductor Design Inductors are widely used in RF circuitry to resonate with capacitors and to provide impedance transformations. The design of on-chip inductors is important as the inductor may dominate the frequency selectivity of a RF circuit and consumes a large area. The frequency selectivity of an inductor, characterized by the quality factor Q, is a major design parameter to be optimized. As evident in the following subsections, there is a tradeoff between Q, practical inductance values, and inductor area.  Physical Dimensions On-chip inductors can be implemented in different shapes such as squares, octagons, and circles. The layout of a square spiral inductor is depicted in Fig. 3.6.  I  7  m  •. b -  Figure 3.6 The layout of a square spiral inductor.  33  Although it may seem counterintuitive, the Q depends very little on the shape [13]. Instead, it mainly depends on the following parameters:  N  The number o f turns in the spiral  D  The inductor's inner radius (For a square spiral, D is the shortest distance between the center and the inner side o f the spiral)  W  The width o f the wire  S  The spacing between two wires  T  The thickness o f the wire. Once the metal layer is chosen, T is fixed.  Inductor Figures of Merit In this section, three common figures o f merit used to describe the characteristics o f an inductor are discussed: inductance, quality factor, and self-resonant frequency.  A. Inductance The calculation o f the inductance o f a structure is based upon the self-inductance o f a conductor, and the mutual inductance between two conductors [23]. The total inductance o f a spiral structure is equal to the sum o f all o f the self-inductances o f the wire segments and the positive and negative mutual inductances between the wire segments. T w o segments have a positive mutual inductance i f the direction o f current flow in them is the same and a negative mutual inductance i f the direction o f current flow in them opposes each other. Inductance calculation is often complicated and is best performed by a computer simulation program such as A S I T I C [24].  34  B. Quality Factor The quality factor Q is a measure o f the amount o f energy loss in a circuit component or network and has implications on their frequency selectivity. It is defined as  Q  =  l  Energy _ stored  n  Energy _ dissipated  =  _g  J L  BW  where a>o and BW are the resonant frequency and bandwidth, respectively, o f the component or network. A n ideal inductor has a Q o f infinity. When the loss is significant (caused by for example interconnect resistance, substrate loss, and the skin effect), the peaking o f a signal at resonance degrades, which in turn lowers the amplifier gain. The degradation o f the frequency selectivity, which results in a large BW may be undesirable as, for example, an L N A should ideally reject out-of-band signals while only amplifying the signal o f interest. The quality factor can be improved by adding a patterned ground shield between the inductor and the substrate to reduce capacitive coupling [25].  C. Self-Resonant Frequency The self-resonant frequency is the frequency at which the inductor resonates with its own parasitic capacitance. Below the self-resonant frequency, the inductor behaves like an inductor, at the self-resonant frequency the inductor behaves like a resistor, and above the self-resonant frequency, the inductor behaves like a capacitor. In general, a physically larger inductor tends to have a lower self-resonant  frequency [13]. Therefore, the  requirement that the inductor operates at most at half its self-resonant frequency places a limit to the size o f the inductor.  35  Inductor Modeling Inductors can be modeled with an electromagnetic field solver tool such as A S I T I C . A frequency-dependent  n model as shown in F i g . 3.7 can be used for narrow-band  applications. R models the resistance o f the interconnect, L models the inductance, C and s  R  s  respectively model the capacitance and resistance from the inductor metal to the  substrate.  R  L  o  O  C2 S  Figure 3.7  Pi-model o f inductor.  36  Chapter 4 Designing for Power-Efficient Operation  The main objective o f this work is to create a design methodology for power-efficient L N A s that can operate at sub-mW power consumption levels. This chapter describes device biasing and sizing, the two fundamental design steps, and presents a step-by-step design procedure.  The following discussion is illustrated with a collection o f graphs that relate device characteristics  such as transconductance  and power consumption to circuit design  parameters such as gate voltage VQS and gate width W. These graphs offer perspectives to explore the design space particularly useful for selecting the biasing condition for the amplifier, which is the first step o f the proposed design procedure. Data from the graphs has been obtained from SpectreRF simulations using a commercial 90nm process design kit.  Device Biasing Since circuit performance is strongly tied to device biasing and that proper biasing involves knowledge o f device characteristics, it is important to incorporate the knowledge o f the device from the beginning o f the design cycle to minimize parameter tuning at the end.  37  Terminal / - V Characteristics 30  —•-20/0.1 40/0.1  25  -A-40/0.2  20 < Q  10 +  5 0  0  Figure 4.1  0.2  0.4  V G S (V)  0.6  0.8  ID vs. Vcs for a 90nrn n F E T (Vos  =  IV).  Figure 4.1 shows the drain current o f a 90nm n M O S F E T as a function o f its gate voltage for three transistor sizes, specified in units o f micrometers. In this process, the threshold voltage VTH is around 0.35V. A l l results thereafter are based on such an n M O S F E T . It is apparent that deep submicron effects such as velocity saturation occur at Vcs > 0.6V, rendering the ID-VGS curve more linear as opposed to quadratic. This suggests that linearity o f a circuit can be improved with a strong gate bias voltage. A l s o evident from Fig. 4.1 is that ID is proportional to the transistor width W for a given length L. However, according to the square law, transistor sizes 20/0.1 and 40/0.2 should have the same current, which is not the case for this 90nm n F E T . W i t h the aid o f this graph, the designer can evaluate the extent o f the deviation o f the 1-V relationship from the classical model.  38  V  DS  Figure 4.2 I vs. V D  DS  [V]  for a 90nm n F E T (W/L = 20 pm/0.1 um, V = I V ) . DS  The ability for a transistor to function as a robust current source is crucial to amplifier design. F i g . 4.2 shows the drain current characteristics o f a 90nm n F E T . For a given Vcs, ID is plotted as a function o f V s- This plot explicitly reveals channel length modulation, D  evident by the dependency o f ID on VDS when the transistor operates in saturation. Channel length modulation manifests itself as non-linearity and gain reduction at the circuit level.  If the power consumption o f a M O S F E T is indicated by the product o f ID and VDS, then a set o f constant power contours, which is also depicted in Fig. 4.2, can be plotted in the IDVDS design space. The plot shows three power levels at 0.1, 0.5, and l m W , with the lower left corner representing a region o f lower power consumption. The intersection o f power contours and  ID-VDS  curves provides different combinations o f Vcs,  turn facilitates the choice o f power-constrained bias selection.  39  VDS,  and  ID,  which in  Gain and Transconductance  250  i  A-A A A A  V G S [V]  Figure 4.3 /rvs. PGS for a 90nm nFET (P£>,s = IV).  The cut-off frequency fr, also called transit frequency, has been widely used as a measure of operating frequency of the device. It is defined as the frequency at which the current gain of the device is equal to unity and is given by  fr =  8n  (4.1)  2x(C +C ) gs  gd  Figure 4.3 illustrates fr as a function of Vcs for different transistor sizes. The curves for transistor sizes 20/0.1 and 40/0.1 overlap, indicating that fr for afixedL is not a function of W. It can be inferred from (4.1) that the increase in transconductance g that results m  from increasing W is offset by the increase in parasitic capacitances. Also evident from Fig. 4.3 is that fr is relatively low at a low Vcs, which is necessary for power-efficient operation, and since a high fr is necessary for a low noise figure, a tradeoff is needed between noise and power. Also, fr is degraded when the device operates in the subthreshold region and when non-minimum L is used.  40  0.4  0.6 V G S [V]  Figure 4.4 g vs. Vcs for a 90nm n F E T (VDS  =  m  The transconductance g  m  IV).  o f a device is important to amplifier design as the gain o f an  amplifier is the product o f its transconductance and output resistance. F i g . 4.4 depicts g  m  as a function o f Vcs- gm is obtained by differentiating the D C drain current ID with respect to Vcs- gm increases rapidly with Vcs until it saturates at a Vcs well above VTH-  To  relate  device performance  transconductance efficiency gjlo  with  power  consumption, it is useful  to  [7]. Fig. 4.5 shows g /Io as a function o f Vcsm  41  define  35  0 H 0  ,  ,  0.2  0.4  -, 0.6  ,  1  0.8  1  V G S (V)  Figure 4.5 gjlo  A s can be seen, gjlo  vs. Vcs for a 90nm n F E T (Vos  =  IV).  is, to the first order, invariant across transistor sizes, indicated by  the overlapping o f the curves for the Z,=0.1um cases and that gjlo  is insensitive to W  when the device is turned on. The fact that g /Io is independent from transistor size is m  significant as this removes transistor  size from the power efficiency optimization  equation, leaving Vcs as the primary variable to be considered. This means that circuit design that optimizes transconductance  efficiency can be broken down into two  sequential steps: first determining bias condition for maximum efficiency, then sizing transistors based on the absolute power requirement. A s shown i n F i g . 4.5, to exploit the high gm/Io, it is ideal to bias the transistor in the subthreshold region. However, as previously shown in F i g . 4 . 3 , / r i n this region may be insufficient. A good compromise is to operate i n moderate inversion.  42  10 1  4-  •  —,  0  ,  0.2  r—  0.4  0.6  ,  1  0.8  VGS[V]  Figure 4.6  r (=l/g ) vs. V for a 90nm n F E T (V = I V ) . 0  ds  DS  DS  A s mentioned previously, an amplifier's gain is a function o f the amplifier's output resistance, which in turn is a function o f the device's output resistance r . r can be 0  expressed as \lgds, where gj  s  0  is the drain-to-source conductance. I f r is small, the fact 0  that it appears i n parallel with the amplifier's load can significantly reduce the output resistance o f the amplifier, hence degrading its gain. For the older technologies, r has 0  been high enough that it can be ignored. A s devices move to deep submicron, r  0  decreases due to channel length modulation, with a small value i n the order o f hundreds o f ohms for practical choices o f VQS- A S can be seen from Fig. 4.6, r is a strong function Q  o f Vcs, W, and L. A l s o , a large W, often required for noise matching at the input stage, degrades r substantially. This posts a challenge for L N A design and is often overcome 0  by an increase i n power consumption.  43  100  0  0.2  0.4  0.6  0.8  1  VGS (V)  Figure 4.7  Intrinsic gain g  m  r (= 0  gjgds)  vs. V  GS  for a 90nm n F E T (V = DS  IV).  To evaluate the ability o f a device to provide gain, the intrinsic gain gjgds is plotted as a function o f Vcs in F i g . 4.7. The intrinsic gain represents the theoretical maximum gain achievable by a single transistor. Curves for L-0.1 urn overlap each other. A s shown i n Fig. 4.7,  g lgds improves significantly as m  L increases. However, using non-minimum L is  often not a good practice in designing L N A s as it degrades the noise performance. This outlines a tradeoff between gain and noise performance. If gain is compromised to achieve low noise, then multiple gain stages may be required. This adds power consumption into the gain-noise tradeoff.  Transistor Sizing The biasing condition, which corresponds to a particular Vcs, determines the drain current density ID/W. Once IQ/W is found, transistor sizing can be performed based on the current density and the drain current allowed by the power specification. Since the objective is to  44  design for low noise, the dependency o f noise on W is examined. F i g . 4.8 shows the N F o f a cascode and a common-source L N A for different gate widths.  Figure 4.8 N F vs. W o f cascode and common-source amplifiers.  A s can be seen, N F decreases as W increase, which suggests a tradeoff between N F and power consumption. A l s o , N F is significant for small W, indicating that low noise is fundamentally difficult to achieve for low-power circuits.  Figure 4.8 reveals an interesting limitation o f conventional power-constrained noise optimization methods proposed to target low-power design. This technique is based on first finding an optimal gate width, then biasing the device with the amount o f drain current allowed by the power constraint [13]. In sub-mW designs, the large optimal gate width combined with a small drain current often force the device to be biased in the subthreshold region. When subthreshold operation is inadequate, such as insufficient  45  frequency  response,  the  technique  is no  longer  applicable.  A n effective  noise  optimization technique for the ultra-low-power design space is needed.  Step-by-step LNA Design Methodology A step-by step design methodology for power-efficient inductively degenerated commonsource or cascode L N A s is proposed. The cascode L N A is depicted in F i g . 4.9. The key difference between the proposed methodology and the conventional ones [1] [5] is that it starts from device biasing instead o f device noise characteristics. Beginning the design procedure with device biasing has the advantage that all o f gain, noise, linearity, and power are taken into consideration at the start o f the design, instead o f optimizing for noise while later possibly resorting to compromising other aspects severely. A l s o , it is important to note that the primary objective o f the proposed design methodology is to reduce power consumption. The performance o f the L N A , especially noise, is inevitably suboptimal.  (b)  (a)  Figure 4.9 Cascode amplifier, (a) Schematic, (b) Simplified small-signal model for input matching analysis.  46  Stepl: Choosing the bias VGS Since power consumption is the focus o f this design methodology, the first step exploits the notion o f transconductance efficiency gjlo-  A s Vcs increases, gjlo  reduces but g  m  (and also ff) improves. This suggests that there is an optimal value o f VGS for a given application. Ideally,  VGS  should be chosen to be a low value to maximize  gmlh,  which  leads to a power-efficient circuit. But the lower bound o f VGS is governed by designing for sufficient g , m  which translates proportionally to amplifier gain, and sufficient  f, T  which provides enough bandwidth for the amplifier operating frequency.  VGS can also determine noise performance in three ways. First, since biasing for higher fj leads to lower device N F , VGS should ideally be large. Second, there exists a characteristic current density o f 0.15mA/um that yields minimum device N F [6]. Having a lower device N F i n turn lowers the overall amplifier N F . Since the characteristic current density corresponds to strong inversion, Vcs should ideally be large. Third, as often seen in subm W designs, the width o f the input transistor is often made small to satisfy the power requirement. But this small W is often not optimal for noise matching. B y lowering  VGS,  although reducing/^and deviating from the characteristic current density, W can be made larger to further approach an optimal noise match. Therefore, an optimal Vcs exists and its selection is nontrivial.  47  VQS can also determine linearity performance. The fact that the device exhibits superb V I P 3 linearity performance when biased in moderate inversion gives the designer more incentive to choose Vcs from a narrow range that corresponds to moderate inversion.  Since g  m  and fr fall dramatically as Vcs enters the subthreshold values, having Vcs  slightly above VTH is often a good choice for R F operations (frequency roughly below 10GHz). For operation at a higher frequency, a higher Vcs is often needed to achieve an fr close to the maximum achievable by the technology.  A s can be seen from the above discussion, all o f gain, noise, and linearity are simultaneously affected by biasing, reflecting the interdependent nature o f analog circuit design.  Step 2: Calculate ID Calculate the drain current ID from the target power consumption (excluding biasing circuits) PDC and target supply voltage VDD, namely ID = PDC / VDD-  Step 3: Transistor Sizing The widths o f the transistors W can then be readily calculated from the drain current ID obtained i n Step 2 with the aid o f (4.2), the expression for I  D  where v  o f a short-channel device,  ~ 10 cm/s is the saturation velocity and E is the critical field (E ~ 6 x l 0 V / c m 7  sat  4  c  c  for electrons and 2 4 x 1 0 V / c m for holes). In L N A design, non-minimum L is rarely 4  chosen as a small L is critical for providing a low N F and gain at R F .  48  ^Vcs  V ) TH  ox  Step 4: Determine  (l +  (4.2)  AV ) DS  g  Transconductance g  m  m  can be obtained by taking the partial derivative o f ID with respect to  VGS for (4.2) or by running a D C simulation.  Step 5: Determine Gate Capacitance  C  gs  Decide whether or not additional gate-to-source capacitance C is beneficial. If the circuit m  is designed to operate at high frequency, C  should be minimized to improve f . If the  gs  T  circuit is designed for operation at relatively low frequency, the lower resonance frequency o f the circuit requires larger combined inductance and capacitance. Since large on-chip inductors cost significant area and cannot be made with high Q i n current standard technologies, it is easier to add capacitance.  Step 6: Impedance  matching  Inductive degeneration is used for input matching. Fig. 4.9(b) is a simplified small-signal model showing the components for matching, where C \ gs  denotes the  gate-source  capacitance o f M\. The input impedance o f the L N A Z can be expressed as in  1  + jco(L  s  +L  jcoC  49  ) +  C  (4.3)  where g  m  is the small-signal transconductance, C  gs  = C \\ C \ is the effective capacitance m  gs  between the gate and source and co is the operating frequency. Since Z  in  50  is to be matched  to the source impedance, which is typically 50Q. i n an R F system, the real and imagery parts o f Z,„ can be expressed as follows:  = R=  50Q  S  1  3m{ZJ  Examining (4.4), given g  m  cuC  + cu(L +L ) s  (4.4)  =0  g  (4.5)  is determined by Vcs and W, L and C s  gs  can be designed. It is  better to design L first as the gain and linearity o f the amplifier is dependent on it. A s  larger L adds more source degeneration and reduces the gain but improves the linearity s  [10].  Another practical  reason  is that  inductors  implementation have a smaller range o f values. Since g  that m  found, C  gs  are  suitable  for  on-chip  is known from Step 4, once L is s  can be readily calculated. Then L can be calculated from (4.5). g  Step 7: Designing the Load Ld and C  Ume  Ld, Ctune, and the parasitic capacitance at the drain o f the cascode device should resonate at the frequency o f operation. C e is often implemented using a bank o f capacitors to tun  provide variable capacitance for channel tuning and calibration for process variation. Ld is often chosen to be as large as possible for on-chip implementation as a large Ld improves gain.  Step 7 concludes the design methodology. The performance and yield o f the design may be further optimized by using C A D tools such as a design optimizer or a yield optimizer.  51  Chapter 5 Design of a Power-efficient LNA and Simulation Results  To demonstrate the application o f the design methodology described in Chapter 4, an L N A is designed and simulated in a commercial 90nm C M O S technology to operate at the 2 . 4 G H z band. This chapter presents the design rationale and the corresponding simulation results.  Circuit Topology and Impedance Matching To alleviate the shortcomings o f the common-source topology as discussed in Chapter 3, the cascode topology as discussed previously is used, hereby reproduced as F i g . 5.1 for convenience.  C  lime  •o RF,out  Figure 5.1  Schematic o f a cascode amplifier.  52  The cascode amplifier consists o f an input transistor M\ and a cascode transistor M2 with a gate bias voltage V . Since the cascode amplifier consists o f two stacked transistors, the B  load should not consume a large voltage headroom. A n inductive load Ld, as opposed to a resistive load, is preferred. A n inductive load has the added benefit o f boosting the gain by resonating with the capacitances  associated with the output  node. Inductive  degeneration is used for input matching.  Power-Efficient LNA Design The biasing o f the transistors has strong implications on L N A performance such as gain, noise, and linearity. When a short-channel M O S F E T is biased in saturation, ID can be expressed by (4.2), herein reproduced as (5.1) below: (V < <*  -V „) ">  2  r  I -Wv C D  sat  K 0X  I'CS  where v  r  T  TH )  d +W )  (5.1)  DS  +  ~ 10 cm/s is the saturation velocity and E is the critical field (E ~ 6 x 1 0 V / c m 7  sat  4  c  c  for electrons and 2 4 x 1 0 V / c m for holes). A s shown by (5.1), when L is kept to its 4  minimum, Vcs and W are key design parameters that directly link to power consumption. The drain current o f a 90nm cascode L N A is plotted i n Fig. 5.2 to quantify the sensitivity of power consumption to Vcs and  (supply voltage = I V ) . F i g . 5.2(a) depicts the drain  current o f a cascode L N A with both transistors sized to 25p.m. The threshold voltage o f the technology used is around 0.4V. In the typical analog design space for this technology (i.e., Vcs in the range o f 0.4V to 0.7V), power consumption increases 6.4x whereas, in Fig. 5.2(b) a change o f W from lOum to 40um (Vcs held constant at 0.4V) leads to a power increase o f 4.2x. It is interesting to note that, given a drain-to-source voltage, the  53  performance o f the M O S F E T is strongly tied to the drain current density IrJW, which is mainly controlled by VGS- The following subsections describe the sensitivity o f gain, noise, and linearity to Vcs and W.  (a) Figure 5.2  (b)  I o f a cascode L N A . (a) I vs. V D  D  CS  (^,=0^=25 um), (b) I vs. D  W(V =0AV). GS  Gain In conventional R F and microwave design approaches [26], [27], primarily developed for high-speed  bipolar circuits, fr  is an indispensable  design parameter. For  CMOS  technologies, there is a characteristic current density associated with operating in strong inversion that yields an optimal fr [6]. For the 90nm C M O S technology used in this work, VGS ~ 0.7V is required to reach the optimal value.  54  18 0.3  0.4  0.6  0.5 V  GS  10  0.7  15  30  35  40  (b)  (a) Figure 5.3  25  20  W[[im]  [V]  Voltage gain o f a cascode L N A . (a) A vs. VGS, (b) A . vs. W. v  v  Figure 5.3(a) shows the simulated voltage gain A o f the cascode amplifier depicted in v  Fig. 5.1 at 2.4GHz. While sweeping  VGS,  VB  is also modified such that the ratio  VGSJVGSI,  hence g \/g 2, is relatively constant. It may seem counterintuitive that A only increases m  m  v  slightly as VGS changes from 0.4V to 0.7V, which corresponds to roughly d o u b l i n g / r a n d g \. The reason lies in the fact that the operating frequency is sufficiently low compared m  to the maximum fr o f the technology and therefore the benefits o f increasing/^ are not as pronounced. This suggests that the use of fr as a design tool may have less influence in modern R F design. In addition, as VGS increases, ID also increases, which reduces the overall output impedance o f the cascode structure. Since gain is the product o f output impedance and transconductance, the reduction o f output impedance partially counteracts the effects o f increasing g \ on the overall gain. For comparison, F i g . 5.3(b) shows m  moderate increase in A as the widths o f both transistors are increased. v  55  Noise  / [GHz] (a)  1  1.5  2  2.5  3  3.5  / [GHz] (b) Figure 5.4  N F o f a cascode L N A . (a) N F vs. Vcs, and (b) N F vs. W .  A s discussed in Chapter 4, there is currently no robust noise optimization technique specifically developed for the sub-mW regime. In the absence o f such a technique, an alternative design approach is to use the knowledge gained in Chapter 4 to establish an initial biasing point and determine the sensitivity o f N F with respect to Vcs and W. For this purpose, a 90nm cascode L N A is simulated. F i g . 5.4(a) shows N F as Vcs o f M\ is  56  swept from 0.3V to 0.7V (W = 25pm). VB is adjusted accordingly as mentioned earlier. A s can be seen from F i g . 5.4(a), N F is inadequate when operating in the subthreshold region (VGS  = 0.3V). For a change o f Vcs from 0.4V to 0.7V, N F is reduced by 0.6dB at  the expense o f a 6.4x increase in the power consumption. F i g . 5.4(b) shows N F as the width o f both transistors are changed simultaneously from 10pm to 40pm (VGS  = 0.4V),  which results i n a 3.4dB N F improvement at the expense o f 4.2x the power consumption. This suggests that increasing Wis a more effective method for reducing N F .  It is also instructive to use the SpectreRF simulator to obtain a noise summary that shows the noise contribution o f components. F i g . 5.5 depicts the R F signal source and the L N A with the inductor models explicitly shown. The noise contributions from inductor parasitic resistances are significant, suggesting high-C? inductors are highly desirable. -  T o p 5 Noise Contributors :  1 (9.2%) 2 (8.6%) 3 (8.2%) 4 (7.3%) 5 (5.5%)  'tune  o  (52%)  Figure 5.5  5  R  Noise contribution o f the signal source and L N A components.  57  Linearity A s discussed i n Chapter 2, there are two types o f linearity performance for an L N A , which are characterized by the input-referred 3 -order intermodulation intercept point rd  (IIP3) and the input-referred l d B voltage compression point ( P l d B ) . 8  -4 -I 0.4  ,  ,  ,  ,  ,  0.45  0.5  0.55  0.6  0.65  V  G  S  1  0.7  M  Figure 5.6 IIP3 vs. VGS o f the cascode L N A .  Figure 5.7  PldB vs. VGS o f the cascode L N A .  Figure 5.6 and F i g . 5.7, respectively, show the IIP3 and P l d B o f the cascode L N A with 25pm transistors. Since linearity is a function o f gain, F i g . 5.6 and F i g . 5.7 also show the  58  linearity o f the L N A with gate widths adjusted to maintain a constant gain across Vcs- V  B  is adjusted accordingly as mentioned earlier. T w o observations can be made. First, IIP3 o f the L N A is indeed the highest in moderate inversion, suggesting that the V I P 3 peak can be exploited i n amplifier design. Second, the IIP3 and P l d B o f the L N A degrade as Vcs  increases.  This  is  an  interesting  observation  since  previous  analysis  and  measurements reveal that the M O S F E T IIP3 performance improves as Vcs increases [9], [10]. Lastly, it has been reported that linearity o f a M O S F E T in moderate inversion is not well studied [9] and that the IIP3 peaking for a C M O S short-channel transistor may not be easily applicable for R F L N A designs [10]. This is due to the fact that source degeneration tends to improve the overall linearity but dampen the peak.  Simulation Results The cascode L N A has been simulated using the B S I M 3 v 3 model provided for the S T Microelectronics 90nm C M O S process. On-chip inductors are modeled and designed using the A S I T I C electromagnetic field solver. F i g . 5.8 depicts the 7i-model for a 5nH spiral inductor used as L and Ld in Fig. 5.1, implemented using the thick metal layer o f a g  90nm technology. This inductor has a Q o f 7.3. To further improve Q, two metal layers can be used to reduce the series resistance o f the inductor. L is modeled similarly. s  4.96nH 4.59C2  o  O  Figure 5.8  7t-model o f a 5nH spiral inductor.  59  In this design, C and C m  tune  are assumed to be implemented using h i g h - g metal-insulator-  metal ( M I M ) capacitors. The widths o f both transistors are sized equally. Vcs is chosen to be 0.4V, slightly above the threshold voltage to exploit the high gjlp  in moderate  inversion. Table 1 is a summary o f component values. TABLE 1 SUMMARY OF L N A  COMPONENT VALUES  (V) L = L (nH) L (nH) VD D  s  d  s  C„(fF) Ctune (fF)  Wx/Lx (um) W /L 2  2  (um)  V , (V) in DC  V (V) B  1 5 2 480 720 25/0.1 25/0.1 0.4 0.9  Figure 5.9 shows the voltage gain A and N F o f the L N A . The voltage gain is 22.7dB in v  the 2 . 4 G H z band with a 3dB bandwidth o f around 3 0 0 M H z .  / [GHz] Figure 5.9  Gain and N F o f the proposed L N A .  60  As.depicted i n F i g . 5.10, an S\\ o f - 1 4 . 7 d B provides a good input impedance matching to 50Q. N F is 2.8dB which is acceptable for short-range applications. IIP3 and P l d B are +5.14dBm and - l O d B m , respectively. Table 2 summarizes the performance o f the L N A . The circuit consumes 943 u W from a I V supply.  o  -25 H 1.5  —-, 2  •——i  :  —i  /[GHz]  Figure 5.10  :  3  2.5  Si i o f the proposed L N A .  TABLE 2 S U M M A R Y OF L N A P E R F O R M A N C E  Gain (dB) . N F (dB) Sn (dB)  IIP3 (dBm)  22.7 2.8 -14.7 5.14  P l d B (dBm)  -10  i>Dc(uW)  943  /c(GHz) Gate L (pm)  2.4 0.09  61  1 3.5  Performance Summary Table 3 shows a performance comparison between the proposed L N A and low-power C M O S L N A s from recent literature. The performance comparison is further illustrated on the gain-power design space as in Fig. 5.11.  TABLE 3 COMPARISON OF C M O S LOW-POWER  LNAS  This work [3]'- [ 2 8 f [if [29]" [30]* [31] ' Gain (dB) 22.7 12 9.2* 13.6 13* 11.5 10.1 N F (dB) 2.8 4.6 3.6 1.8 3.6 3.4 2.9 -14.7 -5 -18 -10 -14 -10.1 5„(dB) <-10 5.14 7.2 -10 -3 +4 IIP3 (dBm) -7.25 PldB (dBm) -0.2 -10 -15.8 -8 -7 0.94 0.26 0.72 0.9 1 4 11.7 PDC (mW) 2.4 1 2.4 0-0.96 2.4 5.5 5.7 /c (GHz) Gate L (um) 0.09 0.18 0.18 0.09 0.18 0.18 0,13 * Power gain, Subthreshold d e s i g n , U W B design, Dual-banc design, #  J  [32f 12.8 1.4  #  -  +13.3  -  —  1  2  3  [33f 19 2.8 -14.5  -  14.4 15 2.0 2.4 0.18 0.18 Measurement  #  < 1mW 30  > 1 mW  i Best  o  T h i - Th  25DO T3, C  1 1lib  20-  9  [33],  15-  'ro  O  [32] , ' 0 6 #  J?]'  I  '(  1  '5  '05  10-  [311.  '05#  rooi [ZO j ,  [-3]  uo  •T30],'  )6  '04  Worse  0 0  '05  B  • [29],  5-  inc  1  2  3  4  5  Noise Figure (dB) Figure 5.11  Graphical illustration comparing recently published L N A s and this work.  62  A direct comparison o f L N A s listed i n Table 3 is a challenge as most L N A s have specifications that are tailored to work with the specific radio architecture and application. A n attempt is made to compare the proposed L N A to comparable low-power, relatively narrow-band L N A s . There are several aspects to note i n this comparison. First, the proposed work is based on simulation results and the others are based on measurements. When a chip is fabricated, its performance tends to degrade due to unaccounted parasitics and the assumptions made during circuit design. Second, not all the L N A s compared operate at the same frequency. Typically, more power is required to provide gain at a higher frequency, for example, the L N A s in [3] and [28] have lower power consumption. Third, all L N A s use the cascode topology or its variants, except for the ones i n [3] and [28]. The L N A in [3] uses a common-source topology, which exploits the relatively high M O S F E T output resistance in 0.18um C M O S . This L N A design may have difficulty delivering gain when ported to the 90nm technology. A l s o , the fact that it is targeted for lower frequency operation enables a subthreshold design, giving it an advantage in transconductance efficiency over other L N A s . The L N A i n [28] uses the common-gate topology as it needs to provide a large bandwidth for the targeted ultra-wideband application. Since this design and the dual-band L N A in [31] need to cover a greater bandwidth, a higher power consumption and a lower gain is inevitable. Fourth, the L N A in [32] employs an extra transistor for post-linearization, which results i n larger power consumption but the best linearity in the comparison. From F i g . 5.11, it can be seen that the L N A designed based on the proposed approach demonstrates a competitive gain and noise figure amongst low-power L N A s .  63  Chapter 6 Conclusions and Future Works  Conclusion In this thesis, a design methodology for low-power C M O S R F inductively degenerated L N A s has been introduced. The design approach presented in this dissertation differs from existing techniques i n that it begins with determining how device biasing affects gain, noise, linearity, and power consumption o f the amplifier to ensure a well-rounded design. Design plots have been used to help the circuit designer in understanding the fundamental  characteristics o f the M O S F E T in preparation to applying the design  methodology. T o demonstrate the technique, a fully integrated R F C M O S L N A is design and simulated. This 2 . 4 G H z 90nm cascode L N A achieves a voltage gain o f 22.7dB, N F of 2.8dB, IIP3 of+5.14dBm, and P l d B o f - l O d B m , while consuming 9 4 3 u W from a I V supply. This study has revealed that for designs that operate well below fr, a balanced design can be achieved by biasing the device just above the threshold voltage to exploit the high g /Io- This achieves low power consumption while avoiding the performance m  degradation associated with the subthreshold region. This observation is significant as many R F circuits for applications operating in the l o w - G H z range implemented in a modern C M O S technology can be designed based on the proposed technique.  64  Future Work Although this work has provided solutions to the challenges o f power-efficient design, it has also uncovered many interesting topics worthy o f further investigation. They often require a deeper understanding and characterization o f the device and are listed as follows:  1) Conventional power-constrained noise optimization methods proposed to target lowpower design have their limits. The techniques is based on first finding an optimal gate width, then biasing the device with the amount o f drain current allowed by the power constraint. In sub-mW designs, the large optimal gate width combined with a small drain current often force the device to be biased in the subthreshold region. When subthreshold operation is inadequate, such as insufficient frequency response, the technique is no longer applicable. A n effective noise optimization technique for the ultra-low-power design space is needed.  2) The proposed design methodology has been devised with a focus o f maximizing transconductance  efficiency, which translates to power-efficient  amplifier designs.  Although current low-power applications tend to have a more relaxed noise requirement, it is worthwhile to incorporate noise formulation into the transconductance efficiency framework so that the establishment o f biasing condition can include a quantitative noise analysis.  65  3) The effectiveness o f the proposed design methodology has thus far been verified with SpectreRF simulations. Silicon implementation is the next logical step to confirm simulation results.  4) There is only a narrow range o f biasing conditions that can exploit the high M O S F E T linearity performance i n moderate inversion. This narrow range demands for accurate biasing circuits; therefore, conventional L N A designs have not exploited this effect. Biasing circuits with improved accuracy may make the use o f the high M O S F E T linearity performance possible and reliable.  5) On-chip inductors are area intensive and do not scale well with technology. They are o f low quality factor and contribute substantially to the noise figure o f the amplifier. Improved on-chip implementation is needed.  6) Process variation is expected to increase as C M O S technology scales. Advanced layout techniques and robust calibration schemes for mitigating process variation is needed.  There is much work to be done in the area o f low power, deep submicron C M O S L N A design. The landscape o f analog circuit design is rapidly changing as technology scales to quantum levels, opening the designer to a new world o f challenges and possibilities.  66  References [I]  D.Shaeffer and T. Lee, " A 1.5V, 1.5 G H z C M O S low noise amplifier," IEEE Solid State Circuits,  v o l . 32, M a y  J.  1997.  [2]  T . - K . Nguyen, S.-K. Han, and S.-G. Lee, "Ultra-low-power 2 . 4 G H z image-rejection low-noise amplifier," Electronics Letters, v o l . 41, no. 15, July 2005.  [3]  D . B . G . Perumana, S. Chakraborty, C . - H . Lee, and J. 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