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UBC Theses and Dissertations

Calculation of the maximum frequency of oscillation for microwave heterojunction bipolar transistors Laser, Allan Paul 1990

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C A L C U L A T I O N OF T H E M A X I M U M F R E Q U E N C Y OF O S C I L L A T I O N F O R M I C R O W A V E H E T E R O J U N C T I O N B I P O L A R T R A N S I S T O R S Allan Paul Laser B. A. Sc. University of British Columbia, 1988 A T H E S I S S U B M I T T E D IN P A R T I A L F U L F I L L M E N T O F T H E R E Q U I R E M E N T S F O R T H E D E G R E E O F M A S T E R O F A P P L I E D S C I E N C E in T H E F A C U L T Y O F G R A D U A T E S T U D I E S D E P A R T M E N T O F E L E C T R I C A L E N G I N E E R I N G We accept this thesis as conforming to the required standard T H E U N I V E R S I T Y O F B R I T I S H C O L U M B I A June 1990 © Allan Paul Laser, 1990 In presenting this thesis in partial fulfillment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department of Electrical Engineering The University of British Columbia 2356 Main Mall Vancouver, Canada Date: Abstract A n investigation into various methods of calculation of the high frequency performance parameter fmax for microwave heterojunction bipolar transistors is presented. Two high frequency representations of the device are developed: equivalent circuits consisting en-tirely of lumped circuit elements, and a two-port network based on drift-diffusion equa-tions. Proper account is taken in these representations of the phase delay associated with carrier transit time through the base and base-collector space charge region. Also included are the charging time effects due to the various parasitic circuit elements asso-ciated with actual devices. A single-sided isolated structure is used in simulations and it is found that both representations yield remarkably similar characteristics for the be-havior of unilateral gain U with frequency. For devices in which the dominant factors limiting high frequency performance are the parasitic resistances and capacitances, it is found that U rolls off at 6 dB/octave through the region where U = 1 and the values predicted for fmax via these two methods, as well as via the widely-used analytical ex-pression involving fx and (RBCc)eff, a r e in agreement. However, when the periods of the oscillations are on the order of the carrier transit times, and the device parasitics are sufficiently low so as to not limit performance, resonance effects occur in U in the region where U = 1 and the prediction of fmax obtained via the two equivalent circuit approaches deviates markedly from the predictions of the analytical expression. n Table of Contents Abstract ii List of Tables v List of Figures vi Acknowledgement x 1 Introduction 1 1.1 Background 1 1.2 Motivation 3 1.3 Method of Analysis 5 1.4 Overview of Thesis 6 2 Model Development 7 2.1 The Intrinsic Transistor . . 7 2.1.1 Device Models 11 2.2 Development of Alpha . ... 13 2.3 Lumped Element Equivalent Circuits 21 2.3.1 The Hybrid-IT Representation 22 2.3.2 The T Equivalent Representation 30 2.4 Parasitica 36 2.5 The D D E Representation 47 2.6 High Frequency Gain 49 iii 2.7 Y -Parameter Derivation 52 2.7.1 V-Parameters of the T Equivalent Circuit 54 2.7.2 y-Parameters of the Hybrid-II Equivalent Circuit 65 2.7.3 V-Parameters of the D D E Equivalent Circuit 67 3 Results and Discussion 73 3.1 Unilateral Gain and Resonance 76 3.2 Comparison of Methods of fmax Calculation 83 3.3 Use of the Correct Alpha in the T Equivalent Circuit 87 3.4 Comparison of the Full Equivalent Circuit Representation to that of Das 89 4 Summary 95 4.1 Conclusions 95 4.2 Recommendations for Future Work 96 References 97 Appendices 104 A Rewriting a'a in terms of its real and imaginary components 104 B Unilateral Gain Determined From the D D E Equivalent Circuit 105 iv List of Tables 2.1 Calculation of // for the HBTs considered in this work 29 2.2 Comparison of values appearing in the expression for the complex collector admittance 34 2.3 Parameters for the H B T structure 37 3.1 Dimensional quantities of the single-sided isolated H B T structure 73 3.2 Component values used in the equivalent circuits. VBC = -3V 74 v List of Figures 2.1 One-dimensional model of the intrinsic transistor displaying current com-ponents 8 2.2 Four terminal network representation of the intrinsic transistor 10 2.3 Intrinsic admittance equivalent circuit 11 2.4 Comparison of the exact magnitude of /? from Eq. (2.18 ) to that predicted by the approximate expression of Eq. (2.21 ) 18 2.5 Comparison of the exact phase angle of /? from Eq. (2.18 ) to that predicted by the approximate expression of Eq. (2.21 ) 19 2.6 Mathematically exact equivalent circuit for the intrinsic transistor 23 2.7 Transmission line equivalent circuit 23 2.8 Replacement of transmission line by 7r-network 24 2.9 R3 and C3 transferred to the output circuit 24 2.10 Replacement of and fiVcb by their Norton equivalents 26 2.11 Figure (2.10 ) redrawn in the common-emitter configuration 27 2.12 Resulting circuit after input circuit current generator approximations. . . 27 2.13 Splitting of the current generator Ic into two parts 28 2.14 Cancellation of input current generator 29 2.15 Intrinsic hybrid-7r equivalent circuit 30 2.16 T equivalent network for a nonreciprocal fourpole. A reciprocal fourpole (zi2 = z2i) would be represented by a passive network, i.e., no voltage generator 31 2.17 Low frequency T equivalent circuit 32 vi 2.18 Simplified high frequency T equivalent circuit 34 2.19 Inclusion of diffusion capacitance de 35 2.20 T equivalent circuit redrawn in the common-emitter configuration 35 2.21 Inclusion of resistive parasitics in the hybrid-7r intrinsic circuit 36 2.22 Inclusion of capacitive parasitics in the hybrid-7r equivalent circuit. . . . 37 2.23 H B T device structure cross-section 38 2.24 Emitter structure detailing resistive components 39 2.25 Base structure indicating resistive components 40 2.26 Collector structure indicating resistive components 42 2.27 H B T structure indicating junction capacitances 43 2.28 Distributed resistive-capacitive network of the base and base-collector junc-tion 44 2.29 Hybrid-7r high frequency lumped element equivalent circuit 46 2.30 Complete high frequency T equivalent circuit 47 2.31 Complete high frequency D D E equivalent circuit 49 2.32 Available power and actual power for a two-port connected to a generator and a load (after Vendelin [48, pg. 27] ) 50 2.33 Required network for unilateral power gain [48, pg. 32] 51 2.34 Transistor in the common-emitter configuration represented as a two-port network. The voltage and current quantities shown are small-signal ac values 53 2.35 T equivalent circuit used to determine yn and 3/21 54 2.36 T equivalent circuit used to determine 7/22 and j/12 60 2.37 Hybrid-7r equivalent circuit used to determine yn and j / 2 i 65 2.38 Hybrid-7r equivalent circuit used to determine j / i 2 and 3/22 66 2.39 D D E equivalent circuit used to determine y n and y2\ 68 vn 2.40 D D E equivalent circuit used to determine yi2 and t/22 70 3.1 Variation of f m a x with VBC 75 3.2 Unilateral gain as a function of frequency at Jc = 5 x 104 A / c m 2 76 3.3 Comparison of U vs / using the D D E approach for high (VBC = — 1 V) and low (VBC = —5 V) collector junction capacitance at Jc — 5 x 104 A / c m 2 . SE = 1 ftm 79 3.4 U vs f for various values of emitter stripe width. Jc = 5 x 104 A / c m 2 . . 80 3.5 U vs / for various values of excess phase m. SE = 0.5/im, TB = 2.48 ps, 23. = 2.38 ps, and J c = 5 x 104 A / c m 2 81 3.6 fmax a s determined by extrapolation of lower frequency data for U for various emitter stripe widths. Jc = 5 x 104 A / c m 2 82 3-7 f m a x as determined by extrapolation of lower frequency data for U for various values of excess phase m. SE = 0.5 / i m , TB = 2.48 ps, ^ jc. = 2.38 ps, and J c = 5 x 104 A / c m 2 83 3.8 Comparison of Eq. (1.3 ), the extrapolated drift-diffusion representation, and the extrapolated lumped element equivalent circuit representation in the calculation of f m a x for three different emitter widths 84 3.9 Comparison of Eq. (1.3 ), the drift-diffusion representation, and the lumped element equivalent circuits in the calculation of f m a x for three different emitter widths 85 3.10 U vs / in the region where U = 0 dB 86 3.11 T equivalent circuit displaying intrinsic emitter current components. . . . 88 3.12 Comparison of the correct (a'0i'e or a'ie) and incorrect (cti'e) methods of assigning a value to the current source in the T equivalent circuit. SE = 1.0 /mi 89 via 3.13 Reduced hybrid-n equivalent circuit used by Das [24] 90 3.14 Comparison of fmax predicted via Das' y-parameters to that obtained using the classical formula. SE = 1-0 /xm 92 3.15 Implications of Das' assumptions. SE = 1-0 fim 93 ix Acknowledgement I am extremely grateful for the excellent guidance and constant encouragement provided by my supervisor, Dr. D.L. Pulfrey. His good nature and remarkable teaching abilities are deeply appreciated. I am also indebted to him for his efforts in the preparation of a paper based on the work done in this thesis. I would like to express my thanks to my colleagues Oon Sim Ang and Haosheng Zhou for their helpful discussions and especially to Simon Ho for developing the H B T device simulation program used extensively in my analyses. Thanks are also in order to David Gagne whose incredible mastery of UNIX saved me a great deal of time and effort on numerous occasions. I would like to thank Dr. R . K . Surridge of Bell-Northern Research, Ottawa for specifying the H B T device structure used in my simulations. The enlightening correspondence with Dr. M . B . Das of Pennsylvania State University regarding aspects of his work was extremely beneficial. Financial assistance provided by the Natural Sciences and Engineering Research Council and by Bell-Northern Research is gratefully acknowledged. Finally, I would like to express my sincere appreciation for the ongoing support of my family and close friends throughout my studies. x Chapter 1 Introduction 1 . 1 Background The high frequency performance advantages of the heterojunction bipolar transistor (HBT) were first recognized by Shockley [1] and later discussed in detail by Kroemer [2]. In his much-referenced paper, Kroemer describes how the wide band gap emitter of the H B T is an example of what he calls the central design principle of heterostructure de-vices: the use of energy gap variations as well as electric fields to control the flow and distribution of electrons and holes, separately and independently of each other [3]. This unique feature of heterostructures is especially important in bipolar devices where both electrons and holes determine the device characteristics. One of the first successful wide band gap emitter transistors was produced in 1969 by Jadus and Feucht in a GaAs-Ge system [4]. These devices achieved a common-emitter current gain of 13. Shortly thereafter, Hovel and Milnes fabricated functional HBTs with a current gain of 70 in a ZnSe-Ge system [5]. These initial devices suffered from lattice mismatch at the emitter-base interface which reduced the emitter injection efficiency [6]. This deficiency was eventually overcome as liquid phase epitaxial (LPE) growth techniques developed and the A l x G a x _ x A s / G a A s system was introduced as a good candidate for H B T fabrication [7]. The emitter region of an A L - G a i ^ A s / G a A s heterojunction bipolar transistor is com-posed of A l x G a ! _ r A s with the level of aluminum mole fraction x determining the band 1 Chapter 1. Introduction 2 gap of this region. By increasing x, the band gap of the emitter is made wider than the band gap of the GaAs base. Most of the energy band gap difference is taken up in the valence band. Thus, in an n-p-n bipolar transistor, a forward biased junction of this type would allow easy passage of electrons from emitter to base but would introduce a barrier to hole flow from base to emitter. This asymmetry of carrier flows leads to near unity injection efficiencies for these devices and high current gains. Soon after the AlGaAs/GaAs system was proposed for HBTs, devices displaying current gains of 350 were developed [8]. This jumped to 1600 only two years later and has since been pushed to a value as high as 12500 [9] [10]. In homojunction transistors, good injection efficiencies are achieved by making the doping concentration of the emitter much higher than that of the base. However this high emitter-base doping ratio leads to an increase in device parasitics such as base resistance and emitter-base junction capacitance, which in turn degrade high speed performance. The HBT's near unity injection efficiency is almost independent of the emitter-base dop-ing ratio. It is this fact that allows the H B T designer to reduce device parasitics and increase the current gain as well as the high frequency performance substantially. By employing low emitter doping the minority carrier storage in the emitter is made negli-gible, thus reducing the emitter-base junction capacitance. Along with this, high base doping is incorporated to decrease both base resistance and output conductance [11]. The high electron mobility of GaAs is another characteristic benefitting the high frequency performance of the AlGaAs/GaAs H B T since low transit times can be achieved. Early reports describing the high frequency performance of HBTs indicated a short-circuit unity current gain cutoff frequency fx of 1 GHz [12]. Improved fabrication techniques such as molecular beam epitaxy (MBE) and, more recently, metal-organic chemical vapor deposition (MOCVD) have made possible the development of advanced H B T structures incorporating layers with precisely controlled doping and compositional Chapter 1. Introduction 3 profiles. These techniques provide designers with the means to shape the energy band characteristics of these devices in an effort to optimize performance. Utilizing this free-dom, researchers have improved the high frequency performance of heterojunction bipolar transistors dramatically. In 1982, the highest level of / y was reported to be 11 GHz with a unity power gain frequency fmax of 4-5 GHz [13]. These figures-of-merit have increased steadily since then and continue to do so. fx values in the 40-50 GHz range were reported between 1984 and 1987 [11][14][15]. The maximum cutoff frequency was increased to 80 GHz and then to over 100 GHz in the following year [16][17][18]. Extremely high values for fmax have been reported from extrapolations of lower frequency 5-parameter mea-surements. Asbeck et al. indicated that fmax values well above 100 GHz were obtainable in 1987 and have since increased their estimate to above 200 GHz [11][19]. In addition to its use in high frequency applications, the AIGaAs/GaAs heterojunction bipolar transistor is gaining acceptance in the area of microwave power device develop-ment due to its high current handling capabilities. Another potential area where these structures may be utilized is in integration with other GaAs-based optical devices on a common substrate. This offers several potential advantages over discrete components including greater simplicity, smaller size, and lower cost. 1.2 Motivation The high frequency performance of a bipolar transistor is frequently characterized by the maximum frequency of oscillation fmax- This is the frequency at which the maximum available power gain as well as the unilateral power gain of the device are unity. The classical expression for fmax was developed by Pritchard [20], i.e. (1.1) Chapter 1. Introduction 4 where / „ is the frequency at which the common-base short-circuit current gain a has dropped 3 dB below its low frequency value, Rb is the base spreading resistance and Cc is the collector-base junction capacitance. fa is approximately equal to the common-emitter short-circuit unity current gain frequency fx [21, pg. 168][22]. fx is defined by the expression in which r e c is the emitter-to-collector signal delay time. Thus, another common expres-sion for fmax is [22] Lindmayer derived this formulation of fmax through a calculation involving the maximum available power gain for a junction transistor [23]. By determining the common-emitter /i-parameters for a junction transistor and then substituting these into a formula for available power gain, he solved for the frequency at which this gain was unity. He concluded that his expression for fmax is applicable to junction transistors with any impurity distribution in the base region, whereas Pritchard's original expression is only appropriate for the case of diffusion transistors. Eq. (1.3) is widely recognized as the most accurate analytical formula for the maximum frequency of oscillation and is thus the expression most often quoted in the literature. Recently the adequacy of Eq. (1.3) for predicting the performance of heterojunc-tion bipolar transistors has been questioned [24] [25]. Das [24] suggests that in devices where the collector-base depletion region signal delay is the dominant time constant, an effect he terms the transadmittance phase delay is responsible for degrading the de-vice performance, leading to lower fmax values than those predicted by Eq. (1.3). Con-versely, Pejcinovic et al. [25], who obtained fmax for some single-sided H B T structures via small-signal numerical calculations, found that the classical formula underestimates (1.3) Chapter 1. Introduction 5 fmax- These conflicting results prompted the present investigation in which fmax for some H B T structures is computed using a method that includes all of the effects known to influence high frequency performance. The objective is to attempt to resolve the issue of the adequacy of Eq. (1.3). 1.3 Method of Analysis In order to perform as small-signal amplifiers, transistors must be biased into their active region of operation by a suitable dc circuit. This circuit establishes an operating point that may be considered fixed relative to a small ac signal that is superimposed on the dc bias. Once the operating point is determined, the transistor can be represented by a small-signal model whose equivalent circuit can then be analyzed in order to determine the ac performance of the device. In all of the high frequency analysis that follows, the devices will be considered biased into the active mode and the model parameters that make up the equivalent circuit regarded as constant as far as the small-signal is concerned. In this work the values used for the equivalent circuit components are computed using the analytical model that has recently been developed by Ho [26]. The model uses a set of modified Ebers-Moll equations to represent the dc currents and voltages of uniform base n-p-n AlGaAs/GaAs HBTs. This model will be used to establish an operating point for devices of this type, around which the small-signal analysis may be performed. The approach we have taken to determine fmax involves the use of high frequency equivalent circuit representations of the H B T . We develop three circuits of this type. Included in these representations are all of the delay effects occurring within the H B T that serve to limit high frequency performance. Thus, all of the parasitic time constants Chapter 1. Introduction 6 as well as the phase delay due to carrier transit time in the base and base-collector space-charge region have been accounted for. The equivalent circuits are then used to find the admittance parameters associated with the device at a particular operating point. These y-parameters provide a means of calculating the unilateral power gain and the maximum frequency of oscillation. This method of analysis is similar to that used by Das [24]. However, in Das' work, several assumptions were made regarding the high frequency hybrid-7r equivalent circuit representation of the H B T and the j/-parameter derivations. These assumptions have been rigorously investigated and found to be inappropriate for the devices considered here. The performance characteristics obtained via the methods outlined in this thesis do not suffer from these inaccuracies. We have developed a technique that may be used to accurately determine fmax and provide insights as to the dominant processes involved in limiting this high frequency performance parameter. 1.4 Overview of Thesis A brief history of the development of the heterojunction bipolar transistor has been presented in Chapter 1. The potential that HBTs have for extremely high frequency performance has been indicated and the subsequent need for an accurate method of determining the high frequency figure-of-merit fmax has been established. In Chapter 2, three methods of modelling the H B T at high frequencies are developed: the hybrid-x equivalent circuit, the T equivalent circuit, and a two-port representation of the transistor based on drift-diffusion equations. The means by which these models may be used to calculate fmax is also outlined in this chapter. In Chapter 3, the results of calculations using these H B T representations as well as results based on Eq. (1.3) are presented and discussed. Finally, conclusions and recommendations are given in Chapter 4. Chapter 2 Model Development 2.1 The Intrinsic Transistor In analyzing a transistor to eventually arrive at its high frequency characteristics, it is convenient to consider an ideal transistor and determine the intrinsic properties of such a device. The intrinsic characteristics include only those phenomena engaging in the fun-damental transistor action. Omitted are consideration of the depletion capacitances and ohmic resistances which carriers encounter in passing through the emitter and collector bodies, the base, and the three terminal leads. A useful starting point is to consider the current components in a single dimension. A simple diagram displaying the electron and hole current components within the ideal-ized transistor is shown in Figure (2.1). Upper case symbols with lower case subscripts are used to represent the rms magnitude and phase of single-frequency small-signal ac quantities. These are considered to be impressed on the direct values which would be written with upper-case subscripts. The directions for the various electron and hole cur-rents are shown for the diffusion of carriers in an npn transistor. The terminal currents Ie and Ic are referenced in the conventional manner (positive current inwards) because we would like to represent the ideal transistor as a four terminal network. 7 n e is the electron charge injected from the emitter into the base. Ipe is the hole charge injected from the base into the emitter. If we consider positive charge flow in the x-direction in the interior of the device as a positive current, we can see that the total emitter current 7 Chapter 2. Model Development 8 e o v—> Collector Depletbn Region O C Emitter Depletion Region x Figure 2.1: One-dimensional model of the intrinsic transistor displaying current compo-nents. Ie is the negative of the sum of these two components. Incc is the electron charge leaving the collector edge of the collector depletion region while Ipcc is the hole charge arriving at the collector edge of the depletion region. The total collector current Ic is the sum of these two components. At high frequencies, even when there are no space charge region recombination-generation currents, it is necessary to distinguish between the currents associated with charge arriving at one side of the base-collector depletion layer and that leaving the other side because of the transit time of carriers through this region. The electron charge arriving at the base edge of the collector depletion layer Inc will not be equal to Incc. This inequality will also be true in the case of Ipcc and Ipc, the hole charge leaving the base edge of the depletion layer. In order to obtain an intrinsic model for the transistor, the response of the device to a small-signal voltage superimposed on the bias voltage must be determined. This entails solving the time-dependent diffusion equation for minority carrier density throughout the device. In the base region of an npn device, the following equation must be solved for electron density [27, pg. 165] d2n n — np 1 dn DnBdt (2.1) dx2 Chapter 2. Model Development 9 where n = electron density np = thermal equilibrium density of electrons in the p-type base LnB = electron diffusion length in the p-type base DUB — electron diffusion coefficient in the p-type base This equation must be solved for the case of generalized applied signals and must include the effects due to base-width modulation. In one dimension, this leads to a solution of the form n(x,t) — n0(x) + rii(x)e^wt where n0(x) is the dc solution and n\{x)e'wt is the ac solution. These two solutions can then be used to calculate the minority carrier current density in the base, jn(x,t) by substitution into the transport equation under the condition of no electric field existing in the base, i.e., jn(x,t) = q D n B ? ^ l (2.2) Multiplying this current density by the emitter area yields the electron component of the base current in(x, t). A similar procedure can be used to determine the remaining electron and hole current components shown in Figure (2.1). Each of the current components i(x, t) derived in this manner will be a function of veb(t) and vcb(t). For sinusoidally varying current, we can use i(x,t) = V2Iejwt (2.3) where I can be recognized as a complex phasor like those shown in Figure (2.1). As well, we have veb(t) = V2Vebejwt (2.4) vcb(t) = V2Vcbejwt (2.5) Substitution of Eqs. (2.3) through (2.5) into i(x,t) yields the complete phasor definition of each current I in terms of the two rms voltages Veb and Vcb. Furthermore, by adding the proper current components as outlined above, the total emitter and total collector rms currents Ie and Ic are obtained in terms of Veb and Vcb-Chapter 2. Model Development 10 This formulation of the currents lends itself well to a representation of the intrinsic device as a four terminal network. The currents and voltages associated with such a network are related by four small-signal admittances, or y-parameters. The four terminal network under consideration is shown in Figure (2.2). The node equations for this network Intrinsic Device -o + Figure 2.2: Four terminal network representation of the intrinsic transistor, are as follows h = 2/n V i + y i 2 V2 (2.6) h = y 2 i V 1 + y 2 2 V r 2 (2.7) Identifying subscripts 1 and 2 with the emitter and collector respectively, and the common terminal as the base, the coefficients of Veb and Vcb in the expressions for current obtained from the continuity equation solutions for the intrinsic transistor can be related to four intrinsic y-parameters. The equations describing the intrinsic transistor in the common-base connection are Ie = VllbVeb + 2/126 K t (2.8) Ic = 2/216 Vet + y22bVcb (2.9) From these equations, the common-base y-parameters for the intrinsic device can be defined individually as [28, pg. 142] L 2/116 = vc6=o the input admittance (2.10) Chapter 2. Model Development 11 2/126 = h vcb veb=o 2/216 = Ic Veb vcb=o 2/226 = Ic Vcb Veb=Q the reverse transfer admittance the forward transfer admittance the output admittance (2.11) (2.12) (2.13) Eqs. (2.8) and (2.9) also define an equivalent circuit in terms of the small-signal admit-tance parameters as shown in Figure (2.3). This circuit is a representation of the ideal transistor, or in other words, the intrinsic portion of the device. O-yeb /llb 321b veb '22b Figure 2.3: Intrinsic admittance equivalent circuit. 2.1.1 Device Models In order to characterize a transistor for small-signal operation, it is necessary to consider the additional parasitic or extrinsic components of a real device in performance calcu-lations. This is most conveniently accomplished by employing some form of intrinsic transistor representation to model the ideal device and adding to this discrete circuit elements to model the parasitics associated with the real device. Two forms of intrinsic transistor representation that are commonly used are: linear two-port networks like the one shown in Figure (2.3) and discrete lumped circuit element representations. Chapter 2. Model Development 12 To make use of the y-parameter representation of the ideal transistor, it is necessary to derive closed form expressions for the four intrinsic y-parameters given by Eqs. (2.10) to (2.13). This method was recently employed by Tiwari to examine the high frequency performance of HBTs [29]. The expressions for the four y-parameters may be obtained by solution of the transport equations in the drift-diffusion approximation as outlined in the previous section. Details of this type of analysis are presented in Section (2.5). In this work, a second method of intrinsic transistor representation has been examined. The H B T can also be represented by two well-known equivalent circuits that do not require the determination of the intrinsic admittance parameters. These are the hybrid-7r equivalent circuit and the T equivalent circuit. Each of these representations has been utilized by other researchers investigating the high frequency performance of HBTs. Recent work by Prasad et al. [30] relies on the use of the T equivalent circuit, while the hybrid-7r representation is used by Das [24]. These authors suggest that the use of these circuits is a valid approach to determining the maximum frequency of oscillation of an H B T . Prasad et al. do qualify their analysis by limiting its use to frequencies below those on the order of the reciprocal of the scattering times of carriers. They state that the validity of using a high frequency equivalent circuit hinges on the accuracy of the drift-diffusion approach taken to describe carrier dynamics in these devices. When the frequency of operation is close to the above-mentioned limit, quantum transport calculations must be invoked to describe the behavior of the carriers. At these frequencies, the drift-diffusion formulation becomes inappropriate so the equivalent circuits can no longer be used. A n upper limit to which this formulation may be considered valid is around 500 GHz [30]. This corresponds to a typical scattering time for electrons of 3 x 1 0 - 1 3 s. A l l of the frequency calculations performed in this work are well below this limit. It can therefore be safely assumed that the equivalent circuits employed in these analyses provide a good Chapter 2. Model Development 13 representation of the devices considered here. The high frequency representations for the entire H B T are arrived at by adding extrin-sic circuit elements to the intrinsic representations. These elements model the parasitics that arise due to junction capacitances and resistances encountered in the leads and bulk portions of an actual device. These elements are needed to represent the charging times occurring during operation that can potentially limit the high frequency performance of the transistor. In addition to the charging times there are signal delays associated with finite carrier transit time across the base and the base-collector depletion region that also influence the performance of the device at high frequencies. In the case of the linear two-port representation of the intrinsic transistor, these transit time delays are included in the j/-parameter expressions. The hybrid-TT and T equivalent circuit representations can be made to include these effects by modifying the common-base short-circuit current gain factor a. The high frequency definition of a is a fundamental component of both equivalent circuits. The following section details the derivation of this parameter. 2.2 D e v e l o p m e n t o f A l p h a Recent advances in H B T development have pushed the fx and fmax values of these devices above 100 GHz [18][31]. The periods of such signals are definitely on the order of the transit times of the carriers through the base and the base-collector depletion region. In the absence of base grading, the carriers move through these regions by the process of diffusion. If device parasitics are minimized, this diffusion process can become a limiting factor in the high frequency performance of the transistor. Sudden changes of minority carrier density injected into the base from the emitter are not reproduced faithfully at the collector because the carriers cannot respond fast enough to propagate the higher frequency signals. The parameter most seriously affected at high frequencies Chapter 2. Model Development 14 is the current gain a, which falls off rapidly when the period of the applied signal is of the order of the transit time. The current gain of a transistor is defined as the ratio of the output current to the input current under ac operation. When the collector-base terminals are short-circuited to ac, the current gain of the common-base circuit is known as the a (alpha) of the transistor, or the common-base short-circuit current gain. By definition, a is given by [32, pg. 172] a = - h. (2.14) J e Vcb=0 using the current references given in Figure (2.1). The value of a is close to but always less than unity for low and moderate frequencies of operation, due primarily to recombination processes occurring in the base. Referring to Figure (2.1) we can redefine alpha in terms of the various electron current components within the device. We have a Ine \ (LA / / n c c \ / h \ Ie ' \I71e ' V Inc ) \Incc' (2.15) Vc6=0 The four bracketed terms of this equation may each be isolated as a transistor parameter. The first factor is known as the emitter injection efficiency 7. - i = I j r (2-16) The negative sign is due to the reference direction given for positive Ie in Figure (2.1). The injection efficiency tells us what percentage of the total charge crossing the emitter is made up of electron current. The wider-bandgap AIGaAs emitter of the H B T creates a potential barrier that greatly suppresses the reverse injection of charge from base to emitter. This results in Ipe being negligible relative to Ine and the injection efficiency 7 being near unity for all current levels and frequencies of operation. We will make the assumption of unity 7 in this derivation. Chapter 2. Model Development 15 The major frequency variation in a comes from the base transport factor /?, where 0=j^ (2.17) Solution of the time-dependent minority carrier continuity equation in the base region provides expressions for the collector and emitter electron current components Inc and Ine. The resulting expression for 0 is a complex function of frequency and intrinsic transistor properties. For a non-graded base, Abraham defines the base transport factor as [33] where (2.18) WB is the quasi-neutral basewidth L n B is the minority carrier diffusion length in the base T n B 1 S the minority carrier lifetime in the base u> is the frequency in radians per second Thomas and Moll [34] describe this expression as having infinitely many poles along the negative real axis and a zero at infinity in the right half of the complex plane. Due to the complexity involved in determining the amplitude and phase characteristics of this ratio as a function of frequency, many authors describe a useful simplification whereby the exact infinite pole expression is converted to a single pole approximation [32, pg. 234][33][34]. The single pole expression is analogous to a resistance-capacitance or RC frequency cutoff characteristic and can be written as Chapter 2. Model Development 16 where u>p is the frequency at which the magnitude of the transport factor is 3 dB below its low frequency value 8Q. In actual devices, the phase characteristic of 8 exhibits more phase shift than the RC type cutoff predicts. Because of this discrepancy, an additional phase term is incorporated in the expression for 8 to more accurately describe the variation of 8 with frequency [33] jujm 0 = f ^ r (2-20) •* uip Here, ra is the excess phase in radians at the 3 dB frequency up. For uniformly doped base transistors, the excess phase is approximately 12 degrees so ra = 0.21 [33] [34]. When the base region has a built-in electric field, as is the case for graded base transistors, the excess phase at u>p is greater than that for the uniformly doped case [33]. For increasing values of aiding electric field strength, the excess phase and thus ra increase. The frequency at which the magnitude of the base transport factor has fallen by 3 dB from its dc value has been calculated by many authors and a value of litfa = 2A3%$- is B widely agreed upon [21, pg. 166] [27, pg. 188] [32, pg. 234]. This is an approximate value obtained from considerations involving the exact definition of 8, Eq. (2.18). Another approximation to the base transport angular cutoff frequency is taken to be ^ where TQ is the transit time of minority carriers across the base. This corresponds to a value of 2TT//3 = f ° r a non-graded base transistor. One can clearly see that this definition of B cutoff frequency is lower than the first definition and will therefore represent the worst case situation in this expression for 8. Thus we have 0 -jumrB 0 = Tir— (2-21) 1 + JUTB This approximate expression is good for frequencies up to ^ but is expected to deviate from the actual value for higher frequencies [30]. This is due to other high frequency poles in the exact expression for 8 becoming more dominant and influencing the behavior of Chapter 2. Model Development 17 the base transport factor. For the devices modeled here, a typical base transit time is 2.5 ps. This corresponds to a frequency of or approximately 65 GHz. Therefore, the use of Eq. (2.21) for these devices should be examined when considering frequencies above 65 GHz. To determine the extent of this error, a comparison was made between the exact ft of Eq. (2.18) and the approximate ft of Eq. (2.21) using a typical H B T with a 2 pm emitter stripe width to establish the required quantities. The details of the device structure are outlined in Section (2.4). Only the vertical dimensions of the device affect the value of ft. The H B T operation was simulated at a high current density of 5 x 104 A / c m 2 . This represents the upper limit of Jc, beyond which the Kirk effect may need to be taken into account [35]. Due to the fact that the base transit time will be longer at this current level (emitter-base depletion region at its narrowest), the error in ft will be at its highest value. The results are presented in Figures (2.4) and (2.5) and indicate that at 65 GHz, the approximate expression underestimates ft by ~0.9 dB. At the actual 3 dB cutoff frequency, up = 78 GHz, the error is ~1.0 dB. At 100 GHz, the error is ~1.15 dB. The error in the phase at the 3 dB cutoff frequency is ~7 degrees using a value of m = 0.21. This phase error changes very slowly with frequency and is still ~7 degrees at 200 GHz. This analysis would indicate that the error in ft is not serious at 65 GHz and does not increase rapidly above this frequency. The use of Eq. (2.21) is maintained in the ensuing development due to the clarity with which it displays magnitude and phase quantities. The third term in the expression given for a in Eq. (2.15) introduces effects occurring in the base-collector depletion layer at high frequencies. We must appreciate that the electron current Inc entering this depletion layer will not be equal to the electron current Incc which is leaving this region. This discrepancy is due to the transit time of the electrons through the depletion region. We take this into account by defining the barrier Chapter 2. Model Development 18 Frequency (Hz) Figure 2.4: Comparison of the exact magnitude of ft from Eq. (2.18) to that predicted by the approximate expression of Eq. (2.21). transit time factor ftm [32, pg. 322] ftm = (2.22) in the absence of avalanche multiplication. Avalanche multiplication occurs when the electrons entering the space-charge region have enough energy to produce electron-hole pairs by impact ionization. This could occur if the collector junction voltage was compa-rable in magnitude to the junction breakdown voltage, leading to Incc being larger than Inc. We can assume that under the normal bias conditions used in these simulations of the HBTs in the active mode, avalanche multiplication is not present and the definition for ftm is valid. Chapter 2. Model Development 19 Frequency (Hz) Figure 2.5: Comparison of the exact phase angle of ft from Eq. (2.18) to that predicted by the approximate expression of Eq. (2.21). The transit time of the electrons through the base-collector depletion region is in-versely proportional to their velocity. This velocity depends on the electric field existing in this region for low field values, but quickly approaches a limiting value for the high electric fields (>100 kV/cm) under consideration here. This limiting value is termed the saturation velocity vs. At a reverse bias of -3 V and for the doping density parameters provided in Table (2.3) the average electric field in the base-collector depletion region is around 120 k V / c m , which corresponds to a vs ~ 7.5 x 106 cm/s [26, pg. 73]. Effects due to velocity overshoot can occur in the GaAs depletion region but will not be considered significant here [36] [37]. The transit time TQ across the base-collector depletion layer Chapter 2. Model Development 20 width WBC 1 S simply WBC TC = — (2 .23) v.. Pritchard shows that the electron current leaving the collector depletion layer is given by [32, pg. 323] Incc — Inc 1 _ g - J W T C J(VTC (2 .24) The barrier transit time factor is which can be rewritten in the form I 1 — e~iwTc 8m = ^ = — (2 .25) I„r lUTn dm = sin 1 ui Tr e~>2 (2 .26) to display separately the magnitude and phase portions of this factor. The amplitude can be seen to be a far less responsive function of frequency than is the case for the phase shift. A typical transit time rc for the HBTs modeled in this work is 5 ps. At a frequency of JT^T) o r around 32 GHz, the amplitude portion of 8m is within 9 6 percent of its low frequency value while the phase shift has risen to 28 degrees. The barrier transit time factor essentially adds an additional delay between ac collector current and ac emitter current in the formulation of a. The final term in the definition of a is known as the collector-body multiplication factor a*. a * = y - (2 .27) •* ncc Ic is equal to the sum of Incc and Ipcc. Ipcc is the hole current due to diffusion across the collector body. It is generally small relative to Incc unless the collector-body multi-plication effect is occurring in the region. This will not happen under normal transistor operation so a* can be considered equal to unity. Chapter 2. Model Development 21 We can now present the full high frequency definition of a in terms of frequency and the dominant transit times TB and TQ. From Eq. (2.15) we have (2.28) With the emitter injection efficiency 7 and the collector-body multiplication factor a* both approximately unity for an H B T in the normal active mode of operation, the common-base short-circuit current gain a is reduced to (2.29) which upon expansion becomes a = sin ( ^ ) 2 o-l-1 + JWTB When u> — 0 we know that a = a0 so the final form of this expression is a sin 2 -ju/(mTj3+^£) (2.30) (2.31) 1 + JUTB From this definition it is clear that the dominant phase term in the frequency response of alpha is that due to the transit time through the base-collector space-charge region. and Tg are approximately equal quantities in the devices studied here so the contribution due to mrg, where m = 0.21 for a uniform base region, is only one-fifth that of the ^ L term. 2.3 Lumped Element Equivalent Circuits The lumped element equivalent circuit is a combination of electric circuit elements con-nected in a particular manner such that the electrical characteristics of this arrangement are equivalent to those of the device under consideration. It is a tool used to relate the Chapter 2. Model Development 22 electrical nature of the device to the mathematical formulations necessary to describe device operation. Despite the fact that its name implies equality, the equivalent circuit should not be considered an exact representation of the device. It is based on an ideal one-dimensional model of a junction transistor and thus cannot possibly be equivalent to the electrical elements that make up the actual device which have non-ideal qualities and operate in three dimensions. As long as we understand the equivalent circuit's limitations, we can make use of the simplicity it affords without worrying about its so-called equivalence. We will make use of two different lumped element equivalent circuits in this work in order to verify that the results obtained are not due to an insufficiency in one circuit or the other. 2.3.1 The Hybrid-LT Representation A fundamental aspect of bipolar transistor operation is the diffusion of minority carriers through the base region. This process can be described by exactly the same equations that apply to a leaky RC transmission line. So far as an equivalent circuit is concerned, the most accurate (one-dimensional) circuits are those in which transmission lines ap-pear. By representing the base region as a distributed RC transmission line we can obtain an ac equivalent circuit of the intrinsic transistor by simply including an ideal amplifier at the end of the line with a voltage gain of K [38, pg. 161]. The result is shown in Figure (2.6). The next step is to convert the ideal amplifier to a more analytical form. One such representation of the intrinsic transistor is shown in Figure (2.7) [28, pg. 212]. This circuit includes a combination of a voltage generator and a current generator to represent the ideal amplifier having a frequency independent voltage amplification fac-tor K = ^ [39] [40]. In Figure (2.7) it is helpful to note that all of the terminals of the transistor have been labeled with lower case letters. These represent internal nodes and define the intrinsic portion of the transistor. External nodes will be labeled upper case Chapter 2. Model Development 23 R R C G' • • • ^^^^y-Figure 2.6: Mathematically exact equivalent circuit for the intrinsic transistor. R Je e o—WW— bo-R •MW-C G' R • • . —WW" 0 CD'--ob Figure 2.7: Transmission line equivalent circuit. in the equivalent circuits yet to be derived. This transmission line equivalent circuit is "exact" insofar as the model for the ideal uniform base transistor is exact. We could simply add the extrinsic parasitic elements of the actual H B T to the intrinsic circuit of Figure (2.7) to arrive at a complete equivalent circuit for the device. However, the transmission line is too complicated to be particularly useful, so approximations are made in order to reduce this circuit to a manageable form. In transmission line theory, the distributed nature of the line as shown in Figure (2.7) is generally represented by line equations that may be solved for terminal conditions [41, pp. 68-70]. To simplify the analysis, the line equations can be transformed into an equivalent circuit representation. A 7r-circuit can be used to model the line by suitably defining the impedance or admittance of each element in the 7r-network. The series Chapter 2. Model Development 24 impedance of such a circuit is made up of the series impedance per unit length of the line multiplied by the length, and similarly for the shunt admittance. This leads to the simpler network of resistors and capacitors as shown in Figure (2.8). The two equal resistors R\ and R3 account for the recombination losses in the base region that serve to reduce Ic relative to Ie. R2 is the equivalent series resistance of the line. C\ and C 3 each represent one-half of the effective capacitance of the line. This circuit can be further simplified by noting that R3 and C 3 are connected in parallel across the constant voltage source uVcb. This means that they may be transferred to the output circuit where, in order to maintain power and phase requirements, they take on the new values of R3 /fi and / / C 3 respectively as displayed in Figure (2.9). Figure 2.8: Replacement of transmission line by 7r-network. e o-R2 Jcm R 1 bo Figure 2.9: R3 and C 3 transferred to the output circuit. Chapter 2. Model Development 25 At this point, the values of the equivalent circuit elements can be determined. If the collector-base terminals are short-circuited to ac (Vcb = 0) the terminal currents are given by Ic = <*0Ie (2.32) h = (1 - a0)Ie (2.33) The low frequency value of alpha, a 0 , is used here and then later modified to include the high frequency effects found in the complete hybrid-7r equivalent circuit. The incremental resistance of the forward-biased emitter-base junction is defined as [28, pg. 108] r. = (2.34) diE and represents the resistance presented to small changes in the voltage across the junction. VEB and %E are the instantaneous total voltage and current at the junction. When considering small-signal ac operation of the transistor, the incremental changes are taking place over a linear region about the operating point and thus may be replaced by rms ac quantities. Thus, we may write [28, pg. 213] re = ^  (2.35) Using this as well as Eqs. (2.32) and (2.33), the two resistances in the input circuit can now be defined in terms of the incremental emitter resistance and alpha. Ri = lT = n Ve\r = (2-36) h (1 - cx0)Ie 1 - aQ R2 = ^  = ik_ = Ii (2.37) Ic a0le ct0 The capacitance C i is an intrinsic device parameter and can be recognized as the diffusion capacitance Cde in the base region. The diffusion capacitance arises as a result of the minority carrier charge stored in the base during normal operation. The ac emitter-base Chapter 2. Model Development 26 junction voltage causes a time variation of this charge. This effect can be represented as a capacitance. For a uniform base region of constant resistivity, Cde is proportional to %E, the instantaneous total emitter current, according to [28, pg. 213] qiE Wl Cde = (2.38) kT 2DnB The next step in this transition process is to replace the voltage generator fiVcb and resistance R2 by their Norton equivalents. The resulting circuit including the derived element definitions is shown in Figure (2.10). e o-bo-1 - OL„ -o c -ob Figure 2.10: Replacement of R2 and fiVcb by their Norton equivalents. The hybrid-7r equivalent circuit is normally presented in the common-emitter config-uration. The circuit of Figure (2.10) has been redrawn in this form in Figure (2.11). Two approximations are made at this point to simplify the input circuit. The first involves the input current generator a0fiVcb/re. For a transistor operating in the active mode of the common-emitter connection, the voltage gain, Vce/Vbe, is much greater than unity. Vce is equal to the sum of Vj,e and Vcb so we have vh > 1 be Vbe + Vcb Vbe V* Vbe Chapter 2. Model Development 27 bo-1 - CL„ e o-a0 a0pVa ' c e lid - aa) i—AW—i 'cb -oe Figure 2.11: Figure (2.10) redrawn in the common-emitter configuration. From this we can see that Vce ~ and the value of the current generator will become a0pVce/re. This generator can be assumed negligible in comparison to Ic due to p, being a very small quantity. Since Ic is flowing in a connecting lead, the input current generator may be removed. However, before this is done it is necessary to consider how it affects the output circuit. Because it is proportional to Vce, the input generator will load the collector and emitter terminals as if it were a resistance of value The addition of otoH this resistance and the removal of the generator are shown in Figure (2.12). bo-1 - an -de je_ aa e M(7 - a j i—AW— i de -OC eo- -o e Figure 2.12: Resulting circuit after input circuit current generator approximations. Chapter 2. Model Development 28 Without affecting the circuit behavior, the current generator Ic can be divided into two generators that have a common junction at the emitter as shown in Figure (2.13). From Eq. (2.37) we can see that re - a0) i—vVW—i -oc eo oe Figure 2.13: Splitting of the current generator Ic into two parts. _ CtpVeb (2.39) The generator on the input side supplies a current proportional to the voltage across its terminals which means that it can be replaced by a resistance of value vbe -veb (2.40) This negative resistance cancels out the positive resistance of the same value across the same terminals. The resulting circuit is shown in Figure (2.14) with the output current generator represented in such a way as to emphasize its dependence on Vbe. The final step taken in the reduction of this circuit to the hybrid-7r form relies on the fact that the quantity fx is very small. It has a value of [28, pg. 20] kT dWB H = (2.41) qWB dVBc This expression was determined for a typical device structure used in this work. The details of the H B T are presented in Section (2.4). Using the technique of finite difference Chapter 2. Model Development 29 Ml - a0) i—AW—i o c eo oe Figure 2.14: Cancellation of input current generator. calculus around a suitable operating point, fi was calculated at various current levels and collector junction voltages. The results of this analysis are summarized in Table (2.1). The value of p is independent of emitter size and largely independent of collector current. As expected, the value of p is indeed small and with a0 ~ 1 we see that the bridging Jc(A/cm2) 12 -> 50000 VBE (V) 1.34 - • 1.59 VBC (V) -0.5 -1.0 -2.0 -3.0 -5.0 V- ~2.7 x 10~5 ~2.4 x 10~5 ~2.0 x 10" 5 ~1.8 x 10" 5 ~1.5 x 10~5 Table 2.1: Calculation of fi for the HBTs considered in this work. resistance ^i2ao) w m ^ e v e r v large and can therefore be assumed an open circuit. We also recognize the output resistance as the inverse of the output conductance g0. The equivalent circuit developed thus far is suitable for low frequency representation of the intrinsic transistor because of the use of a0 in the circuit elements. To provide an accurate model under high frequency conditions, it becomes necessary to include the phase difference effects associated with alpha as discussed in Section (2.2). The magnitude of a0 is modified by the additional term — ' at higher frequencies and the 2 phase is increased by the factor cu(mrj3 + Thus we can improve the intrinsic hybrid-7r Chapter 2. Model Development 30 equivalent circuit by replacing each occurrence of a0 with its modified, high frequency equivalent Ci0 = ft„ sm (? ) 2 (2.42) Note that Eq. (2.42) is a replacement for the low frequency value of a. a itself is a terminal property (jf-^j given by Eq. (2.31). The factor (1 + JOJTB)'1 appearing in Eq. (2.31) is recovered when jfc is calculated using a'a from Eq. (2.42) in the final form of the intrinsic hybrid-7r high frequency equivalent circuit shown in Figure (2.15). oc eo oe Figure 2.15: Intrinsic hybrid-7r equivalent circuit. 2.3.2 The T Equivalent Representation The T equivalent circuit derives its name from the two-port network representation of an active device as shown in Figure (2.16) [42, pg. 244]. The impedance parameters (•Zii> -?i2> ^ 21; ^ 22) shown in this diagram are defined by the network equations Vi = 211/1 + 212/2 (2.43) V 2 = 221/1 + Z22/2 (2.44) The high frequency equivalent circuit of the transistor may be developed from these impedance parameters by first considering their low frequency values. This leads to a purely resistive representation of the various components of the intrinsic transistor. Reac-tance effects are then introduced to this circuit by considering the physical phenomena of Chapter 2. Model Development 31 (z2r 212)h zll - z12 z22 ' z12 '72 Figure 2.16: T equivalent network for a nonreciprocal fourpole. A reciprocal fourpole (z 1 2 = z2\) would be represented by a passive network, i.e., no voltage generator. charge storage and phase delay in the base region as well as phase delay and capacitance in the base-collector space charge region of the device. At low frequencies, only the resistive portions of the impedance parameters are im-portant and can be identified as [28, pg. 145] 1^1 — 1^2 Z\2 Z22 — ^ 12 z 2 \ — Z\2 = rk = r„ (2.45) (2.46) (2.47) (2.48) The output branch of the T equivalent circuit can be modified using Norton's theorem so that the active element becomes a current generator of value Identifying I\ and I2 as l'e and Ic respectively, the circuit may be redrawn as shown in Figure (2.17). It should be noted that the input current l'e is not the full rms ac emitter current Ie. It will be found later on when we introduce the high frequency effects occuring in the intrinsic transistor that Ie comprises an additional reactive component. The various elements of the circuit of Figure (2.17) can be obtained by developing the 2-parameters for the ideal model and then utilizing the definitions given in Eqs. (2.45) to (2.48). This was done by Chapter 2. Model Development 32 e o-b o -Figure 2.17: Low frequency T equivalent circuit. o c ob Pritchard who obtained the following definitions [32, pg. 215] , 1 p(l-cx0) re = — ; 9e 9c p 9c r TTI / 9c ftp - P 1 j " 9c otn where 9e 9c V cb Vcb=0 Iezzconst (2.49) (2.50) (2.51) (2.52) the emitter conductance the output conductance in the C B connection and p is the open circuit reverse voltage transfer ratio defined in Eq. (2.41). The approx-imations to rc and are made by noting that p is a very small quantity. The feedback due to the Early effect (changes in base width due to changes in collector voltage causing variations in emitter current) is reflected by the parameter which, at low frequencies, can be of the same order of magnitude as -V = r e , the ac resistance of the forward biased emitter junction. This complicates the expressions for r'e and r'b at these frequencies and is an unnecessary burden in our development. In order to simplify these expressions, Chapter 2. Model Development 33 it is necessary to consider high frequency operation of the transistor, and thereby stray from a purely intrinsic circuit development. We must introduce the effect of the parasitic collector junction capacitance CJC which occurs in parallel with the output conductance g'c. Thus, the T-parameters become complex and may be written as [32, pg. 216] r. = (2.53) 9e \9c + JUCJC) » (2.54) r (g'c+juCjc) - -r-, T-?^? (2-55) = c!0 (2.56) Note that a 0 has been replaced by the high frequency definition of alpha, ct0 of Eq. (2.42), that includes effects due to phase delay. The capacitive component of the complex collector admittance (g'c + JOJCJC) dominates at high frequencies and effectively removes the terms containing the factor g \ ^ ) C j c > since this quantity will now be very small. In order to confirm this assertion, the quantities of interest here were computed for the H B T devices considered in this work. The expression for CJC is given in Section (2.4). g'c is given by Pritchard as [32, pg. 183] '1 - a„l 2IC Oi„ (4) m CJC and g'c are both dependent on device structure so various emitter widths were exam-ined. The results are tabulated below and indicate that the capacitive term is approx-imately three orders of magnitude larger than the conductive term at the frequencies of interest. The frequencies used in the analysis correspond to the range of fmax for a single-sided isolated H B T structure. SE refers to the emitter stripe width. The emitter length was 100 / M I I . Making use of the approximation mentioned above, the T equivalent circuit may be redrawn as shown in Figure (2.18). Chapter 2. Model Development 34 J c ( A / c m 2 ) 12 -»• 50000 VBE (V) 1.34 - • 1.59 SE (pm) 0.5 VBC (V) -3.0 -1.0 CJC (fF) 48.8 66.2 u; (rad) 6.28 x 109 -> 6.28 x IO11 "Cjc (S) 3.1 x IO"4 -»• 3.1 x IO"2 4.2 x IO"4 -> 4.2 x IO"2 5; (S) 4.1 x IO"9 -> 1.7 x IO"5 5.5 x IO"9 -» 2.3 x IO"5 SE (rim) 1.0 VBC (V) -3.0 -1.0 C J C (fF) 65.1 88.2 u (rad) 6.28 x IO9 -> 3.77 x IO11 U ; C J C (S) 4.1 x IO"4 ->• 2.5 x IO"'2 5.5 x IO"4 3.3 x IO"2 9c$) 8.2 x 10~9 -» 3.4 x IO"5 1.1 x 10~8 4.6 x IO"5 Table 2.2: Comparison of values appearing in the expression for the complex collector admittance. Another component that can be added to this high frequency representation is the effect due to minority carrier storage in the base region. Recalling from the previous section, the time variation of this charge due to the ac emitter-base junction voltage can be represented by a diffusion capacitance Cde- This capacitance is added in parallel with the resistance r e , resulting in the circuit of Figure (2.19). This circuit may be redrawn in e o- -WvV l = r -o c -JC bo- -ob Figure 2.18: Simplified high frequency T equivalent circuit. Chapter 2. Model Development 35 e o bo-' w » -o c Figure 2.19: Inclusion of diffusion capacitance Cde-the common-emitter configuration as shown in Figure (2.20) which includes an additional component g0 to account for the possibility of finite output conductance when operating in the C E mode. This is the final form of the pseudo-intrinsic T equivalent circuit to which the various additional parasitic components may be added. This is done in the following section. > . . 'de' eo--JC t'. -OC -o e Figure 2.20: T equivalent circuit redrawn in the common-emitter configuration. It is beneficial to note that the current generator is controlled by the resistive part of Ie flowing through r e , and proportional to ct0 given by Eq. (2.42) [43, pp. 292-293]. This is in contrast to the equivalent circuits presented by Prasad et al. [30] and Asbeck et al. [11] which use the full common-base current gain expression of Eq. (2.31) multiplying l'e as the current source. We investigate the error that this discrepancy introduces in Section (3.3). Chapter 2. Model Development 36 2.4 Parasitica The circuits of Figures (2.15) and (2.20) contain all of the elements that are inherently associated with the minority carrier transport between emitter and collector. However there are parasitic elements associated with practical HBTs that must be considered if we wish to obtain accurate terminal characteristics. The parasitic regions contribute resis-tance and capacitance between the external terminals and the internal intrinsic transistor regions. At low frequencies these parasitics are limited to the series resistance occurring in the leads and bulk regions of the device. Figure (2.21) includes these resistive elements into the hybrid-ir representation. At the high frequencies that are of primary interest E Figure 2.21: Inclusion of resistive parasitics in the hybrid-7r intrinsic circuit. here, junction capacitance becomes very important and must be represented between the base and collector and the base and emitter. Adding to the circuit of Figure (2.21) we obtain Figure (2.22). The parasitic elements are a function of device structure. The HBTs simulated in this work have been produced by researchers at Bell-Northern Research in Ottawa. The Chapter 2. Model Development 37 Bo—WA Rc WA—oC Figure 2.22: Inclusion of capacitive parasitics in the hybrid-7r equivalent circuit. following derivations pertain to the device structure shown in Figure (2.23). The material parameters are given in Table (2.3). This device structure is referred to as a single-Layer # Material Thickness Doping A l or In (A) (cm" 3) mole fraction x 1 n + - In a ; Gai_ I As 300 1 x 10 1 9 0.6 emitter cap 2 n + - In x Ga!_ r As 300 1 x 10 1 9 0.6-0 linear 3 n + -GaAs 1000 3 x 10 1 8 0 emitter 4 n-Al r Gai_3 ;As 2000 5 x 10 1 7 0.3 base 5 p + -GaAs 1000 3 x 10 1 9 0 collector 6 n-GaAs 4000 5 x 10 1 6 0 collector buffer 7 n + -GaAs 4000 3 x 10 1 8 0 Table 2.3: Parameters for the H B T structure. sided isolated H B T . The single sided structure is in contrast to a pyramidal structure in which base and collector contacts exist on both sides of the emitter region. Provision is made for an isolation region below the base contact. By using either proton or oxygen implantation, the region to the right of the isolation boundary is damaged to such an Chapter 2. Model Development 38 oxide, sidewall C contact $a>—* i isolation r t i p Figure 2.23: H B T device structure cross-section. extent that the p-n junction is destroyed, i.e., the base-collector capacitance is effectively eliminated in this region, thereby serving to reduce CJC- Thus, high speed performance is improved. The three resistances RB, RC and RE introduced in Figure (2.21) can be computed by analyzing the appropriate portion of the H B T structure. The emitter series resistance RE is made up of three components: the contact resistance REC-, the bulk resistance of the cap layers REX-, and the bulk resistance of the emitter REI- Figure (2.24) isolates the emitter structure of the H B T . The emitter contact resistance is defined as REC = PcE SELE (2.58) where pec is the specific contact resistivity of the emitter and LE is the emitter length. Chapter 2. Model Development 39 Figure 2.24: Emitter structure detailing resistive components. The bulk resistance of the three cap layers can be defined by summing the contri-butions of each layer. With N referring to doping concentration, W indicating layer thickness, and employing the subscript notation introduced in Figure (2.24), we can write REX = where Pcap\Wcap\ + PcapuWcapW + pcaplWcap2 SELE 1 (2.59) Pcapl — Pcap\2 — Q^caplpncapl 1 <Z-Wcapl2//ncapi2 1 p qNcaP2rincap2 and fincapi, Pncapu, Pncap2 are the electron mobilities of I n 0 . 6 G a o . 4 A s , I n o . 3 G a o . 7 A s , and GaAs respectively. The mobilities of the two InGaAs layers are constant values obtained by linearly interpolating between the intrinsic electron mobility of GaAs (8500 cm 2 /Vs) and InAs (33000 cm 2 /Vs) and assuming that the mobility of InxGai_;,;As has the same doping dependence as GaAs [26, pg. 70]. Chapter 2. Model Development 40 The devices considered in this work do not incorporate a graded emitter structure, so the resistance of the bulk emitter REI is simply R e i m *<W*-x.) ( 2 6 0 ) JE^E where _ 1  P E qNEfiNE and [LNE is the electron mobility of Alo.3Gao.7As. XE is the depletion layer width on the emitter side of the heterojunction. Summing the three extrinsic components of emitter resistance we obtain RE = REC + REX + REI (2.61) The total resistance of the base region Rg is also made up of three components: the contact resistance RBC, the bulk resistance of the extrinsic base region RBXI a n d the bulk resistance of the intrinsic base region RBI- The pertinent area of the device is displayed in Figure (2.25). !«• sF J IP— SEB %* SB  ly^Y/^V—3*Rbc B a s e Collector Figure 2.25: Base structure indicating resistive components. The base contact resistance is defined as [44] R b c = V ^ i c o t h {sB]^j (2.62) Chapter 2. Model Development 41 where pcs is the specific contact resistivity of the base and L& is the base length. R$B is the sheet resistance of the extrinsic base layer defined as * S B = gNBfhB(WB - XBC) ^ where pps is the hole mobility in the base, NB denotes base doping concentration and XBC is the depletion layer width on the base side of the base-collector junction. The resistance of the extrinsic bulk region is given by [45, pg. 216] RSBSEB t c t C A \ RBX = r (2-64) LB The resistance of the intrinsic bulk region beneath the emitter stack is a function of the geometry through which carrier flow takes place. Carriers move vertically when under the emitter and horizontally when passing through the boundary between the intrinsic and extrinsic base regions. This flow pattern can be accounted for by defining the resistance as [45, pg. 216] RBI = % ^ (2.65) where 1 RdR ' S B qNBriPB(WB - XBC - XBE) is the sheet resistance of the intrinsic base region and XBE is the depletion-layer width on the base side of the heterojunction. The base resistance is thus RB — RBC + RBX + RBI (2.66) Three components also make up the total collector resistance Rc'. the contact resis-tance Rec-, the resistance of the n + buffer layer RCBI a n d the resistance of the intrinsic n layer Rci-Chapter 2. Model Development 42 Figure 2.26: Collector structure indicating resistive components. With reference to Figure (2.26), the collector contact resistance is [26, pg. 74] •<C PcC (2.67) where Rsbuf = qNbufUnbujWbuf Nbuj is the doping concentration of the n + collector buffer layer and p,nbuf is the electron mobility in this layer. pcc is the collector specific contact resistivity and Lc is the collector length. The bulk resistance of the buffer layer is a function of two different geometries and is defined as [45, pg. 216] RCB = RCB + RCB _ RsbufScD RsbufSsC 3Lc Lc The resistance of the intrinsic collector region is given by pc(WCi - Xc) where Rei = Pc SCDL B (2.68) (2.69) 1 qNciPnC Chapter 2. Model Development 43 is the resistivity of the n-GaAs collector. Xc is the depletion-layer width on the collector side of the base-collector junction, Wei is the thickness of the intrinsic collector, Nci is the doping density in this region and pnc is the electron mobility. The total parasitic resistance due to the collector is Rc = Rec + R-CB + Rci (2.70) The remaining parasitic elements shown in Figure (2.22) are the two junction capaci-tances CJE and CJC associated with the emitter-base and base-collector depletion-layers respectively. Figure 2.27: H B T structure indicating junction capacitances. Referring to Figure (2.27) the two junction capacitances are defined as SELE^E^B CJE = CJC = 6EXE + CBXBE SCDLB^C (2.71) (2.72) Xc + XBC where e#, eg and ec are the permittivities of the n-Alo.3Gao.7As emitter, p + -GaAs base, and n-GaAs intrinsic collector regions respectively. XE and Xc are the depletion-layer Chapter 2. Model Development 44 widths in the emitter and collector respectively. XBE and XBC are the base depletion-layer widths next to the base-emitter and base-collector interfaces respectively. By representing all of the parasitic components as lumped circuit elements, a sim-plification has been made. The regions that introduce the parasitics are complex three-dimensional distributed resistive-capacitive regions. The complex networks that would be necessary to accurately represent these regions would again lead to an unwieldy equiv-alent circuit, as was the case with the initial transmission line representation. The circuit of Figure (2.22) is generally a suitable compromise to the actual situation. We will however introduce an additional element to take into partial account the distributed nature of the region involving the base-collector junction. We do this because we can easily verify that the entire capacitance CJC associated with the base-collector depletion-layer is not charged through the full base resistance RB as Figure (2.22) would suggest. A distributed network representation of the region we are interested in is shown in Figure (2.28). Figure 2.28: Distributed resistive-capacitive network of the base and base-collector junc-tion. The collector junction capacitance can be modeled as the sum of three capacitive Chapter 2. Model Development 45 components: Ccc, Ccx a n d Cci- Ccc is the capacitance associated with the non-implanted region of the junction below the base contact. It can be defined as Ccc = S - I s o ^ c (2.73) •X-BC + <&C The region between the contact and the emitter stack contributes Ccx = (2-74) •A-BC • J^C The last component is that portion below the emitter stack. Cc, = -3^22- (2.75) •*BC + -Ac As defined previously, the overall base resistance RB = RBI + RBX + RBC- Only part of the total junction capacitance CJC is charged through the full RB, namely Cci-The remaining portions of the junction capacitance are charged through a fraction of RB- Because of this, an effective base-collector RC time constant ( i ? sCc) e / / should be defined as opposed to the simple combination of RB and CJC [44] [46] [47]. By examining Figure (2.28), ( i ?BCc) e / / can be defined as follows [26, pg. 75] RBX (RBCc)efj = CCI(RBI + RBX + RBC) + Ccx{—^—h RBC) + CCCRBC (2.76) This is the time constant used in the expression for fmax given by Eq. (1.3). The signal delay time r e c appearing in this formula is defined as T e c = TE + TB + TSCR + TCC (2.77) where [26, pp. 68-75] T~E = re(CJE + CJC) + RECJC the emitter charging time Wl TB 2D — the base transit time nB TC TSCR = the base-collector space charge region signal delay time TCQ = RCCJC the collector charging time Chapter 2. Model Development 46 In an effort to incorporate this distributed network into the equivalent circuit repre-sentation of the H B T , the distributed base-collector capacitance is modeled by splitting it into two parts [24]. We can see that the entire capacitance must have the intrinsic collector node as a common terminal. An inner effective capacitance C c , acting between this node and the intrinsic base node can be defined as {RBCC)BU Cc RB (2.78) The second part, referred to as the outer effective capacitance Chc follows as Che = (Cci + Ccx + Ccc) — C c (2.79) The total base resistance is maintained as a single lumped element. This representa-tion is a compromise between the full distributed network and the simple case of Chc = 0 and Cc = CJC- The final form of the hybrid-7r equivalent circuit that will be used in subsequent analysis is shown in Figure (2.29). Rc Figure 2.29: Hybrid-7r high frequency lumped element equivalent circuit. In Figure (2.29) the assumption that fi is a very small quantity has again been applied, Chapter 2. Model Development 47 leading to the removal of the capacitance term fiCde- Also, the resistive and capacitive components across the intrinsic base and emitter nodes have been renamed as follows rv = -±-r (2.80) Cr = Cde + CJE (2.81) The T equivalent circuit for the intrinsic transistor is similarly modified to include extrinsic parameters by including the same lumped circuit elements to the circuit of Figure (2.20). The final form of the T equivalent circuit is shown in Figure (2.30). Cbc Cc E Figure 2.30: Complete high frequency T equivalent circuit. 2.5 The D D E Representation A two-port network representation of the intrinsic transistor has already been introduced in Figure (2.3). The y-parameters used in this representation are based on drift-diffusion Chapter 2. Model Development 48 equations (DDE). They are arrived at by solving the current transport equations in the drift-diffusion approximation. These common-base intrinsic y-parameters ( y n b , y i26, V2\bi y 2 2 t ) have been derived by Pritchard [32, chapter 5] Yh geZcothZ —gcZcschZ -$mgeZcschZ $mgcZcothZ (2.82) where ge = is the ^ n input dc conductance gc = y^wj1 is the output dc conduct; ance [32, pg. 237] The parasitic elements associated with an actual device could simply be added as lumped circuit elements to the circuit of Figure (2.3), but it is computationally more efficient to incorporate some of these extrinsic elements into the intrinsic y-parameters. To this end, we include the emitter junction capacitance CJE and the intrinsic collector capacitance Cci in the definitions of y n(, and y226 respectively. Thus we have (2.83) geZcothZ + JUICJE —gcZcschZ -f3mgeZcschZ f3mgcZcothZ + juCci We can represent the intrinsic transistor in the common-emitter configuration by defining common-emitter y-parameters (yn e , Vi2e, V2ie, 2/22e) as [32, pg. 164] (2.84) (</ll6 + 2/126 + y2l6 + 2/226) "(j /126 + V22b) -(2/216 + y226) 2/226 Another parasitic element that can be incorporated into the intrinsic y-parameters is the intrinsic base resistance RBI defined in Eq. (2.65). This leads to the definition of four new intrinsic common-emitter y-parameters which we will denote by y'Ue, y ' 1 2 e > Vne Chapter 2. Model Development 49 and y'22e. We have [32, pg. 247] Vile y'ne Vile 2/lle 1 + Ramie yi2e 1 + -Rs/yiie 2/21e ^1 3/22, RBW lie 1 + Rsiyiu RBiy\2ey2\e (2.85) (2.86) (2.87) (2.88) 1 + RBiyile The remaining extrinsic elements are added to the two-port equivalent circuit rep-resentation as lumped elements. This leads to the complete equivalent circuit for the actual device shown in Figure (2.31). Ccc + Ccx RBC+RBX Bo W A r Jlle RC dr.. .© hie Vbe J22e Figure 2.31: Complete high frequency D D E equivalent circuit. 2.6 High Frequency Gain For signal amplifier applications, a transistor must have gain, i.e., the transistor must be capable of providing an output signal that is an amplified version of the input signal. Chapter 2. Model Development 50 There are several definitions of power gains involved in amplifier design. The definitions are a result of power flow considerations from the generator to the load as shown in Figure (2.32). Lossless Matching Network M , Available Two-port Pin Actual Lossless Matching Network M 2 P avo Available T Actual Figure 2.32: Available power and actual power for a two-port connected to a generator and a load (after Vendelin [48, pg. 27]). The transducer power gain is defined by GT — j>^-The available power gain is defined by GA = ^p£~-The power gain is defined by G = By utilizing the lossless matching networks as shown in the diagram, the two-port may be conjugately matched to either the load or the generator. Conjugate matching allows for maximum power transfer between two stages. When M 2 is used for conjugate matching, Pi = Pav0 and GT — GA- When M i is used for conjugate matching, P , n = PA and GT = G. Thus, for simultaneous conjugate matching, GT = GA = G and the maximum available power gain, G M A X , will occur. Chapter 2. Model Development 51 The small-signal gains of a transistor can be calculated in terms of its two-port pa-rameters using circuit analysis techniques. The expression for Gmax is [49] Gmax — 2Re(yu)Re(y22) - #e(j/i22/2i) + \i)Re{y22) — i?e(t/i2t/2i)] - [3/122/211 (2.89) where the y are the conventional small-signal admittance parameters for a two-port net-work defined by Eqs. (2.6) and (2.7). The maximum available power gain of a transistor may be used as a device figure-of-merit. However, with completely arbitrary source and load terminations, under certain conditions the amplifier may oscillate which means that Gmax becomes infinite. The transistor is said to be potentially unstable for that particular frequency and bias condition. In this case, some sort of stability criterion such as pre-scribed bandwidth must be imposed on the maximum gain. To achieve an unconditionally stable situation, the definition of maximum gain may be modified. Mason proposed one such figure-of-merit in his unilateral power gain U [50]. This is the maximum available power gain of a unilateral structure. With reference to Figure (2.33), unilateralization is achieved via the feedback network by conspiring to make Y12 = 4 = 0 at a specified 1 frequency. Mi and M 2 are again used for simultaneous conjugate matching. Unilateral Lossless Matching Network T v, Feedback Network Two-port T v2 Lossless Matching Network M 2 Figure 2.33: Required network for unilateral power gain [48, pg. 32]. Chapter 2. Model Development 52 power gain is defined as u = \V2i - yial (2.90) i[Re(yn)Re(y22) - Re(y12)Re{y21)} This is the highest possible gain that an active two-port could ever achieve [48, pg. 33]. The frequency at which U becomes unity defines the boundary between an active and a passive network. This is also true of C 7 m o x , the maximum available gain. Calculation of the frequency at which this occurs will yield the same value using either gain definition. This frequency is referred to as the maximum frequency of oscillation, fmax- Thus, by determining the gain from the above definitions in terms of the transistor y-parameters, we can solve for the maximum frequency of oscillation under various bias conditions. We chose to use U as the vehicle for calculating fmax because the unilateral gain is unconditionally stable. This leads to fewer convergence difficulties when solving for 2.7 F-Parameter Derivation Equation (2.90) defines the unilateral power gain of a transistor in terms of small-signal admittance parameters. Any of the immittance z, y or hybrid h, g parameters could have been used in this expression. We chose to use y-parameters because they lend themselves well to circuit analysis. For the sake of clarity, the defining equations will be repeated here with reference to the circuit of Figure (2.34). U = l. ^l = ynvi + ynv2 (2.91) H = y2\V\ +y22V2 (2.92) and yn - — (2.93) vi „ 2 = o Chapter 2. Model Development 53 Figure 2.34: Transistor in the common-emitter configuration represented as a two-port network. The voltage and current quantities shown are small-signal ac values. 2/12 = — V2 *2 2/21 = — 2/22 i i v2 v2=0 7J1=0 (2.94) (2.95) (2.96) By replacing the transistor within the boxed region of Figure (2.34) with each of our high frequency equivalent circuits in turn, the y-parameters defined by Eqs. (2.93) through (2.96) can be calculated. This will provide us with three sets of y-parameters that may be substituted into the expression for U. Solving for the frequency that gives U = 1 leads to a value for fmax as obtained via the various equivalent circuits. It will be found that the hybrid-7r and T equivalent circuits yield the same result. This may be regarded as a verification of the validity of these two equivalent circuit representations. It should be noted that the admittance parameters defined by Eqs. (2.93) through (2.96) are circuit parameters of the entire H B T . The y-parameters introduced in Sec-tion (2.1) were those associated with the intrinsic device. The distinction is very impor-tant. Chapter 2. Model Development 54 2.7.1 F-Parameters of the T Equivalent Circuit The j/-parameters defined by Eqs. (2.93) and (2.95) may be obtained by assuming a small-signal voltage vx is applied at the input terminals of the two-port and the output terminals are shorted. The currents i\ and ii can by identified as the base and col-lector terminal currents respectively. The high-frequency T equivalent circuit with the appropriate connections is shown in Figure (2.35). 13 Figure 2.35: T equivalent circuit used to determine yn and j / 2 i -From Figure (2.35), VBb = VBE - VbE = vi - vbe - ieRE VBC = vBE - VCE = Vi + icRc Vce = VcE - VeE (2.97) (2.98) Chapter 2. Model Development 55 = -icRc-ieRE (2.99) Vbc = VbE - VcE = vbe + icRc + ieRE (2.100) and ie = k + ic (2.101) By summing the currents at node B we can write H = *3 + U = jwCbcVBc + ^P- (2.102) Substituting Eqs. (2.97), (2.98) and (2.101) into (2.102) and collecting like terms gives us R R 1 1 Summing the currents at node e yields the following equation ie + i'e = i6 + i7 = jwCnVbe + g0vce (2.104) Recognizing that i'e = -vbe/re and substituting Eqs. (2.99) and (2.101) into (2.104) gives us ib(l + g0RE) + ic(l + g0Rc + gQRE) = vbe(— + jwCv) (2.105) r„ Turning to node c we can write ic = i7- i3 - i5 - o!Je gQvce - jwCbcvBc - jwCcvbc + -2—1 (2.106) Chapter 2. Model Development 56 Substituting Eqs. (2.98) through (2.101) into (2.106) yields H{9ORE + jwCcRE) + ic[l + g0Rc + g0RE + jw(CcRc + CCRE + CbcRc)] = vi(-jwCbc) + vbe(^-jwCc) (2.107) re To simplify the remaining analysis, the various real and imaginary components of Eqs. (2.103), (2.105), and (2.107) will be renamed as follows. Refer to Appendix A for the separation of ot0 into its real component a x and its imaginary component a2. cx = 1 + | ^ (2.108) c2 = ^ (2.109) KB c 3 = -wCbcRc (2.110) * = IT <2-nl) KB c5 = wCbc (2.112) dx = l+g0RE (2.113) d2 = \+g0RE+9oRc (2.114) d3 = - (2.115) d4 = wCn (2.116) ei = 9ORE (2.117) e2 = wCcRE (2.118) e3 = l+goRc+g0RE (2.119) e4 = w(CcRc + CCRE + CbcRc) (2.120) e5 = -wCbc (2.121) e6 = - (2.122) e 7 = —-wCc (2.123) Chapter 2. Model Development 57 Using Eqs. (2.108) through (2.123) in Eqs. (2.103), (2.105) and (2.107) we can write three new equations in terms of ib, ic, ui , and vbe: h(ci) + ic(c2+jc3) = vi(c4+jc5) + vbe(-c4) (2.124) ib(di) + ic{d2) ' = vbe(d3 + jd4) (2.125) 4 ( e i + i e 2 ) + ic(e 3 +je 4 ) = Wi0 ' e 5 ) + vbe(e6 + je7) (2.126) We can express vbe in terms of ib and ic via Eq. (2.125). Replacing vbe in Eq. (2.124) by substituting in Eq. (2.125) yields ib(fi + i / 2 ) + » c ( / 3 + JIA) = wi(c4 + j c s ) (2.127) where fi - ci + —1— _ c4d2d4 de c4d2d3 73 = C 2 + c4d2d4 fi = c3 — de and de = dl + d\ Replacing vbe in Eq. (2.126) by substituting in Eq. (2.125) yields ib(h + jfe) + *'c(/7 + jfs) = UiO'cs) (2-128) where /s = ei - ^j-{e6d3 + e7d4) de h = e2 ~ -r{e7d3 - e6d4) Chapter 2. Model Development 58 h — e 3 — -j-(e6d3 + e7d4) « 6 / 8 = e4 - -^(e7d3 — e6d4) de The two currents % and ic can each be solved for in terms of vt by eliminating each one in turn through the simultaneous use of Eqs. (2.127) and (2.128). We can eliminate ic by adding the following two equations h(h + j / 2 ) ( / 7 + jfs) + tc(/ 3 + i / 4 ) ( / 7 + jfs) = «l(C4 + jC5)(f7 + jfs) - » 6 ( / 5 + i / 6 ) ( / 3 + i / 4 ) - » c ( / 7 + i / 8 ) ( / 3 +J /4 ) = " « ! ( j e 6 ) ( / 3 + j f4) The result we obtain is h(gi + 392) = v\{g3 + J9A) (2.129) where 91 — / 1 /7 — /2 /8 — 75/3 + / s /4 92 = / 2 / r + / i / s - Uh ~ UU 93 = C4/7 - c 5 / 8 + e 5 / 4 94 = C5/7 + c 4 / 8 - e 5 / 3 We now have ib in terms of i»i which allows us to write an expression for yn. We have from Eq. (2.93) JL = j l = 93 + 3^ ( 2 1 3 Q ) «1 «1 9l + .7 #2 Eq. (2.90) requires the real part of j / n which is simply r, / x 939i+9492 / o i o i \ ^ e ( ^ i i ) = 0 , 2 (2-131) 5l "T </2 A similar approach is taken to eliminate ib from Eqs. (2.127) and (2.128) yielding ic(g5 + 39e) = vi(97 + 39s) (2.132) Chapter 2. Model Development where 95 = J 3 / 5 — f*f& — / 7 / 1 + /s/2 96 — ^ / s + fsfe ~ f&fi — / r / 2 97 — c4f5 - c 5 / 6 + e 5 / 2 9s = c5f5 + c 4 / 6 - e 5 / i From Eq. (2.95) we can write H ^ 97 + 39s , „ 1 Q Q N 2/21 = — = — = r-r— (2.133) Vi Vi g5 + jg6 Eq. (2.90) requires the real part of y 2 1 which is D / \ 9795 + 9896 /n,OA\ # e(2/2i) = 0,0 (2.134) 95 ~t~ 9e Moving now to the remaining two {/-parameters, y 1 2 and y22, w e must apply Kirchoff's laws to a new circuit. In this case the input terminals are shorted and a small-signal voltage v2 is applied at the output terminals of the two-port as shown in Figure (2.36). From Figure (2.36), VBb = vBE - VbE = - v b e - i e R E (2.135) VBC = VBE — VCE = i c R c - v 2 (2.136) Vce = VcE - VeE = v 2 - i c R c - i e R E (2.137) Vbc = VbE - VcE = vbe - v2 + icRc + ieRE (2.138) Chapter 2. Model Development 60 Bq—•—vvw Rc h Figure 2.36: T equivalent circuit used to determine t/22 and yi2. By summing the currents at node B we can write ib = «3 + U • n , vBb = JwCbcVBc + - 5 -KB Substituting Eqs. (2.135), (2.136) and (2.101) into (2.139) yields • /, . RES , • (RE 1 RB RB Summing the currents at node e results in jwCbcRc) - v2(-jwCbc) + vbe(-—) KB (2.139) (2.140) ie + ie = 6^ + 17 - jwC*Vbe + g0Vc (2.141) Substituting Eqs. (2.137) and (2.101) into (2.141) gives us ib(l + g0Rs) + *c(l + 9oRc + 9oRE) = v2(g0) + vbe(— + jwC*) r„ (2.142) Chapter 2. Model Development 61 Summing the currents at node c yields * .' ic = % 7 - i z - i 5 - a0ie = g0vCe - jwCbcvBc - jwCcvbc + - 2 — i (2.143) Using Eqs. (2.136), (2.137), (2.138) and (2.101) in (2.143) results in H{9ORE + jwCcRE) + ic[l + g0Rc + 90RE + jw(CcRc + CCRE + CbcRc)\ = v2[9o + jw(Cbc + Cc)} + u t e (— - JtvCe) (2.144) The real and imaginary terms that involve v2 in Eqs. (2.140), (2.142) and (2.144) will be renamed as follows ce = -wCbc (2.145) d5 = g0 (2.146) e 8 = 9o (2.147) e9 = w(Cbc + Cc) (2.148) Using the necessary expressions from Eqs. (2.108) through (2.123) as well as (2.145) through (2.148) we can rewrite Eqs. (2.140), (2.142) and (2.144) in their simpler forms h{ci) + ic{c2+jc3) = V2(JCQ) + vbe(-c4) (2.149) + ic{d2) = v2(d5) + vbe(d3+jd4) (2.150) *&(ei+je 2) + ic(e3 + je4) - v2(es + je9) + vbe(e& -f je7) (2.151) Using this set of three equations, we will first eliminate vbe from Eqs. (2.149) and (2.150) by adding the following two equations *b(ci)(<*3 + jd4) + ic(c2 + jc3)(d3 + jd4) = v2(jco)(d3 + jd4) + vbe(-c4)(d3 + jd4) ib(di)(c4) +ic(d2)(c4) = v2(d5)(c4) + vbe(d3 + jd4)(c4) Chapter 2. Model Development 62 The addition yields *kOi + jh2) + ic(h3 + jh4) = v2(h5 + jh6) (2.152) where hi = c\d3 + d\c4 h2 = c\d4 h3 = c2d3 — c3d4 + d2c4 h4 = c3d3 + c2d4 hs = d$c4 — Ced4 h6 = ced3 Eliminating vbe from Eqs. (2.149) and (2.151) by a similar set of simultaneous equa-tions yields hih + jk2) + ic(fc3 + jk4) = v2{kh + jk6) (2.153) where ki = cie 6 + exc4 k2 = c1e7 + e2c4 h = c 2e 6 - c 3 e 7 + e 3c 4 k4 = c 3 e 6 + c 2 e 7 -f e4c4 k5 = e 8c 4 — c^er k6 = CQ66 + e 9c 4 We now have two equations (2.152) and (2.153) in terms of only the two currents ib and ic and the voltage v2 as required. We can eliminate ib from these two equations by Chapter 2. Model Development 63 adding the following set ib(ht + jh2)(k1 + jk2) + ic(h3 + jh4)(ki + jk2) = v2(h5 + jfc 6)(fc 1 + jk2) -ib(h + jk2)(hi + jh2) - ic(k3 + jk4)(h], + jh2) = -v2(k5 + jh){hx + jh2) The result is ic{mi + jm2) = v2(m3 + jm4) (2.154) where mi = h3ki — h4k2 — k3hi -f k4h2 m2 = h4k\ + h3k2 — k4h\ — k3h2 m3 = h5ki — h6k2 — k5hi + k6h2 m4 = + h5k2- k&hx - k5h2 From Eq. (2.154) we can write an expression for y 2 2 . Using Eq. (2.96) ii ic m3+jm4 2/22 = — = — = — : — (2.155) v2 v2 mx + jm2 The expression for U requires the real part of y22 which is m 3 m x + m4m2  R e { m 2 ) = ml + ml ( 2 , 1 5 6 ) We now eliminate ic from Eqs. (2.152) and (2.153) using the same method. This gives us ib(m5 + jm6) - v2(m7 + jm8) (2.157) where m 5 = h\k3 — h2k4 — k\h3-\- k2h4 m,Q - h2k3 + h\k4 — k2h3 — k\h4 m7 = h5k3 — h6k4 — k5h3 + k6h4 m 8 = h6k3 + h5k4 — k6h3 — k5h4 Chapter 2. Model Development 64 From Eq. (2.94) we have J/12 = — = — = —:— (2.158) v2 v2 m5+jm6 The real part of y\2 is also required and is simply m 7 m 5 + m 8 m 6 Referring to Eq. (2.90) we see that it is necessary to find an expression for the square of the magnitude of yi2 — y2\. Subtracting Eqs. (2.158) and (2.133) yields V\i-y2\ = —:— (2.160) TI3 + jn4 where ni = rn7g5 - m$g6 - m5g7 + m6g$ n2 = m&g5 + m7g6 - m5g8 - m6g7 "3 - m5g5 - m6g6 n4 - m6g5 + m5g6 The square of the magnitude of y 1 2 — y2i is | y i 2 - . 2 i | 2 = ^ § (2.161) '*3 T ''4 A l l of the terms used in the expression for unilateral power gain have now been deter-mined in terms of the circuit components that make up the high-frequency T equivalent circuit. By calculating the value of each element at a particular frequency u> and current level Ic, the value of U can easily be determined. Using an iterative technique, the fre-quency at which all of the y-parameters conspire to make U unity can be found. This is the maximum frequency of oscillation. Chapter 2. Model Development 65 2.7.2 F-Parameters of the Hybrid-II Equivalent Circuit A similar approach to the one taken in the previous section is used to determine the small-signal y-parameters from the hybrid-IT equivalent circuit representation of the het-erojunction bipolar transistor. We begin by shorting the collector and emitter terminals and applying a small-signal voltage i>i between the base and emitter terminals as shown in Figure (2.37). RB h h -vwv ' Cbc ic Rc -WW—?C Figure 2.37: Hybrid-7r equivalent circuit used to determine yu and j / 2 i -Referring to Figure (2.37) we can see that Eqs. (2.97) through (2.103) apply to this circuit in the exact form that they are written. By summing the currents at node e we obtain ie = i6 + i7 + i8 H vbe JwCvVbe -f 1- g0VCe + Vbe (2.162) Using Eqs. (2.99) and (2.101) we have 1 a ib(l + 9oRE) + » c(l + g0Rc + g0RE) = vbe(— + — + jwCv) (2.163) Chapter 2. Model Development 66 Noting that = ^ from Eq. (2.80), we can reduce this to t t ( l + g0RE) + t c ( l + g0Rc + g0RE) = vbe{- + jwCT) (2.164) re This is the same equation derived previously as Eq. (2.105). If we now sum the currents at node c, we can write lc = "be + *8 — *3 — *5 r e i a = —Vbe + g0VCe - jwCbcVBc ~ jU)CcVbc (2.165) re This is equal to Eq. (2.106) and when expanded will yield Eq. (2.107). Both equivalent circuits yield the same three equations used to derive j/n and t/2i- It is obvious that if we proceed from here we will obtain the previously denned Eqs. (2.130) and (2.133). Figure (2.38) illustrates the hybrid-ir equivalent circuit with input terminals shorted and output terminals sourced with a small-signal voltage v2. B Figure 2.38: Hybrid-7r equivalent circuit used to determine j/x2 and y22-Once again we see that several equations derived for the T equivalent circuit in the last section may be applied to Figure (2.38) in their exact form. These include Eqs. Chapter 2. Model Development 67 (2.135) through (2.140). Applying Kirchoff's current law to node e we obtain • i • i • i a'o = jwC„vbe + — + g0vce + —vbe (2.166) Using Eqs. (2.137) and (2.101) for vce and ie gives us 1 a ib(l + goRs) + *'c(l + 9oRc + 9ORE) = v2(g0) + vbe(— + + jwC„) (2.167) Replacing with ^—^ reduces this to Eq. (2.142) as we might expect. Finally, summing the currents at node c results in c^ = Vbe + «8 — «3 — «5 re i oc = —Vbe + 9oVCe ~ jwCbcVBc - jwCcVbc (2.168) re This is equal to Eq. (2.143) which can be expanded to get (2.144). The same three circuit equations have again been arrived at. If we were to continue in an effort to find J/22 a n d r/12, the end result would be Eqs. (2.155) and (2.158). Thus we see that both lumped element equivalent circuit representations of the H B T provide the same set of y-parameters to be used in the expression for unilateral power gain. This is to be expected because each equivalent circuit represents the same transistor in the same bias condition. There can only be one fmax value for such a device. 2.7.3 F-Parameters of the DDE Equivalent Circuit As done for the previous two equivalent circuits, we begin by shorting the collector and emitter terminals of the high frequency D D E equivalent circuit and applying a small-signal voltage v\ between the base and emitter terminals as shown in Figure (2.39). From Figure (2.39) we have Chapter 2. Model Development 68 RBC+RBX H B9 WA— -© 'He CCC + ' 2 Ccx © " , © J2U be R, AWv—pc J22t Figure 2.39: D D E equivalent circuit used to determine yX\ and y2i. Vce = VcE - VeE = - i c R c - i e R E (2.169) Vbc = VbE - VcE = vbe + icRc + iERE (2.170) ie = h + i c (2.171) By summing the currents at node b we can write lb = l\ + 12 + y\2eVce = y'llevbe + ju(CCC + CCx)Vbc + y'l2eVce (2.172) Substituting Eqs. (2.169) to (2.171) into (2.172) and collecting like terms gives us ib[l-ju(Ccc + Ccx)RE + y'i2eRE] ~ -y'12e(Rc + RE) + MCcc + Ccx)(Rc + RE)} -Vbe yiu+MCcc + Ccx)] = o (2.173) Chapter 2. Model Development 69 Summing the currents at node c gives us ic = h - H + ynevbe = y22eVce-ju(CcC + CCx)vhc + y21eVbe (2.174) Substituting Eqs. (2.169) and (2.170) into (2.174) and collecting like terms yields ib\V22eRE + MCcc + CCX)RE) + ic[l + y'22E(RC + RE) + MCcc + CCX){RE + Rc)] -Vbe[y'21e-MCcc + CCx)] = 0 (2.175) Applying Kirchoff's voltage law around the loop containing the voltage generator i>i yields iB[RE + RBC + RBX] + iCRE + vbe = «i (2.176) The various coefficients of the currents and voltages in Eqs. (2.173), (2.175) and (2.176) may be rewritten as follows a = 1 - MCcc + Ccx)RE + y'12ERE (2.177) b = -y'i2e(Rc + RE) + MCcc + Ccx)(Rc + RE) (2.178) c = y'lle + JU{CCC + CCx) (2.179) d = y22eRE + MCCC + CCx)RE (2.180) e = 1 + y'22e(Rc + RE) + MCcc + CCx){RE + Rc) (2.181) / = y^-MCcc + ccx) (2.182) 9 = RE + RBC + RBX (2.183) h = RE (2.184) Using these definitions, Eqs. (2.173), (2.175) and (2.176) may be rewritten in the simpler form aib - bic - cvbe = 0 Chapter 2. Model Development 70 dib + eic - fvbe = 0 gib + hic + vbe = vx Solving this set of simultaneous equations for the ratios of 7 ^ and ^ yields «6 2/n = — ce + fb and 2/21 = — = Vi afh + gfb + ae - f db + cge — cdh af — cd (2.185) (2.186) Ui afh + gfb + ae + db - f c<je — cdft Expressions for the remaining two y-parameters may be obtained by referring to Figure (2.40) in which the input has been shorted to ac and a voltage generator v2 applied across the collector-emitter terminals. From Figure (2.40), RBC+RBX H B<?—WA- b Ccc + '2 J'n V Ccx R, f—WA—PC CP".© J22t 0 v2 Figure 2.40: D D E equivalent circuit used to determine j / 1 2 and y22. Vce = VcE — VeE = v2 — icRc — ieRE Vbc = VbE - VcE = vbe - f icRc + ieRE - v2 (2.187) (2.188) Chapter 2. Model Development 71 By summing the currents at node b we obtain ib = H+ ii + Vi2eVce = y'lleVbe + MCCC + CCx)Vbc + y[2eVc Substituting in Eqs. (2.187), (2.188) and (2.171) yields (2.189) ib 1 - JLo(CCC + CCX)RE + y'l2eRE] ~ ic [-y'i2e(Rc + RE) + MCcc + Ccx)(Rc + RE)} Vbe Vile + MCcc + cCx)\ = Vl[y'l2e ~ Ju{CCC + Ccx)] Summing the currents at node c gives us (2.190) ic = h ~ *2 + y2leVbe = y'22evce ~ MCCC + CCx)vbc + y2nvbe (2.191) Substituting Eqs. (2.187), (2.188) and (2.171) into (2.191) and collecting like terms yields ib[y'22eRE + MCcc + CCx) RE] + *c[l + y22e{Rc + RE) + MCcc + Ccx)(RE + Rc)] + Vbe[-y'2\e + MCCC + CCx)] = v2[y'22e + Ju{CcC + Ccx)] Summing the voltages around the input loop results in iB[RE + RBC + RBX] + iCRE + vbe = 0 The coefficients of v2 in Eqs. (2.190) and (2.192) may be rewritten as n = y'\2e -Ju(Ccc + Ccx) S = J/22e + MCCC + Ccx) (2.192) (2.193) (2.194) (2.195) Chapter 2. Model Development 72 Using these two definitions as well as Eqs. (2.177) through (2.184) allows us to rewrite our three equations in the following manner aih — bic — cvhe = nv2 dib + eic - fvbe = sv2 gib + hic + vbe = 0 Simultaneous solution of this set of equations for the ratios of and yields ib en + fhn + sb - sch yu = — = rv, f k , T ^ T (2.196) v2 ajh + gjo + ae + db + cge — cdh and ic a s + cos — dn — fan v2 ajh + gjo + ae + db-r cge — cdh Due to the computational complexity of the definitions for the four network y-parameters, Eqs. (2.185), (2.186), (2.196) and (2.197), the symbolic math processing package MAPLE was employed to provide an analytical expression for U. The results obtained are presented in Appendix B. Chapter 3 Results and Discussion This investigation was initiated because of questions raised in the literature as to the accuracy of Eq. (1.3) in predicting fmax for modern HBTs. The conflicting results that have been reported are likely due to differences in the methods used to calculate this performance parameter. We have thoroughly investigated several of these methods and can now report on how they compare to one another as well as establish the applicability of Eq. (1.3) to these devices. In order to simplify the comparison between the various methods used to calculate fmax, a single H B T structure was employed throughout this analysis. The single-sided isolated H B T described in Section (2.4) was chosen as the test structure due to its simplicity and good performance capabilities. With reference to Figure (2.23), the devices we simulated are characterized by the parameters listed in Table (3.1). SE (pm) 0.5 -> 2.0 SB (pm) 10.2 SC (pm) 6.0 SEB (pm) 0.3 SBc (pm) 1.0 S'CD (Pm) SE+1.0 LE (um) 100 LB (pm) 100 Lc (pm) 100 Table 3.1: Dimensional quantities of the single-sided isolated H B T structure. 73 Chapter 3. Results and Discussion 74 Using the H B T device simulation program developed by Ho [26], an operating point may be established and the various parameters required in the calculation of fmax de-termined. The dc emitter-base voltage VEB w a s varied from 1.34 V to 1.59 V to give a collector current density Jc between 12 and 5 x 104 A / c m 2 . The maximum value of Jc was chosen such that high injection effects, namely base push-out due to the Kirk effect, would be avoided [35]. Typical values for the various quantities appearing in the equivalent circuits are given in Table (3.2). Jc (A/cm 2 ) 12 -* 50000 V B E (V) 1.34 -> 1.59 Ct0 .975 -> .954 SE ( H 0.5 1.0 2.0 g0 (S) varied varied varied r e (ft) 4741 - • 1.22 2371 -»• .608 1185 -> .304 RE (ft) .409 -»• .438 .205 -» .219 .102 -» .109 RBI (ft) .633 -> .632 1.266 -> 1.263 2.533 -> 2.526 RBX + RBC (ft) 4.502 4.502 4.502 Rc (ft) 1.899 1.947 2.043 Cde (fF) .52 2035 1.04 -> 4071 2.08 -> 8142 CJE (fF) 193.9 394.9 387.7 -* 789.8 775.4 -> 1580 Cci (fF) 16.26 32.53 65.05 Ccx + Ccc (fF) 32.53 32.53 32.53 <7e(fF) 38.67 -> 38.68 52.47 52.48 81.41 -> 81.42 Cbc (fF) 10.12 -» 10.11 12.58 -> 12.57 16.17 - • 16.15 Table 3.2: Component values used in the equivalent circuits. VBC = -3V. The majority of the simulations performed in this work were made using a dc reverse bias of -3 V across the collector-base junction. The effect of changing VBC on the value °f fmax 3 5 computed via one of our lumped element equivalent circuits (the choice of hybrid-7r or T is irrelevant because both yield identical results) for a 1 pm emitter width H B T is shown in Figure (3.1). By increasing the reverse bias, the collector-base depletion Chapter 3. Results and Discussion 75 region is widened which reduces CJC and T#. The increase in TQ is outweighed by these factors and high frequency performance is improved. The selection of VBC = -3 V for the remaining simulations is representative of a typical operating bias and provides a common ground for comparison of results. As mentioned previously, the average electric field across the depletion region at this bias is approximately 120 kV/cm. This is below the breakdown field for GaAs (~400 kV/cm) so carrier multiplication effects are avoided. Chapter 3. Results and Discussion 76 3.1 Unilateral Gain and Resonance Now that all of the parameters have been introduced and the operating points established, it is beneficial to examine the behavior of the unilateral gain as a function of frequency under various conditions. Figure (3.2) is a plot of U versus / as determined by the D D E approach as well as by the lumped element equivalent circuits for SE = 0.5 pm. At low Frequency (Hz) Figure 3.2: Unilateral gain as a function of frequency at Jc = 5 x 104 A / c m 2 , frequencies, we see that the two methods differ in their prediction of U depending on Chapter 3. Results and Discussion 77 the value of g0 used in the hybrid-TT or T equivalent circuits. The lack of a constant low frequency gain for g0 = 0 as predicted by these circuits is expected because none of the power signal at the output terminal is being shunted to ground. The inclusion of a non-zero output conductance can be used to reconcile the two methods. The influence of g0 on gain is negligible at frequencies higher than 1 GHz for the values of gQ simulated in Figure (3.2). Therefore, setting g0 = 0 in our calculations of fmax is a reasonable simplification. The predominant 6 dB/octave roll-off in gain observable in this plot of U vs f has been the traditional assumption for the behavior of U at high frequencies. This expected roll-off is due to the dominance of the RC product of base resistance RB and collector junction capacitance CJC- However, when the value of these elements has been reduced to the point where other parasitics and transit time effects become important (as is the case in modern H B T structures), the behavior of U can no longer be expected to fall off as predicted by a single pole approximation. This leads to the most striking feature of Figure (3.2); the appearance of resonance at frequencies above ~100 GHz. This effect has been observed by other researchers who performed similar calculations while studying the high frequency performance of HBTs [29] [30]. Prasad et ai, in their numerical analysis of HBTs, have produced plots very similar to ours (U vs / ) and have discussed at length the issue of the resonance peaks. They used /^-parameters in their equivalent circuit analysis and found that the resonance peaks occurred whenever Re(h22) = Re (J^j. _ q changed sign. This translates to frequency ranges in which the device exhibits negative output resistance. Physically, the negative output resistance of the circuit is due to the phase delay associated with carrier transit times through the device [30] [51] [52]. If the phase difference between an applied ac voltage and the ac current flowing through a device is between 90° and 270°, the device will display an ac negative resistance [53]. This phenomenon was predicted for diodes Chapter 3. Results and Discussion 78 over 25 years ago [54]. Thus, for devices in which carrier transit time is the limiting factor for the speed of operation, resonance behavior is expected to occur over certain ranges of frequency. Tiwari [29] examined the relative importance of these effects compared to the other parasitics associated with the device. He determined that when the parasitic resistances and capacitances were ignored, the transit time effects did indeed cause resonance in U. However, when the parasitics were included, their component values were sufficiently high to swamp the transit time effects. Since we used the same method as Tiwari in formulating the D D E representation, our results using this approach should parallel his. Thus, due to the resonance behavior we observe at high frequencies, we may conclude that the parasitics in our test structure are sufficiently low so as to allow the phase delay effects to dominate. The remarkable similarity of the resonance behavior that we observe when comparing the D D E approach and our own lumped element representations may be taken to be evidence of the validity of these methods. Resonance can be suppressed by increasing the device output conductance [30] or, of course, by increasing the magnitudes of the parasitic base resistance and collector capacitance. Figure (3.1) is indirect evidence of the latter effect as the low bias curves (-1 V to -4 V) do not show the continued rapid increase of fmax with Jc at high JQ which, as we will later show, is attributable to the resonance effects. Confirmation of this is shown in Figure (3.3) where U is plotted for the cases of low collector capacitance (VBC = — 5 V) and large collector capacitance (VBc — — 1 V ) . The onset of resonance is delayed when VBC = —1 V due to the increased influence of the (RBCc)efj time constant. For the devices studied in this work, the range of behavior from parasitic-dominated to transit-time-dominated can also be achieved by simply changing the emitter stripe width. For SE = 2.0 /im, RB and CJC are of sufficient magnitude that U falls at 6 dB/octave at frequencies up to and beyond fmax- As SE is reduced progressively through 1.0 fim to Chapter 3. Results and Discussion 79 Frequency (Hz) Figure 3.3: Comparison of U vs f using the D D E approach for high (VBC = —1 V) and low (VBC = —5 V) collector junction capacitance at JC = 5 x 104 A / c m 2 . SE = 1 M m -0.5 pm the deviation from the 6 dB/octave roll-off occurs at lower frequencies and reso-nance at U > 0 dB becomes more pronounced (see Figure (3.4)). This is a direct result of decreases in the intrinsic base resistance RBI and the intrinsic collector capacitance Cci with decreasing SE-We are interested in fmax as a figure-of-merit for transistor high frequency perfor-mance. Clearly from Figure (3.4), the frequency at which U = 1 increases as SE is reduced. The onset of resonance "draws out" the gain at the higher frequencies. As this Chapter 3. Results and Discussion 80 40 20 O 73 -20 B I—H •a •"^  -40 -60 -80 SE=0.5fjm SE= 1.0 \M\ SE= 2.0 um 9.0 9.5 10.0 10.5 11.0 11.5 10 10 10 10 10 10 Frequency (Hz) Figure 3.4: U vs f for various values of emitter stripe width. Jc = 5 x 104 A / c m 2 . effect is due to transit time phenomena it is not surprising that the frequency at which (7 = 1 can be increased by artificially increasing the phase delay used in our expressions for alpha. Referring to Figure (3.5), where the phase delay u ( m T g + ^ ) has been modi-fied by increasing m, we see that the fmax value as predicted by the frequency at which U = 0 dB increases with an increase in transit time. As has been suggested elsewhere [29][30][51][52], it may be possible to exploit this resonance phenomena to realize useful new, high frequency oscillators and high-gain Chapter 3. Results and Discussion 81 Frequency (Hz) Figure 3.5: U vs f for various values of excess phase m. SE = 0.5/xm, TB = 2.48 ps, 2 £ = 2.38 ps, and Jc = 5 x 104 A / c m 2 . amplifiers. However, it is disconcerting to attribute a higher value of fmax to these devices. It is counter-intuitive to expect an increased transit time to give improved high frequency performance. For this reason, in devices where resonance at U > 1 is present, it is a debatable question as to whether the frequency at which U = 1 is a useful figure-of-merit. In actual measurements on practical devices, circuit parameters are usually extracted from scattering parameter data obtained by examining the incident and reflected voltages Chapter 3. Results and Discussion 82 at both the input and output of the two-port. These S'-parameters are obtained using probing/analyzing systems which operate to 26.5 GHz or, just recently, 40 GHz. Extrap-olation of the data to U = 1 gives the value quoted as f m a x . If we mimic this procedure by plotting the numerical data for our devices out to 26.5 GHz and then extrapolating by means of linear regression to U = 1, we obtain the results shown in Figures (3.6) and (3.7). These results are comforting in that the increase in fmax is less severe as the Frequency (Hz) Figure 3.6: f m a x a s determined by extrapolation of lower frequency data for U for various emitter stripe widths. Jc = 5 x 104 A / c m 2 . parasitics are reduced (compare Figures (3.4) and (3.6)) and now f m a x decreases as the Chapter 3. Results and Discussion 83 9.0 9.5 10.0 10.5 11.0 10 10 10 10 10 Frequency (Hz) Figure 3.7: fmax a s determined by extrapolation of lower frequency data for U for various values of excess phase m. SE = 0.5 /im, TB = 2.48 ps, ^ = 2.38 ps, and Jc = 5 x 104 A / c m 2 . transit time is increased (compare Figures (3.5) and (3.7)). 3.2 Comparison of Methods of fmax Calculation When fmax is determined by extrapolation using the D D E or the lumped element equiv-alent circuit approaches for various current densities, Figure (3.8) results. Note that in this figure, the classical equation for fmax, Eq. (1.3), generally overestimates fmax-This is as would be expected in view of its neglect, amongst other things, of phase delay Chapter 3. Results and Discussion 84 effects. ^ 70 N K O w 60 a o r 3 50 o t/3 ° 40 o C 20 10 oU 10 Classical Equation DDE approach Lumped Element Equivalent Circuit approach 10 10 10 Collector Current Density (A/cm ) Figure 3.8: Comparison of Eq. (1.3), the extrapolated drift-diffusion representation, and the extrapolated lumped element equivalent circuit representation in the calculation of fmax for three different emitter widths. The results of the exact calculation for [7 = 1 are shown in Figure (3.9). Here we see that the D D E and the lumped element equivalent circuit approaches yield similar values to that of the classical equation for frequencies below ~50 GHz. This is due to the dominating effect of the effective base-collector RC time constant (i?B(7c) e / / at these frequencies. As SE and thus (RgCc)eff are reduced, the transit time effects become Chapter 3. Results and Discussion 85 X o 120 110 100 G 90 O •a 3 80 o 00 O 70 o >>60 o c 3 50 cr fc 40 30 20 10 0 — Classical Formula - DDE approach - - Lumped Element Equivalent Circuit approach 10 10 10 10 Collector Current Density (A/cm2) Figure 3.9: Comparison of Eq. (1.3), the drift-diffusion representation, and the lumped element equivalent circuits in the calculation of fmax for three different emitter widths. more important at high frequencies and the two methods that more effectively deal with phase delay begin to diverge from the predictions of Eq. (1.3). These predictions of fmax greater than those obtained by the classical equation are due to continuing to ascribe to fmax the frequency at which U = 1, even when resonance phenomena are present. We suggest that this is what Pejcinovic et al. [25] did in performing their numerical computation of fmax from calculations based on the D D E equations, and we offer this as a reason for their conclusion that Eq. (1.3) underestimates fmax-Chapter 3. Results and Discussion 86 Examining the two more complicated methods of determining / m a r , we see in Figure (3.9) that the results are similar for frequencies below ~80 GHz. This is a satisfying result because the lumped element equivalent circuits were arrived at via considerations of carrier transport through the device and therefore based on the same drift-diffusion equations as the D D E representation. The slight differences that are observable are likely due to the different approaches taken to account for the distributed nature of the base resistance Rg and collector capacitance CJC-Frequency (Hz) Figure 3.10: U vs / in the region where U = 0 dB. The one major discrepancy occurs for the 0.5 fim device at current densities above 104 A / c m 2 . This corresponds to frequencies in excess of ~80 GHz and can be explained by resonance phenomena occurring in the unilateral gain at these oscillation levels. Slight differences in the resonance peaks occurring at U « 0 dB for the two methods account for the difference in the predicted value of fmax at high collector current levels. A blow-up Chapter 3. Results and Discussion 87 of the region under consideration is shown in Figure (3.10) where Jc = b x 104 A / c m 2 . At these frequency levels, the D D E approach provides the more accurate result since it is not based on any major assumptions. The inaccuracy associated with the excess phase factor m used in the hybrid- 7r and T equivalent circuits is the source of the discrepancy. Reconciliation of the two approaches at high frequency levels is possible by using a value of m = 0.195 for the devices studied here. This is not unreasonable because the value used for m is by no means a constant for all bipolar transistors [20]. 3.3 Use of the Correct Alpha in the T Equivalent Circuit As mentioned in Section (2.3.2), the current generator in the T equivalent circuit must be properly accounted for if we wish to obtain accurate results. If we refer to Figure (3.11) in which the T equivalent circuit is presented along with various small signal current components we can see that the intrinsic emitter current ie is made up of two parts: a resistive component i'e that flows through r e and a reactive component i'e' that flows through CV. We can write %e = h + h = i'e + juC„veb (3.1) Noting that veb — i'ere leads to ie = i'e[l + ju>C*re] (3.2) To use the total emitter current ie as the controlling element in the current source in Figure (3.11), we can write Chapter 3. Results and Discussion 88 flO-bc - W W—o c Figure 3.11: T equivalent circuit displaying intrinsic emitter current components. By denning u)a> as ua> = the new expression for alpha becomes a = l + i — (3.4) This is in the same form as the expression for beta given by Eq. (2.19). However, — = reCjE + reCde is not equivalent to J J - ~ reCde and thus the final expression given for a in Eq. (2.31) cannot be used here. We can use either ct'0i'e or a'ie as the value for the current source in the T equivalent circuit. Recent publications have presented similar T equivalent circuits with the a of Eq. (2.31) multiplying i'e as the current source [11] [30]. The error associated with this discrepancy is shown in Figure (3.12). As can be seen, there is no difference at low collector current levels, but the error leads to a severe overestimation of fmax at higher values of JQ. Chapter 3. Results and Discussion 89 110 ^100 N ffi O 90 O 80 ^ 7 0 o VM 60 o g 50 § ? 4 0 tin B 30 •a 2 0 / incorrect — correct 10 10 10 10 '1 Collector Current Density (A/cm ) Figure 3.12: Comparison of the correct (ot'0i'e or etie) and incorrect (ai'e) methods of assigning a value to the current source in the T equivalent circuit. SE = 1-0 pm. 3.4 C o m p a r i s o n of the F u l l E q u i v a l e n t C i r c u i t R e p r e s e n t a t i o n to tha t of D a s The usefulness of the classical formula for predicting fmax was also considered by Das [24]. His work involved the derivation of the y-parameters for a hybrid-7r equivalent circuit very similar to the one developed in Section (2.3.1). In his y-parameter development, he made several assumptions which led him to conclude that the use of Eq. (1.3) would result in an overestimation of fmax for the HBTs he considered. We have examined his derivations and found that several of his assumptions lead to serious errors in the calculation of Chapter 3. Results and Discussion 90 fmax- By applying these assumptions to our {/-parameters, we were able to reconcile Das' approach with ours. In all of his {/-parameter derivations, Das made the assumption that rv >^ at the frequencies of interest and thus removed rr from the hybrid-7r equivalent circuit. As well, Rc and gQ were assumed negligible and do not appear in his expressions. Applying the same circuit analysis techniques that were used in the development of our {/-parameters to Das' reduced hybrid-7r equivalent circuit as shown in Figure (3.13), we obtain the following expressions for the network {/-parameters: Figure 3.13: Reduced hybrid-7r equivalent circuit used by Das [24]. 2/ii 2/21 2/12 2/22 ju>C'T + juCc(l + juClRE) 1 + JUC^RE + RB) + ju>CCRB(l + JUC'^RE) 9m - juCc(l + JUC'^RE)  1 + JOOC^RE + RB) + juCCRB{\ + juC'NRE) -juCe(l + JUCJRE)  1 + juC'N(RE + RB) + juCCRB(l + jwC'RRE) juCCRBg'm + juCe[l + JUC'^RE + RB)} 1 + JUC'^RE + RB) + juCCRB{l + JUC'^RE) + juCbc - juCbc - JuCbc + jvCbc (3.5) (3.6) (3.7) (3.8) Chapter 3. Results and Discussion 91 where l + gmRE l + gmRE 9m ™ {*¥) 2 0.322rB + ^ + — 2 vsat At this stage, Das makes some additional assumptions in order to further simplify these expressions: Assumption 1 : 1 + ju>Cl(RE + RB) > juCcRB{l + juC'„RE) Assumption 2: the phase delay can be ignored everywhere except in the numerator of the g'm term in Eq. (3.6) These two simplifications lead to the following y-parameters as derived by Das juCi + jcoCc(l + juC'„RE) yn -2/21 2/12 2/22 1 + juC'„(RE + RB) g'me-i«+-ju;Ce(l+ju>C'TRE) 1 + JUC^RE + RB) -juCc(l + juC'„RE) - juCbc JU)C\ be with gm redefined as 1 + juC'„(RE + RB) juCCRBg'm + jo t7 e ( l + juC'„RE) 1 + JUC^RE + RB) sinter + jwCbc (3.9) (3.10) (3.11) (3.12) a0 gm = — TV 2 The JUC'^RB term in the numerator of Eq. (3.8) has also been dropped at this point. The implications of Das' assumptions have been investigated by computing fmax from each of these sets of y-parameters. First it is worthy to note how Das' y-parameters Chapter 3. Results and Discussion 92 compare to the classical formula. His claim that Eq. (1.3) overestimates fmax cannot be verified using our test structure (see Figure (3.14)). It appears to be true at low Jc but the opposite occurs for Jc larger than ~ 103 A / c m 2 . These results are due to the combined effect of his various approximations. 1 1 1 1 Das' / ^-parameters/ / s ~ _ / s / s / / / / classical / / formula 1 / — / / / / — / / // // / / / / / / / / / / s / s / ~ l \ \ \ N o c o ti B o O o 70 60 50 40 cr 30 20 S io 10 10^  10 10 Collector Current Density (A/cm2) Figure 3.14: Comparison of fmax predicted via Das' {/-parameters to that obtained using the classical formula. SE = 1-0 pm. The various assumptions will now be progressively removed from his derivation. Fig-ure (3.15) displays the resulting curves. Curve (1) is obtained from Das' {/-parameters Chapter 3. Results and Discussion 93 which encompass all of the assumptions. If we remove assumption 1 and thus use the full denominator in Eqs. (3.5) to (3.8), we get curve (2). We can remove assumption 2 by maintaining the phase delay in gm. This leads to curve (3) which can be seen as a major shift in the prediction of fmax. In order to see the effect of including T V and Rc in the hybrid-7r equivalent circuit, we must use our {/-parameters, modified to incorporate Das' 1 2 3 4 10 10 10 10 Collector Current Density (A/cm ) Figure 3.15: Implications of Das' assumptions. SE = 1.0 pm. <f>, i.e., (rriTB + •z^) is replaced by (0.322TB + ^ + ^ - ) in our expression for ct0. Including Rc gives us curve (4) and finally including rT results in curve (5). This curve is obtained Chapter 3. Results and Discussion 94 without making any approximations and is therefore the desired relationship. Das' curve (1) is a serious departure from this result. The use of Das' equations and the equations developed for the full hybrid-7r equivalent circuit can be reconciled by removing r f f and Rc from our "exact" development and using Das' expression for <f>. The result is identical to curve (3) as one would expect. From this analysis, it is clear that the removal of rv in the hybrid-7r equivalent circuit is a serious error as is the dismissal of e~3U"^ via assumption 2. Das' y-parameters are inappropriate for the device studied in this work. His comments as to the accuracy of Eq. (1.3) are not valid in this situation and therefore cannot be generalized. Chapter 4 Summary 4.1 Conclusions The high frequency performance of some uniform base heterojunction bipolar transistors has been examined by calculating the unilateral gain for these devices as a function of frequency. Two models have been used to characterize the H B T at high frequencies: the D D E representation and the lumped element hybrid-7r or T equivalent circuits. The prediction of fmax using these models has been compared to that of the classical analytical equation. It has proved possible to reconcile the diverse results previously reported for fmax calculations. The following conclusions may be drawn from this work: • There is essentially no difference in the value of fmax computed via the D D E ap-proach or the lumped element equivalent circuit approach. However, since both methods require similar computational efforts, the D D E approach is recommended by virtue of its more "exact" formulation. • In the T equivalent circuit representation, proper account must be taken in the specification of the current source found in this circuit. Improper definition of this element leads to errors in fmax prediction at high collector current densities. • In the hybrid-7r equivalent circuit representation, it is necessary to retain r w and to fully include the effects due to phase delay in the derivation of the circuit y-parameters. A major loss of accuracy occurs in the calculation of fmax when either one of these approximations is made. 95 Chapter 4. Summary 96 • When transit time effects are important, the frequency at which U = 1 is underes-timated by Eq. (1.3). However, it is debatable whether under these circumstances, this frequency is a useful figure-of-merit. When U = 1 is computed via extrapola-tion from values at frequencies at which transit time effects are not important, the classical equation provides a very good approximation to fmax and overestimates it by < 6% when compared to either equivalent circuit approach for all values of emitter width considered here. 4.2 Recommendations for Future Work The interesting phenomenon of resonance in U at high frequencies requires further re-search and understanding. The fact that U is defined for situations of conjugate match-ing at both the source and the load automatically precludes some of this behavior as being realizable because negative resistance terminations do not exist for the ranges of frequency where the device exhibits negative output resistance. However, as has been suggested [51], the unilateral gain may be redefined to incorporate a realistic positive load resistor and the negative output resistance of the device may still occur. This may lead to interesting situations of enhanced gain near fmax-Another aspect of resonance that should be investigated are the peaks and valleys of the U vs f curves seen in Figures (3.4) and (3.5). The frequencies at which these occur may lead to insights as to the dominant mechanisms governing the behavior of U at these levels of oscillation. Finally, effects due to velocity overshoot in the collector-base space charge region could be included in the formulation of TQ and the phase delay associated with this transit time. These effects are likely to influence the high frequency characteristics of non-parasitic-limited devices. References [1] W . Shockley, U.S. Patent No. 2569347, Sept. 25, 1951. [2] H . Kroemer, "Theory of a wide-gap emitter for transistors," Proc. of the IRE, vol. 45, pp. 1535-1537, Nov. 1957. [3] H . Kroemer, "Heterostructure bipolar transistors and integrated circuits," Proc. of the IEEE, vol. 70, pp. 13-25, Jan. 1982. [4] D. K . Jadus and D. L. Feucht, "The realization of a GaAs-Ge wide band gap emitter transistor," IEEE Trans. Electron Devices, vol. 16, pp. 102-107, Jan. 1969. [5] H . J . Hovel and A. G. Milnes, "ZnSe-Ge heterojunction transistors," IEEE Trans. Electron Devices, vol. 16, pp. 766-774, Sept. 1969. [6] S. L . Su, R. Fischer, W. G. Lyons, 0 . Tejayadi, D. Arnold, J . Klem, and H . Markog, "Double heterojunction GaAs /AL J Gai_ : r As bipolar transistors prepared by molecu-lar beam epitaxy," J. of Applied Physics, vol. 54, pp. 6725-6731, Nov. 1983. [7] W . P. Dumke, J . M . Woodall, and V . L . Rideout, "GaAs-GaAlAs heterojunction transistor for high frequency operation," Solid-State Electronics, vol. 15, pp. 1339-1343, Dec. 1972. [8] M . Konagai and K . Takahashi, "(GaAl)As-GaAs heterojunction transistors with high injection efficiency," J. of Applied Physics, vol. 46, pp. 2120-2124, May 1975. [9] M . Konagai, K . Katsukawa, and K . Takahashi, "(GaAl)As/GaAs heterojunction 97 References 98 phototransistors with high current gain," J. of Applied Physics, vol. 48, pp. 4389-4394, Oct. 1977. [10] H. Lin and S. Lee, "Super-gain AlGaAs/GaAs heterojunction bipolar transistors using an emitter edge-thinning design," Applied Physics Letters, vol. 47, pp. 839-841, Oct. 1985. [11] P. M . Asbeck, M . F. Chang, K . C. Wang, D. L . Miller, G. J . Sullivan, N . H . Sheng, E. Sovero, and J . A . Higgins, "Heterojunction bipolar transistors for microwave and millimeter-wave integrated circuits," IEEE Trans. Electron Devices, vol. 34, pp. 2571-2578, Dec. 1987. [12] J . Bailbe, A . Marty, P. H . Hiep, G. E . Rey, "Design and fabrication of high-speed GaAlAs /GaAs heterojunction transistors," IEEE Trans. Electron Devices, vol. 27, pp. 1160-1164, June 1980. [13] P. M . Asbeck, D. L . Miller, W. C. Peterson, and G. G . Kirkpatrick, "GaAs/GaAlAs heterojunction bipolar transistors with cutoff frequencies above 10 GHz," IEEE Electron Device Letters, vol. 3, pp. 366-368, Dec. 1982. [14] P. M . Asbeck, A . K . Gupta, F. J . Ryan, D. L. Miller, R. J . Anderson, C. A . Liechti, and F. H . Eisen, "Microwave performance of GaAs/(GaAl)As heterojunction bipolar transistors," IEDM Tech. Dig., pp. 864-865, Dec. 1984. [15] R. Fischer and H . Markoc, "Reduction of extrinsic base resistance in GaAs/AIGaAs heterojunction bipolar transistors and correlation with high-frequency performance," IEEE Electron Device Letters, vol. 7, pp. 359-362, June 1986. [16] K . Nagata, 0 . Nakajima, Y . Yamauchi, T. Nittono, H. Ito, and T. Ishibashi, "Self-aligned AlGaAs/GaAs H B T with low emitter resistance utilizing InGaAs cap layer," References 99 IEEE Trans. Electron Devices, vol. 35, pp. 2-7, Jan. 1988. [17] T. Ishibashi, O. Nakajima, K . Nagata, Y . Yamauchi, H . Ito, and T. Nittono, "Ultra-high speed AlGaAs/GaAs heterojunction bipolar transistors," IEDM Tech. Dig., pp. 826-829, 1988. [18] T. Ishibashi and Y . Yamauchi, " A possible near-ballistic collection in an A l -GaAs/GaAs H B T with a modified collector structure," IEEE Trans. Electron De-vices, vol. 35, pp. 401-404, Apr. 1988. [19] P. M . Asbeck, M . F. Chang, J . A . Higgins, N . H . Sheng, G. J . Sullivan, and K . Wang, "GaAlAs/GaAs heterojunction bipolar transistors: issues and prospects for application," IEEE Trans. Electron Devices, vol. 36, pp. 2032-2042, Oct. 1989. [20] R. L . Pritchard, "Electric-network representation of transistors - a survey," IRE Trans. Circuit Theory, vol. 3, pp. 5-21, Mar. 1956. [21] R. M . Burger and R. P. Donovan, Fundamentals of Silicon Integrated Device Tech-nology. Englewood Cliffs, N.J . : Prentice-Hall International, Inc., 1968. [22] J . M . Early, "Structure-determined gain-band product of junction triode transis-tors," Proc. of the IRE, vol. 46, pp. 1924-1927, Dec. 1958. [23] J . Lindmayer, "Power gain of transistors at high frequencies," Solid-State Electron-ics, vol. 5, pp. 171-175, May 1962. [24] M . B . Das, "High-frequency performance limitations of millimeter-wave heterojunc-tion bipolar transistors," IEEE Trans. Electron Devices, vol. 35, pp. 604-614, May 1988. References 100 [25] B . Pejcinovic, T. Tang, and D. H. Navon, "High frequency characterization of het-erojunction bipolar transistors using numerical simulation," IEEE Trans. Electron Devices, vol. 36, pp. 233-239, Feb. 1989. [26] S. C. M . Ho, "The effect of base grading on the gain and high frequency performance of AlGaAs /GaAs heterojunction bipolar transistors," M.A.Sc thesis, University of British Columbia, Aug. 1989. [27] R. P. Nanavanti, Semiconductor Devices. New York: Intext Educational Publishers, 1975. [28] D. Le Croissette, Transistors. London: Prentice-Hall International, Inc., 1963. [29] S. Tiwari, "Frequency dependence of the unilateral gain in bipolar transistors," IEEE Electron Device Lett., vol. 10, pp. 574-576, Dec. 1989. [30] S. Prasad, W. Lee, and C. G. Fonstad, "Unilateral gain of heterojunction bipo-lar transistors at microwave frequencies," IEEE Trans. Electron Devices, vol. 35, pp. 2288-2294, Dec. 1988. [31] M . C. F . Chang, P. M . Asbeck, K . C. Wang, G . J . Sullivan, N . H . Sheng, J . A . Higgins, and D. L. Miller, "AlGaAs/GaAs heterojunction bipolar transistors fabri-cated using a self-aligned dual-lift-off process," IEEE Electron Device Lett., vol. 8, pp. 303-305, July 1987. [32] R. L . Pritchard, Electrical Characteristics of Transistors. New York: McGraw-Hill, 1967. [33] R. P. Abraham, "Transistor behavior at high frequencies," IRE Trans. Electron Devices, vol. 7, pp. 59-69, Jan. 1960. References 101 [34] D. E. Thomas and J . L . Moll , "Junction transistor short-circuit current gain and phase determination," Proc. of the IRE, vol. 46, pp. 1177-1184, June 1958. [35] S. C. M . Ho and D. L. Pulfrey, "The effect of base grading on the gain and high-frequency performance of AlGaAs/GaAs heterojunction bipolar transistors," IEEE Trans. Electron Devices, vol. 36, pp. 2173-2182, Oct. 1989. [36] K . Tomizawa, Y . Awano, and N . Hashizume, "Monte Carlo simulation of A l -GaAs/GaAs heterojunction bipolar transistors," IEEE Electron Device Lett., vol. 5, pp. 362-364, Sept. 1984. [37] Y . Yamauchi and T. Ishibashi, "Electron velocity overshoot in the collector depletion layer of AlGaAs/GaAs HBTs," IEEE Electron Device Lett, vol. 7, pp. 655-657, Dec. 1986. [38] J . Lindmayer and C. Y . Wrigley, Fundamentals of Semiconductor Devices. Princeton, N.J . : D. Van Nostrand Inc., 1965. [39] J . Zawels, "Physical theory of new circuit representation for junction transistors," J. of Applied Physics, vol. 25, pp. 976-981, Aug. 1954. [40] J . Zawels, "The natural equivalent circuit of junction transistors," RCA Review, vol. 16, pp. 360-378, Sept. 1955. [41] H. Dommel, Notes on Power Systems Analysis-Srd Edition, 1989. [42] W. W. Gartner, Transistors: Principles, Design and Applications. Princeton, N.J . : D. Van Nostrand Inc., 1960. [43] A . Bar-Lev, Semiconductors and Electronic Devices-2nd Edition. Englewood Cliffs, N . J . : Prentice-Hall International, Inc., 1984. References 102 [44] S. S. Tan and A . G. Milnes, "Consideration of the frequency performance potential of GaAs homojunction and heterojunction n-p-n transistors," IEEE Trans. Electron Devices, vol. 30, pp. 1289-1294, Oct. 1983. [45] A . B . Phillips, Transistor Engineering and Introduction to Integrated Circuits. New York: McGraw-Hill , 1962. [46] G . 0 . Ladd, D. L . Feucht, "Performance potential of high-frequency heterojunction transistors," IEEE Trans. Electron Devices, vol. 17, pp. 413-420, May 1970. [47] D. A . Sutherland and P. D. Dapkus, "Optimizing n-p-n and p-n-p heterojunction bipolar transistors for speed," IEEE Trans. Electron Devices, vol. 34, pp. 367-377, Feb. 1987. [48] G. D. Vendelin, Design of Amplifiers and Oscillators by the S-Parameter Method. New York: John Wiley and Sons, 1982. [49] J . M . Rollett, "Stability and power-gain invariants of linear twoports," IRE Trans. Circuit Theory, vol. 9, pp. 29-32, Mar. 1962. [50] S. J . Mason, "Power gain in feedback amplifiers," IRE Trans. Circuit Theory, vol. 1, pp. 20-25, June 1954. [51] N . Dagli, W. Lee, S. Prasad, and C. G . Fonstad, "High-frequency characteristics of inverted-mode heterojunction bipolar transistors," IEEE Electron Device Lett., vol. 8, pp. 472-474, Oct. 1987. [52] N . Dagli, "Physical origin of the negative output resistance of heterojunction bipolar transistors," IEEE Electron Device Lett., vol. 9, pp. 113-115, Mar. 1988. References 103 [53] H . W. Riiegg, " A proposed punch-through microwave negative-resistance diode," IEEE Trans. Electron Devices, vol. 15, pp. 577-585, Aug. 1968. [54] W . Shockley, "Negative resistance arising from transit time in semiconductor diodes," Bell Syst. Tech. J., vol. 33, pp. 799-826, 1954. Appendix A Rewriting a'0 in terms of its real and imaginary components Alpha is a complex function of frequency common to both lumped element equivalent circuits. It is convenient to isolate the real and imaginary components of this factor for circuit analysis purposes. Referring back to Eq. (2.42) we know that sin ffl 2 = ankne~^ (A.l) where sin ( ^ ) WTc. 2 TQ <f> = rriTB + — Using the identity e •?u"*> = cos(— u(f>) + j sin(—u<j>) we have a'0 = aQk0 [cos(-u(f>) + j sin(-u>0)] (A.2) Separating the real and imaginary parts, we can write ao = «i + J « 2 (A.3) where a\ = a0k0 cos(—u><f>) a2 = a0k0 sin(—u<j>) 104 Appendix B Unilateral Gain Determined From the DDE Equivalent Circuit The equations for the network y-parameters as derived in Section (2.7.3) were supplied to M A P L E as input. The resulting expression for unilateral gain is as follows: U = A , 6 1 + 6 2 . (B. l) 4[e6e3 - e4e5J where = c l ° 3 9 | c 2 a 3 7 C 3 a 4 3 di di d2 c 4 a 4 2 <*2 e 2 = cia37 | c 2 a 3 9 | c 3 a 4 2 di di d2 c 4 a 4 3 <*2 e 3 = c 8 a 4 3 | ^9^42 d2 d2 e 4 — c 3 a 4 3 ^ c 4 a 4 2 d2 d2 e5 = c i a 3 9 | c 2 a 3 7 di di e 6 -c 5 a 3 9 C6a 3 7 di di di = 2 . 2 a3 9 ' ° 3 7 d2 = a 4 3 T ° 4 2 C l - a 3 5 a 3 4 + a 2 5 a 3 3 ~ Q 2 2 a 3 0 — a2ia27RE c2 = # 2 5 ^ 3 0 + o 2 2 a 3 3 — a 2 7 a 3 4 — <12I0.35RE c 3 [ l + a 2 i ( i 2 B + i 2 c ) ] a 4 5 -• a24a4Q — a 4oa 45^?£; + a^a^RE -\-a2ia2Q — a 4 4 a 3 i — a2ia27RE + a 4 4 a 3 si?£; 105 Appendix B. Unilateral Gain Determined From the DDE Equivalent Circuit 106 C4 = [1 + 0,2I(RE + Rc)]aA6 + A24A45 ~ O,40A4&RE — a 4 l 045^15 + a 21°31 + ° 4 4 G26 — Q>21a3hRE ~ <lAAa27RE C5 = [1 + 0,2I(RE + i?c)]«27 — 035024 + 033«26 — 030031 C6 = [1 + CL2I(RE + #c ) ]«35 + 027^24 + 033^31 + 030^26 C 8 = —0,2\0'AbRE + fl34a46 + a 4 o ( ^ B C + RBX + RE)QA5 — a 41 (RBC + RBX + ^ ) a 4 6 + a 2 7 ( - R B C + - R B X + RE)a2\ — 0-Zb{RBC + ^ B X + RE)a4A + 025a21 — A22aAA Cg = —a21«46^JE ~ «34«45 + ^(RBC + i ? B X + RE)O46 + «41 ( - R B C + # B X + -R/i;)a45 + a 2 7 ( i ? B C + RBX + RE)^ + O,35(RBC + RBX + RE)O>2I + 025044 + 022O21 a n d a 9 B «2 = TT ~ 7T 2 n B « i 1 wl a 5 = c o s h ^ - ^ / a ^ ) — c o s ^ y ^ ) d6 = s inh (2 - v /a 4 ) >/a4a 6 v /a 2 "s in (2 x /a 2 " ) O7 = 1 a5 a5 - v / a 4 " s i n ( 2 x / a 2 " ) ^/a7a6 a 8 = f-a 5 a 5 sin(a ;Tc ) [cos(u;Tc )p c a 8 - sm(u>Tc)gca7] 2 1 • / nr\2 aw = s i n h ( v / a 4 " ) + sm(y/a^) yja~isinh(-v/a4") 005(^/02) cosh(^/a7) sin(^/a2) a n = 1 a 1 0 a 1 0 — v / a 7 c o s h ( v ^ ) s i n ( v / a 2 ~ ) yjo^, s i n h ( y ^ ) cos{y/a~2~) a i 2 = 1 a i o a i o sin(a;rc)[cos(a;rc)5feai2 - s in(u;r c )s feOi i ] a 1 3 = Appendix B. Unilateral Gain Determined From the DDE Equivalent Circuit 107 «14 = <7e08 + WCJE — gCO-12 ~ «13 + Og + UjCci sm(ujTc)[cos(u)Tc)gca7 + sm(uTC)gca8] sm(u>TC)[cos(u>Tc)gean + sin(u;Tc)#eai2] ai5 -«16 = Oi7 = 9ea7 - 9cd\\ — « i e + a i 5 a i 8 = (1 + RBian)2 + RBlau - ( a 1 6 - a 1 5 ) i ? B / a i 4 (ai3 - a 9 - uCCi){l + RBICH7) a 1 9 = 1 Ol8 Ol8 (a16 - a15)(l + RBIa17) ( a 1 3 - a 9 - UJCCI)RBIO-\4 a 2 0 = 1 a 1 8 a 1 8 a 2 i = ai5 - RBl[{gca>\\ — 015)020 - (gcai2 - a 9 - w C c / ) a i 9 ] (5f can - a15)a14RBIRE (gcai2 - a9 - uCCi){l + RBI<I\7)RE L R , , N \T> a 2 2 = 1 w\ycc T ^cx )ttE a i 8 a i 8 a 23 = # B / [ ( # c a i i - 015)019 + {gca\2 — 09 — uCci)a2o] a 2 4 - = u{CCc + CCX)(RE + Rc) + (a& + CJCCI - a23)(RE + Rc) 1 , (p c an - a i 5 ) ( l + RBI^RE , ( # c a i2 - a 9 - OJCC^RBICHARE 025 = 1 H h «26 = Al8 <*18 (5 - c a n - a 1 5 ) ( l + RBICII7)(RE + #c) (5^12 - ag - wCCi)RBia14(RE + -Rc) a18 «18 a i 7 ( l + Rsian) a14RBi a27 — 1 « 1 8 « 1 8 « 2 8 - ( « 1 3 — «9 — w C c / ) ( l — RBI0.2I) a17RBia14 a 1 4 ( l + Rsia17) a 2 9 = 1 a18 0 1 8 «30 = — (ai6 — « 1 5 ) ^ B / « 2 9 + «28 — w{CcC + C c x ) , I ^ v i ? 1 R \ 1 ( & q " ~ ais)RBia\A{RE + -Rc) « 3 i = ^(^-cc + L ' c x ) \ R E v Rc) 1 a i 8 (gcal2 - a 9 - a>Cc/)(l + RBI(1\7){RE + Rc) 018 a 3 2 = ( a i 3 — a 9 — UCCI)RBI^2^ 033 = ( a l e - a i 5 ) ( l - RBIO-2T) + G32 a 34 = (°9 + wCci — d2z)RE + u{CcC + CCX)RE Appendix B. Unilateral Gain Determined From the DDE Equivalent Circuit 108 a-nR-Biau , oi 4(l + H-Bi^n) t r i , ^ \ 0 3 5 = 1 \-W\LcC + ^CX) A18 °18 a 3 6 = a3b{RBC + RBX + RE)[1 + a2l(RE + Rc)} CI37 = — CL27a3iRE ~ 035a2lRE + 0,27(Rgc + RBX + Rs)a24 + A36 + a2\aZ\RE +o 3 4a 2 6 + o.2b^oRE + o,22a,33RE + (RBc + RBX + -R£)( a 33 a 3i + o 3 0a 2 6) +025^24 + 022[1 + 0,2I(RE + Rc)} 038 = CI27{RBC + RBX + RE)[1 + a2\{RE + Rc)] 039 = —0>27a2lRE + a35a3<lRE — a3h{RBC + RBX + -RB)O24 + A38 + «21 A 2 6 ^ B —a 3 4 a 3i + a 2 5a 3 3.RE — a 2 2 a 3 0 .R£ + (-RBC + -RBX + -R#)(a33A26 — o 3 0o 3 1) -a22a24 + a 2 5[l + a21(RE + Rc)} 040 = — («i6 — ai5)(l - RBIO.27) — a32 0 41 = («16 — O l 5 ) ^ B / A 2 9 — «28 + w(CcC + Ccx) a 4 2 = —a40(RBc + i?BX + -RB)O3I — a4i(RBc + RBX + RE)O-2& + ^I^IRE + o 3 4o 26 -a27a34RE - o,35a2iRE + 025024 + 022(1 + a2i(RE + Rc)} - a25a4iRE —o22a4ni?£; + O,27(RBC + JRBX + -RB)«24 + o36 043 = — O 4O(-RBC + i?BX + RE)^26 + 041 (-RBC + -RBX + -R#)o3i + a 2 1 a 2 6 i?£; — a 3 4a 3i —a27a2ii?|; -f a,35a34RE + a 2 5[l + a2\{RE + -Rc)] — o 2 2a 24 — CL25O4QRE +0,22(141 RE + «38 — o,3*>{RBc + RBX + RE)a24 0.44 = a9 + wCci — a23 + u(Ccc + Ccx) {gca\i - oi5)(l + RBIO-\T) . (^cOi2 - o9 - UCCI)RBIO,\4 0 4 5 — 1 Ol8 Oi 8 (ffcOn - aXh)RBIal4 (gca12 - a 9 - wCc/)(l + RBI^U) L R , , „ , 0 4 6 = 1 w(C/cc + ^cxJ O i s ais 

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                            <div id="ubcOpenCollectionsWidgetDisplay">
                            <script id="ubcOpenCollectionsWidget"
                            src="{[{embed.src}]}"
                            data-item="{[{embed.item}]}"
                            data-collection="{[{embed.collection}]}"
                            data-metadata="{[{embed.showMetadata}]}"
                            data-width="{[{embed.width}]}"
                            async >
                            </script>
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