A GaAs CERMET GATE CHARGE-COUPLED DEVICE By MAURICE LeNOBLE B.A.Sc, University of British Columbia, 1984 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY in THE FACULTY OF GRADUATE STUDIES Department of Electrical Engineering We accept this thesis as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA April 1989 © Maurice LeNoble, 1989 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department of £leC • £rt(jr. The University of British Columbia 1956 Main Mall Vancouver, Canada V6T 1Y3 Date / CLju /m DE-6(3/81) Abstract The design, implementation and evaluation of a 64-pixel, 4-phase GaAs cermet gate charge-coupled device ( CMCCD ) are described. It is demonstrated that the sig nal charge confinement and the signal charge capacity of the CMCCD are maximized when thin, highly doped active layers are used for implementing the device. The cer-met/GaAs junction within an interelectrode gap of the CMCCD forms a barrier similar to a metal/GaAs Schottky barrier, as revealed by an investigation of the dc current-voltage characteristic of a cermet/GaAs Schottky barrier diode. A transmission line model is described for the cermet/GaAs junction within an interelectrode gap of the CMCCD and is used to demonstrate the relationship of the surface potential variation along the gap as a function of the clock frequency and the material parameters. It is shown that the surface potential variation is monotonic for all frequencies, which is desirable for minimizing the formation of energy troughs within the active layer. En ergy troughs trap and release charge from passing charge packets, causing unwanted signal dispersion. A two-dimensional computer model is used to determine a theoretical maximum frequency of operation of the CMCCD. It is shown that a short transport electrode length for a fixed transport electrode pitch is preferable as it results in the maximum high frequency performance of the CMCCD for the lowest clock power. A computer simulation of a single electrode transfer of a charge packet is demonstrated using the two-dimensional computer model. The computer simulation indicates that efficient charge transfer takes place, suggesting that the CMCCD will have good perfor mance. A GaAs CMCCD with an on-chip GaAs MESFET source follower amplifier has been produced using a six mask level fabrication procedure. The CMCCD and the out put source follower amplifier are demonstrated to operate at 100 MHz. Charge transfer efficiencies of 1.00 and 0.998 for 100 MHz operation are obtained for the CMCCD using the impulse response method and the insertion loss method. ii Table of Contents Abstract ii List of Symbols v List of Tables x List of Figures xi Acknowledgements xiv 1 Introduction 1 2 Theory 6 2.1 Principle of Operation 6 2.2 One-dimensional Potential Distributions 12 2.3 Active Layer Specification 17 3 The Cermet/GaAs Junction 20 3.1 Barrier Properties3.2 Surface Potentials 5 3.3 Verification 32 4 Two-dimensional GaAs CMCCD Model 38 4.1 Geometric Representation 34.2 Device Equations4.3 Finite Difference Grid and the Computational Kernel 40 4.4 Finite Difference Equations for u(x,y) 41 4.5 Boundary Conditions for u(x, y) 4 4.6 Finite Difference Equation for J(x, y) 45 4.7 Discretization of the Continuity Equation 6 4.8 Boundary Conditions for n(x, y) 48 in 4.9 Numerical Solution of the Difference Equations 49 4.10 Computer Simulations . . . . • 52 5 Device Fabrication 59 6 Testing and Evaluation 66 7 Comments 73 7.1 Summary7.2 Considerations for Future Work . 76 Bibliography 78 Appendices A BNL Experiment 787 83 B Polar Transformation of V(y) 89 C Newton's Method 91 D Detailed Device Fabrication Procedure 92 E Test Circuit for VHF Operation 97 iv List of Symbols a(y,u) real part of (Lg — y)j(oj) A,...,G constants Ads logarithmic amplitude AQ amplitude constant A* modified Richardson's constant b(y,u>) imaginary part of (Lg - y)7(w) c(u>) real part of Lgj(u>) Ci integration constant CM maximum potential contour COM distributed cermet film capacitance CD distributed depletion layer capacitance C'o/p parasitic output capacitance CCM lumped cermet film capacitance CD lumped depletion layer capacitance d(u) imaginary part of L57(cu) df differential contour vector E normalized electric field EQ critical electric field Ei intrinsic energy EQ empirical constant fc clock frequency fl+l finite difference equation fmax maximum clock frequency g, h functions comprising the finite difference equation H(y,u) normalized surface potential amplitude v i,j x,y grid point indices iaux,jaux x,y auxiliary grid point indices iint active layer depth grid point index imax wafer thickness grid point index I(y) dc tangential current IQ saturation current jmax pixel length grid point index J electron current density Jo saturation electron current density k time-step index kmax stop time index k\, &2 integration constants / iteration index Lg interelectrode gap length Lp transport electrode pitch m integer index rii intrinsic carrier density Npeak number of pixel transfers between the peak of the observed impulse response and the peak of the ideal impulse response Nc effective density of states in the conduction band Nr> uniform donor density NT number of single electrode transfers fi normalized electron density ngap normalized cermet/GaAs junction electron density no normalized metal/GaAs junction electron density ND normalized uniform donor density vi p number of pixels q electron charge Qintj interface charge density Qs signal charge density Qs,max maximum signal charge density Qph.i+Ph.2 phase 1 and phase 2 signal charge density Qph.2+Pk.3 phase 2 and phase 3 signal charge density r geometric series constant RCM distributed cermet film resistance RL load resistance Rs series resistance RCM lumped cermet film resistance S derivative of the tangential current I(y) t time tdei delay time ttr clock transition period T temperature u normalized potential Ugap normalized cermet/GaAs junction potential Uo normalized metal/GaAs junction potential UT thermal voltage v normalized electron quasi-Fermi potential V(y) dc surface potential V(y,u) ac surface potential Vg applied gate voltage Vgap potential difference across the gap Vin,Iin diode terminal voltage and current vii Vp pinch-off voltage Vo incident voltage w cermet gate width wn space charge region depth wr relaxation parameter x,y spatial coordinates X{,yj spatial position at the i,jth grid point Xint active layer depth coordinate of the maximum potential xmax wafer thickness x,y x, y unit vectors x,y rr-component or y-component Umax pixel length VmLtV-mR transport electrode endpoints Y distributed shunt admittance z complex variable Z distributed series impedance 8 diode ideality factor Sjgap relative position along the gap Suimax normalized potential difference between the Fermi level and the intrinsic energy level at St time increment Sx grid spacing in the x-direction Sx a uniform active layer subdomain grid spacing Sx{,Sy grid spacings at the i,jth grid point fitpmax charge confinement ^Ci+i correction factor viii dielectric constant of GaAs charge transfer efficiency propagation constant electron drift mobility low-field electron drift mobility electron drift velocity radian frequency electrostatic potential maximum potential minimum value of the maximum potential cermet/GaAs Schottky barrier height metal/GaAs Schottky barrier height metal/GaAs junction potential electron quasi-Fermi potential length constant electron transit time surface potential phase shift electron drift velocity function fractional constant binary variable finite difference variable ordinary iterated solution for Cij./t+i relaxed solution for Ci,j,k+i ix List of Tables I A summary of the cermet/GaAs Schottky barrier parameters 26 II The distributed circuit parameters of the cermet/GaAs contact ... 31 III The lengths used in the two-dimensional computer model 40 IV A summary of the equations used in the CMCCD model 50 V The measured threshold voltages of the GaAs CMCCD 68 VI The signal levels applied to the GaAs CMCCD for operation at 100 MHz 69 VII The charge transfer efficiencies of the GaAs CMCCD for 100 MHz operation 72 x List of Figures 1.1 The cross-sectional views of a single pixel of a GaAs CGCCD and a GaAs CMCCD 3 2.1 A cross-sectional view of the 4-phase GaAs CMCCD with representative signal levels applied to the device nodes 7 2.2 The theoretical generation of a charge packet at the input section of a GaAs CMCCD using the diode cutoff method 9 2.3 The theoretical transfer of a charge packet through one pixel of a 4-phase GaAs CMCCD 11 2.4 The output sequence of a GaAs CMCCD 13 2.5 The abrupt charge approximation used in the one-dimensional analysis of the potential tp(x) underneath the center of a CMCCD transport electrode 14 2.6 The potential distribution under a CMCCD transport electrode for a fixed surface potential and a variable signal charge density 16 2.7 The potential distribution under a CMCCD transport electrode for an empty well condition and a variable surface potential 16 2.8 The two electrode model for the charge storage mode within a GaAs CMCCD 18 3.1 The cermet/GaAs Schottky barrier diode used to investigate the barrier properties of the cermet/GaAs junction 21 3.2 The dc current-voltage characteristic of the cermet/GaAs Schottky bar rier diode 23.3 The distributed resistive gate Schottky barrier diode model of the cer met/GaAs Schottky barrier diode 22 3.4 A differential length of the distributed resistive gate Schottky barrier diode model 23.5 The cermet/GaAs transmission line model of the uniform cermet/GaAs contact within an interelectrode gap of a GaAs CMCCD 27 3.6 A differential length of the cermet/GaAs transmission line model .... 27 3.7 The variation of the normalized surface potential along the gap of a GaAs CMCCD as a function of frequency 30 3.8 The variation of the normalized high frequency surface potential along the gap of a GaAs CMCCD as a function of the ratio CD/CCM 33 xi 3.9 The test structure and the test circuit used to demonstrate the validity of the transmission line model for the cermet/GaAs contact within a gap of a GaAs CMCCD 33 3.10 The amplitude response and the phase response of the cermet/GaAs test circuit 35 3.11 The lumped equivalent circuit of the cermet/GaAs transmission line test circuit 6 3.12 The theoretical amplitude response of the cermet/GaAs test circuit . . . 37 3.13 The theoretical phase response of the cermet/GaAs test circuit 37 4.1 The unit cell for modeling the GaAs CMCCD 39 4.2 The main finite difference grid for the GaAs CMCCD model 39 4.3 The nine-point computational kernel 42 4.4 The nonlinear electron velocity-field characteristic of GaAs 48 4.5 The flow diagram for the two-dimensional computer simulations 53 4.6 The maximum frequency of operation of a 4-phase GaAs CMCCD as a function of the clock voltage amplitude and the transport electrode length 55 4.7 The simulated single electrode transfer of a charge packet 56 4.8 The theoretical charge transfer efficiency as a function of time for the GaAs CMCCD obtained from the simulated single electrode transfer of a charge packet 57 5.1 A microphotograph of the fabricated GaAs CMCCD 60 5.2 A microphotograph of the input section of the GaAs CMCCD 61 5.3 A microphotograph of the output section of the GaAs CMCCD 61 5.4 A transmission electron microphotograph of the Cr:SiO ( 45 wt. % Cr ) film 64 5.5 A microphotograph of the plasma etch profile of a 5 micron square via etched through a 1.8 micron thick polyimide film 64 6.1 The wire-bonding configuration for packaging the GaAs CMCCD .... 67 6.2 The insertion loss of the on-chip GaAs MESFET source follower amplifier measured from 300 kHz to 200 MHz 67 6.3 The qualitative demonstration of the performance of the GaAs CMCCD for 100 MHz operation 70 6.4 The impulse response of the GaAs CMCCD for 100 MHz operation ... 70 xii 6.5 The insertion loss of the GaAs CMCCD for 100 MHz operation 71 6.6 The theoretical insertion loss of the GaAs CMCCD for 100 MHz operation 71 A.l A cross-sectional view of the BNL Experiment 787 rare kaon decay spec trometer 85 A.2 The ideal range stack photomultiplier tube output waveform for a pion to muon to electron decay sequence 86 A.3 A system block diagram of the data acquisition system employing a GaAs CMCCD 8A.4 A GaAs CMCCD operating in the frequency compression mode 87 E.l The schematic diagram of the test circuit used to operate the CMCCD in the VHF band 9xiii Acknowledgements I would like to express my thanks to my thesis supervisor, Professor Lawrence Young, for his assistance and guidance throughout this work. I would also like to thank Pro fessor David L. Pulfrey, Professor Richard R. Johnson and Mr. John V. Cresswell for co-supervising this project. My deepest thanks go out to Mr. John V. Cresswell, who is a Senior Research Engineer at TRIUMF, for introducing me to the broad subject of GaAs CCDs. Mr. Cresswell and I have spent many long hours exploring the nuances of these devices. He has my heartfelt thanks for his invaluable assistance throughout this project. A special note of thanks to Dr. R. Sahai of Rockwell International Corporation for the discussions that we had on the various points of interest that we share on the subject of GaAs CCDs. The knowledge gained from these discussions proved to be quite beneficial. There are a number of people that I am indebted to for their help dealing with the marry technical aspects concerning this project: Raymond Bula, Miles Constable, Hiroshi Kato, Yvonne Langley, Peter LeNoble, Michael LeRoss, Tony Leugner, Naomi Shibaoka, Peter Townsley and David Webster. I would also like to thank my colleagues in the Solid State Group within the Department of Electrical Engineering at UBC for the assistance they have given me. Finally, to my beautiful wife, Eveline, for having the patience to endure—I express my love and appreciation. xiv Chapter 1 Introduction The original proposal of a GaAs charge-coupled device was made in 1972 by Schuer-meyer et al [1], The transport electrodes of the proposed CCD structure consisted of metal/semiconductor Schottky barriers instead of the MOS structures commonly used with silicon CCDs. The Schottky barrier CCD has the advantage that it can be fabricated on GaAs using well developed GaAs MESFET fabrication techniques. This is important, as will be described later, for the monolithic integration of GaAs CCDs with auxiliary GaAs MESFET support circuits. A 3-phase GaAs capacitive gate CCD ( CGCCD ) employing metal/GaAs Schot tky barriers separated by narrow ( approximately 1 micron long ) dielectric filled in terelectrode gaps was demonstrated in 1977 by Kellner et al [2], and shortly there after in 1978 by Deyhimy et al [3]. One, two and four-phase GaAs CGCCDs have been produced and operated since the initial demonstrations of the 3-phase GaAs CGCCD [4,5,6]. GaAs CCDs have wider operating bandwidths than silicon CCDs as a result of the approximately five times greater electron mobility within GaAs at low to moderate electric fields. A limitation for the high frequency operation of a sili con CCD is attributed to the lower bandwidths and greater power requirements of the support circuits integrated with the device [1,7]. The highest clock frequency that a silicon CCD has been operated at, that this author is aware of, is 180 MHz which was reported by Esser and Sangster [8]. In comparison, a GaAs CMCCD was operated at 4.2 GHz as demonstrated by Sovero et al [9]. The best reported charge transfer effi ciencies ( CTEs ) attained by GaAs CCDs approach 0.9999 for CCD clock frequencies lying between 1.0 MHz and 1.0 GHz [10,9]. This level of performance has made the GaAs CCD desirable for signal processing applications that extend into the UHF band 1 ( 0.30 GHz-1.12 GHz ) [11,12,13,14,15,16,17]. A limitation that is encountered with using GaAs CGCCDs in UHF signal process ing applications arises from the difficulty of monolithically integrating GaAs CGCCDs with GaAs MESFETs. This difficulty is a consequence of the different active layer re quirements of the two devices. A GaAs CGCCD is typically fabricated on a 1-2 micron deep n-type epitaxial layer grown on a n~-buffer on a semi-insulating GaAs substrate. The donor density for the n-type epitaxial layer is chosen to lie within the range from 1015 cm-3 to 1016 cm-3 to maintain a reasonable pinch-off voltage suitable for the high frequency operation of the CGCCD. The active layer parameters described above for the GaAs CGCCD are not optimal for a typical GaAs MESFET which requires a thinner, more highly doped active layer. It is impractical to grow segregated regions of doped GaAs for CGCCDs and MESFETs using epitaxy, as the present epitaxial growth methods are not well suited to this task [18]. Ion-implantation would yield selectively doped regions of GaAs, but possesses some difficulty providing the deep active layers required for the fabrication of a GaAs CGCCD [19]. The performance of a GaAs CGCCD in a signal processing application is further limited by the charge transfer loss that arises from the formation of energy troughs within the active layer bounded on the GaAs surface by the interelectrode gaps [7,20]. An energy trough within a gap of a GaAs CGCCD has a minimum electron energy less than that of the regions under the transport electrodes adjacent to the gap. This energy trough will form within a gap of a GaAs CGCCD as a result of a non-monotonic surface potential distribution along the gap [7]. During the charge transfer process, the energy trough captures a quantity of charge from a charge packet as it passes through the region of minimum energy. The captured electrons are transferred to the CGCCD output at a later time or lost through recombination resulting in increased signal dispersion. Deyhimy et al [7] used a two-dimensional electrical analog for the GaAs CGCCD to show that the energy trough within a gap of a GaAs CGCCD was 2 Dielectric Y*-<1.0 fj,m Active layer NB*i 10 cm \ ^1.0 fxm J CGCCD Cermet -»-| \*->1.0 nm Active layer iV^Ra 10 cm t <1.0 fj.m I CMCCD Figure 1.1: The cross-sectional views of a single pixel of a GaAs CGCCD and a GaAs CMCCD illustrating the basic physical differences between the two devices. considerably reduced when the gap length was decreased. It was demonstrated that a gap length of less than 1 micron would result in the formation of a minimal energy trough in a GaAs CGCCD having a 2 micron deep active layer uniformly doped with a donor density of 1 • 1016 cm-3. The GaAs CMCCD demonstrated in 1982 by Higgins et al overcomes the practical limitations of using a GaAs CGCCD in a signal processing application [18]. The cross-sectional views of a single pixel of a GaAs CMCCD and a GaAs CGCCD are shown in Figure 1.1. The CMCCD is fabricated on a GaAs MESFET compatible active layer enabling the CMCCD to be monolithically integrated with MESFET support circuitry. The transport electrodes of a CMCCD are thinner than the transport electrodes of a CGCCD and are separated by a wider interelectrode gap. A thinner transport electrode provides an increased tangential electric field component under the electrode, resulting in improved charge transfer within the CMCCD [18,21]. The wider interelectrode sep aration of the CMCCD provides a considerable reduction in the dimensional tolerance 3 required to fabricate the device. The GaAs surface comprising the interelectrode gaps of a GaAs CMCCD is encap sulated with a cermet film. The cermet/GaAs junction was demonstrated in 1974 by Wronski et al [22] to form a Schottky barrier with a series gate impedance comprised of a parallel resistance and capacitance. During the operation of the CMCCD, a current will flow from a transport electrode through the cermet film to an adjacent transport electrode when a voltage difference exists between the two electrodes. The current through the cermet film establishes a potential distribution along the cermet/GaAs junction that varies monotonically in the direction of flow. Walden et al [23] deter mined, using two-dimensional computer modeling, that a monotonic surface potential variation across each of the interelectrode gaps of a CCD will prevent the formation of energy troughs within the device. This result suggests that a CMCCD will have reduced charge transfer loss during operation, and consequently will exhibit improved performance. The performance of the GaAs CMCCD has been demonstrated in two signal pro cessing applications: a high speed GaAs detector array/CMCCD multiplexer [24] and a GaAs VHF/UHF agile bandpass filter [25]. These applications have been developed by a group at the Rockwell International Microelectronics Research and Development Center ( Thousand Oaks, California ) and are the only demonstrated applications of GaAs CCDs that this author is aware of. The high speed GaAs detector array/CMCCD multiplexer has been developed for an acousto-optic spectrum analyzer. In this application, an array of thirty-two GaAs photodiodes are multiplexed by a 64-pixel, 4-phase GaAs CMCCD using a side-feed arrangement. The photodiodes and the CMCCD are interconnected by a gating circuit provided by GaAs MESFETs integrated on-chip. The currents generated by each of the photodiodes are integrated onto hold capacitors producing thirty-two discrete charge packets. The charge packets are injected into the CMCCD channel in a parallel manner 4 using the MESFET gating circuit and are subsequently transferred to the CMCCD output for further processing. Real-time signal processing with this device has been demonstrated using a CMCCD clock frequency of 1.0 GHz. The GaAs VHF/UHF agile bandpass filter has been developed for frequency se lective filtering applications. This device employs GaAs CMCCDs arranged in a pipe-organ structure to provide weighted sampling, programmable delay and summing of analog signals. Supervisory functions are provided by GaAs MESFET circuits in tegrated monolithically with the CMCCDs. The CMCCD agile bandpass filter has demonstrated in excess of 60 dB of dynamic range for lowpass, bandpass and highpass filter operations using a 1.0 GHz input sampling rate [26]. The two GaAs CMCCD applications described above have demonstrated the ability to monolithically integrate the CMCCD with other circuits to provide sophisticated signal processing functions. A GaAs CMCCD signal processing system is presently being developed at TRI-UMF ( Tri-University Meson Facility, Vancouver ) to satisfy the instrumentation re quirements for a nuclear physics experiment—BNL Experiment 787. A 64-pixel, 4-phase GaAs CMCCD comprises an essential part of a wideband data acquisition sys tem capable of recording 250 MHz bandlimited analog signals. The nuclear physics experiment and the GaAs CMCCD wideband data acquisition system are described in Appendix A. The purpose of this work is to provide a theoretical and practical development of a 64-pixel, 4-phase GaAs CMCCD. The design, implementation and evaluation of this device are described in the following chapters. 5 Chapter 2 Theory 2.1 Principle of Operation A GaAs CMCCD functions as a programmable delay line. The input signal is applied to the input ohmic contact ( I/O ) and is sampled by the input section at fixed time intervals producing a sequence of discrete charge packets. The charge packets are sequentially injected into the CMCCD transport region where they are transferred to the output ohmic contact ( 0/P ) under the control of the quadrature clocks. At the output section of the CMCCD, the charge packets are converted to an analog signal corresponding to the original input signal delayed by an amount of time Uel = J (2.1) Jc where t^i is the delay time assuming ideal operation, p is the number of pixels com prising the CMCCD and fc is the CMCCD clock frequency. A cross-sectional view of a 4-phase GaAs CMCCD with representative signal levels applied to the device nodes is shown in Figure 2.1. The signals applied to the nodes of the CMCCD are engaged in a sequential manner during the initial start-up of the device. The bottom surface of the semi-insulating GaAs substrate, the input ohmic contact and the output ohmic contact are biased first, to the reference potential of 0 volts. Next, the control gates Gi, G2 and G3 are biased negatively with respect to the ohmic contacts by amounts that are less than or equal to the pinch-off voltage of the CMCCD active layer ( typically -2.0 volts ), depleting the volume of semiconductor under these gates. The quadrature clocks with voltage levels of 0 volts and -5 volts are subsequently applied to the CMCCD, transferring the remaining electrons within the channel to the output of the device 6 •*HH*~ Time displacement R/G R/S B/D Ph. 2 Ph. 4 Ph. 1 Ge I/P TJJU Ph. 3 Ph. 4 rm TJJJI B/O — nnr CMCCD Active Layer Input Output B/S Figure 2.1: A cross-sectional view of the 4-phase GaAs CMCCD with representative signal levels applied to the device nodes. 7 where they are removed. The input signal is applied to the input ohmic contact once the fully depleted condition is achieved within the channel. Charge packet generation and injection at the input section of the GaAs CMCCD is accomplished using the diode cutoff method developed by Sequin and Mohsen [27]. The input signal is ac coupled to the input ohmic contact and offset by a positive dc bias, resulting in an applied input signal ranging positively from 0 volts. The phase 3 and phase 4 clock signals are ac coupled to the two input control gates Gi and G2, ensuring synchronization between the generation of the charge packet at the input section and the subsequent injection of the charge packet into the transport region. An apparent negative time delay is added to the phase 3 clock signal applied to the input control gate Gi to minimize forward charge injection during the charge packet generation sequence. The negative time delay is achieved by delaying the phase 3 clock signal applied to Gi by a positive amount equal to the clock period less a small time, displacement ( typically 0.5 nanoseconds for a 10 nanosecond clock period ). Figure 2.2 illustrates the theoretical sequence of events that occur to create a dis crete charge packet under the control gate G2 using the diode cutoff method. Initially, the active layer extending from the vicinity of the right-hand edge of the input ohmic contact to the right-hand edge of G2 is depleted of electrons. Electrons flow into the potential well formed under Gi from the input ohmic contact during the positive tran sition of the delayed phase 3 clock applied to Gj. A steady-state condition for the electron density distribution within the potential well under Gi is achieved during the intervening time prior to the positive transition of the phase 4 clock applied to G2. Elec trons from the input ohmic contact and from the potential well formed under Gi flow into the potential well formed under G2 during the positive transition of the phase 4 clock applied to G2. A steady-state electron density distribution is achieved within the composite potential well formed under both of the input control gates during the remainder of the positive half cycle of the delayed phase 3 clock. During the negative 8 I/p 1: 1 2 3 4 1 I/P G, iiiiiiiiiiiiiiiiiiiiiiurr Depleted Figure 2.2: The theoretical generation of a charge packet at the input section of a GaAs CMCCD using the diode cutoff method [27]. 9 transition of the delayed phase 3 clock applied to Gi, the electrons residing within the potential well formed under this gate are swept out through the input ohmic contact leaving a discrete charge packet within a potential well residing under the control gate G2. The magnitude of the localized charge packet within this potential well is a function of the active layer depth, the active layer donor density distribution and the voltage difference between the input ohmic contact and the control gate G2 at the time of the negative transition of the delayed phase 3 clock applied to the control gate Gi. A full well of charge is produced under the control gate G2 when this voltage difference is at its minimum value ( approximately 0 volts ). The charge packet residing in the potential well formed under G2 is subsequently injected into the transport region where it is transferred to the output ohmic contact. The injection of the charge packet into the transport region occurs on the positive transition of the phase 1 clock. Figure 2.3 illustrates the theoretical transfer of a charge packet through one pixel of a 4-phase GaAs CMCCD. As indicated in Figure 2.3, the charge packet occupies a potential well that spans two transport electrodes during the transfer process. This is a consequence of the 4-phase clocking scheme that is used. The directionality of charge motion is achieved by the tangential electric fields that arise within the CMCCD channel as a result of the differences between the clock voltage levels applied to the transport electrodes. The clocking scheme chosen for operating the CMCCD is important as it deter mines the complexity of both the CMCCD and the clock circuits. The 4-phase structure was chosen for the CMCCD as it has the advantage of not requiring 'built-in' direc tionality of charge motion, resulting in reduced fabrication requirements to produce the device. The reduced fabrication requirements for producing the 4-phase CMCCD are made at the expense of increased clock circuit complexity. The quadrature clocks that are needed to operate the 4-phase CMCCD require a modest level of circuit de sign sophistication to achieve the wide bandwidths necessary to operate the device in 10 Ph. 2 1 / i Ph. 3 2 i Ph. 4 Ph. 1 Ph. 1 I I Ph. 2 Ph. 3 Ph. 4 EKXXX>J Ph. 1 rVx-x^yi Transfer direction Figure 2.3: The theoretical transfer of a charge packet through one pixel of a 4-phase GaAs CMCCD. 11 the UHF band. The key issue is the difficulty obtaining stable wideband 90° phase shifts between successive clock phases. The current GaAs MESFET integrated circuit technology is capable of providing a solution to this difficulty [12,13,15,16]. A charge packet transferred to the potential well residing under the final phase 4 transport electrode of the GaAs CMCCD is transmitted to the output ohmic contact on the negative excursion of the phase 4 clock. The output ohmic contact of the CMCCD is precharged to 0 volts during the positive half cycle of the phase 3 clock using the external reset GaAs MESFET. The reset MESFET is disabled during the negative half cycle of the phase 3 clock allowing the output ohmic contact to float at its precharged value. The electrons passing through the potential well formed under G3 exit the CMCCD through the floating output ohmic contact, charging the parasitic capacitance Co/p and driving the output ohmic contact voltage negatively with respect to its precharged value. A full well of charge arriving at the output ohmic contact will drive the output ohmic contact voltage to its most negative level. The signal produced at the output ohmic contact is buffered from the external output signal processing 0 circuitry using a MESFET source follower amplifier integrated monolithically with the CMCCD. There is usually some distortion observed in the signal obtained from the output of the source follower amplifier which is a consequence of the passive feedthrough of the quadrature clocks to the output ohmic contact. This is reflected as a level change at each occurrence of a clock transition and is illustrated in the output sequence shown in Figure 2.4. 2.2 One-dimensional Potential Distributions The one-dimensional solution of Poisson's equation for the potential distribution un derneath the center of a CMCCD transport electrode, perpendicular to the surface, was determined using the abrupt charge approximation shown in Figure 2.5. The charge distribution illustrated in Figure 2.5 is similar to the one used by Hansell [20] with the 12 Qsto 0/P Ph. 4 R/G B/0 Feedthrough Floating Precharge — Empty well — Full well Signal displacement due to Qs/C0//p R/G R/S B/D CMCCD Output: o/p Ph. 4 ivwwza fwvwza O/P — B/0 B/S Figure 2.4: The output sequence of a GaAs CMCCD. The signal obtained from the output of the source follower amplifier includes the effects of passive feedthrough from the clocks to the output ohmic contact. 13 Abrupt 1 — dL Charge Dercsxty Profile , , , Active layer SI substrate O.O to DC int Distance xrxto GaAs: cc Figure 2.5: The abrupt charge approximation used in the one-dimensional analysis of the potential ip(x) underneath the center of a CMCCD transport electrode. exception that the depth of the space charge region is variable. Poisson's equation for the illustrated charge distribution is d2ip(x) _ qND dx* 0 < x < w „ (2.2) for the space charge region within the active layer and d2xp{x) dx2 0 wn < x < xr (2.3) for the quasi-neutral region within the active layer and for the semi-insulating substrate. The signal charge \Qs\ = qND(xint-wn) (2.4) resides within the channel defined by the quasi-neutral region wn < x < x,n<. Here xp(x) is the potential, No is the uniform active layer donor density, q is the charge of 14 an electron, e is the dielectric constant of GaAs, X{ni is the active layer depth, xmax is the wafer thickness and wn is the depth of the space charge region under the transport electrode. The potential ip(x) is related to the intrinsic energy Ej(x) within the GaAs by the relationship —qip(x) — Ei(x) — Ei(xmax). The boundary conditions are described below. The surface potential is equal to the potential difference Vg between the Fermi level at the surface and the Fermi level at the bottom of the substrate less the potential difference between the metal/GaAs Schottky barrier height at the surface </>BM,O and the metal/GaAs Schottky barrier height at the bottom of the substrate (f>BM,xmax V>(0) = %l>0 = Vg - (<f>BMfi - <t>BM,xmax) ; (2.5) the potential and the electric field across the interface at x = wn are continuous i>(wn_) = V(^n+) , (2.6) dx dx (2.7) and the reference energy level is Ei(xmax). The solutions for equation 2.2 and equation 2.3 using the boundary conditions 2.5,.. .,2.7 are qNDx2 (qNDwnxmax qNDw2n \ x . ^(x) = « + 7)—" - + *Po 0 < x < wn (2.8) \ ^ / xmax and / / \ (QNpwl \ x qNDw2n ip(x) = - I — h ip0 I 1 h tyo wn<x< xmax . (2.9) \ / Xmax Z6 The potential variation holding the surface potential ipo constant at zero volts and vary ing the magnitude of the signal charge \QS\ within the CMCCD is shown in Figure 2.6 and similarly the potential variation for the empty well condition \QS\ =0 within the CMCCD and varying the surface potential is shown in Figure 2.7. The peak poten-15 f — d. P'otential Distributions Distance into GaAs: oc Figure 2.6: The potential as a function of position underneath the center of a CMCCD transport electrode. The surface potential ^0 1S held constant at zero volts and the signal charge density is varied. f — d Potentxal Distributions Distance irtto GaAs: ac Figure 2.7: The potential as a function of position underneath the center of a CMCCD transport electrode. The signal charge density is held at the empty well condition \QS\ = 0 and the surface potential ip0 is varied. 16 tial within the CMCCD active layer occurs near the depletion region boundary at the location xm The corresponding maximum potential "4>max at this location is ZQi\f)Xmax \ %max' Xmax y ^Xmax •^max J 2.3 Active Layer Specification The design of a GaAs CMCCD requires choosing an active layer depth and an active layer donor density No that are compatible with GaAs MESFETs. The pinch-off voltage of a typical n-type depletion mode GaAs MESFET usually lies between -3 volts and -1 volt constraining the pinch-off voltage of the CMCCD active layer to lie between these two values. The active layer parameters X{ni and No for the GaAs CGCCD were determined by Deyhimy et al [7] and by Hansell [20] to provide a predetermined maximum potential ipmax. The active layer parameters of the GaAs CMCCD were determined using a new method which simultaneously maximizes the charge confinement and the signal charge capacity. Consider the two adjacent transport electrodes of a CMCCD illustrated schemat ically in Figure 2.8. Under the left-hand electrode resides a full well of charge as defined by equation 2.4 with wn equal to a small fraction </? « 0 of the active layer depth Xint \Qs,max\ = qND(l ~ <p)xint « qNDXint . (2.12) Furthermore, assume that the left-hand electrode is biased to the most positive clock voltage level such that ipo,ieft = 0 volts. The resultant maximum potential under this electrode using equation 2.11 is ^.-Wl-P^2^)^**!) . (2.13) \ ^Zmax xmax I 17 int max, left max, right Figure 2.8: The two electrode model for the charge storage mode within a GaAs CM-CCD. A full well of charge resides in the potential well formed under the left-hand electrode. The two electrodes are biased such that 4>max,ieft > *J>max,righ.t • Similarly, an empty well resides under the right-hand electrode which is biased to the most negative clock voltage level such that rpo,right = V'min < 0 volts. The maximum potential that results under the right-hand electrode using equation 2.11 is '•2 ' ~. N ./. . / Xint x]nt \ qNDx] I _ „/, i €t^min (1 , Xint \ xint'll,min (1 Vmax.right ~ V>min + „ „ , I 1 + ~ I — + I 1 ~ ^yJY U^max N •L'm.a.x' •''max \ _|_ mi I *s %nt 2xmax XmaxJ 2f (2.14) The configuration described above corresponds to the case where a charge packet is confined to a potential well residing under the left-hand electrode as a result of a blocking voltage applied to the right-hand electrode. It is necessary that t/Wx.ie/t > il>max,right for charge confinement. The charge confinement 8tpmax is defined as the potential difference between rpmax,ieft and ipmax,right- The following equation for 6tpmax is obtained from equations 2.13 and 2.14 Hmax = lj>max,Uft ~ ^max,right « (|Vw| ~ \Vp\) ~ (|Vw| ~ ^ ) (2-15) where it has been assumed that xmax ^> X{nt and 2 \VP\ = < |^,n| (2-16) 18 is the magnitude of the pinch-off voltage for a uniformly doped n-type active layer [28]. The following relationship for the maximum signal charge density \Qs,max\ oc 1^1 (2.17) is obtained from equation 2.12 and equation 2.16. The values of X{nt and Nrj for the GaAs CMCCD are determined using the design equations 2.15, 2.16 and 2.17 with the assumption that the pinch-off voltage Vp is a con stant value. To simultaneously maximize the charge confinement 6ipmax and the signal charge capacity Qs,max it is necessary to use a thin, highly doped active layer. Equa tions 2.15 and 2.17 indicate that 8tpmax and QStmax approach maximum values when the active layer depth #;n< approaches a minimum value. Under the assumption of a constant pinch-off voltage, equation 2.16 indicates that the active layer donor density No approaches a maximum value when the active layer depth approaches a minimum value. The above qualitative analysis supports one of the principal advantages of a GaAs CMCCD, the signal charge capacity and the charge packet confinement are opti mum for devices fabricated on active layers that are suitable for MESFETs. The GaAs CMCCDs that were fabricated as part of this research utilized epi-wafers possessing a uniform active layer donor density of 4.5 • 1016 cm-3 and an active layer depth of 0.25 microns, corresponding to a pinch-off voltage of approximately -2.0 volts. 19 Chapter 3 The Cermet/GaAs Junction 3.1 Barrier Properties A distributed resistive gate Schottky barrier ( SB ) diode model is described in this sec tion. This model was used to determine the barrier properties of the cermet/GaAs junc tion from the measured dc current-voltage characteristic of a fabricated cermet/GaAs SB-diode. The experimental current-voltage measurements were conducted with the planar cermet/GaAs SB-diode illustrated in Figure 3.1. The diode consisted of a Cr:SiO ( nom inal 45 wt. % Cr ) cermet gate attached at one end to a gold contact, a Au-Ge/Ni/Au ohmic contact separated from the cermet gate by a 5.0 micron gap and an active layer possessing a donor density of 4.5 • 1016 cm-3 to a depth of 0.25 microns. The dc current through the diode as a function of the applied dc voltage difference between the gold cermet gate contact and the ohmic contact was measured using a Hewlett-Packard HP-4145A Semiconductor Parameter Analyzer connected to a Wentworth probe station. The measurements were conducted in the dark to minimize photocurrent generation within the diode. The diode current I{n measured for discrete input voltages V{n lying between -5 volts and +5 volts is shown in Figure 3.2. It is apparent upon inspection of Figure 3.2 that the cermet/GaAs SB-diode exhibits rectification properties similar to that of a metal/GaAs SB-diode possessing a large series gate resistance. The dc operation of the cermet/GaAs SB-diode illustrated in Figure 3.1 is modeled using the distributed resistive gate SB-diode model shown in Figure 3.3. The resistor Rs is the series resistance ( ohms ) between the gold cermet gate contact and the active region of the diode plus the series resistance of the bulk GaAs, and RCM is the distributed resistance ( ohms/unit length ) of the cermet film. 20 1 Gold g Contact vy, 1 ^^^^^^Cermet ^ ^^^^^^^^^ •« 0.01 cm ^ u Ohmic Contact o >^ o — 5.0 fim Isolated 1 Active Layer 16 —"3 ND=4.5 10 cm xint=0.25 fim Isolated Figure 3.1: The cermet/GaAs Schottky barrier diode used to investigate the barrier properties of the cermet/GaAs junction. I— V Characteristic 16 14 12 ^10 Co a 6 4 Q5 o 3 2 0 -2 10=3.6 rtA (3 =1.17 <j>Bc=0.64 volts M eaaured, data ° Theory aaaaaaau -6 -4 -2 0 2 4 6 Bias Voltage (V) Figure 3.2: The dc current-voltage characteristic of the cermet/GaAs Schottky barrier diode. The solid line is obtained after fitting equation 3.20 to the data. 21 Ohmic contact Figure 3.3: The distributed resistive gate Schottky barrier diode model of the cer met/GaAs Schottky barrier diode. — i( y) RCMdy wwwvw-+ dV(y) -v(y) 'SB dl(y) dy Figure 3.4: A differential length of the distributed resistive gate Schottky barrier diode model. 22 The current normal to the cermet/GaAs junction is modeled using the distributed SB-diode, DSB-A differential length of the distributed resistive gate SB-diode model is shown in Figure 3.4. The differential voltage drop along this length and the differential current normal to the cermet/GaAs junction are dV(y) = RCMl(y)dy (3.1) dl(y) = wJ0 dy (3.2) 6XP \WT) where y is the position variable, w is the cermet gate width, 0 is the ideality factor, U~T is the thermal voltage and Jo is the saturation current density. The saturation current density is given by [29] Jo = A*T2exP(^) (3.3) where A* is the modified Richardson's constant, CJ>BC is the cermet/GaAs Schottky barrier height and T is the temperature. Differentiating equation 3.2 with respect to the variable y gives cPI wJ„ I V \ dV w = WTexp{im)^ • (3'4) Substituting equation 3.1 and equation 3.2 into equation 3.4 yields ^-al^--bl = 0 (3.5) dy2 dy where a = RCM/0UT and b — WRCMJO/0UT are constants. The nonlinear second-order differential equation 3.5 describes the spatial variation of the tangential current along the cermet/GaAs junction. This equation can be solved analytically in the following manner [30]. Substitute S=f (3.6) dy and fl_dS _ dSdl _ gdS_ ^ ^ dy2 dy di dy di 23 into equation 3.5 to give the following first-order linear differential equation S^-(aS + b)I = 0 . (3.8) al The solution to equation 3.8 is obtained using separation of variables S-b-ln(s+b-) = a-f + Cl (3.9) a \ a J 2 where C\ is a constant of integration determined as follows. As the tangential current 7. approaches zero the derivative of the tangential current with respect to the variable y also approaches zero. Hence, the boundary condition for equation 3.9 is S(I = 0) = 0 (3.10) which yields c: = --In (-a \ a, Substituting equation 3.11 into equation 3.9 gives _ 6, /, aS\ al2 S - - In I 1 + — ) = — • a \ b J 2 Equation 3.2, equation 3.6 and the relationship b/a — wJ0 yields S = exp ' V Substituting equation 3.13 into equation 3.12 gives exp (v(y)\ _YM_1 = q2/%) (3.11) (3.12) (3.13) (3.14) \PUT) PUT ' 2b Rearranging equation 3.14 results in an expression for the current I(y) as a function of the voltage V(y) (3.15) i(y) = io exp(m)_m_1 where Io = ±— = ± a l2wpUTJ0 •CM (3.16) 24 is the saturation current. The sign of the saturation current is chosen to be the same as the sign of the voltage V(y). The ideality factor, the saturation current and the Schottky barrier height of the cermet/GaAs Schottky barrier were determined from the measured current-voltage data of the cermet/GaAs SB-diode shown in Figure 3.1. The distributed resistive gate SB-diode model illustrated in Figure 3.3 yields Vin = RSIIN + V(0) (3.17) for the dc terminal parameters of the cermet/GaAs SB-diode. The diode voltage V(0) is obtained from equation 3.15 with 1(0) = IIN Under forward bias conditions where V(0)/3U~T > 3, equation 3.18 yields V(0)^23UT\n(j^j . (3.19) Substituting equation 3.19 into equation 3.17 gives Vm = RJin + 23UT\n(j^j . (3.20) Fitting equation 3.20 to the measured current-voltage data of the cermet/GaAs SB-diode for Vin > 0.2 volts yields the solid line illustrated in Figure 3.2 and the barrier parameters listed in Table I. 3.2 Surface Potentials It was demonstrated in the previous section that the cermet/GaAs junction forms a Schottky barrier. This characteristic is used to control the surface potential within the interelectrode gaps of the GaAs CMCCD. It will be demonstrated in this section using a cermet/GaAs transmission line model that the surface potential varies monotonically along the gap of a GaAs CMCCD. 25 Parameter Value T 300 K UT 0.0259 volts w 100 firn A* 7.8 • 10~8 A///m2-K2 Rs 287.9 kQ RcM 55 kfl/ftm 1.17 Io 3.60 nA <t>BC 0.64 volts Table I: A summary of the cermet/GaAs Schottky barrier parameters. The proposed cermet/GaAs transmission line model of a uniform cermet/GaAs contact within an interelectrode gap of a GaAs CMCCD is illustrated in Figure 3.5 with a differential length of the cermet/GaAs transmission line shown in Figure 3.6. The distributed series impedance Z ( ohms/unit length ) is modeled using the parallel network [22] comprised of the distributed cermet film resistance RCM ( ohms/unit length ) and the distributed cermet film capacitance CCM ( farads-unit length ) 2 RCM 1 + JWRCMCCM where u is the radian frequency. The distributed shunt admittance Y ( siemens/unit length ) is modeled using the distributed depletion layer capacitance of the active layer CD ( farads/unit length ) Y=juCD . (3.22) The position along the gap is denoted by the variable y with y = 0 defined at the right-hand edge of the left-hand transport electrode and y = LG defined at the left-hand edge of the right-hand transport electrode. The spatial variation of the surface potential along the gap is described by the voltage wave equation for a uniform transmission line [31]. For harmonically varying 26 3.21 Cermet Left electrode Right electrode GaAs active layer y y=0 Figure 3.5: The cermet/GaAs transmission line model of the uniform cermet/GaAs contact within an interelectrode gap of a GaAs CMCCD. y Zdy 'CM R, CM UVWWVVV\AJ + dV(y,o}) V(y.io) Ydy dy Figure 3.6: A differential length of the cermet/GaAs transmission line model. 27 voltages this equation is d2V(y,u) = YZV{y,u) . (3.23) where the factor e3Wt has been suppressed. The solution to equation 3.23 is V(y, u>) = kxe^y + k2e~^y (3.24) where &1? k2 are integration constants and 7(0;) is the propagation constant / JUJRCMCD 1 + JUJRCMCCM UJRCMCD \ exp ^1 + (URCMCCM)2 . j ( 1 — arctan 2 \WRCMCCM (3.25) The boundary conditions imposed on the solution 3.24 are V{y = 0) = V0 (3.26) V(y = Lg) = 0 (3.27where V0 > 0 is the incident voltage amplitude. The integration constants ki and k2 are obtained by substituting the boundary conditions 3.26 and 3.27 into equation 3.24 to give kx = — —(3.28) k2 = VlT , , . (3.29) Substituting equation 3.28 and equation 3.29 into equation 3.24 yields the solution for the surface potential along the gap as a function of position and frequency %») = 5%fMF„ . (3.30) smh[L37(cj)J The surface potential V(y,u) is conveniently expressed in polar form as V(y,u) = V0H(y,u;)L6(y,u>) (3.31) 28 where H(y,u) is the normalized magnitude of the surface potential i 'cosh2 [a(y,u)] - cos2 [b(y,u)}\ 2 cosh2 [c(o;)] — cos2 [<i(u>)] (3.32) and Q(y,u>) is the phase shift of the surface potential 0(y,cj) = arctan (coth[a(y,u;)] tan[&(y,u>)]) — arctan (coth[c(u;)] tan[d(u;)]) . (3.33) The functions a(y,u), b(y,u), c{u) and d(u>) are URCMCD a(y,u) = b(y,u) = c(u) = d(u) = yjl + (WRCMCCM)2 URCMCD yjl + (U>RCMCCM)2 ^1 + (URCMCCM)2 URCMCD (Lg - y)cos (Lg - y) sin 1 / 1 - arctan ( — I KOJitCM^CM 1 ( 1 - arctan I —— — 2 \WRCMCCM Lg cos Lg sin n - arctan . . 2 \LORCMCCM / -1 / 1 - arctan I — — 2 \OJRCM^CM {3.34) ,(3.35) (3.36) (3.37) iyi + (OJRCMCCM)' The derivation of the polar form of V(y,o>) is described in Appendix B. The function H(y,u>) described by equation 3.32 decreases monotonically for the choice of boundary conditions 3.26 and 3.27 used above. Interchanging the bound ary conditions will result in the surface potential increasing monotonically, as the cer met/GaAs transmission line model illustrated in Figure 3.5 is symmetric. It is sufficient to show that equation 3.32 satisfies the condition 9H(y,u>) dy < 0 (3.38) w=constant to demonstrate that the surface potential varies monotonically on the interval 0 < y < Lg for all frequencies u > 0. Differentiating equation 3.32 with respect to the variable y gives dy dH(y,u) _ cosh [a(y, u)} sinh [a(y, u>)] ^ff1 + cos [b(y, u)} sin [6(y, u)] (cosh2 [a(y, u)} - cos2 [6(y, u)]) * (cosh2 [c(u)} - cos2 [d(u)]) ' (3.39) 29 Surface Potentials O.O O.S 1.0 1.5 Z.O 2.5 3.0 Distance along the Gap: y (/umj Figure 3.7: The variation of the normalized surface potential along the gap of a GaAs CMCCD as a function of frequency. The functions a(y,u;), b(y,u)), c(u) and d(uj) are positive functions of y and a>, and the derivatives da(y,uj)/dy and db(y,u>)/dy are negative functions of a;. Consequently, the derivative of the normalized surface potential H(y,u>) with respect to the variable y is negative, satisfying the condition 3.38. The variation of the normalized surface potential along a gap of a GaAs CMCCD as a function of frequency is illustrated in Figure 3.7. Equation 3.32 and the parameter values listed in Table II were used to produce the curves. The parameter values were obtained using a Hewlett-Packard HP-4275A Multi-Frequency LCR Meter and an Alessi probe station to perform low-frequency ( 10 kHz ) impedance measurements on a fabricated cermet/GaAs test structure. It is apparent from Figure 3.7 that the surface potential decreases monotonically along the gap for all positive frequencies. There are two special cases which are of interest: the case when the frequency approaches zero and the case when the frequency approaches infinity. 30 Parameter Value Scale Factor RCM 55 kfi/^m X5/127 CCM 0.8 pF-fim 127/L, cD 15 fF/fxm 127L, L3 3.0 fim — Table II: The distributed circuit parameters of the cermet/GaAs contact. The dc surface potential variation along a gap of a GaAs CMCCD is linear. The propagation constant j(u>) is zero when UJ = 0 resulting in an indeterminate form for the normalized surface potential H(y,u> — 0). L'Hospital's rule is used to resolve the indeterminate form H(y,U = 0) = lim Sinh -Y("HO smh[Lfl7(u;)] Hm (Lg-y)cosh.[(Lg-y)j(u)] 7M-0 L3cosh[L57(a;)] (3.40) Equation 3.40 is intuitively correct. At low frequencies the electric current through the cermet/GaAs contact would be dominantly through the distributed cermet film resistance RCM and would result in a linear surface potential variation. This intuitive argument was probably the basis for deriving the name resistive gate CCD applied to the original cermet gate CCD described in reference [18]. The adjective resistive used in the cited reference is considered to be a misnomer [32] as it implies that the surface potential variation along a gap of a GaAs CMCCD is established via resistive conduction only, and does not take into consideration the effect of capacitive coupling within the cermet film at higher clock frequencies. The adjective cermet has been used instead to avoid the implications of the term resistive. The high frequency normalized surface potential variation along a gap of a GaAs 31 CMCCD is H(y,u -» co) = sinh [y/^(L> ~ y)] (3.41) where the high frequency value for the propagation constant 7(0;) is determined using equation 3.25 Equation 3.41 is independent of the distributed cermet film resistance RCM- This suggests that a wide range of cermet film resistivities can be used in the design of a GaAs CMCCD. A requirement that must be satisfied by the cermet film resistivity is that it must be large enough to comply with the power constraints of the CMCCD quadrature clock drivers. The capacitive coupling between the cermet film and the underlying GaAs is responsible for establishing the high frequency surface potential variation along a gap of a GaAs CMCCD. Figure 3.8 illustrates the effect of different ratios of CD/CCM ON the normalized high frequency surface potential H(y,u —> 00). It is apparent from the curves illustrated in Figure 3.8 that it is desirable to minimize the ratio CDJCCM M order to maintain a nearly linear surface potential variation for all frequencies. The reason for this is that a virtual equipotential zone extends along the surface into the gap near the right-hand transport electrode at y = LG for large ratios of CD/CCM-The extent of this zone increases with this ratio. This is undesirable as the tangential electric field within the active layer would be reduced underneath the equipotential zone along the surface, creating a source of potential loss of performance in a GaAs CMCCD operating at high frequencies. Minimizing the ratio CD/CCM would reduce this negative effect. 3.3 Verification Frequency response measurements performed on a 2-port cermet/GaAs test structure were used to test the validity of the cermet/GaAs transmission line model. The test (3.42) 32 Surface Potentials O.O O.O 0.5 1.0 1.5 2.0 2.5 3.0 Distance along the Ga-p: y (fjunx) Figure 3.8: The variation of the normalized high frequency surface potential along the gap of a GaAs CMCCD as a function of the ratio CD/CCM-64 fingers-Ohmic contact Cermet Active region Port 1 Port 2 [) 50 ohmT} HP-85047A Port A j-e- 3.0 fim Ohmic contact Port B 50 ohm )HP-85047A Figure 3.9: The test structure and the test circuit used to demonstrate the validity of the transmission line model for the cermet/GaAs contact within a gap of a GaAs CMCCD. 33 structure was fabricated on a n-type active layer ( ND = 4.5-1016 cm-3, x,ni = 0.25 mi crons ) and consisted of two interleaved arrays of sixty-four, 3 micron long Ti-Pt-Au Schottky barriers encapsulated with a nominal 5000 A thick cermet film deposition of Cr:SiO ( nominal 45 wt. % Cr ). The separation between adjacent metal fingers was 3 microns. Two Au/Ge-Ni-Au ohmic contacts were provided at each end of the 100 micron wide active region. The test structure was packaged in a leadless chip car rier which permitted external connections to be made to the two ports. The ohmic contacts were connected to the reference potential and the two electrode arrays were connected to the measurement apparatus using 50 ohm rigid copper coaxial cables. The test structure and the test circuit are shown schematically in Figure 3.9. The frequency response measurements consisted of measuring the amplitude re sponse and the phase response of the cermet/GaAs test structure. The measurement apparatus consisted of a Hewlett-Packard HP-8753B network analyzer and an HP-85047A s-parameter test set. The 50 ohm port A and port B terminals of the s-parameter test set were connected to the two ports of the test structure. The amplitude response and the phase response were measured using a 0 dBm, 300 kHz-500 MHz swept rf signal and are shown in Figure 3.10. The reference levels are indicated in each of the two plots by the arrows. The marker triangle labeled with the number '1' coincides with the maximum observed phase shift of 53.1° at 12.8 MHz. The lumped equivalent circuit shown in Figure 3.11 was used to model the the oretical frequency response of the cermet/GaAs transmission line test circuit. The transmission line length LG = 3 microns is much less than the effective wavelength of the cermet/GaAs transmission line below 500 MHz operation, hence the one hundred twenty-seven parallel connected cermet/GaAs transmission lines are modeled approx imately using the lumped elements RCM, CCM and CD- The lumped element values are obtained from the distributed element values listed in Table II after multiplying by the scale factors listed in the third column of this table. The theoretical amplitude 34 CHI S21 log I'lflG 3 dB/ REFBclB i: -17. 258 d B START .300 000 MHz STOP 500.000 000 MHz CH 2 S21 phase 7.5 °/ REF 0 0 1: 53.108 0 START .300 000 MHz STOP 500.000 000 MHz Figure 3.10: The amplitude response ( 3 dB/division ) and the phase response ( 7.5°/division ) of the cermet/GaAs test circuit measured from 300 kHz to 500 MHz. 35 o + 'CU R cu 4AA/VWW\r V(0,G>) o-V(L.,a>)$-*i o-Figure 3.11: The lumped equivalent circuit of the cermet/GaAs transmission line test circuit. response of the test circuit is Rj + (CVRLRCMCCM)2 \ (RL + RCM)2 + (URLRCM[CD + CCM})2 ) (3.43) and the theoretical phase response of the test circuit is $ = arctan (WRCMCCM) — arctan ( U^L^M^^ ^CM) j (3.44) ' \ RL + RCM J The theoretical amplitude and phase responses of the cermet/GaAs test circuit are illustrated in Figures 3.12 and 3.13, respectively. The theoretical and measured re sponses are in reasonable agreement, supporting the cermet/GaAs transmission line model described in the previous section. The deviation between the theoretical and measured responses is a result of the parasitic components associated with the inter connect wiring between the cermet/GaAs test circuit and the network analyzer, which are neglected in the above analysis. Ada = -20 log V(Lg,u) = -10 log 36 Figure 3.12: The theoretical amplitude response of the cermet/GaAs test circuit for frequencies lying between dc and 500 MHz. 70 O O Phase Response Measured data a 100 200 300 400 Preqxtertcy (MHz) 500 Figure 3.13: The theoretical phase response of the cermet/GaAs test circuit for fre quencies lying between dc and 500 MHz. 37 Chapter 4 Two-dimensional GaAs CMCCD Model 4.1 Geometric Representation The unit cell for the 4-phase GaAs CMCCD model shown in Figure 4.1 consists of a two-dimensional slice through a single pixel. The slice is assumed to lie on a plane coincident with the central axis of the CMCCD so that the potential and the charge density are considered invariant along the axis normal to this plane. Cartesian coordinate axes are defined as indicated, with the origin located at the intersection between the upper boundary segment and the left-hand boundary segment. The unit cell occupies a domain comprised of two subdomains: the active layer subdomain (0 < x < x,nt,0 < y < ymax) and the semi-insulating substrate subdomain (xint 5: x < xmax,0 < y < ymax)- Along the intersection of the two subdomains at x = Xint is an internal boundary segment. The upper boundary segment at x = 0 consists of the union of two boundary segment sets. The first set includes the four transport electrode boundary segments and the second set consists of the five cer met/GaAs junction boundary segments. The lengths used in the computer model are listed in Table III. 4.2 Device Equations The equations used to describe the variation of both the potential and the electron density in nondegenerate n-type GaAs are [33]: V2u(a:, y) = a[n(x, y) - ND] (4.1) J(x,y) — qmUTfJ.(x,y)[Vn(x,y) + n(x,y)E(x,y)] (4.2) and dn(x,y) dt = — V- J(x,y) qrii (4.3) 38 Ph. 1 Ph. Z Ph. 3 Ph. 4 VlL VlR VZL VzR VsL VsR V 4L V4R KOmH t^^d x^^<x K^y^x (0,0) (xint,0) Active layer i>( XvVj) ( o,ymax) (XinvVmiuc) Semi—insulating substrate I (Xma*>°) (mtix''y max) Figure 4.1: The unit cell for modeling the GaAs CMCCD. Ph. 1 Ph. 2 Ph. 3 Ph. 4 3 a Jm 3XL 3IR 3st 3$R 3AL J*R j uMMMnn IUMMM »MMM MMM^ i ^^^^^^^^^"^^^^^^^^^"^^^^^^^^^^^^^^^^^^^^ max ^ 3 max Figure 4.2: The main finite difference for the GaAs CMCCD model. 39 Parameter Value xint 0.25 nm xmax xint 100 fxm Umax 23.8 /mi VmR — VmL 3.0 nm f°r m = 1,..., 4 VlL 1.4 (JLVO. Vmax V4R 1.4 jim. y(m+l)L — VmR 3.0 fj,m for m = 1,2,3 Table III: The lengths used in the two-dimensional computer model. where n{ is the intrinsic carrier density of GaAs, No — No/rii is the normalized donor density, n(x, y) = n(x, y)/rti is the normalized electron density, u(x, y) = ip(x, y)/Ur is the normalized potential, E(x, y) = — Wu(x, y) is the normalized electric field, J(x, y) is the electron current density and a = qni/eUx is a constant. The minority carriers and the electron generation/recombination processes within the active layer are neglected in the model. 4.3 Finite Difference Grid and the Computational Kernel The model equations 4.1,.. .,4.3 are discretized on a finite difference grid superimposed onto the unit cell. The potential is computed at each main grid point lying within the unit cell, while the electron density is computed at each main grid point lying within the active layer subdomain. An auxiliary grid is interleaved with the main grid lying within the active layer subdomain, on which, the intermediate calculation of the electron current density is made. The auxiliary grid points are located at the midpoints of the main grid intervals. The main grid layout within the unit cell is shown in Figure 4.2. The main grid is composed of 21 by 120 grid points with 1 < i < imax = 21 and 1 ^ j 5: jmax = 120. The grid spacing along the z'-axis is uniform within the active layer interval 1 < i < iint = 11 and is nonuniform within the semi-insulating substrate 40 interval i{nt < i < imax. A uniform grid spacing is maintained along the j-axis of the unit cell. The auxiliary grid within the active layer subdomain is shifted from the main grid as described above with (iaux,jaux) = (i + \,j + |). The grid spacings 6x,- = xt+1 — x, and Sy = yJ+1 — yj within the unit cell are determined from the geometry of the unit cell and the number of grid points lying within the region of interest. The constant grid spacing along the z-axis within the active layer subdomain is Sxi = 8xa = -——— = 0.025 microns for 1 < i < i,-nt — 1 . (4.4) Within the semi-insulating substrate subdomain the grid spacing along the i-axis is nonuniform and is defined using a finite geometric series 6xi - <faar,_,int for iint < i < imax - 1 (4-5) where r is a constant determined from the summation Imax —1 ^ yimax— iint )fig ^moi -Pint / , 6xj — - . (4.6) 1 — r The value of the constant r is 2.364316 for 6xa = 0.025 microns and xmax — Xint — 100 microns. The uniform grid spacing along the jf-axis within the unit cell is fiy — ymax _ Q_2 microns for 1 < i < jmax — 1 . (4.7) Jmax -1-The potential or the electron density at each grid point (i, j) is evaluated using the discrete nine-point computational kernel shown in Figure 4.3. The potential and the electron density are associated with the five main grid points and the components of the electron current density are coupled with the four auxiliary grid points. 4.4 Finite Difference Equations for u(x,y) The generalized two-variable Taylor series for the dimensionless potential u(x, y) near the point (xi,yj) is u(xi±6x,yj ±8y) = u(x,y)\{xi,y]) + (^±8x^ ± 8y^ u(x,y)\(xi^ 41 o.56y —"-0*- °-5Sy —W °-56y —*"0*~ °-56y — 0.56 xt Figure 4.3: The nine-point computational kernel used in the calculation of the potential or the electron density within the unit cell. The five disks represent the main grid points and the four circles denote the interleaved auxiliary grid points. 1 / d d \2 \ ( d d \m + ^.{±6lai±6yd-y) "(*•*•*> + ••• <4-8> where +Sx = 6x{, —Sx = 8xi_i and m is an integer variable. Applying equation 4.8 to each of the four main grid points surrounding the central point of the computational kernel and neglecting third and higher order terms of the resulting Taylor series yields the following set of four equations: Ui-lJ = u',j d Sx2 ! a2 (4.9) Ui,j-1 = Ui,i d £y2 d2 6ydyUi'j + 2 d*yUi" ' (4.10) ui,j+l = UU c d by1 d2 + 6ydyUi'j+ 2 *yU" ' (4.11) = UiJ f d Sx2 d2 + bxi uitj + Uij Ox 2 d2x (4.12) 42 where the shorthand notation Uij = u(x,y)\(Xi,yj) is used. Adding equation 4.9 to equation 4.12 gives d2 2 1 / Sx{_i + 6xA 1 8xi_i 1 lj I 8xi_i8xi J l'3 8x{ ,+1'J d2x ' 8xi_i + 8xi and similarly, adding equation 4.10 to equation 4.11 yields d2 1 (4.13) d2yUi'j 82y The sum of equation 4.13 and equation 4.14 produces the finite difference equation for the Laplacian of the potential utj - 2uij + ui}j+1) . (4-14) 2 _ 2 _l_u _ I 2 2 1,3 8x^(8x^1 + 8xi) l~1,3 82y l'3~1 ySx^Sxi 82yt u hi + ^+1 + Sxi(Sxt2.1 + Sxi)Ui+1'i • (4-15) Equation 4.15 can be simplified when the point resides within the active layer sub-domain. Recall that the grid spacing along the i-axis within the active layer subdomain is a constant, as defined by equation 4.4. Hence, equation 4.15 reduces to V72 1 1 2(62xa + 82y) 1 1 V U" = PxZU^ + Py-U^ ~ 82xa62y ^ + S^y^1 + Px?*1* ' (4>16) The discretization of the Poisson equation 4.1 within the active layer subdomain is obtained using equation 4.16 2(82xa + 82y) 1 1 „ ¥X-Py—^ + p-yU'^ + PxZU^ (4'17) and within the semi-insulating substrate subdomain using equation 4.15 2 1 0Xi-i(0Xi_i + oxi) 8zy (^8x{-i8xi 82y) 1,3 82y 1,3+1 8xi(8xi-i + 8xi) ^ ^ where it is assumed that no charge is present within this region. 43 4.5 Boundary Conditions for u(x, y) The boundary conditions for the potential tt,-j are an extension of the one-dimensional boundary conditions described in Chapter 2. The normalized reference potential along the lower boundary segment at i = imax is assigned a value of zero Ui , = 0 (4.19) The unit cell is considered to be part of a repetitive structure resulting in a periodic boundary condition for the potential that is described by the following two equations (4.20) and (4.21) The potential along the internal boundary segment at i = iint is continuous and satisfies Gauss's law QintJ d d OX '"',J OX '">'J 0 (4.22) where the interface charge density Qint,j is assumed to be zero. From equations 4.1, 4.9, 4.14 and noting that 8xiint_i — 8xiint = 8xa obtain dxU'int'^ - ND) ~ 7J—"w-W 8xa 2 1 2 82xc 2(82xa + 82y) (4.23) Similarly, equation 4.1 with the right-hand side set to zero, equation 4.12 and equa tion 4.14 yield d OX 8xa 2 82y 2(82xa + 82y) 1 2 8*xa82y Uiint'J + ^yU"n"J+1 + 82xc (4.24) 44 Substituting equation 4.23 and equation 4.24 into equation 4.22 gives a_ / fj \ 1 1 2 \niint,j — ^D) — fi2^TUiint-i<i + 'p^Uiin"j-1 2{82xa + 82y) 1 1 62xa82y Ui~'J + S2yuiin*J+* + S*xaUiint+lJ ' 1 ' The potential along a transport electrode boundary segment along the upper boundary segment at i = 1 is defined as U° = v\ ~ (tBMfi ~ <t>BM,xmal)} • (4.26) The potential along an interelectrode gap boundary segment along the upper boundary segment at i = 1 is approximated as a linear function of the voltages applied to the two adjacent transport electrodes, which is consistent with the cermet/GaAs junction theory presented in Chapter 3. The potential along a gap boundary segment is u gap TT WaJeft + SJgapVgap ~ (4>BC ~ 4>BM,xmax)] (4-27) UT where Vg%\ejt 1S the potential of the transport electrode to the immediate left of the gap, Vgap is the potential difference across the gap relative to this electrode and 0 < 8jgap < 1 is the relative position along the gap. 4.6 Finite Difference Equation for J(x,y) The Scharfetter-Gummel ( SG ) method [34,35] is used for discretizing the electron current density equation 4.2. To illustrate this method, the positive x-component of the current density Ji+i j will be determined. The x-component of the electron current density at a point (x, y) using equa tion 4.2 is Jx(x, y) = qniUTfJ.x(x, y) —n(x, y) + n(x, y)Ex(x, y) ox (4.28) where the superscript x denotes the x-component of the variable. Rearranging equa tion 4.28 results in a first order differential equation for the electron density —n(x,y)-an(x,y)-b-0 (4.29) 45 where a = —Ex(x,y) and b = Jx(xyy)/qniUTlJ'X(x,y). The Scharfetter-Gummel method assumes that the electron current density and the electric field within the semiconductor vary more slowly than the electron density and consequently can be ap proximated as local constants. This approximation enables equation 4.29 to be solved analytically using an integrating factor exp [—a(x — a;,-)] to give n(x,y) = - (exp [a(x - a;,-)] - 1) + n(xi,y)exp [a(x - xt-)] (4.30) a where n(xs-,y) is the initial condition. Assigning n(x,-,y) = ntj, fixing x = x,- + 8xa and setting n(xi + 8xa,y) = ni+1j yields Ji+y = O.bqriiUTfi^ij [EI+LTJ coth(Q.oEi+ijSxa)(ni+1j - n^) + (n,-+1j+n,-J-)Ef+iii] (4.31) where the x-components of the electron current density, the electric field and the elec tron drift mobility are computed at the auxiliary grid point (z + Similar finite difference equations are obtained for the three remaining components of the electron current density surrounding the point + (n^ + n^E^A , (4.32) Jij_i = 0.5gnitfr^j-i[£,j_i^ + (n.-j-x + n.j)^--!] , (4.33) Ji)j+i = O.bqniUT^xiEi^cothiQ.bEi^SyXni^ - n^) + (nid+1+nit,)EitJ+,} . (4.34) 4.7 Discretization of the Continuity Equation The electron continuity equation 4.3 is descretized using the Crank-Nicolson equa tion [36] 8t 2 46 —n(xi,yj,tk+1) + —n{xi,yj,tk) = (V ' Ji*M1 + V ' Ji'3'k) (4'35) where 8t is the time increment and the subscript A; is the discrete time-step. The spatial derivatives on the right-hand side of equation 4.35 are discretized using central differences of the form V.J,-i= J,'+*'c~ Jt-U + J^h-J^-h {AM) 8xa by Substituting equations 4.31,.. .,4.34 into equation 4.36 yields ^V-J-' = [ ^ )n^ + { si—)""-* 6xa ) — V- • 1 + 2 h - n',j 8y + l"-^—2-)n^ + { jxZ (4'37) where v = /J,U~TE is the nonlinear electron drift velocity of GaAs and v = v coth(Q.5E8xa). A finite difference equation for the electron density at the point for the k + 1st time-step is obtained upon substituting equation 4.37 into equation 4.35 to give 0 = ^—» jnt_hhk+1+{^ --jn,^ + —8y Tt)n^ + TY J + [ ^ J ni+1JMi + V • JiJifc + jnijik . (4.38) The electron drift velocity of GaAs is a nonlinear function of the electric field strength. To incorporate this into the model, the empirical relationship between the 47 Velocity vs Field, 25 i 1 1 O 5 IO 15 20 Electric Field (x10sV/cm) Figure 4.4: The nonlinear electron velocity-field characteristic of GaAs obtained from the empirical equation 4.39, developed by Chang and Fetterman [37]. electron velocity and the electric field strength developed by Chang and Fetterman is used [37] /J.0UTE v = (4.39) y/l + (\UTE\ - E0yEc2u(\UTE\ - EQ) where U(\U~TE\ —E0) is a unit step function equal to zero for |£/;r-E7| < Eo- The remaining constants are: /i0 = 7500 cm2/V-sec, E0 = 2800 V/cm and Ec = 1100 V/cm. The nonlinear electron velocity-field characteristic obtained from this equation is shown in Figure 4.4. 4.8 Boundary Conditions for n(x,y) The electron density along the upper boundary segment at i = 1 is assumed to be equal to the equilibrium electron density at the surface neglecting Schottky barrier height lowering. For the metal/GaAs junction the electron density is 48 n° = -n7eXPl"-^"j (4'40) and for the cermet/GaAs junction the electron density is Nc ( <t>Bc\ ,AAU naap = —exp^-—j (4.41) where Nc is the effective density of states within the conduction band of GaAs. The periodic boundary condition for the electron density is described by the following two equations «i,o = niJmax (4.42) and ra.jm«+i = (4.43) for 1 < i < i{nt. The electron density along the internal boundary segment at i = iint is assumed to be equal to the equilibrium electron density along this boundary = exP ,j - °^moJ (4.44) where Suimax is the normalized potential difference between the Fermi level and the intrinsic energy level along the bottom of the substrate at i = imax. 4.9 Numerical Solution of the Difference Equations Newton iteration with successive relaxation [20,38,39,40] is used for solving the CMCCD model equations summarized in Table IV. The finite difference equations summarized in this table are expressed as the sum of two functions fi+i = 0(C-i,j,fc+n Cij-i,fc+i> (i,j,k+i->Ci,j+i,k+i-> Ci+i,j,fc+i) + = 0 (4.45) where I = 0,1,2,3,... is the iteration counter, ( represents either the potential u or the electron density h and the function h is a constant during the k + 1st time-step. The functions g and h are g = A(<_hhk+1 + £Cl_i,*+i + CO+i + D$j+i,k+i + ECUJMI (4-46) 49 Potential Electron Density Region of Application 4.17 4.38 Active layer subdomain 4.18 — Semi-insulating substrate subdomain 4.19 — Lower boundary segment 4.20 4.42 Left-hand boundary segment 4.21 4.43 Right-hand boundary segment 4.25 4.44 Internal boundary segment 4.26 4.40 Electrode boundary segments 4.27 4.41 Gap boundary segments Table IV: A summary of the equations used in the CMCCD model. and h = Fnitj,k + G (4.47) where A,...,G are constants obtained from the finite difference equations. The func tion flk+1 defined by equation 4.45 is a function of either the potential ulk+1 or the electron density nlk+1 implying that the finite difference equations are decoupled. This enables the potential and the electron density distributions to be computed indepen dently at each discrete time-step. The solution for the potential distribution within the unit cell is iterated first, followed by the iterated solution for the electron density distribution within the active layer subdomain. The potential distribution at the k + 1st time-step within the unit cell is iterated first using the electron density distribution computed at the kth time-step, as the elec tron density distribution at the k-\-\st time-step is unavailable. The rate of convergence of the iterates is accelerated if the electron density distribution at the kth time-step is replaced by an estimated distribution for the k+lat time-step. This estimate is obtained using the Boltzmann equation and is ni,j,k+i ~ eu'i^k+1~Vi-i-k = nj)jifce"u*'J'>feeu''.>.*+i (4.48) where Vijtk — <j>n(xi,yj,tk)/UT is the normalized quasi-Fermi potential for the electrons 50 within the active layer subdomain. Substituting equation 4.48 into equation 4.47 yields the revised equation for the function h h = Fni<jtk exp[{(uliJM1 - u.-j,*)] + G (4.49) where £ = Oif£ = nor£ = lif£ = u. A single Newton iteration step consists of adding a correction factor S(k+l = Cfc+i — Cfc+i to each of the unknown variables in equation 4.45 using the following relation described in Appendix C The following expansion is obtained for equation 4.50 n _ fi . xfi d/fe+i , cri dfl+i , cri dfL+i i *W dfk+l , dfk+1 (A KI ^ Substituting equation 4.45 into equation 4.51 and recalling the definitions for the func tions g and h given by equations 4.46 and 4.49 yields the following equation for a single Newton iteration of the variable £ 0 = AC£iJifc+1 + BCijIi,*+i + (f + Fnililfc£ exp J>fl - u^)]) £Ji+i + ^cgi+i + £c£iJ>f i + ^.-^(i - eC-lfc+i)-«p - «.-.;.*)] + G . (4.52) A single Newton iteration step through the matrix of unknowns proceeds in the usual reading order. The rate of convergence of the sequence of iterates is accelerated using successive relaxation. The ordinary iterated solution for C'jjt+i i-s obtained from equation 4.52 C'S+i = - (C + F*ij*t ^P [t(u'itjM1 - Uij,k)]) _1 {ACl+lJMl + Sd,fc+1 + G) (4.53) 51 where the most recently iterated values for the variables are used. The accelerated The ordinary iterated solution is obtained from equation 4.54 if wr = 1. 4.10 Computer Simulations A flow diagram for a two-dimensional computer simulation is illustrated in Figure 4.5. A simulation begins from an initial guess for the potential and the electron density distributions within the unit cell for the initial bias conditions at k — 0. The bias voltages are adjusted, the time-step counter k is incremented by 1 and the simulation proceeds. The potential u at each grid point within the unit cell is iterated until the maximum absolute residual for the potential within the active layer subdomain is less than 0.0005. The electron density at each grid point within the active layer subdomain is subsequently iterated until the maximum relative error for the electron density is less than 0.001. The simulation continues until a stop time kmax is reached. This simulation procedure was used to produce the two-dimensional potential and charge density distributions for investigating the maximum frequency of operation and the charge transfer performance of a 4-phase GaAs CMCCD. The theoretical maximum frequency of operation of a GaAs CMCCD was deter mined using the single electron transit time model developed by Deyhimy et al [7] and Prokop'ev [41]. The transit time r required for an electron to travel within the fully depleted active layer between the centers of two adjacent transport electrodes is given by the line integral solution rCS k+1 using successive relaxation is (4.54) (4.55) 52 Initialize u^Qi nw and V7y() k=k+1 Adjust Biases I Compute Uyjg+f I Compute niJk+1 I Save uidk+1, nyfc+/ and WUfc+/ Z3Z k>k max \ T Stop Figure 4.5: The flow diagram for the two-dimensional computer simulations. 53 where Cm is the curve coinciding with the maximum potential contour between the elec trode centers, ux(xm(y), y) and uy(xm(y), y) are the x-component and the y-component of the electron velocity vector along this curve, df = xdx + ydy is the differential contour vector and xm(y) is the depth of the maximum potential as a function of the position y between the electrode centers. Equation 2.10 is used to determine an ap proximate value for the depth of the maximum potential. If wn = x,nt = 0.25 microns, ND = 4.5 • 1016 cm-3, xmax ^> x,-n< and |^0| < 10 volts then the second and third terms on the right-hand side of equation 2.10 are negligible which gives xm{y) &wn = xint (4.56) for the depth of the maximum potential between the electrode centers. Substituting equation 4.56 into equation 4.55 yields T !=S I"' -A—, (4-57) Jo vy{xinUy) where Lp is the distance between the two adjacent transport electrode centers. The electron transit time is computed with the electron velocity vy(xint,y) described by equation 4.39 with the y-component of the normalized electric field Ey(xini,y) deter mined from a static two-dimensional potential distribution. The theoretical maximum frequency of operation fmax of a 4-phase GaAs CMCCD is /m«« = ^- • (4.58) 4r The maximum frequency of operation of a 4-phase GaAs CMCCD as a function of the clock voltage amplitude and.the interelectrode gap length for a constant transport electrode pitch Lp is illustrated in Figure 4.6. As indicated in this figure, the maximum frequency of operation of the CMCCD increases with the clock voltage amplitude and with the interelectrode gap length. This relationship is intuitively correct as the electron 54 •Mobx-imiMrrt Opera-tiriff Frequency 12 3 4 5 Clock Voltage Am.jplitixdie (-volts) Figure 4.6: The maximum frequency of operation of a GaAs CMCCD as a function of the clock voltage amplitude and the transport electrode length. transit time is dominated by the time required for the electron to travel through the low-field region underneath the transport electrode. The electron transit time underneath the transport electrode is reduced by increasing the fringing field penetration from the adjacent transport electrode. This is accomplished either by increasing the clock voltage amplitude or by reducing the transport electrode length. It would appear from the above description, that the transport electrodes of a GaAs CMCCD should have a minimum length in order to achieve the maximum operating bandwidth possible for the lowest clock power requirements. The charge transfer performance of a GaAs CMCCD was investigated in a manner similar to that used by Sodini et al [42]. A simulated single electrode transfer of a half full well charge packet ( Qs — 0.5 • IO-10 coul/cm ) was performed and is illustrated in Figure 4.7. The charge packet initially resides under the phase one and phase two transport electrodes and is transferred to the region under the phase two and phase 55 <=0 pS Mm t=SS pS t=ee ps Figure 4.7: The simulated single electrode transfer of a charge packet. The transport electrode length is 3.0 microns. 56 Charge Transfer Efficiency 0.4 O 20 40 60 Time (-picosecond,s) 80 too Figure 4.8: The theoretical charge transfer efficiency as a function of time for the GaAs CMCCD obtained from the simulated single electrode transfer of a charge packet. three transport electrodes. The quadrature clock voltage function consisted of a 2 volt amplitude trapezoidal pulse with 100 picosecond edge transitions. A time increment of 8t = 0.1 picoseconds was used in the simulation. The theoretical charge transfer efficiency as a function of time for the GaAs CMCCD was obtained from the simulation results. The charge transfer efficiency i]{t) is defined as the ratio of the charge transferred to the transfer well to the charge initially residing in the storage well. For the simulation of the 4-phase GaAs CMCCD Qph.2+Ph.3(t) (4.59) Qph.i+Ph.2(t = o) Figure 4.8 illustrates the theoretical charge transfer efficiency of the GaAs CMCCD obtained from the computer simulation described above. This figure indicates that the packet of charge is essentially fully transferred at the completion of the clock transition period ttr = 100 picoseconds. This result implies that the simulated transfer of the 57 charge packet was not transit time limited and that the 4-phase GaAs CMCCD should exhibit good charge transfer at clock frequencies approaching fc = l/4i<r = 2.5 GHz. Sovero et al [9] measured a charge transfer efficiency of 0.99 per transfer for a GaAs CMCCD operating at a clock frequency of 2.5 GHz, supporting the above theoretical result. 58 Chapter 5 Device Fabrication Figure 5.1 shows a microphotograph of a 64-pixel, 4-phase GaAs CMCCD. The input section is located on the left-hand end of the device and is shown in detail in Figure 5.2. The control gates Gi and G2 are nominally 5 microns in length and are separated by 2 micron gaps from the input ohmic contact, from the first transport electrode and from each other, respectively. There are 256 transport electrodes comprising the sixty-four pixels within the transport section of the CMCCD. The transport electrodes are 3 microns in length and are separated by 3 micron gaps. The phase one transport electrodes and the phase three transport electrodes are interconnected along the lower side of the device while the phase two transport electrodes and the phase four transport electrodes are interconnected along the upper side of the device. The entire transport section is encapsulated with a cermet film. The output section is located at the right-hand end of the device and is shown in detail in Figure 5.3. The output ohmic contact, the control gate G3 and the output source follower amplifier comprise this section. The control gate G3 is 5 microns in length and is separated by 2 micron gaps from the final transport electrode and from the output ohmic contact. The CMCCD channel is nominally 100 microns wide. The GaAs wafer that was used for producing the CMCCD was an undoped (100) oriented semi-insulating substrate onto which an n-type epitaxial layer was grown. The substrate was grown using the liquid encapsulated Czochralski technique [43] and had a sheet resistivity exceeding 107 ohm-cm. Metal-organic chemical vapour phase deposition [44] was used to grow the n-type active layer onto the substrate. This layer consisted of a nominal 1-2 micron thick n~-buffer layer onto which the 0.25 micron n-type active layer was grown. The active layer was uniformly doped, with No = 59 Figure 5.1: A microphotograph of the fabricated GaAs CMCCD. The bonding pads are 100 micron squares. 4.5 • 1016 cm"3. The fabrication of the GaAs CMCCD required six mask levels that employed a 2.0 micron minimum design rule. The mask levels provided the patterns for fabricating the ohmic contacts, the isolated active regions, the metal/GaAs Schottky barriers, the cermet/GaAs Schottky barriers, the interconnect vias and the second level metalliza tion. Conventional contact lithography was used to produce the device. A detailed list of the fabrication steps is described in Appendix D. The ohmic contacts [45] of the CMCCD and the MESFETs were fabricated ini tially. A 1.2 micron thick positive photoresist film was patterned onto the wafer surface. A nominal 1200 A Au-Ge ( 12 wt. % Ge ), 200 A Ni and 1400 A Au ohmic contact metallization was sequentially deposited onto the wafer surface using thermal evapora tion and electron-beam evaporation in a high vacuum chamber. The unwanted metal was removed from the wafer surface using the photoresist liftoff method [46]. The 60 Figure 5.2: A microphotograph of the input section of the GaAs CMCCD. 61 ohmic contacts were completed by alloying the ohmic contact metallization with the underlying GaAs. To achieve a planar device structure, multiple energy proton isolation implants were used to isolate the active device regions. Early investigators of the GaAs CGCCD used a mesa etch to achieve the required isolation [47,48]. Although this technique is simple to implement and provides good isolation, it has the drawback that the subse quent lithography is hampered by the different elevations between the mesa plateaus and the surrounding valleys. A planar GaAs CGCCD was realized using Schottky barrier channel stops [49] to isolate the active device regions. A channel stop must completely surround the active device region to be effective, which is a disadvantage as it becomes difficult to run first level metallizations directly between isolated re gions. Proton bombardment was used to isolate the active device regions of a GaAs CGCCD [50]. This method has the desirable feature that it does not alter the GaAs surface profile and thus does not have the associated problems of the above isolation techniques. The active regions for the CMCCD and the MESFETs were electrically isolated using a sequence of three proton implants at different beam energies. A nominal 7 mi cron thick patterned photoresist film was used as a barrier to protect the active device regions during the implants. The exposed GaAs was sequentially bombarded using protons at ion energies of 180 keV, 90 keV and 30 keV. Fluences of 1013 cm-2 and 5 • 1013 cm-2 were used for the first two implants and the final implant, respectively. No post-implantation anneal was performed. Good electrical isolation was achieved, with the measured resistivity of the deactivated GaAs exceeding 105 ohm-cm. The metal/GaAs Schottky barriers comprising the transport electrodes and the MESFET gates were patterned using the photoresist liftoff method. A nominal 500 A Ti, 100 A Pt and 2150 A Au multilayer film was sequentially electron beam evaporated onto the wafer surface through a 1.2 micron thick photoresist mask. The 62 photoresist and the unwanted metallization were removed in an ultrasonic N-methyl-2-pyrrolidone solvent bath. The cermet/GaAs Schottky barriers within the interelectrode gaps of the CMCCD were patterned using the photoresist liftoff process. A nominal 5000 A thick film of Cr-SiO ( nominal 45 wt. % Cr ) was rf diode sputtered from a 6 inch composite target onto the wafer surface through a 2.1 micron thick photoresist mask. The target was separated from the substrate table by 1.5 inches and was sputtered at 13.56 MHz in a 10 mTorr argon environment [51]. The input power to the target was approximately 250 watts rms, achieving a dc target bias of -800 volts relative to the substrate table. It was observed that a target bias of less than -1000 volts was detrimental to the photoresist film. An extended 24 hour chamber preconditioning period was required prior to the 30 minute deposition to achieve a uniform Cr:SiO film. The photoresist and the unwanted cermet film were removed in an ultrasonic N-methyl-2-pyrrolidone solvent bath subsequent to the deposition. Figure 5.4 shows a transmission electron microphotograph of the structure of the Cr:SiO film. The dark areas correspond to the regions of highest atomic density and are believed to be the result of chromium compounds [52]. Energy dispersive x-ray analysis ( EDX ) was used to ascertain the chemical composition of the film and it was found to be 41.7 weight percent chromium, which is in agreement with the manufacturer's target specification of 45 weight percent chromium. A 1.8 micron thick interlayer dielectric film of polyimide was used to protect the active GaAs surface and to separate the two metallization levels from each other. A layer of diluted Du Pont PYRALIN PI-2550 polyimide was applied to the GaAs wafer surface using a spin-on technique [53]. The polyimide was diluted to a lower viscosity using Du Pont T-9039 thinner at a 1:1 dilution ratio. The polyimide was imidized in a controlled forced air convection oven using a low temperature 250 °C heating cycle for nearly 3 hours [54]. This heating cycle was below the eutectic temperature of the ohmic 63 Figure 5.4: A transmission electron microphotograph of the Cr:SiO ( 45 wt. % Cr ) film at 150,000 times magnification. The number '1' in the label corresponds to a height of 2.0 mm at this magnification. Figure 5.5: A microphotograph of the plasma etch profile of a 5 micron square via etched through a 1.8 micron thick polyimide film. 64 contacts [45] and the annealing temperature of the proton isolation implants [55,56] and consequently did not alter the electrical characteristics of these fabricated structures. The interconnect vias between the first level metallization and the second level metallization were chemically etched through the imidized polyimide film using a three step plasma etch process employing plasma enhanced chemical vapour etching [57,58]. A nominal 600 A thick titanium film was deposited onto the imidized polyimide surface using electron beam evaporation. The surface of the titanium film was subsequently covered with a 1.2 micron thick patterned photoresist mask. The exposed regions of the titanium film were etched through the photoresist mask using a CF4/02 plasma, transferring the photoresist pattern to the titanium film. The exposed regions of the polyimide film were etched through the titanium mask using an O2 plasma, transferring the original photoresist pattern to the polyimide film. The photoresist film was also removed from the titanium surface during this etch. The titanium mask was removed in a final CF4/O2 plasma etch. Figure 5.5 shows the resultant vertical etch profile of a 5 micron square interconnect via etched through the polyimide film using the above plasma etch process. The second level metallization was patterned using the photoresist liftoff method. A nominal 500 A Ti and 4000 A Au multilayer metallization was sequentially electron beam evaporated onto the wafer surface through a 2.1 micron thick photoresist mask and the subsequent liftoff was performed in an ultrasonic acetone bath, completing the fabrication of the GaAs CMCCD. The intermediate titanium layer provided the required adhesion between the polyimide film and the second level metallization gold layer. 65 Chapter 6 Testing and Evaluation A series of dc threshold voltage measurements were performed on the GaAs CMCCD prior to packaging the device to determine if the control gates and the transport elec trode arrays were functional. A Tektronix TEK-576 curve tracer attached to an Alessi probe station was used to make these measurements. The input ohmic contact and the output ohmic contact of the CMCCD were used as the drain and the source, respec tively. A 5 volt drain to source bias was applied to the device. Each of the three control gates and each of the four transport electrode arrays were biased, in turn, negatively with respect to the source node until no further change was observed in the drain to source current. The observed gate to source voltage corresponding to this condition was recorded as the threshold voltage. Table V contains a list of the measured threshold voltages of the GaAs CMCCD. The CMCCD was mounted in a 32 pin ceramic flat package. A discrete DEXCEL-2502 GaAs MESFET die was also mounted in the package for use as a reset switch at the output ohmic contact of the CMCCD. The CMCCD, the on-chip GaAs MESFET source follower amplifier and the discrete GaAs MESFET die were wire-bonded in the package using the configuration shown in Figure 6.1. This packaging configuration resulted in a minimum parasitic capacitance Co/p at the output ohmic contact of the CMCCD. This is desirable for obtaining maximum output signal amplitudes from the CMCCD, as the signal charge arriving at the output ohmic contact is converted to a voltage with an amplitude inversely proportional to Co/p-The on-chip GaAs MESFET source follower amplifier buffered the output ohmic contact of the CMCCD from the external output electronics. It consisted of two deple tion mode 2 micron by 30 micron MESFETs configured in a totem pole arrangement 66 Figure 6.1: The wire-bonding configuration used to interconnect the CMCCD, the on-chip GaAs MESFET source follower amplifier and the discrete GaAs MESFET die. Figure 6.2: The insertion loss of the on-chip GaAs MESFET source follower amplifier measured from 300 kHz to 200 MHz. 67 Gate Threshold Voltage (Volts) Gi -2.4 G2 -2.45 G3 -2.4 Ph. 1 -1.8 Ph. 2 -1.8 Ph. 3 -1.85 Ph. 4 -1.7 Table V: The measured threshold voltages of the GaAs CMCCD. which provided a low capacitance, high impedance load to the output ohmic contact of the CMCCD. A threshold voltage of approximately -2.2 volts and a saturation current of approximately 5.0 milliamperes was measured for these transistors using a Tektronix TEK-579 curve tracer. The insertion loss of the source follower amplifier terminated in 50 ohm source and load impedances was measured from 300 kHz to 200 MHz using a Hewlett-Packard HP-8753A network analyzer and an HP-85046A s-parameter test set. The measured insertion loss is shown in Figure 6.2. The GaAs CMCCD was operated in the VHF band at 100 MHz and was evaluated for operation at this frequency using the impulse response method [59] and the insertion loss method [60]. The CMCCD was operated using the signal levels listed in Table VI, which were provided by a test circuit comprised of emitter-coupled logic ICs and discrete GaAs MESFETs. A schematic diagram of the CMCCD test circuit is provided in Appendix E. Charge injection into the CMCCD was obtained using the diode cutoff method described in Chapter 2. The test circuit had a bandwidth of approximately 150 MHz and was the limiting factor for testing the CMCCD at higher clock frequencies. A Tektronix PG-502 250 MHz pulse generator and a TEK-7904 oscilloscope frame mounted with a 7A24 dual trace amplifier and a 7B92A dual timebase unit were used for the impulse response measurement and a Hewlett-Packard HP-8753A network analyzer with an HP-85046A s-parameter test set was used for the insertion loss measurement. 68 Figure 6.3: The qualitative demonstration of the performance of the GaAs CMCCD for 100 MHz operation. Figure 6.4: The impulse response of the GaAs CMCCD for 100 MHz operation. 69 Figure 6.5: The insertion loss of the GaAs CMCCD for 100 MHz operation. Frequency Response 10\ , ,— , 3 O -nnnunnunt ^-10 &-20 N -30 s §-40 -50 rj = 0.998 Measured data. a Theory O 10 20 30 40 Input Signal Frequency (MHz) 50 Figure 6.6: The theoretical insertion loss of the GaAs CMCCD for 100 MHz operation. 70 Gate Signal level(s) ( volts ) I/P 0 to +0.5 Gx -0.8 to -5.8 G2 +0.3 to -4.7 Ph. 1 0 to -5.0 Ph. 2 0 to -5.0 Ph. 3 0 to -5.0 Ph. 4 0 to -5.0 R/G 0 to -5.0 G3 -2.7 to -2.7 B/D +5.0 to +5.0 B/S -5.2 to -5.2 R/S 0 to 0 Table VI: The signal levels applied to the GaAs CMCCD for operation at 100 MHz. A qualitative demonstration of the performance of the GaAs CMCCD for 100 MHz operation is shown in Figure 6.3. The oscillograph contained in this figure displays the CMCCD input signal along the upper signal trace and the processed CMCCD output signal along the lower signal trace. The input signal was obtained by passing a trape zoidal pulse through a passive lowpass filter having a cutoff frequency of 20.5 MHz. The damped oscillations were a result of the filter response to the 1 nanosecond transitions of the input pulse. The processed CMCCD output signal was obtained by filtering the buffered CMCCD output signal using a lowpass filter similar to the one used at the input. Figure 6.3 demonstrates the good signal fidelity of the CMCCD for 100 MHz operation. Figure 6.4 shows an oscillograph of the impulse response of the CMCCD for 100 MHz operation. The CMCCD input signal is along the upper signal trace and the buffered CMCCD output signal is along the lower signal trace. The input signal con sisted of a 5 nanosecond wide, 2.4-volt amplitude, 1 nanosecond transition trapezoidal impulse. The buffered CMCCD output waveform contains the modulation envelope of the impulse and the passive feedthrough of the quadrature clocks. The modulation 71 Method Charge Transfer Efficiency Impulse Response 1.00 Insertion Loss 0.998 Table VII: The charge transfer efficiencies of the GaAs CMCCD for 100 MHz operation. envelope of the impulse consists of a single pulse transient delayed by 640 nanoseconds with respect to the input signal. The charge transfer efficiency of the CMCCD was determined from the CMCCD impulse response using the calculation [59] Npeak = NT(l-ri) (6.1) where NT is the number of single electrode transfers through the CMCCD and Npeak is the number of pixel transfers between the peak of the observed CMCCD impulse response and the peak of the ideal CMCCD impulse response. The computed charge transfer efficiency is listed in Table VII. The insertion loss of the GaAs CMCCD for 100 MHz operation is shown in Fig ure 6.5. A -10 dBm swept frequency sinusoidal signal spanning the range from 300 kHz to the Nyquist frequency of 50 MHz was applied to the input ohmic contact of the CMCCD and the insertion loss of the device was measured. Figure 6.5 indicates that the CMCCD has a nearly uniform insertion loss over the entire 50 MHz input signal bandwidth, which is indicative of good performance. The charge transfer efficiency of the CMCCD was determined by fitting the equation [60] ADB = 20 log A0exp -NT(l - ?y) cos (f (6.2) to the measured data. Here AJ,B is the insertion loss, A0 is a constant amplitude term, u> is the input signal frequency and fc is the CMCCD clock frequency. The calculated charge transfer efficiency using the insertion loss method is listed in Table VII and the curve fit to the measured data is shown in Figure 6.6. 72 Chapter 7 Comments 7.1 Summary Contributions were made towards developing the GaAs CMCCD for high frequency sig nal processing applications. The design, implementation and evaluation of the CMCCD were considered and are summarized in this section. The design equations for determining the active layer requirements of the GaAs CMCCD were described in Chapter 2. The design protocol that was outlined assumes that the active layer was uniformly doped and was constrained to have a pinch-off voltage that was typical of an n-type depletion mode MESFET. It was demonstrated that the full well charge confinement and the full well capacity of the CMCCD were simultaneously maximized if the device was fabricated on a thin, highly doped active layer. This result suggested that the optimum CMCCD active layer was similar to the active layer of a low to medium power n-type depletion mode GaAs MESFET, which was advantageous when the two devices were integrated monolithically. It was indicated in Chapter 1 that the GaAs CGCCD could not be monolithically integrated with GaAs MESFETs in a simple manner as the CGCCD was typically fabricated on thick, lightly doped active layers which were not directly compatible with MESFETs. It was demonstrated in Chapter 3 that a cermet/GaAs Schottky barrier diode exhibits rectification properties similar to that of a metal/GaAs Schottky barrier diode with a large series resistance. The Schottky barrier height and the ideality factor of the cermet/GaAs junction were determined using a distributed resistive gate Schottky barrier diode model of the fabricated planar cermet/GaAs Schottky barrier diode. A Schottky barrier height of 0.64 eV and an ideality factor of 1.17 were determined for the cermet/GaAs junction. 73 A transmission line model described in Chapter 3 for the cermet/GaAs junction within an interelectrode gap of the CMCCD was used to demonstrate that the surface potential distribution along the gap was monotonic for all frequencies. A differential length of the transmission line model consisted of a differential series impedance and a differential shunt admittance. The series impedance modeled the cermet film and was comprised of a parallel resistance and capacitance. The shunt admittance modeled the depletion layer capacitance of the underlying GaAs. It was determined from an analysis of the transmission line model that the high frequency surface potential variation along a gap of the CMCCD was independent of the distributed cermet film resistance. This was an important result as it indicated that the operation of the CMCCD was not critically dependent upon the distributed cermet film resistance, provided that it was large enough to satisfy the power constraints of the quadrature clocks. It was further demonstrated in Chapter 3 using the transmission line model that the distributed cermet film capacitance was preferably greater than the distributed depletion layer capacitance in order to maintain a nearly linear surface potential variation along the gap of a CMCCD for all frequencies. This was desirable for achieving an optimal uniform tangential electric field distribution within the CMCCD active layer to assist charge transfer. A two-dimensional computer model for investigating the operation of the GaAs CMCCD was described in Chapter 4. A unit cell representing a single pixel of a 4-phase GaAs CMCCD consisted of a domain comprised of the active layer subdomain and the semi-insulating substrate subdomain. The transport electrodes were defined as equipotential boundaries and the interelectrode gaps were defined as linear potential boundaries. A finite difference grid was superimposed onto the unit cell, on which the semiconductor equations were solved. A Newton iteration scheme with successive relaxation was used to solve the finite difference equations for the potential and the electron density. Computer simulations for the static potential distributions within the 74 CMCCD were used to determine the theoretical maximum frequency of operation of the device as a function of the interelectrode gap length and the peak clock voltage amplitude for a constant transport electrode pitch. It was demonstrated that the CMCCD transport electrodes should have a minimum length to achieve the maximum frequency of operation for the lowest possible power requirements. A simulation of the dynamic single electrode transfer of a half full well of charge in 100 picoseconds was demonstrated. This simulation indicated that the charge packet was essentially fully transferred by the end of the transfer interval, suggesting that the CMCCD will demonstrate good performance at frequencies approaching 2.5 GHz. A six mask level fabrication process for producing the GaAs CMCCD was de scribed in Chapter 5. Conventional contact lithography was used to fabricate the device. The six mask levels provided the patterns for the ohmic contacts, the proton isolation implants, the metal/GaAs Schottky barriers, the cermet/GaAs Schottky barri ers, the interconnect vias and the second level metallization. The Au-Ge/Ni/Au ohmic contacts, the Ti/Pt/Au metal/GaAs Schottky barriers and the Cr:SiO cermet/GaAs Schottky barriers were patterned directly on the n-type active layer. Three proton im plants at different beam energies were used to isolate the CMCCD active region and the MESFET source follower amplifier active region, maintaining a planar device structure. A polyimide interlayer dielectric film was used to separate the first level metallization from the second level metallization. Connections between the two metallization levels were made through interconnect vias that were plasma etched through the polyimide film. The operation of the GaAs CMCCD was described in Chapter 6. The dc threshold voltage measurements were used to select the CMCCD from the fabricated devices. The CMCCD, the on-chip MESFET source follower amplifier and a discrete GaAs MESFET die were wire-bonded in a 32 pin ceramic package. The MESFET was used as a reset switch on the output ohmic contact of the CMCCD. A test circuit was used to 75 provide the signals to the packaged components. The diode cutoff method described in Chapter 2 was used to inject charge into the CMCCD. The CMCCD was operated using a clock frequency of 100 MHz and was evaluated at this operating frequency using the impulse response method and the insertion loss method. The CMCCD demonstrated good performance at 100 MHz clock frequency with charge transfer efficiencies of 1.00 and 0.998 calculated respectively using the above two evaluation techniques. 7.2 Considerations for Future Work This work was focused on the design, implementation and evaluation of a 64-pixel, 4-phase GaAs CMCCD. The issues which could be addressed in further developing this device are described in this section. The 64-pixel, 4-phase GaAs CMCCD that was developed in this work was not fully optimized. The fabricated CMCCD had an active layer with a uniform donor den sity of 4.5 • 1016 cm-3 to a depth of 0.25 microns. These active layer parameters were satisfactory for demonstrating the operation of the CMCCD with a GaAs MESFET, but would not necessarily yield the best possible device performance. The 3 micron CMCCD transport electrode length was chosen for convenience, in order that the fab rication requirements to produce the device would be reduced. A revision to the above CMCCD structure would consist of using a CMCCD active layer with a uniform donor density of approximately 2.0 • 1017 cm-3 to a depth of approximately 0.1 microns which is more consistent with the active layer requirements of a nominal -2.0 volt n-type depletion mode GaAs MESFET. Furthermore, the analysis described in Chapter 2 indicates that the revised active layer parameters are preferred, as the signal charge confinement and the signal charge capacity of the CMCCD would be improved. The revised CMCCD transport electrode length would be 1.0 microns or less in order that the high frequency performance and the associated power requirements of the CMCCD would be improved as described in Chapter 4. 76 The monolithic integration of the peripheral support electronics with the GaAs CMCCD is essential for obtaining maximum performance from the device. In particular the output reset switch and the output signal processing circuitry should be directly integrated with the CMCCD. This level of integration would increase the operating bandwidth, increase the dynamic range and increase the signal to noise ratio of the CMCCD. This would be a consequence of the reduction in the parasitic component values attached to the output node of the CMCCD. A 2-phase GaAs CMCCD structure could also be considered for further investi gation as it would maximize the utilization of the active device area by achieving a greater pixel density and it would significantly reduce the clock driver circuit require ments. Hansell developed a castellated 2-phase GaAs CGCCD that exhibited a charge transfer efficiency of 0.93 [20]. It was determined by Hansell that the reduced charge transfer efficiency of the 2-phase CGCCD was largely due to the presence of energy troughs within the active layer volume bounded on the surface by the interelectrode gaps. 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Elec tron Devices, ED-29(7):1051-1058, Jul. 1982. J.W. Coburn. Plasma-assisted etching. Plasma Chemistry and Plasma Processing, 2(l):l-40, 1982. 81 [58] F.D. Egitto, F. Emmi, R.S. Horwath, and V. Vukanovic. Plasma etching of organic materials. 1. polyimide in 02-CF4. J. Vac. Sci. Technol. B, 3(3):893-904, May 1985. [59] CH. Sequin and M.F. Tompsett. Charge Transfer Devices, pages 73-76. Academic Press, New York, 1975. [60] G.F. Vanstone, J.B.G. Roberts, and A.E. Long. The measurement of the charge residual for CCD transfer using impulse and frequency responses. Solid-State Electronics, 17:889-895, 1974. [61] J.V. Cresswell, I. Carvahlo, M. LeNoble, O. Berolo, and R. Kule. A 500 MHz CCD serial analog memory. IEEE Trans. Nucl. Sci., NS-33(1):90-91, Feb. 1986. [62] D.A. Bryman. TRIUMF, private communication. [63] BNL, Princeton, TRIUMF Collaboration. Current Goals, R&D, Design, and Con struction Status of Detector for AGS Experiment #787—A Study of the Decay K+ TT+VV. Technical Report, TRIUMF, Oct. 1985. [64] J.V. Cresswell, S. Ahmad, E.W. Blackmore, D.A. Bryman, N. Kahn, Y. Kuno, and T. Numao. A cylindrical drift chamber for the measurement of K —> irvv decay. IEEE Trans. Nucl. Sci, 35(l):460-463, Feb. 1988. [65] J.V. Cresswell. TRIUMF, private communication. 82 Appendix A BNL Experiment 787 The development of the GaAs CMCCD was inspired by the need for a wideband data acquisition system for Experiment 787, which is currently being prepared for implemen tation at the Brookhaven National Laboratory [61]. This nuclear physics experiment is being conducted collaboratively with scientists and engineers from Brookhaven, Prince ton University and TRIUMF. The experimental goals of Experiment 787, the relevant technical aspects of the detector apparatus for this experiment and the application of a CMCCD in the data acquisition system for instrumenting the detector are described in this appendix. The development of a comprehensive Standard Model for describing the interac tions that occur amongst the elementary subatomic particles is of current interest to nuclear physicists. The existence of three neutrino generations has been established within the current framework of this model and must be experimentally verified. A test for the number of neutrino generations will be attempted in Experiment 787 by directly observing and measuring the rate of decay of a kaon to a pion and neutrino/anti-neutrino pair. This particular decay sequence is extremely rare and is anticipated to occur once in approximately every ten billion kaon decays [62]. Should the observed decay rate lie in the vicinity of the expected rate, then a positive test for the existence of three neutrino generations will have been made. It has been suggested that new gen erations of neutrinos, or perhaps, new elementary particles may exist if the observed rate of decay of a kaon to a pion and neutrino/anti-neutrino pair is greater than about five times the anticipated rate [63]. A sophisticated rare kaon decay spectrometer is currently being developed for Experiment 787 to provide the required detection capability for observing the decay 83 of a kaon to a pion and neutrino/anti-neutrino pair. A cross-sectional view of this apparatus displaying its relevant features is shown in Figure A.l. The detector is cylindrical in shape with overall dimensions of approximately 6 metres in length by 5 metres in diameter. The target is located along the central axis of the detector core and is surrounded by a cylindrical drift chamber [64] that is enclosed within a scintillation counter range stack. A burst of highly energetic kaons from the BNL accelerator arrives along the central axis of the detector penetrating the target. The majority of incident kaons are stopped within the target and decay into other particles. The newly formed decay particles traverse the detector in a manner that is dependent upon their energy, mo mentum and lifetime. The cylindrical drift chamber is used to monitor the energies and the trajectories of the particles as they are emitted from the target. The pions that result from a decaying kaon pass through the cylindrical drift chamber and are ulti mately stopped within the scintillation counter range stack where they decay into other particles. A primary function of the scintillation counter range stack is to provide the positive identification of the pions that emerge from the drift chamber. This is achieved by tracking the decay of the pion to a muon and the subsequent decay of the muon to an electron using energy versus time measurements. These interactions are detected as electrical signals at the output of the photomultiplier tubes that are attached to the scintillation counter range stack. The ideal output waveform obtained from a range stack photomultiplier tube for the pion to muon to electron decay sequence is shown in Figure A.2. The waveform shown in Figure A.2 is a simplification of the complex series of interactions that occur between the energetic particles and the nuclear instruments. In principle, the observed pulses tend to pile up onto each other due to the previous history within the spectrometer. Consequently, the waveform illustrated in Figure A.2 for the practical case will consist of many superimposed pulses having peak separations that 84 BEAM / VETO PHOTOTUBES RANGE STACK 1 PHOTOTUBES •*-BEAM MWPC SC1NT; i •TARGET TARGET RM.SUPPORT" Figure A.l: A cross-sectional view of the BNL Experiment 787 rare kaon decay spec trometer. 85 Decay Energy us Time 50 40 >»• •<s> CO o 30 20 -^10 O o 10 20 30 40 Time (ns) 50 60 Figure A.2: The ideal output waveform for a pion to muon to electron decay sequence obtained from a photomultiplier tube attached to the end of the scintillation counter range stack. The leading peak corresponds to the energy deposited by a pion to muon decay and the trailing peak corresponds to the energy deposited by the subsequent muon to electron decay. The vertical bars represent discrete pulse amplitudes obtained for a 2 nanosecond sampling rate [62]. Range Stack PMT 500 MHz Timebase Trigger A/D Converter Data Routing Off-line Processing Off-line Processing Off-line Processing Figure A.3: A system block diagram of the GaAs CMCCD based data acquisition system for the analog to digital conversion of a signal from a range stack photomultiplier tube [65]. 86 Figure A.4: The 64-pixel, 4-phase GaAs CMCCD providing frequency compression. The input signal along the upper trace ( 20 ns/cm ) acquired at 483 MHz consists of two superimposed 30 ns pulses. The output signal along the lower trace ( 1 //s/cm ) shows the processed input signal after frequency compression. vary from zero to many tens of nanoseconds. A data acquisition system employing a 64-pixel, 4-phase GaAs CMCCD is currently being developed at TRIUMF for recording these waveforms. A block diagram of the GaAs CMCCD data acquisition system [65] is shown in Figure A.3. In this application the GaAs CMCCD provides frequency compression of a 250 MHz band-limited analog input signal. The input signal applied to the CMCCD is obtained from a photomultiplier tube attached to the scintillation counter range stack. An externally generated acquisition trigger pulse enables the application of a 500 MHz high frequency clock to the CMCCD. The acquisition cycle occurs for 128 nanosec onds filling the CMCCD with sixty-four discrete samples of the input signal. The two nanosecond resolution of the input signal is considered sufficient for discriminating the two energy peaks that are observed during the pion to muon to electron decay se-87 quence [62]. Subsequent to the completion of the data acquisition cycle, a 7.81 MHz low frequency clock pulse burst is applied to the CMCCD compressing the acquired signal by a factor of sixty-four. The compressed signal is transmitted to an analog to digital converter and the binary data resulting from the analog to digital transformation is routed to a data bus for sparse data processing and distribution to off-line computer re sources. Figure A.4 shows an oscillograph illustrating the preliminary results obtained for a 64-pixel, 4-phase GaAs CMCCD operating in the frequency compression mode. 88 Appendix B Polar Transformation of V(y) The complex harmonically varying surface potential is given as %^)=sMl|'Vff"^ • smh[Ls7(u;)] where the factor e3ujt has been suppressed. Let (L9-yh(u) = a(y,L>)+]b(y,u) and Lg^(u) — C(UJ) + jd(u>) with 7(0;) defined as 7(<*>) = WRCMCD exp yjl + (URCMCCM) The functions a(y,u>), b(y,u>), c(ui) and d(to) are WRCMCD J ( 1 - arctan I — —— . .2 XURCM^CM' • a(y,u) c(u) d(u) ^Jl + {WRCMCCM)2 URCMCD , \fl + (URCMCCM)2 WRCMCD , y^l + (URCMCCM)2 URCMCD {Lg - y) cos (If, - y) sin 1 1 / 1 - arctan I — I KUJKCM^CM 1 / 1 - arctan (— —— Lg COS Lg sin arctan . 2 KURCM&CM 1 / 1 - arctan I —— — 2 \URCM&CM \ yjl + (WRCMCCM) Substitute equation B.2 and equation B.3 into equation B.l yields \r( \ sinh(a + j6) v{y,u) = ^-77—;—-Vo sinh(c + jd) gjd ^ c g jd ea [cos(6) + j sin(o)] — e~a [cos(o) — j sin(o)] ec [cos(d) + j sin(cf)] — e_c [cos(d) — j sin(rf)] sinh(a) cos(6) + j cosh(a) sin(6) V0 sinh(c) cos(cf) + j cosh(c) sin(d) Vo 89 Transforming equation B.9 into polar form yields Jsinh2(a) cos2(fe) + cosh2(a) sin2(6)Z arctan f c°t(°JsinS) )/sinh2(c) cos2(rf) + cosh2(c) sin2(rf)Z arctan (^ffiffj) Using the trigonometric identities sinh2(2) = cosh2(» - 1 and (B.H) sin2(^) = l-cos2(z) (B.12) gives V(y,u) = V0H(y,u)ie(y,Lo) (B.13) where H(y,u>) is the normalized magnitude of the surface potential TT(„ .-A ICOsh2 ^ ~ C°s2 ^y' ^ ^1* mU) Hyy>u)- 12r / \i 2Ur \i (B.14J \ cosh [C(UJ)\ — cos^ |a(w)J / and Q(y,u>) is the phase shift of the surface potential 0(y,u>) = arctan (coth[a(y,a;)] tan[6(y,u>)]) — arctan (coth[c(o;)] tan[<i(a;)]) . (B.15) 90 Appendix C Newton's Method Newton's method [39] is a numerical technique for finding the roots of a general function /(C) = 0 ana is described in this appendix. Consider a point that is in the vicinity of a root of the function /(C)- The function /(C) can be expanded in a Taylor series about the point Q to give /(O = /(Ok. + (c - c,)/'(C)k. + • • • + —xc - or/(m)(0k. + • • • . (c.i) m! A root of the equation /(C) = 0 can be obtained approximately by replacing /(C) with the first two terms of the expansion given in equation C.I /(C)lc, + (C-CO/'(C)lc. = o • (C2) Rearranging equation C.2 and performing the function evaluations at Q gives < = G-$§ • (C3) The value of £ computed in this manner is an improved estimate for the original root (i of the function /(C), and can replace Q in equation C.3 to provide an even better estimate for the root. This can be written in the generalized form W+i = W £(£1 (CA) from which the correction factor for the Ith iterate is $C' = C'+1-C' • (C5) From equations C.4 and C.5 one obtains /(C) + *C7'(C) - o (c.6) which forms the basis of the Newton iteration technique for numerically solving the set of finite difference equations listed in Table IV. 91 Appendix D Detailed Device Fabrication Procedure 1. Ohmic contact formation 1.1— 3 min. immersion in an ultrasonic acetone bath. 1.2— 3 min. sequential immersion in each of hot trichloroethylene, hot acetone, and hot 2-propanol baths. 1.3— 1 min. N2 wafer dry. 1.4— Spin-coat the wafer @ 4000 RPM for 30 sec. with AZ 4110 photoresist. 1.5— Softbake the photoresist coated wafer in a forced air oven @ 90 ± 2 °C for 30 min. 1.6— Expose the photoresist coated wafer to 405 nm, 4.5 mWcm-2 ultraviolet light for 14 sec through the 'ohmic contact' mask. 1.7— Spray develop the exposed photoresist using AZ 400K developer diluted to a volume ratio of 1:3 with DI H20. 1.8— Immerse the wafer in a 20 ml:200 ml, NH4OH:DI H20 oxide etch bath for 30 sec. 1.9— 1 min. DI H20 rinse and subsequent 1 min. N2 wafer dry. 1.10— Sequentially evaporate the following metal films under high vacuum 1.10.1— 1150 A Au-Ge ( 12 wt. % Ge ), 1.10.2— 200 A Ni, 1.10.3— 1400 A Au. 1.11— 3 min. immersion in an ultrasonic acetone bath to lift-off the unwanted metal. 1.12— 3 min. immersion in an ultrasonic acetone bath. 1.13— 3 min. sequential immersion in each of hot trichloroethylene, hot acetone, and hot 2-propanol baths. 1.14— 1 min. N2 wafer dry. 1.15— Alloy ohmic contacts @ 468 °C for 1.5 min. in a zone controlled quartz tube furnace with 0.8 1/min N2 flowing through the tube. 2. Proton isolation implants 92 2.1— 3 min. immersion in an ultrasonic acetone bath. 2.2— 3 min. sequential immersion in each of hot trichloroethylene, hot acetone, and hot 2-propanol baths. 2.3— 1 min. N2 wafer dry. 2.4— Spin-coat the wafer @ 4000 RPM for 30 sec. with AZ 4620 photoresist. 2.5— Softbake the photoresist coated wafer in a forced air oven @ 90 ± 2 °C for 30 min. 2.6— Expose the photoresist coated wafer to 405 nm, 4.5 mWcm-2 ultraviolet light for 98 sec through the 'proton implant' mask 2.7— Spray develop the exposed photoresist using AZ 400K developer diluted to a volume ratio of 1:3 with DI H20. 2.8— Postbake the photoresist coated wafer in a forced air oven @ 120 ± 2 °C for 30 min. 2.9— Perform the multiple-energy proton implants 2.9.1— Ei = 180 keV, Di = 1013 cm"2, 2.9.2— E2 = 90 keV, D2 = 1013 cm"2, 2.9.3— E3 = 30 keV, D3 = 5 • 1013 cm"2. 2.10— 15 min. immersion in a hot N-methyl-2-pyrrolidone bath to remove the photoresist. 3. Metal/GaAs Schottky barrier formation 3.1— 3 min. immersion in an ultrasonic acetone bath. 3.2— 3 min. sequential immersion in each of hot trichloroethylene, hot acetone, and hot 2-propanol baths. 3.3— 1 min. N2 wafer dry. 3.4— Spin-coat the wafer @ 4000 RPM for 30 sec. with AZ 4110 photoresist. 3.5— Softbake the photoresist coated wafer in a forced air oven @ 90 ± 2 °C for 30 min. 3.6— Expose the photoresist coated wafer to 405 nm, 4.5 mWcm-2 ultraviolet light for 14 sec through the 'metal/GaAs Schottky barrier' mask. 3.7— Spray develop the exposed photoresist using AZ 400K developer diluted to a volume ratio of 1:3 with DI H20. 93 3.8— Immerse the wafer in a 20 ml:200 ml, NH4OH:DI H20 oxide etch bath for 30 sec. 3.9— • 1 min. DI H2O rinse and subsequent 1 min. N2 wafer dry. 3.10— Sequentially evaporate the following metal films under high vacuum 3.10.1— 500 A Ti, 3.10.2— 100 A Pt, 3.10.3— 2150 A Au. 3.11— 15 min. immersion in a hot N-methyl-2-pyrrolidone ultrasonic bath to lift off the unwanted metal. 3.12— 5 min. immersion in an ultrasonic acetone bath. 4. Cermet/GaAs Schottky barrier formation 4.1— 3 min. immersion in an ultrasonic acetone bath. 4.2— 3 min. sequential immersion in each of hot trichloroethylene, hot acetone, and hot 2-propanol baths. 4.3— 1 min. N2 wafer dry. 4.4— Spin-coat the wafer @ 4000 RPM for 30 sec. with AZ 4210 photoresist. 4.5— Softbake the photoresist coated wafer in a forced air oven @ 90 ± 2 °C for 30 min. 4.6— Expose the photoresist coated wafer to 405 nm, 4.5 mWcm-2 ultraviolet light for 28 sec through the 'cermet/GaAs Schottky barrier' mask. 4.7— Spray develop the exposed photoresist using AZ 400K developer diluted to a volume ratio of 1:3 with DI H20. 4.8— Postbake the photoresist coated wafer in a forced air oven @ 120 ± 2 °C for 30 min. 4.9— Immerse the wafer in a 20 ml:200 ml, NH4OH:DI H20 oxide etch bath for 30 sec. 4.10— 1 min. DI H20 rinse and subsequent 1 min. N2 wafer dry. 4.11— rf diode sputter Cr-SiO ( 45 wt. % Cr. ) onto the surface —frequency: 13.56 MHz, —background chamber pressure: < 2 • 10-6 mTorr, —gas: Ar, —deposition chamber pressure: 10 mTorr, 94 —rf forward power: w 250 Watts, rf reflected power: < 13 Watts resulting in a target bias of -800 volts, —Precondition time: 24 hrs., —Deposition time: 30 min. 4.12— 5 min. immersion in a hot N-methyl-2-pyrrolidone ultrasonic bath to lift-off the unwanted cermet film. 4.13— 5 min. immersion in an ultrasonic acetone bath. 5. Interconnect via formation 5.1— 3 min. immersion in an ultrasonic acetone bath. 5.2— 3 min. sequential immersion in each of hot trichloroethylene, hot acetone, and hot 2-propanol baths. 5.3— Immerse the wafer in a 20 ml:200 ml, NH4OH:DI H20 oxide etch bath for 30 sec. 5.4— 1 min. DI H2O rinse and subsequent 1 min. N2 wafer dry. 5.5— Spin-coat the wafer @ 4000 RPM for 1 min. with Du Pont PYRALIN PI-2550 polyimide diluted to a volume ratio of 1:1 with Du Pont T-9039 thin ner. 5.6— Imidize polyimide in a forced air oven @ 250 ± 2 °C for 3 hrs. 5.7— Evaporate 600 A of Ti onto the polyimide surface under high vacuum. 5.8— Spin-coat the wafer @ 4000 RPM for 30 sec. with AZ 4110 photoresist. 5.9— Softbake the photoresist coated wafer in a forced air oven @ 90 ± 2 °C for 30 min. 5.10— Expose the photoresist coated wafer to 405 nm, 4.5 mWcm-2 ultraviolet light for 14 sec through the 'interconnect vias' mask. 5.11— Spray develop the exposed photoresist using AZ 400K developer diluted to a volume ratio of 1:3 with DI H20. 5.12— Plasma etch the interconnect vias —background chamber pressure: < 25 mTorr, —rf power: 150 Watts, 5.12.1— PcF* = 256 mTorr, P02 = 23 mTorr and Pckmter = 279 mTorr for 90 sec. 5.12.2— PCF4 = 0 mTorr, Po2 = 250 mTorr and Pchamber = 250 mTorr for 10 min. 95 5.12.3— PCF4 = 256 mTorr, Po2 = 23 mTorr and Pchamber = 279 mTorr for 90 sec. 6. Second level interconnect metal formation 6.1— 3 min. immersion in an ultrasonic acetone bath. 6.2— 3 min. sequential immersion in each of hot trichloroethylene, hot acetone, and hot 2-propanol baths. 6.3— 1 min. N2 wafer dry. 6.4— Spin-coat the wafer @ 4000 RPM for 30 sec. with AZ 4210 photoresist. 6.5— Softbake the photoresist coated wafer in a forced air oven @ 90 ± 2 °C for 30 min. 6.6— Expose the photoresist coated wafer to 405 nm, 4.5 mWcm-2 ultraviolet light for 28 sec through the 'second level metallization' mask. 6.7— Spray develop the exposed photoresist using AZ 400K developer diluted to a volume ratio of 1:3 with DI H20. 6.8— Sequentially evaporate the following metal films under high vacuum 6.8.1— 500 A Ti, 6.8.2— 4000 A Au. 6.9— 3 min. immersion in an ultrasonic acetone bath to lift-off the unwanted metal. 6.10— 3 min. immersion in an ultrasonic acetone bath. 6.11— 3 min. sequential immersion in each of hot trichloroethylene, hot acetone, and hot 2-propanol baths. 6.12— 1 min. N2 wafer dry. 96 Appendix E Test Circuit for VHF Operation The GaAs CMCCD was operated in the VHF band at 100 MHz using the test circuit illustrated in Figure E.l. Figure E.l: The schematic diagram of the test circuit used to operate the CMCCD in the VHF band. 97
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A GaAs cermet gate charge-coupled device LeNoble, Maurice 1989-10-13
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Title | A GaAs cermet gate charge-coupled device |
Creator |
LeNoble, Maurice |
Publisher | University of British Columbia |
Date Issued | 1989 |
Description | The design, implementation and evaluation of a 64-pixel, 4-phase GaAs cermet gate charge-coupled device ( CMCCD ) are described. It is demonstrated that the signal charge confinement and the signal charge capacity of the CMCCD are maximized when thin, highly doped active layers are used for implementing the device. The cermet/GaAs junction within an interelectrode gap of the CMCCD forms a barrier similar to a metal/GaAs Schottky barrier, as revealed by an investigation of the dc current-voltage characteristic of a cermet/GaAs Schottky barrier diode. A transmission line model is described for the cermet/GaAs junction within an interelectrode gap of the CMCCD and is used to demonstrate the relationship of the surface potential variation along the gap as a function of the clock frequency and the material parameters. It is shown that the surface potential variation is monotonic for all frequencies, which is desirable for minimizing the formation of energy troughs within the active layer. Energy troughs trap and release charge from passing charge packets, causing unwanted signal dispersion. A two-dimensional computer model is used to determine a theoretical maximum frequency of operation of the CMCCD. It is shown that a short transport electrode length for a fixed transport electrode pitch is preferable as it results in the maximum high frequency performance of the CMCCD for the lowest clock power. A computer simulation of a single electrode transfer of a charge packet is demonstrated using the two-dimensional computer model. The computer simulation indicates that efficient charge transfer takes place, suggesting that the CMCCD will have good performance. A GaAs CMCCD with an on-chip GaAs MESFET source follower amplifier has been produced using a six mask level fabrication procedure. The CMCCD and the output source follower amplifier are demonstrated to operate at 100 MHz. Charge transfer efficiencies of 1.00 and 0.998 for 100 MHz operation are obtained for the CMCCD using the impulse response method and the insertion loss method. |
Genre |
Thesis/Dissertation |
Type |
Text |
Language | eng |
Date Available | 2010-10-13 |
Provider | Vancouver : University of British Columbia Library |
Rights | For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use. |
DOI | 10.14288/1.0098319 |
URI | http://hdl.handle.net/2429/29138 |
Degree |
Doctor of Philosophy - PhD |
Program |
Electrical and Computer Engineering |
Affiliation |
Applied Science, Faculty of Electrical and Computer Engineering, Department of |
Degree Grantor | University of British Columbia |
Campus |
UBCV |
Scholarly Level | Graduate |
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