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The design, simulation and fabrication of a gallium arsenide monolithic sample and hold circuit Durtler, Willem G. 1986

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THE DESIGN, SIMULATION AND FABRICATION OF A GALLIUM ARSENIDE MONOLITHIC SAMPLE AND HOLD CIRCUIT  by  WILLEM G. DURTLER B.Eng.  McGill University  A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE  in  THE FACULTY OF GRADUATE STUDIES DEPARTMENT OF ELECTRICAL ENGINEERING  We accept this thesis as conforming to the required  standard  THE UNIVERSITY OF BRITISH COLUMBIA June 1986 © Willem G. Durtler 1986  In p r e s e n t i n g  t h i s t h e s i s i n p a r t i a l f u l f i l m e n t of  requirements f o r an advanced degree at the  the  University  o f B r i t i s h Columbia, I agree t h a t the L i b r a r y s h a l l make it  f r e e l y a v a i l a b l e f o r reference  and  study.  I  further  agree t h a t p e r m i s s i o n f o r e x t e n s i v e copying o f t h i s t h e s i s f o r s c h o l a r l y purposes may  be granted by  department o r by h i s or her  the head of  representatives.  my  It i s  understood t h a t copying or p u b l i c a t i o n of t h i s t h e s i s f o r f i n a n c i a l gain  s h a l l not be  allowed without my  permission.  Department o f  ELECTRICAL  The . U n i v e r s i t y of B r i t i s h 1956 Main Mall Vancouver, Canada V6T 1Y3  1986 06 12  ENGINEERING  Columbia  written  ABSTRACT  This thesis describes work done towards the development of a gallium arsenide monolithic sample-and-hold  circuit.  The l i t e r a t u r e relevant to  high-speed e l e c t r o n i c sampling i s reviewed, and the d i f f e r e n t types of highspeed sampling c i r c u i t s are discussed.  The requirements of a sampling  c i r c u i t f o r use i n a d i s t r i b u t e d sampling amplifier are analyzed, and i t i s found that the most important requirement i s a high input impedance.  A  c i r c u i t suitable f o r monolithic integration i s designed and analyzed using the computer program mwSPICE. The d i f f e r e n t f a b r i c a t i o n technologies f o r gallium arsenide integrated c i r c u i t s are discussed, with emphasis on the s e l f - a l i g n e d gate technologies, which can give reduced p a r a s i t i c source and drain resistances.  The  processing steps f o r the refractory metal s e l f - a l i g n e d gate technology developed f o r t h i s thesis at the University of B r i t i s h Columbia are given i n detail.  DC measurement procedures f o r MESFETs and Schottky diodes are given  and r e s u l t s are presented f o r s e l f - a l i g n e d gate MESFETs fabricated at UBC. These r e s u l t s indicate that the r e f r a c t o r y metal s e l f - a l i g n e d gate process developed at UBC should be suitable f o r the f a b r i c a t i o n of the monolithic sample-and-hold  circuit.  TABLE OF CONTENTS ABSTRACT  i i  LIST OF TABLES  v  LIST OF FIGURES  vi  ACKNOWLEDGEMENT  ix  1  2  INTRODUCTION  1  1.1 1.2 1.3 1.4 1.5  1 1 3 4 7  Overview Requirement f o r h i g h - s p e e d m o n o l i t h i c i n t e g r a t e d c i r c u i t s Elements o f m o n o l i t h i c microwave i n t e g r a t e d c i r c u i t s Semiconductor m a t e r i a l s f o r MMICs The sampling a m p l i f i e r concept  HIGH-SPEED SAMPLING 2.1 Sample-and-hold waveforms and d e f i n i t i o n s 2.2 Sample-and-hold d e s i g n c o n s i d e r a t i o n s 2.3 B a s i c sample-and-hold c i r c u i t s 2.4 Sampling s w i t c h e s 2.5 Survey o f l i t e r a t u r e on sample-and-hold c i r c u i t s 2.5.1 D i s c r e t e m e c h a n i c a l sampling heads 2.5.2 D i s c r e t e s o l i d s t a t e samplers 2.5.3 M o n o l i t h i c sample-and-hold c i r c u i t s 2.5.4 T h e o r e t i c a l a n a l y s i s and modeling o f h i g h - s p e e d sample-and-hold c i r c u i t s  10 10 12 12 15 20 21 22 23  3  DESIGN AND SIMULATION 3.1 System requirements 3.2 Buffer amplifiers 3.3 The sampling s w i t c h  30 30 40 47  4  PROCESSING TECHNOLOGY FOR GaAs MESFETs AND MMICs 4.1 Introduction 4.2 Review o f GaAs MESFET f a b r i c a t i o n t e c h n o l o g i e s 4.2.1 A c t i v e l a y e r f o r m a t i o n 4.2.2 D e v i c e i s o l a t i o n 4.2.3 Gate f o r m a t i o n 4.2.4 Ohmic c o n t a c t f o r m a t i o n 4.2.5 P a s s i v e components 4.3 UBC r e f r a c t o r y m e t a l s e l f - a l i g n e d gate MESFET f a b r i c a t i o n technology  56 56 58 59 62 65 71 74  MEASUREMENT TECHNIQUES AND RESULTS 5.1 Introduction 5.2 Diode measurements 5.3 T r a n s i s t o r Measurements  89 89 90 94  5  - iii-  27  77  6  CONCLUSIONS AND SUGGESTIONS FOR FUTURE WORK  REFERENCES  107 111  APPENDIX Al A2 A3  mwSPICE l i s t i n g f o r t r a n s f e r curve a n a l y s i s mwSPICE l i s t i n g f o r b u f f e r a m p l i f i e r t r a n s i e n t response mwSPICE l i s t i n g f o r d u a l - g a t e s w i t c h t r a n s i e n t a n a l y s i s  -iv-  115 116 117  LIST OF TABLES TABLE  DESCRIPTION  PAGE  1.,1  Components f o r m o n o l i t h i c microwave i n t e g r a t e d  1..2  Important p r o p e r t i e s  4,.1  Detailed  5..1  Typical  o f s i l i c o n and g a l l i u m  circuits  arsenide  s e l f - a l i g n e d gate p r o c e s s l o g s e l f - a l i g n e d gate MESFET model parameters  -V-  5 6 80 105  LIST OF FIGURES FIGURE  TITLE  PAGE  1.1  Sampling a m p l i f i e r b l o c k diagram.  8  2.1  Sample-and-hold waveforms and d e f i n i t i o n s e t a l . [13] ) .  2.2  B a s i c sample-and-hold c i r c u i t s : (a) s i m p l e s t , b u f f e r e d , ( c ) i n p u t and output b u f f e r e d , (d)  2.3  M u l t i s t a g e sample-and-hold c i r c u i t s : (b) ground r e f e r e n c e d .  2.4  S i x - d i o d e sampling  2.5  FET sampling  2.6  S i l i c o n m o n o l i t h i c sample-and-hold c i r c u i t e t a l . [13] ) .  2.7  GaAs m o n o l i t h i c sampling  2.8  GaAs m o n o l i t h i c sample-and-hold c i r c u i t e t a l . [19] ) .  3.1  B l o c k diagram o f the sampling p r o p a g a t i o n times.  3.2  Input  delay l i n e  3.3  Input  dc l o s s as a f u n c t i o n o f the number o f c h a n n e l s :  ( after Stafford  (b) output integrator.  (a) feedback,  17  (a) n-channel MOSFET,  switch  (b) n-channel MESFET. ( after Stafford  ( a f t e r Saul  [17] ).  ( after Harrold  a m p l i f i e r showing t h e c r i t i c a l  low frequency  equivalent c i r c u i t .  3.4  Input  3.5  Input ac l o s s as a f u n c t i o n o f channel p o s i t i o n : (a) R = 10 kfi, wC = 10" , (b) R = 10 kQ, wC = 10 *  equivalent c i r c u i t .  2  in  in  25  26 28  31  35  in  d e l a y l i n e h i g h frequency  19  34  (a) R = 1 k n , (b) R = 10 kfl in  13  16  switch.  switch:  11  _  in  in  36  38  3.6  S i m u l a t e d r e t u r n l o s s and t r a n s m i s s i o n l o s s o f t h e l o a d e d input delay l i n e .  3.7  M o n o l i t h i c FET b u f f e r a m p l i f i e r ( a f t e r Hornbuckle e t a l . [23] ). 42  3.8  B u f f e r a m p l i f i e r s i m p l i f i e d low frequency equivalent c i r c u i t .  3.9  Simulated  b u f f e r a m p l i f i e r frequency  -vi-  small s i g n a l  response.  39  43  45  FIGURE  TITLE  PAGE  3.10  Simulated  b u f f e r a m p l i f i e r t r a n s i e n t response.  3.11  S i n g l e - g a t e MESFET s w i t c h : (a) schematic diagram, (b) ON s t a t e e q u i v a l e n t c i r c u i t , ( c ) OFF s t a t e e q u i v a l e n t c i r c u i t .  48  3.12  Dual-gate MESFET s w i t c h : (a) schematic diagram, (b) ON s t a t e e q u i v a l e n t c i r c u i t , (c) OFF s t a t e e q u i v a l e n t c i r c u i t .  51  3.13  Simulated  s i n g l e - g a t e GaAs MESFET s w i t c h  54  3.14  Simulated  dual-gate  4.1  D e v i c e i s o l a t i o n methods: (a) s e l e c t i v e i o n - i m p l a n t a t i o n , (b) i s o l a t i o n i o n - i m p l a n t a t i o n , ( c ) mesa e t c h i n g .  63  4.2  Buried-channel r e f r a c t o r y metal s e l f - a l i g n e d - g a t e process ( a f t e r Yokoyama e t a l . [42] ).  66  4.3  T - s t r u c t u r e s e l f - a l i g n e d - g a t e process ( a f t e r Levy e t a l . [43] ).  68  4.4  S e l f - A l i g n e d I m p l a n t a t i o n o f N - l a y e r Technology ( SAINT ) p r o c e s s ( a f t e r Yamasaki e t a l . [45] ).  70  4.5  S i d e w a l l - a s s i s t e d p a t t e r n i n v e r s i o n process Hagio e t a l . [46] ).  72  4.6  A i r b r i d g e f a b r i c a t i o n process.  4.7  UBC r e f r a c t o r y metal s e l f - a l i g n e d - g a t e f a b r i c a t i o n  GaAs MESFET s w i t c h  46  t r a n s i e n t response.  t r a n s i e n t response.  +  process  ( after  55  76  flowchart.  79  4.8  Sample-and-hold mask l a y o u t .  86  4.9  Photomicrograph o f sample-and-hold c h i p .  87  4.10  Scanning e l e c t r o n micrograph o f d u a l gate MESFET.  88  5.1  T y p i c a l capacitance/voltage  92  5.2  T y p i c a l diode c u r r e n t / v o l t a g e  5.3  Symmetric MESFET model e q u i v a l e n t ( a f t e r C u r t i c e e t a l . [50] ).  5.4  Small-gate-length  5.5  T y p i c a l p l o t o f 7 l D S versus V used t o determine v o l t a g e V and g a i n parameter K.  doping p r o f i l e . plot.  93  circuit 95  MESFET d e p l e t i o n r e g i o n . G S  T  -vii-  97 threshold 99  FIGURE  TITLE  PAGE  5.6  Measurement setup used t o determine R  5.7  Typical  5.8  T y p i c a l p l o t o f transconductance g  5.9  S e l f - a l i g n e d gate MESFET t r a n s f e r c u r v e s : ( ) measured, ( • • • ) simulated  s  and R . D  end-resistance plot giving R .  102  s  -viii-  m  101  versus V . GS  104  105  ACKNOWLEDGEMENT  Many p e o p l e h e l p e d  i n d i r e c t o r i n d i r e c t ways i n the r e s e a r c h and  preparation of this thesis.  In p a r t i c u l a r ,  I would l i k e t o thank Dr. L.  Young f o r h i s encouragement and guidance d u r i n g a l l stages work.  P e t e r Townsley was l a r g e l y r e s p o n s i b l e f o r the a c u a l  fabrication.  o f my graduate device  I a l s o g r a t e f u l l y acknowledge the c o n t r i b u t i o n s o f my f e l l o w  graduate s t u d e n t s ,  Kim Tan, Dave H u i , Salam Dindo and Wade Tang, as w e l l as  Rod Walker f o r h i s p r o o f r e a d i n g .  F i n a l l y , I would l i k e t o thank my  c o l l e a g u e s and management a t H a r r i s - F a r i n o n Canada, L t d . , o f D o r v a l , f o r t h e i r a c t i v e support  and encouragement.  - ix-  Quebec,  CHAPTER 1  1.1  INTRODUCTION  Overview  T h i s t h e s i s d e s c r i b e s the d e s i g n and f a b r i c a t i o n o f a m o n o l i t h i c , h i g h speed, sample-and-hold a m p l i f i e r f o r use The  introduction w i l l  circuits,  i n signal processing applications.  d i s c u s s the requirements  f o r high-speed  the a p p l i c a t i o n o f g a l l i u m a r s e n i d e and  the fundamentals o f  g a l l i u m a r s e n i d e m o n o l i t h i c microwave i n t e g r a t e d c i r c u i t s and  the concept  o f d i s t r i b u t e d sample-and-hold  Chapter 2 w i l l  In chapter  a b l e f o r use  ( GaAs MMICs ),  amplification.  d i s c u s s the t h e o r e t i c a l and p r a c t i c a l a s p e c t s  speed sample-and-hold c i r c u i t s the f i e l d .  and  3 the d e s i g n of a sample-and-hold a m p l i f i e r s u i t -  r e s u l t s u s i n g the computer program mwSPICE w i l l be  given.  w i l l present  1.2  Columbia w i l l be d e s c r i b e d .  r e s u l t s w i l l be g i v e n i n c h a p t e r  c o n c l u s i o n s and  suggestions  Requirement f o r high-speed  simulation  In c h a p t e r 4  development o f a s e l f - a l i g n e d gate GaAs p r o c e s s i n g t e c h n o l o g y U n i v e r s i t y of B r i t i s h  of high  g i v e an overview o f p u b l i s h e d work i n  i n a d i s t r i b u t e d a m p l i f i e r w i l l be d e s c r i b e d and  and e x p e r i m e n t a l  monolithic  at  Measurement 5, and  finally  the  procedures chapter  f o r f u t u r e work.  monolithic integrated  circuits  I n the p a s t t h e r e has been an e v o l u t i o n to f a s t e r and more complex circuits, circuits  with c i r c u i t s  of a given complexity  becoming ever f a s t e r  o f a g i v e n speed becoming ever more complex.  -1-  the  and  A t the same time  6  these  c i r c u i t s are becoming b o t h cheaper and p h y s i c a l l y s m a l l e r i n s i z e .  These developments are s p u r r e d by h i g h volume subsystems i n areas r a d a r and  r e a l time g r a p h i c s .  the requirement f o r r e l a t i v e l y cheap,  such as s i g n a l p r o c e s s i n g , phased a r r a y Phased a r r a y r a d a r ,  f o r example, uses  t r a n s m i t power a m p l i f i e r s , r e c e i v e low n o i s e a m p l i f i e r s , t r a n s m i t / r e c e i v e switches  and  the r a d a r these  d i g i t a l l y c o n t r o l l e d phase s h i f t e r s ,  frequency  o f t y p i c a l l y 8 GHz.  at  In p r e s e n t l y a v a i l a b l e systems  f u n c t i o n s are implemented u s i n g m a i n l y h y b r i d i n t e g r a t e d c i r c u i t  technology  which i s b u l k y  f o r assembly and monolithic  tuning.  and expensive due A l l these  integrated c i r c u i t  seems to be  to the s k i l l e d manpower r e q u i r e d  subsystems have been demonstrated u s i n g  technology  the l i m i t i n g f a c t o r .  been d e v e l o p e d i t i s l i k e l y one  a l l which must operate  [1,2,3,4], but a t p r e s e n t  yield  Once a s u i t a b l e h i g h y i e l d t e c h n o l o g y  t h a t a l l these  f u n c t i o n s w i l l be  has  i n t e g r a t e d on  chip. Another h i g h volume a p p l i c a t i o n t h a t i s b e i n g  12 GHz  D i r e c t Broadcast  t e l e v i s i o n market.  Satelite  ( DBS  These c i r c u i t s  preamplifier, a local oscillator,  ) r e c e i v e r s f o r the  a mixer, a bandpass f i l t e r frequency  f u n c t i o n s have been demonstrated i n m o n o l i t h i c  A very circuits  complete r e c e i v e r s on a c h i p important  can be  amplifier. form, amd  noise and  an  A l l these s e v e r a l papers have  [5,6].  advantage o f m o n o l i t h i c microwave c i r c u i t s over h y b r i d  i s t h a t the p a r a s i t i c r e a c t a n c e s  connections  commercial  t y p i c a l l y c o n s i s t o f a low  automatic g a i n c o n t r o l i n t e r m e d i a t e  presented  actively investigated is  g r e a t l y reduced.  inter-  T h i s c o n s i d e r a b l y i n c r e a s e s the maximum  a t t a i n a b l e bandwidth which i s important  -2-  a s s o c i a t e d w i t h component  for instrumentation  and e l e c t r o n i c  warfare  applications.  By i n c o r p o r a t i n g t h e p a r a s i t i c c a p a c i t a n c e s  of a  number o f FETs i n t o a t r a n s m i s i o n l i n e s t r u c t u r e , s o - c a l l e d t r a v e l l i n g wave, or d i s t r i b u t e d ,  a m p l i f i e r s can a c h i e v e bandwidths o f a decade o r more up to  20 GHz [ 7 ] ; t h i s performance i s o n l y p o s s i b l e w i t h m o n o l i t h i c The  s m a l l s i z e and minimal p a r a s i t i c s a l s o a l l o w MMICs t o be used w e l l  i n t o the millimetre-wave guide  circuits.  ( 30 - 300 GHz ) r e g i o n  c i r c u i t s were u s a b l e  I n the d i g i t a l  field  i n t h i s frequency  [8].  Up t o now o n l y wave-  range.  t h e r e i s a l a r g e requirement  for very high  l o g i c f o r such a p p l i c a t i o n s as r e a l time s i g n a l p r o c e s s i n g and r e a l graphics.  speed time  Other uses f o r h i g h speed d i g i t a l ICs a r e supercomputers and h i g h  d a t a - r a t e telecommunications modems. c i r c u i t s are commercially  A t present,  GaAs-based SSI and MSI  a v a i l a b l e t h a t operate up t o about 4 GHz [9] b u t  their cost i s s t i l l p r o h i b i t i v e l y high.  1.3  Elements o f m o n o l i t h i c microwave i n t e g r a t e d c i r c u i t s  A m o n o l i t h i c microwave i n t e g r a t e d c i r c u i t c i r c u i t used t o perform GHz,  ( MMIC ) c a n be d e f i n e d as a  a g i v e n f u n c t i o n a t f r e q u e n c i e s g r e a t e r than about 1  where the a c t i v e and u s u a l l y p a s s i v e elements a r e f a b r i c a t e d on a  s i n g l e semiconductor c h i p .  This d e f i n i t i o n allows  for c r i t i c a l  passive  components, such as r e s o n a t o r s , o r b u l k y n o n - c r i t i c a l components, such as d e c o u p l i n g c a p a c i t o r s , t o be o f f t h e c h i p . A c t i v e components, such as metal-semiconductor f i e l d ( MESFETs ) and Schottky frequency  diodes  are r e q u i r e d to achieve  c o n v e r s i o n and o t h e r n o n l i n e a r f u n c t i o n s .  -3-  effect  transistors  gain, f o r  Passive devices,  such  as c a p a c i t o r s , i n d u c t o r s , r e s i s t o r s and t r a n s m i s s i o n l i n e s are used f o r bandwidth d e t e r m i n a t i o n , impedance t r a n s f o r m a t i o n , b i a s i n g and o t h e r linear functions. where a p p l i c a b l e ,  The most important  elements,  t h e i r common uses and,  t h e i r f a b r i c a t i o n t e c h n o l o g i e s are l i s t e d  i n table  1.1.  One problem w i t h MMICs t h a t c o n t a i n many p a s s i v e elements i s t h a t the c h i p s i z e can become q u i t e l a r g e , a cm  2  o r more i s n o t uncommon.  i n c r e a s e s the c o s t and can decrease y i e l d etc.  Another p o t e n t i a l disadvantage  tune a c i r c u i t  due to breakage, s u b s t r a t e flaws  o f MMICs i s t h a t p r e s e n t t e c h n i q u e s  a f t e r f a b r i c a t i o n are rudimentary  hybrid circuits.  Therefore  to  compared w i t h c o n v e n t i o n a l  a very careful i n i t i a l  design i s required using  the b e s t p o s s i b l e component models and a d e s i g n p h i l o s o p h y based sensitivity  This  t o component and p r o c e s s i n g v a r a t i o n s .  on minimum  Computer-aided a n a l y s i s  and d e s i g n a r e a b s o l u t e l y e s s e n t i a l f o r most MMIC d e s i g n s .  1.4  Semiconductor m a t e r i a l s f o r MMICs  A t p r e s e n t b o t h s i l i c o n and g a l l i u m a r s e n i d e a r e b e i n g used f o r the p r o d u c t i o n o f MMICs. S i has the advantages o f h a v i n g lower c o s t and a w e l l developed speed.  and s i m p l e r p r o d u c t i o n t e c h n o l o g y w h i l e GaAs has i n h e r e n t l y h i g h e r  The main c h a r a c t e r i s t i c s o f the two a r e l i s t e d  a l s o has p o t e n t i a l as a s u i t a b l e semiconductor developed  in  t a b l e 1.2.  InP  b u t has n o t y e t been  t o the e x t e n t o f S i and GaAS.  The low f i e l d e l e c t r o n m o b i l i t y o f GaAs i s much h i g h e r than t h a t o f S i which i s the r e a s o n f o r i t s h i g h e r speed p o t e n t i a l .  -4-  However,  i t s hole  COMPONENT  FABRICATION TECHNOLOGY  Capacitors  interdigitated  < 1 pF  metal-insulator-metal  1 - 100 pF  loop  < 10 nH  s h o r t e d high-impedance l i n e  < 10 nH  multiturn  10 - 100 nH  Inductors  Resistors  thinfilm  Transmission  lines  ( with airbridges )  sputtered  - 10 kO  10 fl - 1 kil  microstrip  20 - 130 O  coplanar  40 - 200 O  waveguide  epitaxial  Schottky  ion-implanted  T a b l e 1.1.  10  semiconductor  MESFETs and diodes  APPROXIMATE VALUE RANGE  Components f o r m o n o l i t h i c microwave i n t e g r a t e d circuit fabrication.  -5-  PROPERTY  Intrinsic  Si  resistivity,  Dielectric  fi-cm  2.3X10  constant  GaAs  5  11.9  10  8  13.1  Electron d r i f t mobility,  cm /V-s  1500  8500  Hole d r i f t m o b i l i t y ,  cm /V-s  450  400  2  2  Bandgap, eV  1.12,  Crystal  structure  diamond  zincblende  Lattice  constant,  5.431  5.653  2.33  5.32  Density,  g/cm  A  3  indirect  1.42,  direct  Linear c o e f f i c i e n t of 2.6X10"  t h e r m a l expansion, K"  1  6  6.86X10"  Thermal c o n d u c t i v i t y , W/K-cm  1.5  0.46  Melting  1415  1238  p o i n t , °C  A l l values  T a b l e 1.2.  specified  6  a t 300 K.  Important p r o p e r t i e s  -6-  o f s i l i c o n and g a l l i u m  arsenide.  m o b i l i t y i s lower than t h a t o f S i and hence n-channel FETs are used almost exclusively.  GaAs does not have a n a t i v e oxide w i t h a p p r o p r i a t e p r o p e r t i e s  f o r use w i t h MOS, given r i s e than MIS forward  and o t h e r i n s u l a t o r s such as S i N 3  to v e r y h i g h i n t e r f a c e t r a p d e n s i t i e s ,  s t r u c t u r e s are used f o r the FET gate v o l t a g e to about 0.6  and  A  Si0  have thus f a r  2  so S c h o t t k y b a r r i e r s  gates which l i m i t s  the  usable  V.  The h i g h r e s i s t i v i t y o f GaAs even a f t e r p r o c e s s i n g i s one advantages because i t p r o v i d e s  rather  o f the main  i n h e r e n t i s o l a t i o n between d e v i c e s and  also  a l l o w s the f a b r i c a t i o n of r e l a t i v e l y low l o s s t r a n s m i s s i o n l i n e s on c h i p . At 2 GHz and  i t s d i e l e c t r i c l o s s i s about 0.008 dB per cm  0.001 The  dB  f o r alumina, a common h y b r i d MIC  d i r e c t bandgap o f GaAs a l l o w s  l a s e r s and  compared to 0.4  substrate  dB f o r S i  [10].  i t to be used to make s o l i d s t a t e  s i n c e i t i s t r a n s p a r e n t to i n f r a r e d l i g h t  i t i s an  ideal  m a t e r i a l f o r making i n t e g r a t e d o p t o - e l e c t r o n i c d e v i c e s such as m o n o l i t h i c f i b r e - o p t i c repeaters, although application Although  InP may  be  an even b e t t e r c h o i c e f o r t h i s  [11]. much work remains to be  c a t i o n technology,  done to develop  i t appears t h a t GaAs w i l l be  a suitable fabri-  the semiconductor o f  c h o i c e f o r most MMIC d e s i g n s .  1.5  The  sampling  a m p l i f i e r concept  The work done f o r t h i s t h e s i s was of producing  d i r e c t e d at s t u d y i n g the  a m o n o l i t h i c v e r s i o n o f the sampling  Defense R e s e a r c h E s t a b l i s h m e n t  a m p l i f i e r developed  Ottawa ( DREO ) [12].  -7-  feasibility at the  A b l o c k diagram of the  F i g u r e 1.1  Sampling a m p l i f i e r b l o c k diagram.  -8-  sampling a m p l i f i e r i s g i v e n i n f i g u r e 1.1 delay l i n e The  (A) and i s f i n a l l y d i s s i p a t e d i n the i n p u t l o a d r e s i s t o r ( B ) .  N i n p u t switches  (C) a r e p e r i o d i c a l l y c l o s e d t o sample the s i g n a l along  the i n p u t l i n e and the sampled v o l t a g e processing, amplifiers  The i n p u t t r a v e l s a l o n g the i n p u t  i s s t o r e d on c a p a c i t o r s (D). S i g n a l  such as i n t h i s case a m p l i f i c a t i o n , occurs ( E ) , a f t e r which the output  s i g n a l t o t h e output  delay l i n e  (G).  switches  i n the v i d e o  (F) f e e d the p r o c e s s e d  H a l f the s i g n a l t r a v e l s i n the  opposite  d i r e c t i o n as the i n p u t s i g n a l and i s absorbed by the output  load  resistor  (H), the o t h e r h a l f i s low pass f i l t e r e d t o remove the s w i t c h i n g  n o i s e and i s a v a i l a b l e a t the output. The bandwidth o f the sampling a m p l i f i e r i s determined m a i n l y by the w i d t h o f the sampling p u l s e which s h o u l d be made as narrow as p o s s i b l e .  The  bandwidth r e q u i r e d o f the v i d e o a m p l i f i e r s i s s l i g h t l y g r e a t e r than h a l f o f the  i n p u t bandwidth d i v i d e d by the number o f channels.  d e l a y between a d j a c e n t  switches  The optimum time  i s determined by the maximum i n p u t  freqency,  the number o f channels and the time d e l a y o f the s w i t c h c o n t r o l s i g n a l between a d j a c e n t The  switches,  which w i l l be non-zero i n p r a c t i c e .  advantages o f the sampling a m p l i f i e r a r e t h a t low bandwidth  ampli-  f i e r s c a n be u s e d t o a m p l i f y wideband s i g n a l s and t h a t the d e s i g n i s i n h e r e n t l y redundant so t h a t the f a i l u r e o f one s u b - a m p l i f i e r w i l l n o t cause the f a i l u r e o f the complete sampling a m p l i f i e r .  -9-  CHAPTER 2  2.1  HIGH SPEED SAMPLING  Sample-and-hold waveforms and d e f i n i t i o n s  An  i d e a l sample-and-hold c i r c u i t  is a circuit  t r a c k s the i n p u t s i g n a l and whose output,  t h a t , i n the sample mode,  on r e c e i p t o f a h o l d command,  takes on t h e v a l u e o f the i n p u t s i g n a l a t the i n s t a n t the command i s r e c e i v e d and h o l d s  t h i s value u n t i l  the next  command i s g i v e n [ 1 3 ] .  In p r a c t i c e c e r t a i n s i g n a l d i s t o r t i o n s and time d e l a y s occur limit  the performance o f a sample-and-hold c i r c u i t .  i n p u t , output idealities.  that w i l l  F i g u r e 2.1 shows the  and c o n t r o l waveforms w i t h the t y p i c a l l y o c c u r r i n g nonA f t e r the h o l d command i s g i v e n a f i n i t e time i s r e q u i r e d f o r  the s w i t c h t o open; t h i s i s termed d e l a y time.  P e d e s t a l i s the term g i v e n to  the change i n output v o l t a g e when the sampling  switch  to  i s opened and Is due  the c a p a c i t i v e d i v i d e r e f f e c t o f the h o l d c a p a c i t o r and the sampling  switch p a r a s i t i c capacitances.  S e t t l i n g time i s the time r e q u i r e d f o r any  t r a n s i e n t s t o d i e down when the s w i t c h i s opened. h o l d c a p a c i t o r w i l l s l o w l y charge o r d i s c h a r g e , polarity.  The c o r r e s p o n d i n g  I n the h o l d mode, the  depending on s i g n a l  change i n output v o l t a g e i s termed droop r a t e .  When the sample command i s g i v e n the time r e q u i r e d f o r the s w i t c h t o c l o s e , the h o l d c a p a c i t o r t o charge t o the i n p u t l e v e l and the output s e t t l e down i s termed a c q u i s i t i o n  time.  -10-  s i g n a l to  INPUT  SETTLING - TIME —  UJ CO  OUTPUT  o > _J PEDESTAL F. r  DELAY TIME  SAMPLE  HOLD  DROOP  ACQUISITION TIME  SAMPLE  TIME  F i g u r e 2.1 e t a l . [13]  Sample-and-hold waveforms and d e f i n i t i o n s ).  -11-  ( after  Stafford  2.2  Sample-and-hold d e s i g n c o n s i d e r a t i o n s  For a g i v e n a p p l i c a t i o n t h e r e are two t a k e n i n t o account.  The  first  s e t s o f c o n s t r a i n t s t h a t must be  i s determined  by  the e x t e r n a l system r e q u i r e -  ments and c o n s i s t s o f such f a c t o r s as bandwidth, i n p u t and output g a i n , power h a n d l i n g c a p a b i l i t y and power consumption, l i n e a r i t y sampling  accuracy.  determines  On the o t h e r hand, the p h y s i c a l c i r c u i t  the c i r c u i t c o m p l e x i t y  r e q u i r e d i n the system  and c o s t and  impedance, and  implementation  the t r a d e o f f s t h a t w i l l  be  requirements.  S p e c i f i c d e s i g n g o a l s were not g i v e n f o r the d i s t r i b u t e d a m p l i f i e r work done a t the U n i v e r s i t y o f B r i t i s h Columbia.  I t was  to r u n as f a s t  as  p o s s i b l e , r u n a t a f a i r l y low s i g n a l l e v e l and be s u i t a b l e f o r m o n o l i t h i c integration.  S i n c e a l a r g e number o f switches  are connected  in parallel  a l o n g the d e l a y l i n e s the i n p u t impedance o f each must be h i g h to a v o i d a s i g n i f i c a n t v o l t a g e drop a l o n g the l i n e . possible  the c i r c u i t c o m p l e x i t y  2.3  B a s i c sample-and-hold  In o r d e r to keep y i e l d as h i g h  should, a t l e a s t i n i t i a l l y ,  be kept  low.  circuits  I n p r i n c i p l e , a l l sample-and-hold c i r c u i t s c o n s i s t o f a s i g n a l s w i t c h a hold capacitor. c i r c u i t s and requirements.  as  Other elements, such as b u f f e r c i r c u i t s ,  and  switch d r i v e  feedback c i r c u i t s can be added to b e t t e r meet system The  s i m p l e s t type o f sample-and-hold i s simply a s w i t c h  c a p a c i t o r , f i g u r e 2.2a.  The  disadvantages  -12-  of this c i r c u i t  and  are t h a t a l l the  IN  OUT  -13-  hold capacitor charging  c u r r e n t must be  s u p p l i e d by  which means t h a t the a c q u i s i t i o n time w i l l be impedance.  C o n v e r s e l y , the droop r a t e w i l l be  impedance o f subsequent c i r c u i t r y , there the  can be  dependent on the dependent on the  increase  time. improved by  f o l l o w i n g the  c a p a c i t o r w i t h a b u f f e r a m p l i f i e r as shown i n f i g u r e 2.2b. a consistent, high  impedance l o a d and  disadvantage of t h i s c i r c u i t  thus a low  and  hold  This results i n  droop r a t e .  i s increased'complexity,  The  major  the b u f f e r must be  d e s i g n e d t o a v o i d h a v i n g i t l i m i t speed performance, cause  d i s t o r t i o n or g i v e a dc o f f s e t . still  input  i f t h i s impedance i s i n d u c t i v e ,  sample-and-hold performance can be  properly  source  s i g n i f i c a n t r i n g i n g o f the sampled s i g n a l , which w i l l  settling The  and,  the sampled source,  not w e l l d e f i n e d and  The  i n p u t impedance o f t h i s c i r c u i t i s  i s time v a r y i n g , which can  cause problems i n h i g h  f r e q u e n c y systems. The  next l o g i c a l improvement i s to a l s o put  a b u f f e r a m p l i f i e r at  i n p u t to i s o l a t e i t from the source as shown i n f i g u r e 2.2c. of a number o f s w i t c h e s i n p a r a l l e l a h i g h was  discussed  have a h i g h previous  i n s e c t i o n 2.2.  The  input b u f f e r should  the major d i s a d v a n t a g e s are  p o s s i b i l i t y o f d i s t o r t i o n and  the output b u f f e r a m p l i f i e r i s c o n f i g u r e d  the s w i t c h  case  As  a l s o be  d e s i g n e d to  i n the case o f  increased  as  the  c o m p l e x i t y and  the  dc o f f s e t .  Another type o f sample-and-hold c i r c u i t  c a p a c i t o r i n the  the  i n p u t impedance i s n e c e s s a r y  slew r a t e to reduce a c q u i s i t i o n time.  circuit,  For  the  feedback l o o p .  The  Here  as an i n t e g r a t o r , w i t h the  hold  main advantage o f t h i s c i r c u i t  i s e s s e n t i a l l y always o p e r a t i n g  -14-  i s shown i n f i g u r e 2.2d.  a t ground p o t e n t i a l , thus  i s that easing  the d r i v e requirements  and a l l o w i n g a l a r g e r i n p u t v o l t a g e swing.  l i m i t e d h i g h frequency  use, however, due  microwave "op-amp" type  I t has  to the d i f f i c u l t y o f o b t a i n i n g  amplifiers.  In c e r t a i n a p p l i c a t i o n s ,  such as sampling  oscilloscopes,  i t i s required  to have v e r y s h o r t a c q u i s i t i o n times but a t r e l a t i v e l y low sampling In such cases  the more complex m u l t i s t a g e sample-and-hold c i r c u i t s o f the  type shown i n f i g u r e 2.3 capacitor C its  x  rates.  are o f t e n used.  I n the c i r c u i t  i s i n i t i a l l y charged up to a s m a l l f r a c t i o n ,  steady s t a t e v a l u e b e f o r e s w i t c h S  the much l a r g e r c a p a c i t o r C  2  i s opened a g a i n .  1  of f i g u r e  2.3a,  t y p i c a l l y 5%, Switch  over a l o n g e r p e r i o d o f time and  S  the  of  charges  2  amplifier  g a i n A and the feedback f a c t o r are chosen to charge b o t h c a p a c i t o r s to the o r i g i n a l input value. charged  to a f r a c t i o n o f i t s steady  charge the l a r g e r c a p a c i t o r C achieved S  2  2.4  Sampling  C  I n the c i r c u i t o f f i g u r e 2.3b,  opens and S  3  2  1  is similarly  s t a t e v a l u e and the g a i n A i s chosen to  to the f u l l  steady  i s c l o s e d to d i s c h a r g e C  1  state value.  Once t h i s i s  back to ground p o t e n t i a l .  switches  For the s w i t c h i n g element i t s e l f t h e r e are two p o p u l a r c o n f i g u r a t i o n s . The  first  i s the diode r i n g shown i n f i g u r e 2.4.  open ) , the c o n t r o l v o l t a g e V i n o r d e r to keep d i o d e s D _ 5  Conversely,  i n the ON  6  c  must be  c  s t a t e ( switch  l e s s than the peak s i g n a l v o l t a g e  forward b i a s e d and  state V  In the OFF  V  s  reverse biased.  must be g r e a t e r than V . s  The b i a s v o l t a g e  V  b  i s dependent on the b i a s r e s i s t o r v a l u e and diode s e r i e s r e s i s t a n c e as w e l l as on the maximum i n p u t s i g n a l swing  [12].  -15-  (a)  Figure 2.3  Multistage sample-and-hold c i r c u i t s : (a) feedback, (b) ground referenced.  -16-  + CONTROL  + BIAS  D5  BIAS  1  01  V  s  03  OUT  . IN D4  02  R  D6  BIAS  - BIAS - CONTROL  Figure 2.4  Six-diode sampling switch.  -17-  The main advantage  o f the diode r i n g s w i t c h i s t h a t , due  c o n t r o l d r i v e requirement,  t o the b a l a n c e d  the complementary sampling p u l s e s t e n d to c a n c e l  a t the i n p u t and output p o r t s i f well-matched  diodes are used.  I t can a l s o  h a n d l e l a r g e i n p u t s i g n a l l e v e l s i f the b i a s and c o n t r o l v o l t a g e s and b i a s r e s i s t o r s are chosen p r o p e r l y , and can have a h i g h OFF/ON impedance I t s d i s a d v a n t a g e s are a s i g n i f i c a n t dc power consumption  and the  ratio.  requirement  f o r a h i g h speed complementary s w i t c h c u r r e n t d r i v e , e s p e c i a l l y i f a l a r g e number o f s w i t c h e s are to be used i n p a r a l l e l . The  o t h e r p o p u l a r type o f s w i t c h uses a f i e l d e f f e c t t r a n s i s t o r as a  voltage controlled resistor, to a few tens o f MHz,  figure 2.5.  For lower speed a p p l i c a t i o n s ,  a s i l i c o n MOSFET i s most u s e f u l s i n c e i t s gate  up  cannot  be f o r w a r d b i a s e d i n t o c o n d u c t i o n as i s p o t e n t i a l l y the case w i t h a JFET or MESFET.  H i g h e r speed a p p l i c a t i o n s , however, r e q u i r e the f a s t s w i t c h i n g  speed o f a GaAS MESFET. The advantages  o f a FET s w i t c h are t h a t i t s s t a t e i s c o n t r o l l e d by a  single-ended voltage signal,  thus e a s i n g the d r i v e requirements compared to  a diode s w i t c h , and the n e g l i g i b l e dc power consumption.  However, s i n c e  the s w i t c h r e s i s t a n c e i s dependent on the gate to c h a n n e l v o l t a g e , and the c h a n n e l v o l t a g e i s s i g n a l l e v e l dependent, a l i m i t a t i o n i s p l a c e d on the maximum u s e f u l s i g n a l l e v e l t h a t can be h a n d l e d .  I n o r d e r t o minimize  e f f e c t s the s w i t c h c o n t r o l b i a s and p u l s e h e i g h t must be chosen such  these  that  the c o n t r o l gate does not become forward b i a s e d i n t o c o n d u c t i o n a t the l o w e s t s i g n a l v o l t a g e and t h a t the channel r e s i s t a n c e does n o t become too l a r g e a t the h i g h e s t s i g n a l l e v e l s i n c e t h i s would cause the  acquisition  time t o be s t r o n g l y s i g n a l l e v e l dependent. In p r a c t i c e t h i s l i m i t s  -18-  the  (a)  I  CONTROL  OUT  (b)  F i g u r e 2.5  CONTROL  FET sampling s w i t c h : (a) n-channel MOSFET, (b) n-channel MESFET.  -19-  s i g n a l v o l t a g e swing t o about 1 v o l t Another major advantage  peak-to-peak.  o f the FET s w i t c h i s i t s s i m p l i c i t y .  I t i s not  r e q u i r e d t o have matched d e v i c e s and the p h y s i c a l l a y o u t i s l e s s  critical  than i n the case o f the diode s w i t c h . The  d i s a d v a n t a g e o f the FET s w i t c h i s t h a t the s i n g l e - e n d e d d r i v e does  n o t g i v e any sample p u l s e f e e d t h r o u g h c a n c e l l a t i o n .  T h i s feedthrough i s  e s s e n t i a l l y caused by the g a t e - s o u r c e c a p a c i t a n c e f o r m i n g a c a p a c i t i v e d i v i d e r w i t h the h o l d c a p a c i t o r and i s thus dependent on the r a t i o o f the v a l u e s o f these c a p a c i t a n c e s . I t i s more or l e s s independent and w i l l n o t be an important f a c t o r i n many a p p l i c a t i o n s .  of s i g n a l  The  level  other  d i s a d v a n t a g e o f the MESFET s w i t c h i s the low a l l o w a b l e i n p u t v o l t a g e swing as d i s c u s s e d p r e v i o u s l y .  2.5  Survey o f l i t e r a t u r e on sample-and-hold  To determine  circuits  the s t a t e o f the a r t o f sample-and-hold  c i r c u i t s both a  computer a i d e d s e a r c h and a manual s e a r c h were performed u s i n g s u b j e c t and c i t a t i o n indexes. literature.  S u r p r i s i n g l y l i t t l e has been p u b l i s h e d i n the  The most important papers o f what has been p u b l i s h e d w i l l  discussed i n four categories:  (a) d i s c r e t e m e c h a n i c a l  (b) d i s c r e t e s o l i d s t a t e sampling c i r c u i t s , and  scientific  sampling heads,  (c) m o n o l i t h i c sampling  (d) t h e o r e t i c a l a n a l y s i s and modeling o f h i g h speed sampling  -20-  be  circuits  circuits.  2.5.1  D i s c r e t e m e c h a n i c a l sampling heads  The h i g h e s t speed e l e c t r o n i c switches are found i n t h i s c a t e g o r y .  The  sampling heads are g e n e r a l l y used i n sampling o s c i l l o s c o p e s and s i n c e they have been developed by p r i v a t e l a b o r a t o r i e s f o r use  i n commercially  a v a i l a b l e t e s t equipment l i t t l e has been p u b l i s h e d on the a c t u a l d e s i g n procedure. Packard.  The  f i r s t r e c e n t paper o f i n t e r e s t i s by Grove  In i t he d i s c u s s e d the d e s i g n and m o d e l l i n g o f a two  l o c a t e d i n the c e n t r e o f a d i e l e c t r i c - f i l l e d Using a s i m p l i f i e d l i n e a r for  [14] o f Hewlettdiode  sampler  biconical transmission line.  ( s m a l l s i g n a l ) model he o b t a i n e d an e x p r e s s i o n  the sampler bandwidth,  which i s determined by the diode  characteristics,  the sampling p u l s e w i d t h and the t r a n s m i s s i o n l i n e c h a r a c t e r i s t i c s f o r both the  s i g n a l and the sampling p u l s e .  than 15 GHz  and s t i l l  d e s i g n gave a bandwidth o f g r e a t e r  forms the b a s i s o f p r e s e n t day sampling heads and  not been s i g n i f i c a n t l y improved In  The  upon.  a more r e c e n t paper R i a d [15] gave a more r i g o r o u s a n a l y s i s o f the  1430A sampling head, which has a nominal bandwidth o f 12.4 p u l s e r i s e t i m e o f 28 ps. to  the one  diodes.  The  sampling head i t s e l f  GHz  i n p u t and output impedance matching  s o p h i s t i c a t e d , and feedback sampled l e v e l as was  i s similar i n construction sampling  s t r u c t u r e s are more -  i s used to b i a s the diodes to the p r e v i o u s  d i s c u s s e d i n s e c t i o n 2.3.  By d o i n g t h i s the  network measures o n l y the d i f f e r e n c e between c o n s e c u t i v e samples, i m p r o v i n g the dynamic range.  HP-  and a nominal  d i s c u s s e d i n [14], w i t h a b i c o n i c a l t a p e r e d l i n e and two  The  has  The  sample p u l s e i t s e l f  -21-  sampling thus  i s o b t a i n e d by  r e f l e c t i n g a fast risetime voltage cavity. circuit  step o f f a s h o r t c i r c u i t w a l l i n the  When the l e a d i n g edge o f the step i t i s i n v e r t e d and,  upon r e a c h i n g  i s r e f l e c t e d o f f the the diodes,  cancels  wave l e a v i n g o n l y a narrow p u l s e whose w i d t h i s determined by d i s t a n c e between the diodes and  the s h o r t  A f t e r d e s c r i b i n g the sampler and model o f i t which i n c l u d e s the  the  incoming  the round  trip  circuit.  i t s o p e r a t i o n R i a d goes on to develop a  i n p u t and  l a y o u t , c o n s t r u c t i o n and b i a s , and  short  output matching networks, the  diode  the feedback network.  M e c h a n i c a l sampling heads u s i n g d i s c r e t e diodes are the f a s t e s t e l e c t r o n i c samplers c u r r e n t l y a v a i l a b l e , the f a s t e s t h a v i n g about 18 GHz.  T h e i r disadvantage i s t h e i r h i g h c o s t  a s s e m b l i n g t h e i r components ) and  2.5.2  ( f o r machining  their r e l a t i v e l y large  and  size.  D i s c r e t e s o l i d s t a t e samplers  I n c o n t r a s t to the m e c h a n i c a l samplers d i s c u s s e d s o l i d s t a t e samplers do n o t n o r m a l l y signal.  bandwidths o f  have matching networks f o r the  T y p i c a l l y , a complete sampler w i l l use  a m p l i f i e r s to i s o l a t e the s w i t c h  i n the p r e v i o u s  i n p u t and  input  output b u f f e r  from the e x t e r n a l c i r c u i t r y .  impedance o f the a m p l i f i e r s i s u s u a l l y h i g h w h i l e  section,  The  input  the output impedance i s  low. The  s w i t c h can c o n s i s t o f e i t h e r a diode b r i d g e  I n r e c e n t work the FET  s w i t c h has  f a b r i c a t i o n and much s i m p l e r  or a FET  o f some s o r t .  been p r e f e r r e d because o f i t s ease o f  d r i v e requirements.  A r e p r e s e n t a t i v e paper d e s c r i b i n g the s t a t e o f the a r t o f such d i s c r e t e  -22-  sampling c i r c u i t s  i s t h a t by Givens [16].  He uses h i g h slew r a t e m o n o l i t h i c  b u f f e r a m p l i f i e r s and d i s c r e t e DMOS FET s w i t c h e s f o r h i s c i r c u i t , which i s p r i m a r i l y i n t e n d e d f o r a n a l o g - t o - d i g i t a l c o n v e r t e r systems. i s n o t as i m p o r t a n t as a c c u r a c y . 50 MHz  f o r a 2 V peak-to-peak  As such, speed  H i s d e s i g n a c h i e v e s a bandwidth o f about  input, but with high l i n e a r i t y ,  and low p e d e s t a l , which he terms h o l d - s t e p e r r o r .  low droop  rate  The low p e d e s t a l i s  a c h i e v e d by u s i n g a charge compensation c i r c u i t to s u p p l y the same amount o f charge t o the h o l d c a p a c i t o r as was  t r a n s f e r r e d to the s w i t c h .  The r e s t o f the paper d e s c r i b e s the t r a d e o f f s i n v o l v e d i n sample-and-hold d e s i g n and some o f the t e c h n i q u e s used to measure t h e i r  characteristics.  The advantage o f d i s c r e t e s o l i d s t a t e samplers i s t h e i r low c o s t s m a l l s i z e compared to m e c h a n i c a l ones.  and  The d i s a d v a n t a g e i s t h a t the  i n e v i t a b l e c i r c u i t p a r a s i t i c s w i l l t e n d to l i m i t the maximum speed to a few GHz,  although c i r c u i t s  o f t h i s bandwidth have n o t y e t been r e p o r t e d i n the  literature.  2.5.3  For  M o n o l i t h i c sample-and-hold  l a r g e volume a p p l i c a t i o n s ,  circuits  such as the sampling a m p l i f i e r  i n this project, monolithic c i r c u i t s  can be e x p e c t e d t o g i v e  envisioned  substantially  reduced c o s t as w e l l as i n c r e a s e d u n i f o r m i t y and p o t e n t i a l l y h i g h e r performance.  F o r h i g h speed a p p l i c a t i o n s , GaAs i s the semiconductor o f  c h o i c e due t o i t s h i g h e r e l e c t r o n m o b i l i t y r e l a t i v e to s i l i c o n .  Processing  t e c h n o l o g y i s much l e s s developed f o r GaAs, however, and much work needs done b e f o r e the f u l l p o t e n t i a l o f GaAs sample-and-hold c i r c u i t s  -23-  can be  to be  realized. The  e a r l i e s t paper d e s c r i b i n g a m o n o l i t h i c sample-and-hold was by  S t a f f o r d e t a l . [13] i n 1974.  They used s i l i c o n t e c h n o l o g y  and a f a i r l y  complex i n t e g r a t o r / f e e d b a c k system t o o b t a i n the medium speed, medium performance sample-and-hold c i r c u i t  shown i n f i g u r e 2.6.  Although  they do  not g i v e the speed performance, t h e i r quoted s e t t l i n g time was 1 jus, g i v i n g a maximum sampling The [17]  r a t e o f about 250 kHz.  f i r s t paper d e s c r i b i n g a m o n o l i t h i c sample-and-hold s w i t c h i s by Saul  i n 1980.  He used a quad r i n g o f MESFETs as a s w i t c h , b u t used an  e x t e r n a l h o l d c a p a c i t o r and no b u f f e r a m p l i f i e r s ,  f i g u r e 2.7.  U s i n g MESFETs  w i t h a 4 fj.m gate  l e n g t h and a 13 pF h o l d c a p a c i t o r S a u l was a b l e t o o b t a i n a  maximum sampling  r a t e o f 150 MHz.  parasitic  inductance  reasonable  t o expect  The major l i m i t i n g f a c t o r was the  a s s o c i a t e d w i t h the e x t e r n a l c a p a c i t o r . t h a t , u s i n g a submicron gate  pF m o n o l i t h i c h o l d c a p a c i t o r , a sampling  I t i s therefore  l e n g t h s w i t c h and a 1 o r 2  r a t e o f a t l e a s t an o r d e r o f  magnitude h i g h e r c a n be o b t a i n e d . In h i s s w i t c h d e s i g n S a u l uses a quad r i n g o f MESFETs, presumably based on the s t a n d a r d diode r i n g . mentary, the main r e a s o n feedthrough  However, s i n c e the MESFETs a r e n o t comple-  f o r using a ring  by u s i n g a b a l a n c e d  structure having  ( which i s t o reduce sample p u l s e  drive ) i s lost.  What remains i s a complex  the same c h a r a c t e r i s t i c s as a s i n g l e MESFET o f the same  geometry. A more r e c e n t paper d e s c r i b i n g a GaAs m o n o l i t h i c sample-and-hold  circuit  was p u b l i s h e d by B a r t a e t a l . i n 1983 [ 1 8 ] . They use a t r i p l e - g a t e MESFET s w i t c h w i t h an on-chip  metal-insulator-metal  -24-  ( MIM ) c a p a c i t o r f o l l o w e d by a  SUB  SWITCH  - IN + IN CLAMPS  OUT  ft  CHARGE CANCEL DEVICE  A  CONTROL  F i g u r e 2.6  HOLD  V  SWITCHING CIRCUIT  S i l i c o n m o n o l i t h i c sample-and-hold c i r c u i t e t a l . [13] ) .  -25-  ( after  Stafford  + BIAS  OUT  CONTROL  - BIAS Figure 2.7  GaAs monolithic sampling switch ( a f t e r Saul [17] ). -26-  feedback b u f f e r a m p l i f i e r t o minimize l o a d i n g e f f e c t s on the performance o f the sampler i t s e l f .  The use o f a t r i p l e - g a t e s w i t c h , w i t h the sample p u l s e s  a p p l i e d t o the c e n t r e gate and the o u t e r gates  grounded, was found to  s i g n i f i c a n t l y reduce sample p u l s e feedthrough t o the i n p u t and output.  They  r e p o r t e d an o v e r a l l 3dB bandwidth o f 1.1 GHz w i t h a maximum sampling r a t e o f 500 MHz. A more complex s w i t c h has been r e p o r t e d by H a r r o l d e t a l . [19] f o r use i n a switched 2.8,  c a p a c i t o r bandpass f i l t e r  IC.  uses d r i v e c i r c u i t r y which a l l o w s  t r a c k the i n p u t s i g n a l ,  Their c i r c u i t ,  shown i n f i g u r e  the gate o f the s w i t c h i n g FET t o  thus a l l e v i a t i n g the i n p u t v o l t a g e  swing  limitation.  They r e p o r t e d a maximum s w i t c h i n g speed o f about 1 GHz.  2.5.4  T h e o r e t i c a l a n a l y s i s and modeling o f h i g h speed sample-and-hold circuits  A number o f papers a l r e a d y d i s c u s s e d i n t h i s s e c t i o n c o n t a i n an a n a l y s i s or model o f the sampling p r o c e s s . a n a l y s i s o f samplers i n g e n e r a l .  Grove Riad  [14] g i v e s a s i m p l i f i e d  linear  [15] g i v e s a thorough model o f the  HP-1430A sampling head which i n l u d e s a n o n l i n e a r model f o r the s w i t c h i n g diodes.  H i s main o b j e c t i v e was t o o b t a i n the sampling head step  Other papers have d e a l t more w i t h the t h e o r e t i c a l a s p e c t s Blum [20] i n v e s t i g a t e s the e f f e c t s o f a p e r t u r e  response.  o f sampling.  time u s i n g F o u r i e r a n a l y s i s .  Wollman [21] does a s i m p l i f i e d a n a l y s i s o f the e f f e c t s o f n o n l i n e a r resistance, Finally,  showing t h a t t h i s w i l l Sonders  give r i s e to intermodulation  switch  distortion.  [22] d e f i n e s the parameters i n v o l v e d i n the dynamic  -27-  + BIAS  IN  HOLD  OUT  - BIAS  CONTROL  F i g u r e 2.8  GaAs m o n o l i t h i c sample-and-hold c i r c u i t e t a l . [19] ).  -28-  ( after  Harrold  performance o f h i g h speed sample-and-hold c i r c u i t s  and g i v e s a t r a n s f o r m e r  b r i d g e t e c h n i q u e f o r the measurement o f those parameters. In  c o n c l u s i o n , the l i t e r a t u r e  p u b l i s h e d to date p r o v i d e s some i d e a o f the  the  promise o f GaAs h i g h speed sampling c i r c u i t s ,  not  y e t been r e a l i z e d . The work b e i n g done a t the U n i v e r s i t y was  c o n t i n u e the development  although t h i s  promise has  o f h i g h - s p e e d m o n o l i t h i c sample-and-hold  d e s i g n e d to circuits,  b o t h i n terms o f p r o c e s s i n g and c i r c u i t c o m p l e x i t y and i n terms o f speed.  -29-  CHAPTER 3  3.1  DESIGN AND  SIMULATION  System requirements  I n o r d e r t o s p e c i f y the performance subsystems,  requirements o f the sampling  the system requirements o f the sampling a m p l i f i e r i t s e l f must  f i r s t be d e f i n e d .  A d e t a i l e d b l o c k diagram o f the sampling a m p l i f i e r i s  shown i n f i g u r e 3.1. o v e r a l l system,  The a n a l y s i s w i l l be d i v i d e d i n t o t h r e e s e c t i o n s :  the  the i n p u t network and the output network.  The e x t e r n a l parameters  o f i n t e r e s t f o r the o v e r a l l system are  g a i n , i n p u t impedance and output impedance.  Secondary  bandwidth,  c h a r a c t e r i s t i c s are power  h a n d l i n g c a p a b i l i t i e s , n o i s e and d i s t o r t i o n c h a r a c t e r i s t i c s . parameters  amplifier  These  are determined by s e v e r a l f a c t o r s such as sampling r a t e S and  sample p u l s e w i d t h W,  s p a c i n g between a d j a c e n t s w i t c h e s , i n p u t and output  impedances o f the s w i t c h e s and g a i n and bandwidth Typically,  o f the v i d e o a m p l i f i e r s .  i n d e s i g n i n g such a system one would f i r s t  p r i m a r y parameters: bandwidth  determine  B, g a i n A and system impedance Z . 0  maximum a l l o w a b l e sampling p u l s e w i d t h i s determined by the  the The  bandwidth  requirement,  W . * max  V2B  (3.1)  The sampling r a t e and the number o f channels N r e q u i r e d f o r complete r e c o n s t r u c t i o n o f the sampled  s i g n a l are r e l a t e d by  -30-  Figure  3.1  B l o c k diagram o f the sampling p r o p a g a t i o n times.  -31-  a m p l i f i e r showing the  critical  (3.2)  N = B/S  The  time d e l a y between a d j a c e n t channels  bandwidth.  T  s  i s a l s o dependant on the  I t i s g i v e n by  T  s  = 1/2B  (3.3)  I n p r a c t i c a l systems t h e r e w i l l a l s o be a d e l a y i n the sampling between a d j a c e n t channels  T  s e  =T  S  ± T  T  p  pulse  which r e s u l t s i n an e f f e c t i v e s i g n a l d e l a y o f  (3.4)  p  depending on whether the sampling  pulse i s t r a v e l l i n g  i n the same d i r e c t i o n  (-) as o r o p p o s i t e t o (+) the i n p u t s i g n a l . Thus, the bandwidth i s g i v e n by  B = V2T  (3.5)  s e  The v i d e o a m p l i f i e r bandwidth requirement i s  B  v i d e o  >  S/2  (3.6)  I t would appear t h a t , f o r a g i v e n i n p u t s i g n a l bandwidth, one c o u l d decrease  the v i d e o bandwidth requirement  channels  and d e c r e a s i n g the sampling  channels  i s l i m i t e d by t h e l o a d i n g o f the i n p u t and output networks on t h e i r  -32-  by i n c r e a s i n g the number o f  rate.  I n p r a c t i c e the number o f  respective delay  lines.  T h i s l o a d i n g c o n s i s t s o f t h r e e components,  l o a d i n g due t o the r e s i s t i v e component  o f the i n p u t and output  an ac l o a d i n g which i n c l u d e s the i n p u t and output r e a c t a n c e s  a dc  impedances,  and a p e r i o d i c  l o a d i n g due t o t h e d i s t r i b u t e d n a t u r e o f the i n p u t and output l i n e s .  In  the f o l l o w i n g d i s c u s s i o n the l o a d i n g e f f e c t s on t h e i n p u t l i n e w i l l be analyzed;  s i m i l a r e f f e c t s a l s o h o l d f o r t h e output  line.  The low f r e q u e n c y e q u i v a l e n t c i r c u i t o f the i n p u t l i n e i s shown i n f i g u r e 3.2, where R  R  eq  in  i s the i n p u t r e s i s t a n c e o f t h e sampling c i r c u i t , and  = R /N  The l o s s f o r t h i s c i r c u i t  L  (3.7)  in  i s g i v e n by  = 201og( 1 + Z N/2R  i n d c  0  in  )  dB  T h i s i s p l o t t e d i n f i g u r e 3.3 as a f u n c t i o n o f N f o r Z R  in  (3.8)  0  = 50 0 and  = 1 kO and 10 kQ. The ac l o a d i n g e f f e c t i s s i m i l a r t o t h e dc s i t u a t i o n , b u t now b o t h t h e  t r a v e l l i n g wave n a t u r e o f the i n p u t s i g n a l and the i n p u t c a p a c i t a n c e t a k e n i n t o account. f i g u r e 3.4.  The e q u i v a l e n t c i r c u i t  I n t h i s case t h e v o l t a g e  the l o s s i n c r e a s e s  f o r the ac case i s shown i n  o f the i n p u t s i g n a l d e c r e a s e s ( i . e .  ) as the s i g n a l t r a v e l s a l o n g  Assuming t h a t the t r a n s m i s s i o n the Nth sampling c i r c u i t  must be  the t r a n s m i s s i o n  line.  l i n e i t s e l f has n e g l i g i b l e l o s s the l o s s a t  i s g i v e n by  -33-  IN  R  Who  •AA/vV  1  (l)  -A/VW  1  (2)  1  (3)  (4)  (N-1)  1  Figure 3.2  (N)  Input delay l i n e low frequency equivalent c i r c u i t .  -34-  20  10  20  50  100  200  500  NUMBER OF CHANNELS  Figure 3.3  Input dc loss as a function of the number of channels: (a) R = 1 kfl, (b) R - 10 kfl. in  ln  -35-  1000  R IN 0  u  -WW-  I  HVWVi  1  (i)  'IN  rAWn  (2)  -K-  rAAAAn  (3)  -K-  T  rAA/vVi  F i g u r e 3.4  Input d e l a y l i n e h i g h frequency  -36-  1  (N)  equivalent c i r c u i t .  Lin..e<N) = 201og( 1 + HNZo|Y | ) dB  (3.9)  in  where Y  = 1/R  i n  in  + jwC . in  T h i s i s p l o t t e d i n f i g u r e 3.5 f o r R  in  = 10 kQ  and uC = I O . -4  The t h i r d form o f l o a d i n g i s due t o the p e r i o d i c n a t u r e circuit.  o f t h e sampling  I n t e r n a l r e f l e c t i o n s caused by the d i s c o n t i n u i t i e s o f the sampling  c i r c u i t s c a n i n t e r f e r e d e s t r u c t i v e l y t o g i v e n u l l s i n the t r a n s f e r characteristics. adjacent  T h i s w i l l be most severe when the e l e c t r i c a l l e n g t h between  channels approaches 9 0 ° . The e f f e c t o f p e r i o d i c l o a d i n g on the  t r a n s f e r c h a r a c t e r i s t i c s may n o t be as n o t i c e a b l e f o r s u b m u l t i p l e s but w i l l  still  appear i n the i n p u t and output  R e t u r n Loss = 201og| S  where S  li  i s the i n p u t  i±  ( i = l ) o r output  |  return loss,  o f 90°  d e f i n e d as  dB  (i=2) r e f l e c t i o n  (3.10)  coefficient.  P e r i o d i c l o a d i n g was s i m u l a t e d u s i n g the microwave a n a l y s i s program Touchstone.  A c h a i n o f 20 sampling c i r c u i t s connected by l o s s l e s s 50 O  t r a n s m i s s i o n l i n e segments was assumed; the sampling c i r c u i t s were m o d e l l e d as a p a r a l l e l c o m b i n a t i o n o f a 10 kfi r e s i s t o r and a 1 pF c a p a c i t o r , and the t r a n s m i s s i o n l i n e segments were chosen t o have an e l e c t r i c a l l e n g t h o f 45° a t 2 GHz.  The c a l c u l a t e d i n p u t r e t u r n l o s s and t r a n s m i s s i o n l o s s a r e shown  i n f i g u r e 3.6, the p e r i o d i c r i p p l e i n the r e t u r n l o s s and the n u l l i n the t r a n s m i s s i o n a t 4 GHz c a n be c l e a r l y  seen.  In o r d e r t o minimize l o a d i n g e f f e c t s i t i s c l e a r t h a t the i n p u t o f the i n p u t sampling c i r c u i t s and the output  -37-  impedance  impedance o f the output  Figure 3.5  Input ac loss as a function of channel p o s i t i o n . (a) R = 10 kfl, o>C = 10-2, (b) R = 10 kfl. C =10-* in  in  -38-  in  W  in  DB[S11] LINE  . DB[S2i] LINE  0.0000  1  LOSS,  dB  /S11 / Return loss  \  15.00  \A  AA A  \ Transinission loss  0.0000  Figure 3.6  3.000  FREQ-GHZ  Simulated return loss and transmission loss of the loaded input delay l i n e . -39-  6.000  sampling c i r c u i t s must be maximized, and t h a t the s i g n a l t r a n s m i s s i o n d e l a y T  s  must be kept l e s s than 90° a t the maximum i n p u t f r e q e n c y . The s i t u a t i o n a t the output i s s i m i l a r to t h a t d i s c u s s e d f o r the i n p u t .  I t i s , however, much more d i f f i c u l t impedance a m p l i f i e r s  to implement wideband, h i g h output  than h i g h i n p u t impedance a m p l i f i e r s .  The s i t u a t i o n i s  l e s s c r i t i c a l a t the output than a t the i n p u t s i n c e i t i s n o t n e c e s s a r y to f e e d a l a r g e number o f channels from one s o u r c e .  The l o s s mechanisms are  s i m i l a r f o r the i n p u t and the output, b u t to some e x t e n t the e f f e c t s  will  c a n c e l s i n c e the channel t h a t has the h i g h e s t l o s s a t the i n p u t w i l l have the lowest l o s s a t the output and v i c e v e r s a . I f the sampling p u l s e w i d t h i s l e s s than the t o t a l time r e q u i r e d f o r the sampling p u l s e to t r a v e l t o the a d j a c e n t channel, the a d j a c e n t s w i t c h to open and the output s i g n a l t o t r a v e l back to the f i r s t output s i g n a l w i l l state.  s w i t c h , then the  see the o t h e r switches o n l y i n t h e i r h i g h impedance  S i n c e t h i s i s p r e c i s e l y the c o n d i t i o n s p e c i f i e d i n e q u a t i o n s 3.1 and  3.5, no output b u f f e r a m p l i f i e r s are r e q u i r e d .  3.2  Buffer  amplifiers  B u f f e r a m p l i f i e r s a t the  sample-and-hold i n p u t s have two  functions.  They can be d e s i g n e d t o have a h i g h i n p u t impedance to reduce the l o a d i n g problems d i s c u s s e d i n the p r e v i o u s s e c t i o n , and they can be d e s i g n e d to have a low output impedance to decrease the time r e q u i r e d to charge capacitor.  In a d d i t i o n ,  the h o l d  they w i l l a l s o i s o l a t e the s i g n a l l i n e from the  sample p u l s e l i n e .  -40-  The b u f f e r a m p l i f i e r c o n f i g u r a t i o n o f f i g u r e 3.7 was chosen because o f i t s h i g h i n p u t impedance and because u n i f o r m i t y requirements.  the feedback o f Q  eases the p r o d u c t i o n  2  A m p l i f i e r s o f t h i s type have been d e s c r i b e d i n  [23] and have shown g a i n s o f 10 dB w i t h a 5 GHz  bandwidth.  A s i m p l i f i e d low f r e q u e n c y s m a l l s i g n a l e q u i v a l e n t c i r c u i t amplifier  i s shown i n f i g u r e 3.8.  The FETs a r e assumed t o be i d e a l and have  i d e n t i c a l transconductance g , zero b i a s c u r r e n t I sa  per u n i t gate w i d t h , and W  and I  A  Qi.  W I 3  Rearranged,  0  - W(  I  x  0  0  of  - W  3  I f W +W = W 2  m  in  and gate c a p a c i t a n c e C  0  + I  2  or  ) + W(  I  )/W  }I /g  2  0  + ^  )  (3.11)  t h i s gives  V ut = (( W  x  + g V  0  a r e the gate w i d t h and t o t a l c u r r e n t o f  L  A t low f r e q u e n c i e s , 13 = ^  o f the b u f f e r  3  2  - W  x  2  0  m  - ( W/W ) V x  2  (3.12)  i n  t h e r e w i l l be no dc o f f s e t and the a m p l i f i e r w i l l have a g a i n  -Wj/Wg independant  of transistor  transconductance.  The maximum output c u r r e n t i s determined by Q  4  and Q ; 5  i f these a r e  chosen t o have e q u a l w i d t h the a m p l i f i e r w i l l have a symmetrical c u r r e n t drive c a p a b i l i t y of W I . 4  because  0  W  4  cannot be i n c r e a s e d i n d e f i n i t e l y ,  the c o r r e s p o n d i n g i n c r e a s e i n gate c a p a c i t a n c e w i l l  frequency  however,  limit  the h i g h  response.  The d i o d e s a r e r e q u i r e d t o keep the gate o f Q output v o l t a g e i s n e g a t i v e .  4  r e v e r s e b i a s e d when the  S i n c e the t r a n s i s t o r s a r e assumed to be  -41-  VDD  Q3 W=100 jjm  IN  r-  1  Q4  I  W=100jJm  SZ  02  Q2 " — i W=49 jJ  Ql W=51JJm  OUT  h  Q5 W=100 jJm  V  F i g u r e 3.7  M o n o l i t h i c FET b u f f e r a m p l i f i e r ( a f t e r Hornbuckle e t a l . [23] ) .  -42-  ss  OUT  Figure 3.8  Buffer amplifier s i m p l i f i e d low frequency small signal equivalent c i r c u i t . -43-  identical,  t h e v o l t a g e a t the gate o f Q  4  must be e q u a l t o V / 2 .  The number  DD  and a r e a o f t h e d i o d e s a r e chosen such t h a t the v o l t a g e a t the source o f Q  4  i s n o t g r e a t e r t h a n about 0 . 5 V r e f e r r e d t o t h e gate a t t h e minimum output voltage.  This gives  M( V  d  + WIR 4  0  S  ) + |V  o u t j m i n  where M i s t h e number o f d i o d e s , V diode s e r i e s  d  | * V /2  (3.13)  DD  i s the diode v o l t a g e drop and R  s  i s the  resistance.  To o b t a i n a more e x a c t i d e a o f t h e t r a n s i e n t and h i g h f r e q u e n c y  response  c h a r a c t e r i s t i c s o f such a b u f f e r a m p l i f i e r the computer program MicrowaveSPICE was used t o s i m u l a t e t h e a m p l i f i e r . parameters  The FET and diode model  a r e d e r i v e d i n c h a p t e r 5, and the SPICE program l i s t i n g s a r e  g i v e n i n appendix A.  Two a n a l y s e s were performed,  a m p l i f i e r f r e q u e n c y response and one t o determine  one t o determine t h e the t r a n s i e n t  response  when d r i v i n g a c a p a c i t i v e l o a d .  The f r e q u e n c y response curve f o r a l i g h t l y  l o a d e d GaAs FET a m p l i f i e r  = 1 kfl ) i s shown i n f i g u r e 3.9. A t low  ( R  l o a d  f r e q u e n c i e s t h e a m p l i f i e r has a l o s s o f about 0.1 dB, a t h i g h e r f r e q u e n c i e s t h e r e i s about 3 dB peaking; t h i s  i s caused by the e f f e c t i v e decrease i n  n e g a t i v e feedback due t o t h e phase s h i f t  in Q  4  and t h e d i o d e s .  The 3 dB  bandwidth o f t h e a m p l i f i e r i s almost 10 GHz. The  s i m u l a t e d t r a n s i e n t response  i s shown t o g e t h e r w i t h t h e i n p u t s i g n a l  i n f i g u r e 3.10; t h e l o a d i n t h i s case i s a 1 pF c a p a c i t o r . that the a m p l i f i e r  I t c a n be seen  i s i n v e r t i n g w i t h r o u g h l y u n i t y g a i n ; the d i f f e r e n c e  between t h e p o s i t i v e and n e g a t i v e g a i n i s caused by t h e e x t r a  -44-  resistance  -45-  VOUT  VIN  HEAL  REAL  0.0000  Figure  5.0E-09  3.10  Simulated b u f f e r a m p l i f i e r t r a n s i e n t  -46-  TIME  response.  l.OE-OB  of  the diodes  r i n g i n g and  i n the s o u r c i n g h a l f c y c l e ( p o s i t i v e output v o l t a g e ) .  overshoot  are due  to the l i m i t e d bandwidth o f the a m p l i f i e r .  same a m p l i f i e r w i t h the l o a d i n c r e a s e d to 10 pF, a l s o i n c r e a s e d t e n times,  3.3  The  The 2.4. FET  sampling  a l l the i n p u t  w i l l be  s i n g l e gate  circuit,  times  showed almost no r i n g i n g .  s w i t c h over a diode  s w i t c h were g i v e n i n s e c t i o n  I n t h i s s e c t i o n the s w i t c h i n g c h a r a c t e r i s t i c s o f s i n g l e and  The  dual  gate  discussed.  s w i t c h i s shown s c h e m a t i c a l l y , w i t h  i n f i g u r e 3.11.  For a s y m m e t r i c a l l y  d r a i n t e r m i n a l s are i n t e r c h a n g e a b l e ; for  and  The  switch  advantages o f a FET  switches  The  i t s equivalent  designed  FET  the terms "source"  and  r e f e r e n c e o n l y , w i t h the s w i t c h i n p u t c o n s i d e r e d to be  the s m a l l s i g n a l l e v e l s used here the FET w i l l always be l i n e a r regime so t h a t the use  the source  and  " d r a i n " are used the s o u r c e .  For  o p e r a t i n g i n the  o f a r e s i s t a n c e to model the  source-drain  c o n d u c t i o n mechanism i s a p p r o p r i a t e . The  most important  s w i t c h c h a r a c t e r i s t i c i n the ON  s t a t e i s the  r e s i s t a n c e , which s h o u l d be minimized to minimize a q u i s i t i o n R e f e r r i n g to f i g u r e 3.11, given  i t can be  seen t h a t the s w i t c h ON  switch  time. resistance i s  by Ron = R  s  + Rch + R  For s e l f - a l i g n e d gate FETs, R resistance,  (3-14)  D  s  and R  the r e s i s t a n c e o f the n  +  -47-  D  c o n s i s t o f the ohmic c o n t a c t  l a y e r between the ohmic c o n t a c t and  the  F i g u r e 3.11 S i n g l e - g a t e MESFET s w i t c h : (a) schematic diagram, (b) ON s t a t e e q u i v a l e n t c i r c u i t , (c) OFF s t a t e e q u i v a l e n t c i r c u i t .  -48-  channel,  and  a s h o r t s e c t i o n o f channel t h a t i s not modulated by  The  c h a n n e l r e s i s t a n c e i s dependant on the g a t e - t o - c h a n n e l  for  s m a l l d r a i n and  o f the d r a i n and that V  and V  s  D  source v o l t a g e s  source v o l t a g e s .  doping p r o f i l e  are s m a l l and V =0, the channel r e s i s t a n c e can G  approximated by  gate.  v o l t a g e , where  the c h a n n e l v o l t a g e w i l l be For a u n i f o r m  the  the average and  assuming  be  [24] 1 R  -  ch  (L/W)  { 1 - 7( V / V bi  p  ) }-i  (3.15)  qN /ia D  where V  bi  i s the b u i l t - i n v o l t a g e o f the Schottky  o f f v o l t a g e o f the FET,  V  given  barrier, V  i s the  p  pinch-  by  = qN a /2e  (3.16)  2  p  D  and a i s the c h a n n e l t h i c k n e s s . geometry o f the FET, channel thickness.  In o r d e r to reduce R  ch  one  can change the  i n c r e a s e the doping c o n c e n t r a t i o n or i n c r e a s e The  latter  which, a s i d e from l o w e r i n g  two  the  a l s o i n c r e a s e the p i n c h - o f f v o l t a g e  the channel r e s i s t a n c e , a l s o makes the r e s i s t a n c e  l e s s s e n s i t i v e to v a r i a t i o n s i n c h a n n e l v o l t a g e . I n the OFF  s t a t e the most important  v a l u e o f the gate c a p a c i t a n c e s Assuming a g a i n t h a t V approximately  s  and V  D  C  and  C , GD  which must be  are s m a l l , the two  e q u a l and w i l l be  C  GS  c h a r a c t e r i s t i c o f the s w i t c h  given  G S * GD « «WL/2a  i s the  minimized.  capacitances  will  be  by  (3.17)  C  -49-  E q u a t i o n 3.17  a l s o assumes t h a t V  the gate v o l t a g e V  p  »  V bi  kT/q  and t h a t , i n the OFF  e q u a l s the t h r e s h o l d v o l t a g e  G  V. t  T h i s d e p l e t i o n c a p a c i t a n c e model assumes a one-dimensional d i s t r i b u t i o n under the gate.  state,  electric  field  In r e a l i t y , w i t h the s h o r t gate l e n g t h s used  h e r e , t h e r e w i l l be an a d d i t i o n a l f r i n g i n g c a p a c i t a n c e t o the s i d e s o f the d e p l e t i o n r e g i o n which can be q u i t e s i g n i f i c a n t . important w i t h s e l f - a l i g n e d gate d e v i c e s due r e g i o n s to the gate. w i t h gate b i a s due  T h i s w i l l be  especially  to the p r o x i m i t y o f the  n+  S i n c e t h i s l a t e r a l d e p l e t i o n w i d t h cannot v a r y much  t o the h i g h doping l e v e l s o f the n - r e g i o n , the +  gate c a p a c i t a n c e w i l l be l a r g e r than c a l c u l a t e d by e q u a t i o n 3.17 s e n s i t i v e to gate b i a s than one would expect u s i n g the s t a n d a r d dimensional d e p l e t i o n capacitance  total  and be  less  one-  formulas.  I t i s the gate c a p a c i t a n c e t h a t produces a sample-and-hold p e d e s t a l by f o r m i n g a c a p a c i t a n c e d i v i d e r w i t h the h o l d c a p a c i t o r ; i t can be reduced  by  d e c r e a s i n g the w i d t h or, to a l e s s e r e x t e n t , the l e n g t h o f the gate or by i n c r e a s i n g the channel t h i c k n e s s . The use o f a d d i t i o n a l gates to i s o l a t e the c o n t r o l s i g n a l from the i n p u t and output l i n e s was  f i r s t proposed by B a r t a e t a l . [18].  They used a  gate FET w i t h the c o n t r o l s i g n a l a p p l i e d to the c e n t r e gate and the o u t s i d e gates grounded to g i v e i s o l a t i o n to b o t h the i n p u t and the  triple  two output.  I n the p r e s e n t case a b u f f e r a m p l i f i e r i s assumed to p r o v i d e i s o l a t i o n to the i n p u t l i n e so t h a t a d u a l gate FET can be used.  The  d u a l gate FET used as a s w i t c h i s shown i n f i g u r e 3.12. r e s i s t a n c e i s g i v e n i n t h i s case  by  -50-  c o n f i g u r a t i o n of a The  switch  ON  OUT  IN  CONTROL CONTROL  (a)  I  IN  DEPLETION ° REGION o  ° DEPLETION o o REGION  o l  FL  RCH  i—OUT  k  GG  -vwv-  RCH W  W  S.I. GaAs (b) CONTROL OUT  IN  S.I. GaAs  (c) Figure 3.12 Dual-gate MESFET switch: (a) schematic diagram, (b) ON state equivalent c i r c u i t , (c) OFF state equivalent c i r c u i t . -51-  R  on  -  R  S  +  2 R  ch  +  R  D  +  (3.18)  ^GG  where R Q Q i s the unmodulated r e s i s t a n c e between the g a t e s .  Assuming  s p a c i n g s between the source and d r a i n and the gates, R Q Q w i l l be l e s s R  S  and R  D  than  because i t does n o t i n c l u d e a c o n t a c t r e s i s t a n c e component.  I n the OFF s t a t e the source and d r a i n c a p a c i t a n c e s o f the f i r s t be  equal  the same as f o r a s i n g l e gate FET.  The second FET w i l l  FET w i l l  a l s o have  c a p a c i t a n c e s a s s o c i a t e d w i t h i t which w i l l be l a r g e r than the OFF c a p a c i tances o f the f i r s t  FET s i n c e the gate v o l t a g e i s l e s s , and w i l l be  e s s e n t i a l l y c o n s t a n t assuming a g a i n t h a t the source and d r a i n v o l t a g e s remain e s s e n t i a l l y a t ground p o t e n t i a l . If  a s i n g l e and d u a l gate s w i t c h o f the same gate geometries a r e  compared one sees t h a t t h e ON r e s i s t a n c e o f the d u a l gate s w i t c h i s about double  t h a t o f the s i n g l e gate s w i t c h . The p e d e s t a l i s reduced  slightly for  the d u a l gate s w i t c h s i n c e the t o t a l h o l d c a p a c i t a n c e now i n c l u d e s the gate c a p a c i t a n c e s o f the second FET, w h i l e the OFF c a p a c i t a n c e o f the f i r s t FET remains the same as f o r the s i n g l e gate case.  In p r a c t i c a l a p p l i c a t i o n s  t h i s e f f e c t i s n e g l i g i b l e s i n c e the h o l d c a p a c i t o r i s u s u a l l y chosen t o be much l a r g e r than the gate c a p a c i t a n c e s .  The e x t r a channel  r e s i s t a n c e o f the  second FET does h e l p smooth the e f f e c t s o f p e d e s t a l b u t does n o t s i g n i f i c a n t l y reduce them, w h i l e s i g n i f i c a n t l y i n c r e a s i n g h o l d c a p a c i t o r charging The  time.  s i n g l e and d u a l gate FET switches were s i m u l u l a t e d u s i n g the  q u a d r a t i c GaAs MESFET model on Microwave SPICE, the i n p u t l i s t i n g s a r e g i v e n i n appendix A.  F o r comparison purposes the s i n g l e and d u a l gate FETs were  -52-  b o t h taken t o have the same gate w i d t h o f lOO/^m; the h o l d c a p a c i t o r was chosen t o be 1 pF i n b o t h c a s e s .  The sample p u l s e w i d t h was taken to be 100  ps w i t h a r e p e t i t i o n r a t e o f 100 MHz.  The t r a n s i e n t response o f the s i n g l e  gate s w i t c h i s shown i n f i g u r e 3.13 and o f the d u a l gate s w i t c h i n f i g u r e 3.14. I t c a n be seen t h a t the p e d e s t a l shows up as a s l i g h t n e g a t i v e o f f s e t i n the sampled s i g n a l which i s n e a r l y independant i s v e r y s i m i l a r i n magnitude i n b o t h c a s e s .  of signal l e v e l ,  The number o f c y c l e s  and which required  to r e a c h a s t e a d y s t a t e h o l d v o l t a g e i s g r e a t e r f o r the d u a l gate s w i t c h . The d u a l gate s w i t c h a l s o has a h i g h droop r a t e f o r l a r g e n e g a t i v e s i g n a l s which i s due t o c o n d u c t i o n o f the gate diode o f the second FET. In b o t h cases the a q u i s i t i o n time f o r p o s i t i v e s i g n a l s i s g r e a t e r than f o r n e g a t i v e s i g n a l s due t o the v a r i a t i o n o f R minimize  this effect,  DS  w i t h gate v o l t a g e .  To  the s w i t c h FET p i n c h o f f v o l t a g e s h o u l d be made as  l a r g e as i s c o m p a t i b l e w i t h o t h e r e x t e r n a l and i n t e r n a l c i r c u i t  parameters.  1.000  volts  0.0000  -1.000 0.0000  Figure 3.13  B.0E-08  TIME  2.0E-07  Simulated single-gate GaAs MESFET switch transient response.  -54-  1.000  volts  0.0000  -1.000 0.0000  Figure 3.14  B.0E-0B  TIME,  S  2.0E-07  Simulated dual-gate GaAs MESFET switch transient response.  -55-  CHAPTER 4  4.1  PROCESSING TECHNOLOGY FOR GaAs MESFETS and MMICs  Introduction  An important  a s p e c t o f MMIC f a b r i c a t i o n i s the c h o i c e o f a s u i t a b l e  f a b r i c a t i o n technology.  I n a g e n e r a l MMIC t e c h n o l o g y  the f o l l o w i n g steps are  used: -active layer -device  formation  isolation  -gate f o r m a t i o n and f i r s t -ohmic c o n t a c t  level metalization  formation  - p a s s i v e component f o r m a t i o n - p a s s i v a t i o n and p r o t e c t i o n -backside v i a h o l e p r o c e s s i n g . The  o r d e r may v a r y depending on the p a r t i c u l a r t e c h n o l o g y b e i n g used and  some c i r c u i t s may r e q u i r e a d d i t i o n a l s t e p s w h i l e o t h e r s may omit some. each s t e p t h e r e a r e s e v e r a l p o s s i b l e t e c h n o l o g i e s a v a i l a b l e ;  For  the c h o i c e  will  depend on the f i n a l use o f the MMIC, the equipment a v a i l a b l e and c o s t considerations.  The d i f f e r e n t p r o c e s s i n g s t e p s w i l l be d i s c u s s e d i n the  following sections. The  expected  r e d u c t i o n i n c o s t i s one o f the main reasons b e h i n d the  l a r g e amount o f i n d u s t r i a l r e s e a r c h i n t o GaAs MMICs, and the c h o i c e o f technology  d i r e c t l y e f f e c t s the c o s t i n s e v e r a l ways.  the equipment, the throughput  The c a p i t a l c o s t o f  and the a c h i e v a b l e l e v e l o f automation  d i r e c t l y determine the c o s t p e r wafer, and the u n i f o r m i t y o f the p r o c e s s  -56-  across  the wafer, and from wafer t o wafer, w i l l  higher  y i e l d o f course g i v i n g a lower c o s t p e r c h i p .  To  some e x t e n t  processing  t h e f i n a l use o f the MMIC w i l l a l s o determine the  technology.  F o r example, i f a c i r c u i t  s i g n a l l e v e l environment i t s h o u l d be o p t i m i z e d noise  i n p a r t determine the y i e l d , a  FETs t y p i c a l l y a r e b i a s e d  i s t o be used i n a low  f o r n o i s e performance.  Low  f a i r l y c l o s e t o p i n c h - o f f and have a  r e l a t i v e l y t h i n , l i g h t l y doped channel  [25] .  r e s i s t a n c e must be m i n i m i z e d w h i l e p a r a s i t i c  I n a d d i t i o n , gate p a r a s i t i c source and d r a i n  resistances  are n o t as important s i n c e the channel i s almost p i n c h e d o f f . Thus, important c h a r a c t e r i s t i c s o f a low n o i s e uniformly  technology are i t s a b i l i t y to  and r e p r o d u c i b l y produce a t h i n , l i g h t l y doped c h a n n e l and t o  a c h i e v e a low gate r e s i s t a n c e . On  t h e o t h e r hand, power a m p l i f i e r s r e q u i r e a r e l a t i v e l y t h i c k , h i g h l y  doped c h a n n e l t o g i v e a l a r g e p i n c h - o f f v o l t a g e , voltage  allowing  swing, and t o a l l o w a h i g h c u r r e n t d e n s i t y  r e s i s t a n c e i s no l o n g e r  a large  i n the c h a n n e l .  input Gate  c r i t i c a l b u t t h e source and d r a i n r e s i s t a n c e s  should  be m i n i m i z e d t o reduce power d i s s i p a t i o n and thus improve e f f i c i e n c y and reliability. The  most c r i t i c a l component i n an MMIC i s t h e MESFET.  i n v o l v e s t h e most p r o c e s s i n g the  smallest,  steps  This  and because the gate l e n g t h  and thus most d i f f i c u l t  i s because i t i s usually  t o reproduce, dimension on t h e c h i p .  S e c t i o n 4.2 g i v e s a review o f GaAS MESFET and MMIC f a b r i c a t i o n t e c h n o l o g i e s , w h i l e s e c t i o n 4.3 d e s c r i b e s  i n d e t a i l t h e s e l f - a l i g n e d gate t e c h n o l o g y  d e v e l o p e d a t t h e U n i v e r s i t y o f B r i t i s h Columbia f o r t h i s p r o j e c t .  -57-  4.2  Review o f GaAs MESFET f a b r i c a t i o n t e c h n o l o g i e s  The  s t a r t i n g p o i n t f o r a l l GaAs MESFET f a b r i c a t i o n t e c h n o l o g i e s i s h i g h  r e s i s t i v i t y s e m i - i n s u l a t i n g ( S.I. ) GaAs. a v a i l a b l e GaAs was ( HB and  grown a l o n g the <111>  ) t e c h n i q u e , b u t HB wafers  ( LEC  <100> a x i s .  HB  earliest  commercially  a x i s u s i n g the h o r i z o n t a l Bridgman  are i r r e g u l a r l y shaped which reduces  i n h i b i t s automated p r o d u c t i o n .  Czochralski  The  The more r e c e n t l i q u i d  ) technique a l l o w s c i r c u l a r wafers  and e a r l y LEC wafers  yield  encapsulated  to be grown a l o n g the  r e q u i r e d chromium i n the g a l l i u m  a r s e n i d e t o g i v e the h i g h r e s i s t i v i t y c h a r a c t e r i s t i c s . Chromium p i n s the b u l k Fermi  l e v e l a p p r o x i m a t e l y midway between the c o n d u c t i o n and  bands, thus g i v i n g the h i g h r e s i s t i v i t y c h a r a c t e r i s t i c s  [26].  valence  Recently,  improvements i n c r y s t a l growth t e c h n o l o g y have a l l o w e d undoped LEC GaAs to be made which e x h i b i t s h i g h r e s i s t i v i t y w i t h o u t thought  t h a t i n t h i s case the Fermi  the a d d i t i o n o f Cr.  l e v e l i s p i n n e d between the  and v a l e n c e bands by a t r a p p i n g l e v e l due  conduction  t o a c r y s t a l d e f e c t i n which As  atoms are l o c a t e d on Ga s i t e s i n the c r y s t a l l a t t i c e , defect  It is  the  A s G a  antisite  [26].  R e g u l a r LEC-grown wafers t y p i c a l l y 10  4  been produced  - 10  5  cm" . 2  show a f a i r l y h i g h number o f d i s l o c a t i o n s ,  R e c e n t l y , s o - c a l l e d d i s l o c a t i o n f r e e wafers  by doping the GaAs w i t h about 1% In which can reduce  d i s l o c a t i o n d e n s i t y t o l e s s than 10 cm" . 2  the  T h i s a p p a r e n t l y i n c r e a s e s the  f r a g i l i t y o f the wafers, however, thus p o t e n t i a l l y r e d u c i n g y i e l d ,  and i t i s  n o t y e t c l e a r to what e x t e n t d i s l o c a t i o n s a f f e c t d e v i c e performance.  -58-  have  4.2.1  Active layer formation  Once a wafer The  first  type has been s e l e c t e d , MESFETs and MMICs can be f a b r i c a t e d .  s t e p , which i s common t o a l l p r o c e s s e s , i s t h e f o r m a t i o n o f an n-  doped c h a n n e l l a y e r on the S.I. GaAs s u b s t r a t e . dopant  The most common n-type  i s S i , a l t h o u g h Se, S and Te a r e a l s o used.  The two methods used t o  form t h e n - l a y e r a r e e p i t a x y and i o n - i m p l a n t a t i o n . In  t h e case o f e p i t a x y , c r y s t a l l i n e GaAs o f the d e s i r e d doping l e v e l i s  grown on t h e s t a r t i n g wafer. deposited f i r s t ,  U s u a l l y a b u f f e r l a y e r o f h i g h p u r i t y GaAs i s  t h i s i s e s p e c i a l l y important i n t h e case o f Cr-doped  s u b s t r a t e s s i n c e Cr has t h e tendency  t o migrate i n t o t h e c h a n n e l ,  changing t h e d e v i c e c h a r a c t e r i s t i c s over time.  thus  Once t h e b u f f e r l a y e r i s  grown, t h e a c t i v e l a y e r i s d e p o s i t e d t o the d e s i r e d t h i c k n e s s . There a r e t h r e e types o f e p i t a x y t h a t a r e n o r m a l l y used: ( LPE ), vapour phase ( VPE ) and m o l e c u l a r beam ( MBE ). s t a r t i n g wafer The  l i q u i d phase I n LPE, the  i s p l a c e d i n a h o t s o l u t i o n c o n t a i n i n g Ga, As and t h e dopant.  s o l u t i o n i s then c o o l e d and the doped GaAs c r y s t a l i z e s o u t on t o the  wafer  [ 2 7 ] . I n VPE, gases c o n t a i n i n g compounds o f Ga and As a r e p a s s e d over  the h e a t e d wafer where they r e a c t and d e p o s i t on t o t h e wafer. o r g a n i c c h e m i c a l vapour are [28].  I n metal-  d e p o s i t i o n ( MOCVD ), o r g a n i c compounds o f Ga and As  used which a l l o w lower temperature  formation o f the e p i t a x i a l  layer  I n MBE, which i s the l a t e s t t e c h n o l o g y , e l e m e n t a l Ga, As and donor  i o n s a r e d e p o s i t e d on the wafer d i r e c t l y i n a h i g h vacuum environment. thin layers,  i n t h e o r d e r o f a few atomic l a y e r s ,  l a y e r c a n be doped i n d i v i d u a l l y ,  Very  can be d e p o s i t e d , and each  a l l o w i n g such d e v i c e s as M o d u l a t i o n Doped  -59-  FETs ( MODFETs ) to be f a b r i c a t e d [ 2 9 ] . In i o n - i m p l a n t e d f o r m a t i o n o f the a c t i v e l a y e r , s p e c i e s a r e a c c e l e r a t e d i n vacuum and implanted The  i o n s o f the dopant  i n t o the GaAs s u b s t r a t e .  doping p r o f i l e t h a t r e s u l t s may be c a l c u l a t e d u s i n g a model due to  L i n d h a r d , S c h a r f f and S c h i o t t m a t e r i a l i s amorphous.  [30] based  on the assumption  t h a t the t a r g e t  When c r y s t a l l i n e m a t e r i a l s , such as GaAs, a r e used  the wafer i s t i l t e d and r o t a t e d to p r e s e n t a "random e q u i v a l e n t " p r o f i l e to the i o n beam [ 3 1 ] . The doping p r o f i l e t h a t i s o b t a i n e d r o u g h l y f i t s a t r u n c a t e d g a u s s i a n curve, and w i t h t y p i c a l a c c e l e r a t i n g v o l t a g e s o f 50 t o 200 kV the doping peak occurs a t between 200 and 1500 A f o r S i i n t o GaAs. I f the random e q u i v a l e n t c o n d i t i o n i s n o t met the i m p l a n t e d through  i o n s can channel  the c r y s t a l l a t t i c e r e s u l t i n g i n a deeper implant which tends to be  q u i t e nonuniform.  T h i s would produce a l a r g e v a r i a t i o n o f t h r e s h o l d v o l t a g e  o f the MESFETs. I n a d d i t i o n t o the depth p r o f i l e o b t a i n e d w i t h i o n - i m p l a n t a t i o n t h e r e o c c u r s a c e r t a i n amount o f l a t e r a l movement known as s t r a g g l e . o f s e l e c t i v e i m p l a n t a t i o n ( see s e c t i o n 4.2.3  ) this w i l l  abrupt t r a n s i t i o n between the implanted and non-implanted Although  the doping p r o f i l e  I n the case  r e s u l t i n a nonregions.  f o r a s i n g l e implant i s r o u g h l y g a u s s i a n i n  shape i t i s , i n theory, p o s s i b l e to approximate many u s e f u l doping by u s i n g m u l t i p l e implants o f d i f f e r e n t doses and e n e r g i e s .  One can a l s o  use p h o t o r e s i s t o r o t h e r s u i t a b l e m a t e r i a l s to b l o c k the implant c e r t a i n areas o f the wafer.  profiles  from  I t i s thus, f o r example, p o s s i b l e t o f a b r i c a t e  b o t h low n o i s e and h i g h power FETs on the same c h i p by u s i n g two masks.  -60-  implant  When t h e GaAs i s implanted  the c r y s t a l l a t t i c e  i s s e v e r e l y damaged.  In  o r d e r t o r e p a i r the damage and a l s o t o a c t i v a t e the implant by a l l o w i n g the implanted  i o n s t o l o c a t e themselves  t r e a t e d , o r annealed.  on Ga s i t e s ,  t h e wafer must be h e a t  P r e s e n t l y the most common method t o do t h i s  i s to  h e a t t h e i m p l a n t e d wafer i n a f u r n a c e t o about 800 t o 850 °C f o r approximately  20 minutes.  A major problem w i t h heat t r e a t i n g GaAs i s t h a t t h e As s t a r t s t o v a p o r i z e a t temperatures  above about 500 °C.  T h i s o u t g a s s i n g changes the  s t o i c h i o m e t r y o f t h e c r y s t a l near t h e s u r f a c e and can s e v e r e l y degrade a c t i v e l a y e r performance. can be used.  I n o r d e r t o a v o i d t h i s problem s e v e r a l s o l u t i o n s  The s i m p l e s t i s t o e n c a p s u l a t e the wafer w i t h a  temperature-  s t a b l e d i e l e c t r i c t o c o n t a i n the As d u r i n g a n n e a l i n g ; b o t h S i N 3  are commonly used.  4  and S i 0  2  However, s i n c e the thermal c o e f f i c i e n t s o f expansion o f  these m a t e r i a l s a r e n o t matched t o t h a t o f GaAs, s t r e s s e s o c c u r d u r i n g a n n e a l i n g which reduce  t h e o v e r a l l a c t i v a t i o n and which a l s o r e s u l t i n  d i f f e r e n c e s i n performance f o r o t h e r w i s e  i d e n t i c a l FETs a l i g n e d a l o n g  d i f f e r e n t c r y s t a l o g r a p h i c axes [32]. I n t h e p a s t y e a r s s e v e r a l c a p l e s s f u r n a c e anneal systems have been developed  t h a t use an o v e r p r e s s u r e o f As gas near  outgassing.  t h e wafer t o p r e v e n t  The As gas i s u s u a l l y o b t a i n e d by p l a c i n g powdered InAs,  which  g i v e s a h i g h e r p a r t i a l p r e s s u r e than GaAs, i n a s p e c i a l boat which a l s o c o n t a i n s t h e wafer [33]. Another method o f c a p l e s s a n n e a l i n g uses two GaAs wafers contact  i n face-to-face  [34]. I n t h e o r y no o t h e r As sources a r e r e q u i r e d b u t s i g n i f i c a n t  outgassing can s t i l l  o c c u r near the edges o f the wafers,  -61-  thus  reducing  yield.  Use  p r e s s u r e has  o f proximate c o n t a c t a n n e a l i n g a l s o been r e p o r t e d  seen much i n t e r e s t i n the l a s t  i s the s o - c a l l e d r a p i d thermal anneal  system  wafer i s r a p i d l y h e a t e d u s i n g i n f r a r e d l i g h t , i n t e n s i t y tungsten f o r furnace  minutes or so n o r m a l l y annealing  [36,37,38].  f o r d u r a t i o n s o f a few used w i t h f u r n a c e  Here  than those  anneals.  the same token c h e m i c a l  Device  20  As  overout-  ions due  to  diffusion.  isolation  I n a d d i t i o n to the a c t i v e l a y e r f o r m a t i o n by one i n the p r e v i o u s  used  r e a c t i o n s with other m a t e r i a l s i s  minimized, as i s the r e d i s t r i b u t i o n o f the implanted  4.2.2  high-  In p r i n c i p l e t h i s r a p i d  s h o u l d a l l o w c a p l e s s anneals to be performed w i t h o u t  By  the  seconds r a t h e r than the  p r e s s u r e because the s h o r t times i n v o l v e d do not a l l o w s i g n i f i c a n t diffusion.  few  such as t h a t produced by  lamps, to temperatures s l i g h t l y h i g h e r  anneals but  over-  [35].  Another r e c e n t development t h a t has years  i n c o n j u n c t i o n w i t h As  o f the methods d e s c r i b e d  s e c t i o n an i s o l a t i o n step must be used so t h a t those  parts  o f the c h i p t h a t are not r e q u i r e d to be e l e c t r i c a l l y a c t i v e become, or remain, s e m i - i n s u l a t i n g . between t r a n s i s t o r s and t h r e e ways to a c h i e v e  T h i s i s r e q u i r e d b o t h to e l i m i n a t e i n t e r a c t i o n s to b u i l d h i g h q u a l i t y p a s s i v e components.  isolation:  s e l e c t i v e i o n - i m p l a n t a t i o n i n t o S.I.  i s o l a t i o n i m p l a n t a t i o n and mesa e t c h i n g , see f i g u r e With s e l e c t i v e i m p l a n t a t i o n an implant areas  4.1.  mask i s used to p r o t e c t  o f the wafer t h a t are to remain s e m i - i n s u l a t i n g from the  d u r i n g implant.  There are  A f t e r the implant  those  i o n beam  the mask i s s t r i p p e d o f f l e a v i n g the  -62-  GaAs,  DOPANT IONS  \ \\\ \\ \ ii I I J I I I J I I I . I I n j  i I*J  (a) ISOLATION IONS ^  ^  ^  I T T t . l l is.»i n . i r  ^  ^  ^  ^  • • «i.r* n . i i r j 7  \X*  X * X  > x x x  v %•%•••«  J  v V  y  *x* X  x X  * X \  K X 1 X  X  (b)  i  II.II  *.*••*  i^»y<|^n,»  Y«« •< *• • V ** • V *• * V \*  ••_•*  *»W V'J  1  • V *• • *•* •* • V  s  •  •* V  •  (0 _ X X X X XXX x  x* x  x" *  n-DOPED 6aAs  Figure 4.1  S.I. GaAs  X  " x »  GaAS  PHOTORESIST  Device i s o l a t i o n methods: (a) s e l e c t i v e ion-implantation, (b) i s o l a t i o n ion-implantation, (c) mesa etching.  -63-  d e s i r e d p a t t e r n [39]. An An  i s o l a t i o n implant must be performed  a f t e r the wafer has been  annealed.  implant mask i s a g a i n used b u t i n t h i s case i t c o v e r s the d e s i r e d a c t i v e  regions.  A h i g h dose, h i g h energy  c r y s t a l l a t t i c e elsewhere,  implant i s then performed  t o damage the  thus p r o v i d i n g the s e m i - i n s u l a t i n g p r o p e r t y [ 4 0 ] .  T y p i c a l i s o l a t i o n implant s p e c i e s a r e p r o t o n s , b o r o n and oxygen. implants c a n be used w i t h b o t h s e l e c t i v e and channel  implants but are not  n o r m a l l y used w i t h e p i t a x i a l wafers because o f the h i g h v o l t a g e s r e q u i r e d t o p e n e t r a t e the few microns  Isolation  accelerating  o f the e p i t a x i a l  layer.  In the case o f a mesa e t c h the a c t i v e l a y e r i s e t c h e d away from t h a t p a r t o f the c h i p t h a t i s t o become s e m i - i n s u l a t i n g .  S p e c i a l e t c h a n t s a r e used t o  o b t a i n s l o p i n g s i d e w a l l s which a l l o w continuous m e t a l i z a t i o n between the mesa and the e t c h e d s e c t i o n s [ 4 1 ] . The  advantage o f s e l e c t i v e i m p l a n t a t i o n and i s o l a t i o n i m p l a n t a t i o n i s  t h a t they a r e c o m p l e t e l y p l a n a r which s i m p l i f i e s  interconnect metalization.  S e l e c t i v e i m p l a n t a t i o n i s the s i m p l e r o f the two b u t t h e r e i s some evidence t h a t an i s o l a t i o n implant g i v e s b e t t e r i s o l a t i o n and reduces  backgating  [40], which i s the i n t e r a c t i o n o f the gate o f one t r a n s i s t o r on the I c h a r a c t e r i s t i c s o f o t h e r nearby d e v i c e s .  Backgating  D S  i s n o t so much o f a  problem f o r MMICs as i t i s f o r d i g i t a l ICs w i t h t h e i r much h i g h e r p a c k i n g density.  The advantage o f mesa e t c h i n g i s t h a t i t c a n be used  e p i t a x i a l wafers  and t h a t i t p r o v i d e s v e r y good  -64-  isolation.  with  4.2.3  The  Gate f o r m a t i o n  a c t i v e l a y e r f o r m a t i o n s t e p s are common to a l l FET p r o c e s s e s .  next s t e p s can o c c u r i n two t e c h n o l o g y b e i n g used. formed f i r s t  and  The  d i f f e r e n t o r d e r s , depending on the type o f  In the e p i t a x i a l p r o c e s s e s , ohmic c o n t a c t s are  the gate d e p o s i t e d l a t e r .  p r o c e s s e s , which a l l use  I n the s o - c a l l e d  self-aligned  i o n - i m p l a n t a t i o n f o r the a c t i v e l a y e r  the gate, o r sometimes dummy gate, i s d e p o s i t e d f i r s t implant mask f o r a second,  and a c t s as  h i g h dose, implant which i s used  source and d r a i n p a r a s i t i c r e s i s t a n c e s .  formation, an  to reduce  the  S i n c e the emphasis f o r the p r e s e n t  work has been on s e l f - a l i g n e d gate t e c h n o l o g i e s , gate f o r m a t i o n f o r b o t h types o f p r o c e s s e s w i l l be d i s c u s s e d f i r s t . In  principle,  i t s h o u l d be p o s s i b l e t o use a h i g h temperature  m a t e r i a l as an implant mask f o r the n - i m p l a n t .  The  +  w i t h s t a n d the h i g h temperatures  about 100 keV  i s used  p r o x i m i t y t o the n  +  f o r the n - i m p l a n t ,  regions.  +  significant  I f an implant energy  the gate w i l l be  of  i n very close  T h i s w i l l r e s u l t i n a v e r y low breakdown  v o l t a g e as w e l l as a v e r y h i g h gate f r i n g i n g c a p a c i t a n c e . [42] proposed  gate  gate must be a b l e to  o f the a n n e a l i n g c y c l e w i t h o u t  d e g r a d a t i o n o r i n t e r a c t i o n w i t h the GaAs c h a n n e l .  stable  u s i n g a high-energy  n  +  Yokoyama e t a l .  implant to move the doping peak deeper  i n t o the s u b s t r a t e and thus f u r t h e r away from the gate; a f l o w c h a r t o f t h e i r process  i s shown i n f i g u r e 4.2.  Although  t h i s does improve  c a p a c i t a n c e and breakdown c h a r a c t e r i s t i c s i t a l s o i n c r e a s e s the r e s i s t a n c e because the doping near the s u r f a c e i s low.  -65-  The  the  series  l a t e r a l straggle  \ \ \\\ \ CHANNEL IMPLANT  SEMI-INSULATING GaAs  ANNEAL  UWIIWIIlJUl  PHOTORESIST REFRACTORY 6ATE METAL DEPOSITION • M.11  ii.ii  * ••••• • • 4»r«  GATE DEFINITION ETCH  ttlHtt n  +  OHMIC IMPLANT  ANNEAL  n-DOPED 6aAs  M GATE METALIZATION  v +++ ++ +  im. P59 ++  n* -DOPED  Mi  OHMIC CONTACT DEPOSITION  68A8  ALLOYING  OHMIC CONTACT METALIZATION  F i g u r e 4.2  B u r i e d - c h a n n e l r e f r a c t o r y metal s e l f - a l i g n e d - g a t e ( a f t e r Yokoyama e t a l . [42] ).  -66-  process  i s a l s o i n c r e a s e d which l i m i t s how source and d r a i n n  +  Levy e t a l . [43]  s h o r t the gate can be made b e f o r e the  r e g i o n s s h o r t out the c h a n n e l . found a simple s o l u t i o n t o t h i s problem; a f l o w c h a r t o f  t h e i r p r o c e s s i s shown i n f i g u r e 4 . 3 .  A f t e r the channel implant has been  done the whole wafer i s c o v e r e d w i t h gate m e t a l .  A second l a y e r o f m a t e r i a l  i s d e p o s i t e d on top o f t h i s and p a t t e r n e d w i t h the gate mask. ( gate ) m e t a l  to have a slow r e a c t i o n r a t e w i t h the plasma s p e c i e s used  e t c h the gate m e t a l .  masking l a y e r .  bottom  i s then e t c h e d away u s i n g a plasma t e c h n i q u e , the top metal  h a v i n g been chosen to  The  The wafer i s o v e r - e t c h e d t o s l i g h t l y undercut  When the wafer i s now  i m p l a n t e d a g a i n f o r the ohmic c o n t a c t s  t h i s u n d e r c u t p r o v i d e s the n e c e s s a r y s e p a r a t i o n between the n - r e g i o n s +  the gate.  the  A f t e r i m p l a n t a t i o n the top metal  and  i s removed, u s u a l l y u s i n g wet  e t c h i n g t e c h n i q u e s , and the wafer i s annealed. Levy used TiW,  which i s r a p i d l y e t c h e d by f l u o r i n e - b a s e d plasmas, as  gate m e t a l and A l or N i as the implant mask. poor a d h e s i o n t o GaAs, and subsequent amongst o t h e r s .  The presence  workers have a l s o used WSi^  The  has  [44],  o f T i , w h i l e g r e a t l y improving adhesion, i s  thought by some t o degrade d e v i c e performance during annealing.  T h i s i s because pure W  the  by r e a c t i n g w i t h the GaAs  r e f r a c t o r y metal s i l i c i d e s  do n o t s u f f e r from  this  problem, b u t b o t h a d h e s i o n and S c h o t t k y gate c h a r a c t e r i s i c s are v e r y dependent on c h e m i c a l c o m p o s i t i o n , and they a l s o have a s l i g h t l y h i g h e r resistivity The  than the m e t a l l i c  compounds.  c h o i c e o f masking l a y e r depends on the r e q u i r e d s t o p p i n g power and  the d e s i r e d ease o f p r o d u c t i o n , p o t e n t i a l m a t e r i a l s b e i n g , amongst o t h e r s , A l , N i , Cr and p h o t o r e s i s t .  -67-  P h o t o r e s i s t i s the e a s i e s t to use  V Y V Y V V  V CHANNEL IMPLANT SEMI-INSULATING GaAs  ANNEAL PHOTORESIST REFRACTORY BATE METAL DEPOSITION GATE IMPLANT MASK DEFINITION  GATE IMPLANT MASK  GATE DEFINITION ETCH (WITH UNDERCUT)  ¥ V  Y  Y  V  Y  V  n-DOPED n OHMIC IMPLANT +  GaAs  STRIP GATE IMPLANT MASK  ANNEAL  T.W GATE METALIZATION  * +  l  +  +  +  J  ++ ++. +  +  |T -DOPED  y s\  w  + +  GaAs OHMIC CONTACT DEPOSITION ALLOYING OHMIC CONTACT METALIZATION  Figure 4.3  T-structure self-aligned-gate process ( a f t e r Levy et a l . [43] ).  -68-  but, b e i n g and  the l e a s t dense, has  Cr have much h i g h e r  and remove.  acceptable  A completely  implant  s t o p p i n g power.  s t o p p i n g powers but are more d i f f i c u l t  A l i s e a s i l y e v a p o r a t e d and  a c i d , and has  i s e a s i l y etched  Ni  to d e p o s i t  i n hydrochloric  s t o p p i n g powers f o r most a p p l i c a t i o n s .  d i f f e r e n t approach to s e l f - a l i g n e d gate MESFET  f a b r i c a t i o n was  taken by Yamasaki e t a l . [45].  the S e l f - A l i g n e d I m p l a n t a t i o n i n f i g u r e 4.4.  T h e i r technology,  called  o f N -Layer Technology ( SAINT ), i s shown +  A f t e r s e l e c t i v e i m p l a n t a t i o n o f the c h a n n e l n r e g i o n ,  wafer i s c o v e r e d (1500  the lowest  w i t h a m u l t i l a y e r r e s i s t c o n s i s t i n g o f PECVD S i N 3  A ) , bottom p h o t o r e s i s t (8000 A ) , s p u t t e r e d S i 0  photoresist.  The  top p h o t o r e s i s t i s p a t t e r n e d  2  4  (3000 A) and  f o r the n  the  top  r e g i o n s and i s  +  used as a mask f o r the f l u o r i n e - b a s e d r e a c t i v e i o n e t c h o f the S i 0 ,  after  2  which the bottom p h o t o r e s i s t i s o v e r - e t c h e d ion  e t c h to o b t a i n an undercut p r o f i l e .  are used as the n  +  The  2  t h i c k n e s s o f the f l a t areas  Si0  2  and  u s i n g the S i 0  alloyed. 2  remaining  p h o t o r e s i s t and  s i d e w a l l s are t h i n compared to  and are e a s i l y e t c h e d  the removal o f the remaining  ohmic windows are e t c h e d deposited  The  i n p l a n t , a f t e r which the wafer i s c o v e r e d w i t h  magnetron-sputtered S i 0 .  f o l l o w e d by  u s i n g an oxygen-based r e a c t i v e  through the S i 0 The  2  and  Si N 3  4  and  After  3  as an etchmask, and p a t t e r n and  the  A  HF,  annealing,  ohmic c o n t a c t s  l a s t step i s to e t c h the S i N  under the  are  gate  d e p o s i t the gate metal.  gate l e n g t h i s determined by the l e n g t h o f the bottom p h o t o r e s i s t a f t e r undercut etch, while determined by  the s e p a r a t i o n between the gate and  the n  +  - 6 9 -  was  The the  regions i s  the amount o f u n d e r c u t .  Another type o f s e l f - a l i g n e d technology  2  RF  away u s i n g b u f f e r e d  photoresist.  Si0  r e p o r t e d by Hagio e t a l .  V  11  V  SEMI-INSULATING GaAs  CHANNEL IMPLANT  DEPOSIT SILICON NITRIDE DEPOSIT BOTTOM PHOTORESIST —IT ! « - • • I I J I I I J I I I J I  H i l l J "  PHOTORESIST  SPUTTER SILICON 0I0XIDE  V »J%.»^«..'^V-J».V-.»«.£/ ,  ,  <  PATTERN TOP PHOTORESIST FOR n IMPLANT +  V VV V V V V  FIRST LAYER SILICON DIOXIDE  REACTIVE ION ETCH SILICON DIOXIDE WITH UNDERCUT OF BOTTOM PHOTORESIST n  T  IMPLANT  SECOND LAYER SILICON DIOXIDE  • • • ^ • • • «.  V*.. ••••  n-DOPED GaAs  SPUTTER SECOND LAYER SILICON DIOXIDE +  g ' y' A iVJ++ + +| + + 1  +  +  ETCH SECONO LAYER SILICON DIOXIDE SIDEWALLS  + ++  n -DOPED GaAs  REMOVE REMAINING PHOTORESIST ANNEAL + + + +  OPEN WINDOWS FOR OHMICS  SILICON NITRIDE  DEPOSIT OHMIC CONTACTS ALLOY  y % • + ++ +  METALIZATION  ETCH GATE WINDOW THROUGH SILICON NITRIDE DEPOSIT GATE METAL  Figure 4 . 4  OHMIC CONTACT  GATE METAL  Self-Aligned Implantation of N+-layer Technology ( SAINT ) process ( a f t e r Yamasaki et a l . [ 4 5 ] ) .  -70-  [46], a f l o w c h a r t o f t h e i r p r o c e s s i s shown i n f i g u r e 4.5. i m p l a n t a t i o n a dummy S i 0  2  After  channel  gate i s formed and then c o v e r e d w i t h plasma-  enhanced c h e m i c a l vapour d e p o s i t e d S i N . 3  The plasma d e p o s i t i o n causes the  4  n i t r i d e t o cover the s i d e s o f the gates as w e l l as the wafer s u r f a c e . the wafer i s then implanted,  the n  +  When  r e g i o n s a r e s e p a r a t e d from the dummy  gate by t h e t h i c k n e s s o f the n i t r i d e l a y e r .  A number o f s e l e c t i v e plasma  e t c h s t e p s a r e then done t o expose t h e GaAs where t h e dummy gates were located.  A n o n - c r i t i c a l p h o t o l i t h o g r a p h y s t e p a l l o w s the gate metal  d e p o s i t e d a f t e r which t h e the r e m a i n i n g masking l a y e r s a r e removed.  t o be As i n  the SAINT p r o c e s s , the main advantage o f t h i s p r o c e s s i s t h a t the gate need not w i t h s t a n d the h i g h a n n e a l i n g temperatures gate metal can be used. process  so t h a t a lower  resistivity  An advantage o f t h i s t e c h n o l o g y over the SAINT  i s t h a t t h e s e p a r a t i o n between the ohmic r e g i o n s and t h e gate i s  c o n t r o l l e d by a d e p o s i t i o n r a t h e r than by an undercut  etch, deposition being  p o t e n t i a l l y more u n i f o r m a c r o s s the wafer.  4.2.4  The  Ohmic c o n t a c t f o r m a t i o n  source and d r a i n c o n t a c t s o f an FET s h o u l d be n o n - r e c t i f y i n g and  have a s u f f i c i e n t l y low r e s i s t a n c e .  The n o n - r e c t i f y i n g  i s o b t a i n e d by h a v i n g a v e r y h i g h ( >10 the metal-semiconductor through  19  characteristic  cm" ) donor c o n c e n t r a t i o n near 2  i n t e r f a c e , a l l o w i n g the e l e c t r o n s t o t u n n e l  the v e r y narrow d e p l e t i o n r e g i o n [47].  Ohmic c o n t a c t r e s i s t a n c e c o n s i s t s o f two p a r t s :  the contact  r e s i s t a n c e o f the i n t e r f a c e and the sheet r e s i s t a n c e o f t h e semiconductor  -71-  \ \\\\\ \ CHANNEL IMPLANT  n *i.>i n.rr rt'rr n,ir iicvv-jr  K» •» • v  s • v • v *• • v v s •! -  SILICON DIOXIDE DUMMY GATE FORMATION  PECVD SILICON NITRIDE DEPOSITION AND PATTERNING  SEMI-INSULATING GaAs  PHOTORESIST  SILICON DIOXIDE  n IMPLANTATION r  ANNEALING  n-DOPED GaAs  NITRIDE ETCH + + ++ +  +  OHMIC CONTACT METALIZATION RESIST COATING  n -DOPED GaAs  RESIST PLASMA ETCH  DUMMY GATE REMOVAL  SILICON NITRIDE  OHMIC CONTACT METALIZATION GATE METAL EVAPORATION AND LIFT OFF  Figure 4.5  GATE METAL  Sidewall-assisted pattern inversion process ( after Hagio et a l . [46] ).  -72-  between the ohmic a r e a and the c h a n n e l .  C o n t a c t r e s i s t a n c e i s reduced  by  i n c r e a s i n g the c a r r i e r c o n c e n t r a t i o n a t the s u r f a c e , w h i l e sheet r e s i s t a n c e i s reduced by i n c r e a s i n g the c a r r i e r c o n c e n t r a t i o n o r by  effectively  i n c r e a s i n g the t h i c k n e s s o f the doped l a y e r . Ohmic c o n t a c t sheet r e s i s t a n c e r e d u c t i o n i s used w i t h b o t h and  i o n - i m p l a n t e d FETs.  epitaxial  E p i t a x i a l FETs use the gate r e c e s s technique  e t c h the channel to the d e s i r e d t o t a l doping l e v e l .  During  to  epitaxial  growth the e p i l a y e r i s made t h i c k enough to p r o v i d e the d e s i r e d low sheet r e s i s t a n c e .  S i n c e the channel  i s e t c h e d anyways i t i s a l s o  p o s s i b l e to grow a t h i n n - l a y e r on top o f the channel l a y e r to f u r t h e r +  decrease  sheet  resistance.  Most i o n - i m p l a n t e d FETs use a second,  h i g h dose implant t o decrease  sheet r e s i s t a n c e o f the ohmic c o n t a c t a r e a s .  T h i s can be  e i t h e r by u s i n g a s e p a r a t e implant mask o r by u s i n g one t e c h n i q u e s d e s c r i b e d i n the p r e v i o u s The  the  accomplished  o f the  self-aligned  section.  o t h e r component o f ohmic r e s i s t a n c e i s the c o n t a c t r e s i s t a n c e o f  the i n t e r f a c e between the ohmic metal and the semiconductor.  The  t e c h n i q u e used almost u n i v e r s a l l y w i t h GaAs i s to i n c l u d e a c e r t a i n amount o f n-type dopant i n the ohmic c o n t a c t m e t a l . and l i f t - o f f  evaporation  the ohmic c o n t a c t s must be a l l o y e d to a l l o w the dopant to  d i f f u s e i n t o the s u r f a c e o f the  GaAs.  S i n c e the d i f f u s i o n depth  v e r y h i g h s u r f a c e doping c o n c e n t r a t i o n can be The most commonly used procedure  N i i s o f t e n evaporated  i s small a  obtained.  i s to evaporate  AuGe ( 88-12% by weight ) which i s a l l o y e d a t 400 minutes.  After  a e u t e c t i c mixture  - 500  of  °C f o r about 2  on top o f the AuGe; i t a p p a r e n t l y a c t s  -73-  as a w e t t i n g  agent d u r i n g a l l o y i n g and r e s u l t s i n improved ohmic c h a r a c t e r -  i s t i c s as w e l l as g i v i n g a h a r d e r  and more d u r a b l e  surface.  another, t h i c k e r l a y e r o f Au i s o f t e n d e p o s i t e d t o f a c i l i t a t e During  After alloying wirebonding.  the a l l o y i n g c y c l e the ohmic m e t a l m e l t s and forms s m a l l bumps  on the s u r f a c e o f the c o n t a c t  ( see f i g u r e 4.10, page 88 ) .  the l a r g e r these bumps a r e the p o o r e r  In general,  the ohmic c h a r a c t e r i s t i c s w i l l be.  Kuzuhara e t a l . [48] r e p o r t e d an a l t e r n a t i v e technique  which does n o t  r e q u i r e an a l l o y i n g temperature above the AuGe e u t e c t i c p o i n t and which thus r e s u l t s i n a smooth s u r f a c e morphology.  The h i g h s u r f a c e donor  c o n c e n t r a t i o n was o b t a i n e d by i o n - i m p l a n t i n g S i a t a dose and energy o f >7xl0  13  cm"  2  and 150 keV r e s p e c t i v e l y .  thermal a n n e a l i n g  The implant  i s a c t i v a t e d by r a p i d  a t 1120 °C f o r 5 seconds u s i n g a S i O N x  y  encapsulant,  after  which AuGe-Ni c o n t a c t s a r e e v a p o r a t e d and l i f t e d o f f and the wafer i s briefly  4.2.5  h e a t e d t o 300 °C t o a c t i v a t e the c o n t a c t .  Passive  components  I n a d d i t i o n t o MESFETs, most MMICs w i l l a l s o r e q u i r e p a s s i v e The  different  1.3;  types  o f p a s s i v e components were b r i e f l y  this section w i l l  components.  discussed i n section  d i s c u s s the p r o c e s s i n g s t e p s r e q u i r e d t o f a b r i c a t e  them. Many p a s s i v e components c a n be made u s i n g e s s e n t i a l l y the same p r o c e s s i n g s t e p s as u s e d f o r MESFET f a b r i c a t i o n , a l t h o u g h  often apparently  redundant  s t e p s a r e added so as t o n o t compromise FET y i e l d o r c h a r a c t e r i s t i c s .  There  are two a d d i t i o n a l "components" t h a t a r e o f t e n used which r e q u i r e a d d i t i o n a l  -74-  processing  steps;  these are a i r b r i d g e s and b a c k s i d e v i a h o l e s .  are used where low inductors in  and  capacitance  crossovers  large gatelength  f i g u r e 4.6.  A first  power FETs.  are r e q u i r e d , The  such as  Airbridges spiral  f a b r i c a t i o n p r o c e s s i s shown  thick layer of photoresist i s patterned  h o l e s where the a i r b r i d g e w i l l c o n t a c t  the f i r s t  o f m e t a l i s then s p u t t e r d e p o s i t e d  a second p h o t o r e s i s t l a y e r i s used to  define  the a i r b r i d g e s .  The  a f t e r which the top p h o t o r e s i s t  l e a v i n g the f i n a l Via  holes  are used when low  wafer i s t h i n n e d and  200  /jm,  first  l a y e r o f p h o t o r e s i s t i s removed,  i n d u c t a n c e microwave grounds are r e q u i r e d i n  A f t e r a l l the t o p s i d e p r o c e s s i n g  i s done  the  from the b a c k s i d e to the f i n a l t h i c k n e s s , u s u a l l y between and  the b a c k s i d e i s p a t t e r n e d  and  a l i g n e r s are u s u a l l y used to a l i g n the back to the  etched.  With the p r o c e s s i n g components can be  steps  discussed  fabricated.  I n f r a r e d mask  front.  taken a f t e r t h i n n i n g because the t h i n wafers are v e r y  technologies  undesired  bridge.  m i c r o s t r i p based designs.  be  i s removed.  e l e c t r o - p l a t e d g o l d i s then used as an e t c h mask to remove the  s p u t t e r e d m e t a l , a f t e r which the  100  A thin layer  exposed s p u t t e r e d m e t a l i s e l e c t r o - p l a t e d w i t h  g o l d to about 1 fim t h i c k n e s s The  and  l a y e r metal.  to open  Great c a r e must fragile.  so f a r , a l l MMIC p a s s i v e  For most d e v i c e s  a choice  such as a v a i l a b l e equipment and  and  reliability,  cost.  active  of possible  e x i s t s w i t h the f i n a l d e c i s i o n b e i n g based on  r e q u i r e m e n t s such as t o l e r a n c e  and  circuit  and p r o d u c t i o n  constraints  R e s i s t o r s can be made e i t h e r by  s p u t t e r d e p o s i t i n g a t h i n f i l m r e s i s t i v e m a t e r i a l or by u s i n g n-doped GaAs. I n the implant  l a t t e r case a s e p a r a t e r e c e s s ( f o r ion-implanted  etch  ( f o r e p i t a x i a l wafers ) or  wafers ) i s o f t e n used to a l l o w  -75-  independent  Illlllllll  LUTJ  llllllllllllilll  STARTING WAFER WITH FIRST LEVEL METALIZATION  PATTERN SUPPORT PHOTORESIST  DEPOSIT THIN CONDUCTIVE LAYER  PATTERN BRIDGE PHOTORESIST  ELECTROPLATE Au BRIDGE CONDUCTOR  REMOVE PHOTORESIST  ETCH THIN CONDUCTIVE LAYER  I  1 GaAs WAFER  Figure 4.6  fflTTJJJ FIRST LEVEL METALIZATION  V////A  PHOTORESIST  THIN CONDUCTIVE LAYER  Airbridge f a b r i c a t i o n process.  -76-  GOLD AIRBRIDGE  o p t i m i z a t i o n o f FET channel parameters and r e s i s t o r c h a r a c t e r i s t i c s .  The  s p u t t e r e d r e s i s t o r r e q u i r e s s l i g h t l y more p r o c e s s i n g b u t c a n be more accurate  and u n i f o r m  and have a lower temperature c o e f f i c i e n t o f r e s i s t a n c e  than the semiconductor r e s i s t o r , which takes up l e s s C a p a c i t o r s can be made e i t h e r w i t h a p l a n a r using a metal-insulator-metal c a p a c i t o r i s more r e p e a t a b l e  space.  i n t e r d i g i t a t e d s t r u c t u r e or  ( MIM ) sandwich s t r u c t u r e . ( b u t much h a r d e r  The i n t e r d i g i t a l  t o model ), e a s i e r t o make  and has a h i g h e r y i e l d than the MIM c a p a c i t o r b u t i s l i m i t e d i n v a l u e t o about 1 pF. or T a 0 2  5  For l a r g e r values  an MIM c a p a c i t o r i s r e q u i r e d ; s p u t t e r e d  or plasma-deposited S i N 3  4  Si0  2  a r e the u s u a l d i e l e c t r i c s and an  a i r b r i d g e i s o f t e n u s e d t o connect the top p l a t e t o the r e s t o f the c i r c u i t to reduce the chance o f a s h o r t c i r c u i t a t the edge o f the c a p a c i t o r . Inductors  are e i t h e r simulated using a short length of high  l i n e o r made as a loop to access  4.3  M u l t i t u r n i n d u c t o r s r e q u i r e an a i r b r i d g e  the c e n t r e o f the i n d u c t o r , o r a v i a h o l e c a n be used i n the case  o f shunt elements. these  inductor.  impedance  Coupled i n d u c t o r s have a l s o been demonstrated u s i n g  techniques.  R e f r a c t o r y m e t a l s e l f - a l i g n e d gate MESFET f a b r i c a t i o n  The  r e f r a c t o r y m e t a l s e l f - a l i g n e d gate MESFET f a b r i c a t i o n  technology  technology  d e v e l o p e d a t the U n i v e r s i t y o f B r i t i s h Columbia i s c l o s e l y based on t h a t by Levy and Lee [43] and S a d l e r  [35]. The complete p r o c e s s  o f MESFET  f a b r i c a t i o n r e q u i r e s f i v e masks, w h i l e a s i x t h mask i s r e q u i r e d f o r the MIM c a p a c i t o r o f the sample-and-hold.  The UBC p r o c e s s  -77-  differs significantly i n  the wafer c l e a n i n g p r o c e d u r e s , the p h o t o l i t h o g r a p h y conditions.  steps  There a r e s e v e r a l o t h e r minor m o d i f i c a t i o n s  a plasma e t c h r a t h e r than a r e a c t i v e i o n e t c h mask and the c h o i c e o f implant  and the a n n e a l i n g such as the use o f  ( RIE ) t o u n d e r c u t the gate  dose and energy t o o b t a i n d e p l e t i o n mode  r a t h e r than enhancement mode FETs. A flowchart by  i s shown i n f i g u r e 4.7; a d e t a i l e d step  step d e s c r i p t i o n f o l l o w s i n t a b l e 4.1.  processing and  o f the MMIC p r o c e s s  The development o f t h i s  technology i s to a large extent  an e v o l u t i o n a r y p r o c e s s  e r r o r ; when a p a r t i c u l a r r u n does n o t y i e l d e x p e c t e d r e s u l t s  difficult  t o i s o l a t e the step t h a t caused the problem.  d e s c r i b e d here g i v e s reasonable main s t e p s  devices  of t r i a l  i t i s often  A l t h o u g h the process  i t i s by no means f u l l y mature.  The  t h a t c o u l d use improvement a r e d i s c u s s e d below, as a r e those t h a t  are n o t s e l f - e x p l a n a t o r y . Steps 1-2 Wafer c l e a n i n g The  wafers a r e r e c e i v e d a t UBC w i t h b o t h s i d e s p o l i s h e d .  i s done u s i n g a c o m b i n a t i o n o f c h e m i c a l  The p o l i s h i n g  and a b r a s i v e means.  The  r e s u l t i n g s u r f a c e damage, and a l s o p o s s i b l e s u r f a c e c o n t a m i n a t i o n , cause i n c o n s i s t e n t and poor r e s u l t s .  Therefore,  the s u r f a c e l a y e r s a r e  removed by e t c h i n g p r i o r t o subsequent p r o c e s s i n g . thoroughly  Step 1 i s used t o  degrease and c l e a n the wafer, immediately t h e r e a f t e r step 2 i s  used t o e t c h about 2 The  can  pirn  from the s u r f a c e  i n a slow and u n i f o r m manner.  same e t c h i n g s o l u t i o n i s a l s o used f o r the r e g i s t r a t i o n mark e t c h ,  a l l o w i n g the e t c h r a t e and hence the s u r f a c e e t c h depth t o be determined from the r e g i s t r a t i o n mark depth and e t c h  -78-  time.  V  VV  V Y Y V  CHANNEL  IMPLANT SEMI-INSULATING GaAs  PHOTORESIST  REFRACTORY  GATE  METAL DEPOSITION  GATE IMPLANT MASK DEFINITION  GATE  IMPLANT MASK  GATE DEFINITION ETCH (WITH UNDERCUT)  Y  Y  Y  Y  Y  Y  Y  rrrTTrnTira y s l v •» • Z* vViViii' n-DOPED  n  n OHMIC +  GaAs  IMPLANT  r T T T n T T J T T T j  STRIP GATE IMPLANT MASK  ANNEAL  TiW  GATE  METALIZATION  • :+++. rr -DOPED  r f F f r s  + +  • •••» V  6aAs + + +  OHMIC CONTACT DEPOSITION ALLOYING OHMIC CONTACT METALIZATION  ure 4.7  UBC refractory metal self-aligned-gate process flowchart. -79-  MESFET f a b r i c a t i o n  TABLE 4.1 STEP 1  DETAILED SELF-ALIGNED GATE PROCESS LOG DESCRIPTION  PROCESS * * * *  Wafer c l e a n i n g  etch  (=2 /zm)  1% Alconox s o l u t i o n (NaH P0 ) , 4 min DI r i n s e , 1 min, N blow d r y b o i l i n g acetone, 5 min b o i l i n g i s o p r o p a n o l , 5 min 2  4  2  * 2H 0 : 5NH 0H: 240H 0, 2 7 ° , 10 min * DI r i n s e , 30 s e c * b o i l i n g i s o p r o p a n o l , 5 min  2  Surface  3  Photoresist  4  R e g i s t r a t i o n mark exposure and develop  * 320 ran, 20 mWcnf , 30 s e c * spray develop, 30 sec ( 37 s e c i f chlorobenzene treatment used ) * DI r i n s e , 15 sec  5  R e g i s t r a t i o n etch  * 2H 0 : 5NH 0H: 240H 0, 2 7 ° , 30 s e c * DI r i n s e , 15 s e c  6  Strip photoresist  * b o i l i n g acetone, 5 min  7  Photoresist  8  Channel exposure  9  Light cleaning  deposition  2  2  4  2  * s p i n - o n S1400-30, 4000 rpm, 20 s e c * s o f t b a k e 95°, 25 min, cooldown 2  2  2  A  2  * b o i l i n g isopropanol, deposition  etch  * as i n step 3 * as i n step 4 * 1H 0 : 1NH 0H: 240H 0, 2 7 ° , 3 sec 2  10  Channel  11  Photoresist  12  * * * * * * *  implant  strip  Light cleaning  etch  5 min  * * * * * *  2  4  2  DI r i n s e , 15 sec 10% NH 0H, 1 min ( G a 0 removal ) BHF, 1 min ( A s 0 removal ) DI r i n s e , 10 min N blow d r y S i , energy=100 keV, dose=2.5xlO- cnT wafer o r i e n t a t i o n : 7° t i l t , 22° r o t a t i o n A  2  2  3  5  2  2 9  12  b o i l i n g acetone, 10 min " m i c r o s t r i p " , 9 0 ° , 5 min DI r i n s e , h o t , 15 s e c b o i l i n g acetone, 5 min b o i l i n g i s o p r o p a n o l , 5 min N blow d r y 2  * as i n step 9 -80-  2  13  Gate m e t a l d e p o s i t i o n TiW, 2000 A  * r f s p u t t e r d e p o s i t i o n , Ar 100 W, 33 mTorr, 22 min  14  Gate m e t a l p a t t e r n i n g and exposure  * * * *  15  Gate implant mask deposition  * evaporate  16  Liftoff  * b o i l i n g acetone,  17  Gate undercut  etch  S1400-30, 4000 rpm, 20 sec s o f t b a k e 95°, 25 min, cooldown immerse i n chlorobenzene, 2.5 min expose as i n s t e p 4 4400 A A l ( o r 3500 A Cr )  4  2  n patterning and exposure  * as i n steps  19  L i g h t cleaning etch  * as i n s t e p 9  20  N  *  21  Photoresist strip  22  A l removal  23  L i g h t cleaning etch  24  Si N encapsulent deposition  implant  agitation  2  18  +  gentle  * C F / 0 plasma, 100 W, 500 mTorr 120° CF = 200 seem, 0 •= 8 seem, 2 min 4  +  atmosphere,  2 8  Si,  100  3-4  keV,  lxl0 cnf 1 3  2  * wafer o r i e n t a t i o n as i n s t e p  3  * as i n step  11  * warm cone. HC1,  4  Implant  anneal  1  min  * as i n s t e p 9 * NH plasma p r e c l e a n , 5 min * plasma d e p o s i t i o n , 500 A, 300°, 100 1500 mTorr, He = 500 seem, S i H = 550 seem, NH = 3 7 . 6 seem 3  4  25  10  3  * M i n i b r u t e f u r n a c e , 825°, 1 -0/min N atmoshere  25  min  2  26  Si N  27  S i N p a s s i v a t i o n and capacitor d i e l e c t r i c deposition  * as i n step  24  28  Ohmic c o n t a c t p a t t e r n i n g and  * as i n step  14  29  3  3  4  removal  * 40% HF, 3 min, b u f f e r e d HF, * DI r i n s e , 10 min  4  exposure  Light cleaning etch  * as i n s t e p 9  -81-  1.5  min  W  30  Ohmic d e p o s i t i o n  * evaporate AuGe N i , 200 A  (88-12%), 2000 A,  31  Liftoff  * as i n s t e p 16  32  Alloy  * M i n i b r u t e f u r n a c e , 425°, 1 i / m i n N atmosphere 2  33  Ohmic g o l d and c a p a c i t o r top p l a t e p a t t e r n i n g and exposure  * as i n s t e p 14  34  Au d e p o s i t i o n  * evaporate  35  Liftoff  * as i n s t e p 16  -82-  2000 A Au  2 min,  Step 6  Photoresist s t r i p  A number o f d i f f e r e n t t e c h n i q u e s are used depending on the d i f f i c u l t y o f removal. the r e s i s t remover.  In most cases b o i l i n g acetone i s s u f f i c i e n t , but a f t e r implants i s damaged and r e q u i r e s the use o f 0  2  plasma o r  "microstrip"  There i s no apparent damage t o the GaAs by any o f these  methods.  Step 9 I t was  Light cleaning etch found t h a t the d e v i c e c h a r a c t e r i s t i c s are s t r o n g l y a f f e c t e d by  surface contamination.  any  The c l e a n i n g p r o c e s s used here removes about 50 A  from the s u r f a c e which does n o t s i g n i f i c a n t l y a l t e r the doping p r o f i l e even a f t e r r e p e a t e d a p p l i c a t i o n and i s o r g a n i c contaminant used b e f o r e each implant and each metal or n i t r i d e  Step 13  free.  It is  deposition.  Gate metal deposition  T h i s s t e p was  p r e v i o u s l y proceded by an i n s i t u Ar s p u t t e r e t c h o f the  GaAs b e f o r e d e p o s i t i o n .  The r e s u l t i n g poor a c t i v a t i o n i s thought to be  due t o the s u r f a c e s t o i c h i o m e t r y change caused by the l i g h t e r Ga atoms b e i n g more e a s i l y s p u t t e r e d t h a n As.  Step 14  Gate metal patterning and exposure  A chlorobenzene soak i s used here b e f o r e d e v e l o p i n g to remove the s o l v e n t s from the top l a y e r o f p h o t o r e s i s t .  The r e s u l t i n g h a r d e r top  l a y e r develops more s l o w l y than the r e s t o f the p h o t o r e s i s t so t h a t overhanging r e s i s t p r o f i l e r a t i o n t h i s overhang  i s obtained.  Step 16  D u r i n g subsequent m e t a l evapo-  ensures a d i s c o n t i n u i t y between the d e s i r e d  u n d e s i r e d m e t a l i z a t i o n areas which eases  Liftoff  -83-  an  liftoff.  and  I f necessary, but  a b r i e f immersion i n an u l t r a s o n i c b a t h can a i d l i f t o f f ,  i f overdone t h i s can a l s o remove the A l implant metal  desired Step 25  from the  areas. Anneal  O r i g i n a l l y two  anneals were done, one  a f t e r each implant, but b e t t e r  a c t i v a t i o n was  a c h i e v e d w i t h o n l y one  anneal a f t e r the i s o l a t i o n  The  implant.  a n n e a l i n g temperature i s r e l a t i v e l y low compared to c o n v e n t i o n a l  f u r n a c e anneals  to minimize i n t e r a c t i o n s between the TiW  f a i r b i t o f e x p e r i m e n t a t i o n was  done u s i n g r a p i d thermal  and the GaAs. annealing,  and  although  the b e s t runs gave b e t t e r a c t i v a t i o n s than the b e s t  furnace  anneals,  the r e s u l t s were not r e p r o d u c i b l e from run to run.  T h i s might  be  a t t r i b u t a b l e to the use o f wafers from d i f f e r e n t s u p p l i e r s and  d i f f e r e n t b o u l e s , and s i n c e r a p i d thermal p o t e n t i a l l y s u p e r i o r i t warrants Step 27  Si N 3  4  p a s s i v a t i o n and  a n n e a l i n g seems to be  further investigation.  capacitor d i e l e c t r i c deposition  A s e p a r a t e n i t r i d e l a y e r i s used r a t h e r than the a n n e a l i n g cap  to  minimize the p r o b a b i l i t y o f p i n h o l e s h o r t s . Step  32  Ohmic c o n t a c t  Some work was technique anneal  The  alloying  done to i n v e s t i g a t e the use o f the r a p i d thermal  to a l l o y the ohmic c o n t a c t s .  As  i n the case o f the  anneal channel  t h i s i s p r o m i s i n g b u t needs more i n v e s t i g a t i o n .  sample-and-hold mask s e t l a y o u t i s shown i n f i g u r e 4.8.  c o s t , t h r e e mask l a y e r s were put on each mask so t h a t o n l y one rows on the wafer c o n t a i n s u s e f u l d e v i c e s .  -84-  The bottom row  To  reduce  out o f three  of f i g u r e  4.8  A  c o n t a i n s the i n p u t b u f f e r a m p l i f i e r , and  the output b u f f e r a m p l i f i e r .  and d u a l gate t r a n s i s t o r s ,  a d u a l gate  s w i t c h , an MIM c a p a c i t o r  On the top row t h e r e a r e d i s c r e t e s i n g l e  a diode and a c a p a c i t o r f o r t e s t i n g purposes.  photomicrograph o f the c h i p i s shown i n f i g u r e 4.9, an SEM c l o s e u p gate  FET a f t e r removal o f the n i t r i d e  l e n g t h s a r e about 0.5  Lim  w i t h about 4  i s shown i n f i g u r e 4.10. Lira  nonuniform t e x t u r e o f the ohmic c o n t a c t s i s a l s o v i s i b l e .  -85-  o f a dual  The gate  s p a c i n g between the g a t e s .  A  The  Ed <  co  Eb Eb 03 Et] — tI E- Eb  EEd Eb CO Ed  <  a.  as  _2  E- 0*  o«* Ed  a o  X  o E»—i 3 CO  o  w  — i i o  E<  s: a,  — i i «C £  <c a  U  D a Ed Eb a O Ed CQ i-t Eb E- i-t  Ed E4 O Ed E_] Ed O EL, Z  .-. CO  a, a.  CO »  Z  X  Figure 4.8  Sample-and-hold mask layout.  -86-  X  F i g u r e 4.9  Photomicrograph o f sample-and-hold  -87-  chip.  I  5  F i g u r e 4.10  1  ym  Scanning e l e c t r o n micrograph o f d u a l gate MESFET.  -88-  CHAPTER 5  5.1  MEASUREMENT TECHNIQUES AND RESULTS  Introduction  The  measurement o f d e v i c e parameters and performance i s a v i t a l and non-  t r i v i a l p a r t o f the development o f a p r o c e s s i n g t e c h n o l o g y chapter  t h e measurement t e c h n i q u e s  be d i s c u s s e d and r e s u l t s The  [49].  In this  used t o e v a l u a t e d e v i c e performance w i l l  presented.  measurements used c a n be d i v i d e d i n t o two c a t e g o r i e s , low frequency  or s t a t i c measurements which g i v e i n f o r m a t i o n about the the i n d i v i d u a l d e v i c e model parameters, and microwave measurements which g i v e about the h i g h frequency  information  c h a r a c t e r i s t i c s o f the d e v i c e as a whole.  If  measurements and modeling a r e c a r r i e d out c o r r e c t l y t h e r e s h o u l d be good correspondence between the low frequency The  and the h i g h frequency  emphasis i n t h i s t h e s i s i s on low frequency  results.  measurements.  The reasons  f o r t h i s c a n be summarized as f o l l o w s - a v a i l a b i l i t y o f t e s t equipment -ease o f wafer s c a l e t e s t i n g -ease o f i s o l a t i n g d e v i c e parameters -can be done a t d i f f e r e n t p o i n t s i n the f a b r i c a t i o n Two c a t a g o r i e s o f low frequency citance versus voltage S c h o t t k y b a r r i e r diodes  measurements c a n be d i s t i n g u i s h e d .  Capa-  ( CV ) measurements c a n be made o f r e v e r s e b i a s e d t o o b t a i n doping p r o f i l e s .  ( IV ) measurements c a n be made o f diodes current,  process.  Current versus  voltage  to obtain reverse s a t u r a t i o n  i d e a l i t y f a c t o r and b a r r i e r h e i g h t , and o f t r a n s i s t o r s t o o b t a i n  -89-  s a t u r a t e d c u r r e n t , t h r e s h o l d v o l t a g e , t r a n s c o n d u c t a n c e and source and d r a i n resistance.  I n the f o l l o w i n g s e c t i o n s the t e c h n i q u e s used t o make these  measurements w i l l be p r e s e n t e d .  5.2  Diode measurements  The most important a p p l i c a t i o n o f diode measurements i s t o determine the q u a l i t y o f the c h a n n e l anneal s t e p . r e f r a c t o r y metal-based  T h i s i s p a r t i c u l a r l y important i n a  s e l f - a l i g n e d gate t e c h n o l o g y s i n c e the gate i s  p r e s e n t d u r i n g the anneal and can p o t e n t i a l l y r e a c t w i t h the GaAs. CV measurements u s i n g a HP4061A LCR meter c o n t r o l l e d by a HP9816 computer are performed active layer.  on l a r g e a r e a diodes t o determine The doping p r o f i l e N (W)  the doping p r o f i l e o f the  i s o b t a i n e d by measuring the  D  c a p a c i t a n c e a t d i f f e r e n t b i a s l e v e l s and a p p l y i n g the f o l l o w i n g f o r m u l a s . The c a p a c i t a n c e p e r u n i t a r e a i s  C(V) = e/W(V)  (5.1)  where W(V) i s the d e p l e t i o n w i d t h a t b i a s v o l t a g e V, and  N (W) = ( -2/q€ ){ d ( l / C ) / d V } 2  (5.2)  _1  D  T h i s method o f o b t a i n i n g the doping p r o f i l e b i a s on the d i o d e .  i s l i m i t e d t o a s m a l l forward  I f the b i a s i s i n c r e a s e d too much the r e s u l t i n g c u r r e n t  makes a c c u r a t e d e t e r m i n a t i o n o f the c a p a c i t a n c e i m p o s s i b l e .  -90-  Accurate  d e t e r m i n a t i o n o f the doping p r o f i l e near the s u r f a c e i s thus n o t p o s s i b l e with t h i s technique. the " b e s t f i t "  A t y p i c a l doping p r o f i l e  i s shown i n f i g u r e 5.1. w i t h  LSS p r o f i l e c a l c u l a t e d u s i n g a program w r i t t e n by D a v i d H u i .  Diode IV measurements a r e made u s i n g the HP4145A semiconductor analyzer.  parameter  The parameters o f i n t e r e s t a r e the i d e a l i t y f a c t o r n, the r e v e r s e  s a t u r a t i o n c u r r e n t I , the S c h o t t k y b a r r i e r h e i g h t <j>  h  0  resistance R . s  and the diode  series  The b a s i c diode e q u a t i o n , n e g l e c t i n g R , i s s  I(V) = I [ exp( qV/nkT ) - 1 ] 0  (5.3)  For V > ~ 3nkT/q the f a c t o r 1 can be n e g l e c t e d , and t a k i n g the n a t u r a l l o g a r i t h m o f b o t h s i d e s and d i f f e r e n t i a t i n g w i t h r e s p e c t t o V g i v e s  d l n ( I ) / d V = qV/nkT + l n ( I ) 0  (5.4)  P l o t t i n g l n ( I ) v e r s u s V y i e l d s a s t r a i g h t l i n e f o r a l i m i t e d range o f V, the s l o p e o f which i s p r o p o r t i o n a l t o 1/n and the y - i n t e r c e p t o f which i s I , 0  which c a n be used  to o b t a i n  <f>  h  from  <f> = ( kT/q ) l n ( A**T S/I 2  h  0  )  (5.5)  where where A** = 8.4 Acm" K" i s the e f f e c t i v e R i c h a r d s o n c o n s t a n t f o r GaAs 2  2  and S i s the a r e a o f the diode [ 3 5 ] . A t y p i c a l diode IV p l o t o b t a i n e d w i t h the HP4145A i s shown i n f i g u r e 5.2. The  a n a l y z e r i s programmed t o c a l c u l a t e n d i r e c t l y t o f a c i l i t a t e measuring a  -91-  Figure 5.1  Typical capacitance/voltage doping p r o f i l e .  -92-  LNI  ) CURSOR ( MARKER (•  3400V . •296E-03 2300V . •491E-03  6.356mA ) •5.940nA )  IF  (mA)  10.00  119.71 E-03 j  1.000 /div  48.47 /div  -604.4 -.5000 LINEl! LINE2J  .0000 2.000  2500/div ( V) 1/GRAD j Xintercept| Yinterceptj 911EHD3_j 1_. 10_E+00i 666E-03 [ -606E-03 1 " 1 " " ""-]  LNI  Figure 5.2  ( )  26E-3*LN (ABE (I) )  T y p i c a l diode current/voltage p l o t .  -93-  l a r g e number o f d e v i c e s . a l i g n e d gate  T y p i c a l l y , n ~ 1.1  f o r r e f r a c t o r y metal  self-  devices.  As the v o l t a g e i s i n c r e a s e d the l i n e a r dependance o f l n ( I ) on V down due  to the presence  o f the p a r a s i t i c s e r i e s r e s i s t a n c e R .  breaks  As  s  the  v o l t a g e i s i n c r e a s e d the v o l t a g e drop a c r o s s the r e s i s t a n c e dominates the drop a c r o s s the diode so t h a t a p l o t o f I v e r s u s V g i v e s another l i n e with slope  5.3  straight  1/R . S  T r a n s i s t o r measurements  A c c u r a t e measurement o f t r a n s i s t o r parameters i s important  to study  the  e f f e c t s o f changes i n p r o c e s s i n g s t e p s and to a l l o w r e a l i s t i c m o d e l l i n g l a r g e r s c a l e c i r c u i t s to be  of  performed.  The MESFET model used i n the s i m u l a t i o n s i n t h i s t h e s i s i s a symmetric square  law model, w i t h the gate-source  and g a t e - d r a i n j u n c t i o n e f f e c t s  by a S c h o t t k y diode model [50], the g e n e r a l e q u i v a l e n t c i r c u i t f i g u r e 5.3.  The  diode parameters I , n and <j>  discussed i n section  b  0  i s shown i n  can be o b t a i n e d i n the manner  5.2  Because o f the s m a l l gate a r e a o f microwave t r a n s i s t o r s  i t i s not  p o s s i b l e to d i r e c t l y o b t a i n a c c u r a t e gate c a p a c i t a n c e measurements. c a p a c i t a n c e s can be measured on s o - c a l l e d f a t FETs which can have l e n g t h s and widths o f 100 firn or more. measured w i t h the source  The  Gate  gate  z e r o b i a s gate c a p a c i t a n c e i s  and d r a i n t i e d t o g e t h e r and y i e l d s a d e p l e t i o n  capacitance per u n i t area. transistor  given  Since w i t h a s e l f - a l i g n e d gate p r o c e s s  i s p h y s i c a l l y the same on b o t h  -94-  the source  and  the  the d r a i n s i d e ,  the  Figure 5.3  Symmetric MESFET model equivalent c i r c u i t ( a f t e r Curtice et a l . [50] ). -95-  zero b i a s gate-source  and g a t e - d r a i n c a p a c i t a n c e s s h o u l d a l s o be the same  and can be o b t a i n e d from the f a t FET v a l u e s by m u l t i p l y i n g by the gate As mentioned i n s e c t i o n 3.3,  area.  f o r s m a l l gate l e n g t h t r a n s i s t o r s t h e r e  a l s o be a s i g n i f i c a n t f r i n g i n g c a p a c i t a n c e from the edges o f the gate; i s shown s c h e m a t i c a l l y i n f i g u r e 5.4,  d e p l e t i o n r e g i o n i s d i v i d e d i n t o two dimensional formulas  regions.  regions  +  [51].  Region I i s the  and  The one-  r e g i o n under the gate, the s t a n d a r d d e p l e t i o n c a p a c i t a n c e  are assumed to h o l d h e r e .  Region I I c o n s i s t s o f two  c i r c u l a r r e g i o n s on e i t h e r s i d e o f the gate, w i t h r a d i u s W, d e p l e t i o n w i d t h o f r e g i o n I.  W = J{  Q  =  ( 2e/qN  " I  )( V  D  - V - kT/q  bi  ) }  2  D  D  quarter-  where W i s the  Then,  4qN 7rW  qN LW +  ^TOTAL  E q a t i o n 5.7  this  assuming a u n i f o r m doping p r o f i l e  i g n o r i n g the p r o x i m i t y o f the source and d r a i n n  will  5Q/aV  | -  e(  L/W  +  Tr  )  cm  (5.5)  C  (5.6)  Fern"  (5.7)  2  g i v e s the t o t a l gate c a p a c i t a n c e per u n i t gate width,  the t r a n s i s t o r i s assumed to be symmetric, the d r a i n and source w i l l b o t h be g i v e n by C  T 0 T A L  /2.  The  and,  since  components  z e r o b i a s source and d r a i n c a p a c i t a n c e s  r e q u i r e d by the model are then g i v e n by  CGSO  =  C  G  D  0  =  7(  qN eL /8V 2  D  -96-  bi  ) + Tre/2  Fern"  1  (5.8)  GATE  p e r cm o f gate w i d t h .  The f i r s t  term can be o b t a i n e d from  diode o r f a t FET d a t a so t h a t no d e t a i l e d knowledge o f the doping p r o f i l e i s required. The FET c h a n n e l c u r r e n t i n the s a t u r a t i o n regime c a n be m o d e l l e d by  I  where V  DS  "  K  (  V  GS  "  V  T  ) (  +  1  2  V  D S  ) (  T  A  N  « DS  H  )  V  (  5  -  9  )  i s t h e t h r e s h o l d v o l t a g e , and K, A and a depend on the d e v i c e  T  geometry and semiconductor parameters versus V  G S  well.  T  V  A  asymptote  i s shown i n f i g u r e 5.5.  [47,50].  It fits  A typical plot of , / l  D S  the l i n e a r a p p r o x i m a t i o n q u i t e  i s d e f i n e d as the x - a x i s i n t e r c e p t o f the q u a d r a t i c r e g i o n and K i s g i v e n by the square o f i t s s l o p e .  in  the l i n e a r regime  It  c a n be determined from the s l o p e o f I  a =  The v a r i a t i o n o f I  i s c o n t r o l l e d by the h y p e r b o l i c tangent parameter a.  A I  D  S /  A  D S  f o r small V  D S  as  D S  V  (5.10) K-V  2 T  V = 0, V GS  D S  The c h a n n e l l e n g t h m o d u l a t i o n parameter  «  V _ D S  s a t  A i s o f t e n used i n computer  s i m u l a t i o n programs t o account f o r the s m a l l s l o p e o f I s a t u r a t i o n regime;  D S  D S  versus V  D S  i n the  i t can be e v a l u a t e d from  AI /AV DS  DS  (5.10)  A = K-V  2 T  v = o, v > V GS  DS  DS  t  The measurement o f source and d r a i n r e s i s t a n c e s i s more c o m p l i c a t e d  -98-  if A) CURSOR (-2.4200V MARKER (-3.0000V  16.6E-03. 2.80E-03,  124.0 E-03  12.39 /div  1580 -3.440 LINE1 LINE2  GRAD 32.1E-03 SQBT  Figure 5.5  VG  4300 ( V) .4,300/div Xintercept Yintercept 1/GRAD 31.1E+00 -2.94E+00 94.3E-03  (/A) - / I S  T y p i c a l p l o t of J l versus V used to determine threshold voltage V and gain parameter K o s  T  -99-  GS  because o f the d i f f i c u l t y o f i s o l a t i n g the p a r a s i t i c r e s i s t a n c e s , which a r e not modulated by the a p p l i e d gate v o l t a g e , and the c h a n n e l r e s i s t a n c e , which is.  The method used i n t h i s t h e s i s was proposed by Lee e t a l . [52] and i s  shown s c h e m a t i c a l l y i n f i g u r e 5.6.  I n t h i s setup  forward  b i a s e d w i t h r e s p e c t t o the source  flows.  A t the same time, a c o n s t a n t  small d r a i n current while current i s perturbed  so t h a t a s m a l l gate c u r r e n t  c u r r e n t source  the d r a i n - s o u r c e v o l t a g e  slightly.  the gate i s s l i g h t l y  i s used to o b t a i n a i s m o n i t o r e d as the gate  As the d r a i n c u r r e n t i n c r e a s e s the d r a i n  s i d e o f the gate becomes i n c r e a s i n g l y r e v e r s e b i a s e d and the gate c u r r e n t gets c o n c e n t r a t e d resistance R  i n the source  s i d e o f the channel.  The d i f f e r e n t i a l end  i s d e f i n e d as  end  av R  DS  (5.12)  end a  i  G S  Ipg—const and  i n [52] i t i s shown t h a t , f o r a l i m i t e d range o f I  R  end = s + n k T / q I  D S  , t h i s becomes  (5.13)  R  Thus, by p l o t t i n g A V / A I D S  G S  DS  versus  1/I  D S  and f i n d i n g the y - a x i s i n t e r c e p t o f  the l i n e a r p o r t i o n w i t h s l o p e nkT/q one can determine R . s  source  and d r a i n t e r m i n a l s one can o b t a i n R .  figure  5.7.  D  -100-  By r e v e r s i n g the  A t y p i c a l p l o t i s shown i n  -101-  REND (ft ) CURSOR ( 454E+00 . 30.0E+00. MARKER [ 454E+0Id . 30.0E+00. 50.00 E+00  -\  / 5.000 /div  /  /  /  f  /  /  /  )  r  / •  *  •  .0000 .0000 LINE1 LINE2  1.500 IDINV .1 500/div ( ) E+03 Xintercept Yintercept GRAD 1/GRAD 6.18E+00 52.6E-03 19.0E.00 -117E+00  REND IDINV  Figure 5.7  (O ) - AVDS/AIG ( ) - 1/ID  Typical end-resistance p l o t giving R . s  -102-  Another parameter which i s commonly used i s the defined  transconductance  as a i  DS  (5.14) Vpg=const  I t i s u s u a l l y e x p r e s s e d i n m i l l i s i e m e n s per m i l l i m e t e r o f gate w i d t h . a s m a l l s i g n a l parameter, however, and it  i s most o f t e n measured a t V  versus  V  GS  i s shown i n f i g u r e  GS  depends s t r o n g l y on o p e r a t i n g  = 0 or V  GS  = +0.8  The  point;  V. A t y p i c a l p l o t o f  5.8.  For comparison purposes the K - f a c t o r d e f i n e d e a r l i e r f i g u r e of merit  It is  i s a more u n i v e r s a l  s i n c e i t i s not o p e r a t i n g p o i n t dependant.  model parameters f o r a t y p i c a l r e c e n t FET  are g i v e n i n t a b l e  These parameters are used i n the SPICE s i m u l a t i o n s  of chapter  3.  To  the v a l i d i t y o f a t l e a s t the s t a t i c p a r t o f the model, the s i m u l a t e d measured t r a n s f e r c u r v e s o f t h i s FET  -103-  are shown t o g e t h e r  i n figure  5.1. show and  5.9.  (mS) CURSOR ( .OOOOV MARKER ( ,6000V 1  -1  r  5.98E+00. 7.17E+00  i  ^  _ . I i . I i i  E+00  i  cn  !!  j  6976 /div  \  .... (  i (  !  !  I  1  r !  i  ---f-—  0000 -3.440  SQRT GM  Figure 5.8  VG  4300/div  0 .4300 ( V)  if A) - / I S (mS) - 1000KAID/AVG  Typical p l o t of transconductance g,,, as a function of gate bias. -104-  SPICE DESIGNATION  PARAMETER  VALUE  VTO  -1.80 V  Hyperbolic tangent parameter, a  ALPHA  0.86  Transconductance parameter, /9  BETA  2.68X10"  Channel length modulation parameter, A  LAMBDA  2xl0"  Source resistance, Rg  RS  6.17 n  Drain resistance, R  RD  20.7  Gate resistance, R Q  RG  3 kfi  Threshold voltage, V  T  D  Zero-bias gate-source capacitance, C Zero-bias gate-drain capacitance, C  GS0  GD0  5  n  CGSO  0.28 pF  CGDO  0.28 pF  Gate diode i d e a l i t y factor, n  N  2.2  Gate b u i l t - i n p o t e n t i a l , ^  VBI  0.8 V  CDS  0.07 pF  b  Drain-source capacitance, C  Table 5.1.  DS  3  Self-aligned gate MESFET model parameters used i n SPICE simulations.  -105-  A/V  2  EEsof - mwSPICE r- 5/9/BB - 16: IB: 14 - DTA SAGFET .  IDS REAL  0.0150  —  0.0050  •  • •«  0.0000  Figure 5.9  !L 1  1.500  •  •  •  •  •  •  •  •  m  •  •  » *  •  _. ,. . . a —  VDS  UBC s e l f - a l i g n e d gate MESFET transfer curves: ( ) measured, ( • • • ) simulated.  -106-  •  '  1  <  <  • 3.000  CHAPTER 6  CONCLUSIONS AND  SUGGESTIONS FOR  FUTURE WORK  The work done i n t h i s t h e s i s can be d i v i d e d i n t o two  sections.  d e a l s w i t h h i g h speed sampling and i t s a p p l i c a t i o n to the sampling  The  first  amplifier  concept developed a t the Defense Research E s t a b l i s h m e n t Ottawa ( DREO ). l i t e r a t u r e s u r v e y was sampling c i r c u i t s .  done t o determine  I t was  A  the s t a t e o f the a r t f o r h i g h speed  found t h a t the h i g h e s t speed e l e c t r o n i c  sampling  i s a c h i e v e d u s i n g s o l i d s t a t e m e c h a n i c a l sampling heads used i n sampling o s c i l l o s c o p e s , w i t h bandwidths o f about 18 GHz.  The h i g h e s t speed  m o n o l i t h i c c i r c u i t s are made w i t h g a l l i u m a r s e n i d e and have bandwidths o f about 2 GHz.  Some o f the d i f f e r e n t types o f sample-and-hold  c i r c u i t s were  d i s c u s s e d , r a n g i n g i n c o m p l e x i t y from a s i n g l e s w i t c h and s t o r a g e c a p a c i t o r to m u l t i s t a g e feedback The  circuits.  important parameters  investigated.  I t was  o f the two most common types o f s w i t c h were a l s o  found t h a t the s i x diode r i n g s w i t c h can h a n d l e  the  l a r g e s t v o l t a g e swing but r e q u i r e s a b a l a n c e d c u r r e n t s w i t c h d r i v e , which can be d i f f i c u l t  to o b t a i n i f a number o f switches are t o be used i n  p a r a l l e l a t a h i g h sampling r a t e .  The FET s w i t c h uses a s i n g l e - e n d e d  v o l t a g e d r i v e and i s t h e r e f o r e more s u i t e d f o r a p p l i c a t i o n s , sampling a m p l i f i e r ,  such as the  r e q u i r i n g a l a r g e number o f switches i n p a r a l l e l .  High  speed s w i t c h i n g w i l l r e q u i r e the use o f GaAs MESFETs so t h a t the maximum a l l o w a b l e v o l t a g e swing w i l l be l i m i t e d t o about 0.5 the f o r w a r d b i a s e d gate d i o d e .  V by the c o n d u c t i o n o f  The use o f a d u a l - g a t e MESFET to reduce  sample p u l s e feedthrough, as was  r e p o r t e d i n [18], was  found t o have minimal e f f e c t i n most p r a c t i c a l  -107-  investigated  applications.  and  The  e f f e c t s o f sampling  sampling  c i r c u i t parameters on the performance o f the  a m p l i f i e r were i n v e s t i g a t e d i n c h a p t e r 3.  main f a c t o r d e t e r m i n i n g the number o f channels  I t was  found t h a t the  t h a t can be used  without  i n t r o d u c i n g e x c e s s i v e l o s s i s the i n p u t impedance o f the sampling I n o r d e r to minimize  t h i s l o s s , h i g h input-impedance b u f f e r a m p l i f i e r s  r e q u i r e d t o i s o l a t e the switches such a m p l i f i e r was  from the d e l a y l i n e .  one  a n a l y z e d u s i n g a s i m p l i f i e d low f r e q u e n c y model as w e l l as  t h i s a m p l i f i e r s h o u l d be adequate up to a t l e a s t 10  used  are  The performance o f  s i m u l a t e d u s i n g the computer program Microwave-SPICE.  The  circuits.  The performance o f  GHz.  o t h e r main a r e a o f i n v e s t i g a t i o n i n t h i s t h e s i s i s the t e c h n o l o g i e s  i n the manufacture o f g a l l i u m a r s e n i d e m o n o l i t h i c i n t e g r a t e d c i r c u i t s .  The main components used  i n MMICs were d i s c u s s e d , and the most  important  p r o c e s s i n g t e c h n o l o g i e s r e p o r t e d i n the l i t e r a t u r e were d i s c u s s e d In some detail.  Much work i s b e i n g done to develop  s e l f - a l i g n e d gate t e c h n o l o g i e s ,  which have the advantages o f m a i n t a i n i n g a p l a n a r s t r u c t u r e and p o t e n t i a l l y s i m p l e r t o manufacture, as w e l l as h a v i n g improved performance due  being speed  t o the r e d u c t i o n o f p a r a s i t i c source and d r a i n r e s i s t a n c e s  by r e d u c i n g the s p a c i n g between the gate and the ohmic n  +  regions.  development o f a r e f r a c t o r y metal T-gate s e l f - a l i g n e d gate p r o c e s s a t the U n i v e r s i t y o f B r i t i s h Columbia was  presented;  o f the gate implant mask.  d u r i n g the a n n e a l , and much e f f o r t was  The  technology  i n t h i s process  d i s t a n c e between the gate and the ohmic r e g i o n s i s determined of undercut  The  by the amount  gate m a t e r i a l i t s e l f  r e q u i r e d to determine  a n n e a l i n g c o n d i t i o n s i n o r d e r t o o b t a i n adequate a c t i v a t i o n  i s present  the b e s t without  e x c e s s i v e i n t e r a c t i o n between the t i t a n i u m - t u n g s t e n gate m a t e r i a l and  -108-  the  the  gallium  arsenide.  Chapter 5 d e a l s w i t h the measurements used to c h a r a c t e r i z e the performance o f the Schottky  diodes  and MESFETs made a t UBC.  The  emphasis i s  on dc measurements s i n c e i t i s e a s i e r to i s o l a t e the v a r i o u s parameters, the measurements themselves are e a s i e r to perform.  and  The measurement methods  used to o b t a i n the v a r i o u s model parameters used f o r computer s i m u l a t i o n were g i v e n and r e s u l t s g i v e n f o r some r e c e n t l y f a b r i c a t e d FETs.  The  s i m u l a t i o n r e s u l t s showed good agreement w i t h the measured v a l u e s . j i g was  test  made to a l l o w measurement o f the microwave parameters o f one  b e t t e r FETs a t H a r r i s / F a r i n o n i n M o n t r e a l , t r a n s i t to M o n t r e a l The  A  but the FET was  damaged i n  so t h a t no measurements were p o s s i b l e .  f a b r i c a t i o n s t e p s used to make d i s c r e t e d e v i c e s are r e a d i l y  to a l l o w f a b r i c a t i o n o f a complete m o n o l i t h i c sample-and-hold i n c l u d i n g i n p u t and output b u f f e r a m p l i f i e r s , a MESFET sampling hold capacitor. i n p u t and  I n the i n i t i a l mask d e s i g n ,  feedback t r a n s i s t o r s was  the c u r r e n t source  o f the  transistor.  which caused the output  stages  the sum  extended  circuit, s w i t c h and  o f the widths o f  the  not chosen to be e q u a l to the w i d t h o f  T h i s r e s u l t e d i n a s i g n i f i c a n t dc to be  offset  t u r n e d o f f under normal o p e r a t i o n ,  no  measurements o f a m p l i f i e r performance were t h e r e f o r e p o s s i b l e . Most o f the f u t u r e work w i l l be r e q u i r e d i n the p r o c e s s i n g a r e a . main areas o f i n t e r e s t are the use channel  and n  +  implants w i t h o u t  o f r a p i d thermal  a l l o y the ohmic c o n t a c t s . the gate m a t e r i a l and  a n n e a l i n g to anneal  u s i n g a d i e l e c t r i c a n n e a l i n g cap and  minimum i n t e r a c t i o n between the gate and  The the  with  the g a l l i u m a r s e n i d e as w e l l as to  The p h y s i c a l e f f e c t s o f the i n t e r a c t i o n between  the s u b s t r a t e d u r i n g anneal  -109-  c o u l d a l s o warrant  a  investigation. The use o f the s e l f - a l i g n e d gate p r o c e s s i n g t e c h n o l o g y to f a b r i c a t e a complete sample-and-hold c i r c u i t s h o u l d be attempted. amplifier,  For the  sampling  a h i g h sampling r a t e i s not r e q u i r e d so one o f the m u l t i s t a g e  sampling c i r c u i t s  d i s c u s s e d i n c h a p t e r 2 c o u l d be used.  The  buffer  a m p l i f i e r t o p o l o g y d i s c u s s e d i n c h a p t e r 3 s h o u l d be s u i t a b l e i f the gate dimensions  are a p p r o p r i a t e l y chosen;  the dimensions  given i n figure  3.7  suggested.  Given s u i t a b l e drive c i r c u i t r y ,  l e a s t 1 GHz  s h o u l d be a t t a i n a b l e , w i t h sampling times o f l e s s than 100  -110-  maximum sampling r a t e s o f a t ns  REFERENCES R.E. Lehmann and D.D. IEEE T r a n s . Microwave 1985.  Heston, " X-band m o n o l i t h i c s e r i e s feedback LNA," Theory and Techniques, V o l . MTT-33, No.12, Dec.  C. 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O'Connor, " A s i m p l i f i e d c a p l e s s a n n e a l i n g o f GaAs f o r MESFET a p p l i c a t i o n s , " IEEE T r a n s . E l e c r o n D e v i c e s , V o l . ED-31, No.4, Apr. 1984. [34] B. Molnar, " C l o s e - c o n t a c t a n n e a l i n g o f i o n implanted A p p l . Phys. L e t t . , Vol.36, No.11, 1 June 1980.  GaAs and  InP,"  [35] R.A. S a d l e r , " F a b r i c a t i o n and performance o f submicron GaAs MESFET d i g i t a l c i r c u i t s by s e l f - a l i g n e d i o n i m p l a n t a t i o n , " Ph.D. Dissertation, C o r n e l l U n i v e r s i t y , Jan. 1984. [36] H. Kanber, R.J. C i p o l l i , W.B. Henderson and J.M. Whelan, " A comparison of r a p i d thermal a n e a l i n g and c o n t r o l l e d atmosphere a n n e a l i n g o f S i i m p l a n t e d GaAs, J . A p p l . Phys., Vol.57, No.10, 15 May 1985. [37] K.S. Seo, S. Dahr and P.K. B a t t a c h a r y a , " High q u a l i t y S i - i m p l a n t e d GaAs a c t i v a t e d by a two-step r a p i d thermal anneal t e c h n i q u e , " A p p l . Phys. L e t t . , Vol.47, No.5, 1 Sept. 1985. [38] T. O h n i s h i , Y.Yamaguchi, T. Inada, N. Yokoyama and N. N i s h i , " A p p l i c a t i o n o f the lamp a n n e a l i n g method to the n - l a y e r o f WSi -gate s e l f - a l i g n e d GaAs MESFETs, EDL-5, No.10, Oct. 1984. +  x  [39] M.H. Badawi, D.R. Dundobbin and J . Mun, " S e l e c t i v e i m p l a n t a t i o n o f GaAs f o r MESFET a p p l i c a t i o n s , " E l e c t r o n i c s L e t t . Vol.10, No.15, [40] D.C. D'Avanzo, " P r o t o n i s o l a t i o n f o r GaAs MESFET's," IEEE Trans. Microwave Theory and Techniques, V o l . MTT-30, No.7, J u l y 1982.  -113-  [41] f o r example, see R.E. House, 1984.  W i l l i a m s , " GaAs p r o c e s s i n g t e c h n i q u e s , " A r t e c h  [42] N. Yokoyama, T. Mimura, M. Fukata and H. Ishikawa, " A new s e l f - a l i g n e d s o u r c e / d r a i n t e c h n o l o g y f o r u l t r a h i g h s p e e d GaAs MESFET VLSI," ISSCC Tech. D i g e s t , Feb. 1981. [43] H.M. Levy and R.L. Lee, " S e l f - a l i g n e d submicron i n t e g r a t e d c i r c u i t s , " EDL-4, No.4, Apr. 1983.  gate d i g i t a l GaAs  [44] T. O h n i s h i , N. Yokoyama, H. Onodera, S. Suzuki and A. Shibatomi, " C h a r a c t e r i z a t i o n o f WSi /GaAs S c h o t t k y c o n t a c t s , " A p p l . Phys. L e t t . , V o l . 4 3 , No.6, 15 Sept 1983. x  [45] K. Yamasaki, K. A s a i , T . M i z i t a n i and K.Kurumada, " S e l f - A l i g n I m p l a n t a t i o n f o r N - l a y e r Technology (SAINT) f o r h i g h - s p e e d GaAs ICs, E l e c t r o n i c s L e t t e r s , Vol.18, No.3, 1982. +  [46] M. Hagio, S. Katsu, T.Tagaki, M. Kazumura G. Kano, I . Teramoto and H. Mizuno, " A new s e l f - a l i g n t e c h n o l o g y f o r low n o i s e GaAs MESFET's S i d e w a l l - a s s i s t e d p a t t e r n i n v e r s i o n t e c h n o l o g y - , " 1984 IEDM Symposium Digest. [47] f o r example, see S.M. Sze, " P h y s i c s o f semiconductor E d i t i o n , W i l e y - I n t e r s c i e n c e , 1981.  d e v i c e s , " 2nd  [48] M. Kuzuhara, T. Nozaki and H. Kohzu, " N o n - a l l o y e d ohmic c o n t a c t s to S i - i m p l a n t e d GaAs a c t i v a t e d u s i n g S i O ^ - c a p p e d i n f r a r e d r a p i d thermal a n n e a l i n g , " J . A p p l . Phys., Vol.58, No.3, 1 Aug. 1985. [49] H. F u k u i , " D e t e r m i n a t i o n o f b a s i c d e v i c e parameters B e l l System Tech. J . , Vol.58, No.3, Mar. 1979.  o f a GaAs MESFET,"  [50] W.R. C u r t i c e and M. E t t e n b u r g , " A n o n l i n e a r GaAs FET model f o r use i n the d e s i g n o f output c i r c u i t s f o r power a m p l i f i e r s , " IEEE T r a n s . Microwave Theory and Techniques, V o l . MTT-33, No.12, Dec. 1985. [51] T. Takada, K. Yokoyama, M. Ida and T. Sudo, " A MESFET v a r i a b l e c a p a c i t a n c e model f o r GaAS i n t e g r a t e d c i r c u i t s i m u l a t i o n , " IEEE Trans. Microwave Theory and Techniques, V o l . MTT-30, No.5, May 1982. [52] K. Lee, M.S. Shur, A . J . V a l o i s , G.Y. Robinson, X.C. Zhu and A. Van Der Z i e l , " A new t e c h n i q u e f o r the c h a r a c t e r i z a t i o n o f "End" r e s i s t a n c e i n Modulation-doped FETs," IEEE T r a n s . E l e c r o n D e v i c e s , V o l . ED-31, No.10, Oct. 1984.  -114-  ! ! ! !  name: 468S128E (2,4) date: 86 05 07 purpose: COMPARE SIMULATED AND MEASURED TRANSFER CURVES FOR UBC SELF-ALIGNED GATE GaAs MESFET.  CKT S2PA_A1 1 2 DEF2P 1 2  0  [MODEL=gasmdl area=l] SAGFET  MODEL gasmdl GAS M0DEL=1 VTO=-1.80 ALPHA=.86 BETA=2.68E-3 LAMBDA=2e-5 + RS=6.17 RD=20.7 CGS0=.28p CGD0=.28p CDS=.07p VBI=0.8 N=2.1 RG=3K SOURCE SAGFET SAGFET SAGFET  IVS_Vds 2 3 IVS_Vmon 0 3 IVS_Vgs 10  DC=3.0 DC=0 DC =-.4  CONTROL SAGFET  DC Vds 0 3 . 2  Vgs -2 0.5 .5  SPICEOUT SAGFET END  DC V ( a l l )  Appendix A l .  I(all)  mwSPICE l i s t i n g f o r t r a n s f e r curve  -115-  analysis.  ! b u f f e r amp s i m u l a t i o n u s i n g GaAsFET model !output t r a n s i e n t a n a l y s i s dim cap p f r e s oh ckt S2PA A l 1 2 0 [model=gl area= =5.1] [model=gl area= =4.9] S2PA_A2 7 2 0 S2PA_A3 2 3 4 [model=gl area= =10] S2PA A4 2 3 2 [model=gl area= =10] [model=gl area= =10] S2PA_A5 6 7 6 [model=dl] S1PA D l 4 5 [model=dl] S1PA_D2 5 7 DEF2P 1 7 AMP MODEL D l D CJO=10p IS=1E-15 N = l . l RS=100 VJ=.8 G l GAS VT0=-1.8 BETA=2.68E-4 LAMBDA=2E-5 RD=62 RS=62 CGS0=3.If TAU=10p RG=3k ALPHA=.86 VBI=.8 CGD0=3.If CDS=.75f SOURCE AMP IVS_Vdd 3 0 DC=4 AMP IVS_Vss 6 0 DC=-2 0 tran=pwl(0 0 .2n 0 .4n .5 4.4n .5 4.8n -.5 8.8n -.5 9n 0) AMP IVS_Vin CAP_Cload 7 8 c=l AMP RES R l o a d 8 0 r=50 AMP CONTROL t r a n .In l O n AMP o p t i o n s l i s t node AMP SPICEOUT AMP tran v ( l ) v(7) i(cap_cload)  Appendix A2.  mwSPICE l i s t i n g f o r the b u f f e r a m p l i f i e r t r a n s i e n t  -116-  response.  ! s i m u l a t i o n o f a GaAsFET s w i t c h dim cap p f r e s oh CKT S2PA_A1 1 3 2 [MODEL=gl area=10] S2PA_A2 0 4 3 [model=gl area=10] CAP_Chold 4 0 c = l DEF2P 1 4 SWITCH MODEL g l gas VTO=-1.80 LAMBDA=2E-5 BETA=2.68E-4 alpha=.86 + RS=62 RD=62 CGS0=3.If cgdo=3.If VBI=0.8 CDS=.75f SOURCE SWITCH RES_Rin 10 2 r=10 SWITCH IVS_Vin 10 0 t r a n pwl(0 0 40n 0 41n .5 lOOn .5 102n -.5 150n -.5 151n 0) SWITCH I V S _ V c n t r l 1 0 t r a n p u l s e ( - 3 0 .In .In .In .In lOn) CONTROL SWITCH t r a n lOOp 200n u i c SWITCH i c v(4)=-0 SWITCH OPTIONS NODE ACCT SPICEOUT SWITCH t r a n v ( 4 ) v ( 1 0 )  Appendix A3.  mwSPICE l i s t i n g f o r d u a l - g a t e s w i t c h t r a n s i e n t  -117-  analysis.  

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