UBC Theses and Dissertations

UBC Theses Logo

UBC Theses and Dissertations

The design, simulation and fabrication of a gallium arsenide monolithic sample and hold circuit Durtler, Willem G. 1986

Your browser doesn't seem to have a PDF viewer, please download the PDF to view this item.

Item Metadata

Download

Media
831-UBC_1986_A7 D87.pdf [ 5.23MB ]
Metadata
JSON: 831-1.0096908.json
JSON-LD: 831-1.0096908-ld.json
RDF/XML (Pretty): 831-1.0096908-rdf.xml
RDF/JSON: 831-1.0096908-rdf.json
Turtle: 831-1.0096908-turtle.txt
N-Triples: 831-1.0096908-rdf-ntriples.txt
Original Record: 831-1.0096908-source.json
Full Text
831-1.0096908-fulltext.txt
Citation
831-1.0096908.ris

Full Text

THE DESIGN, SIMULATION AND FABRICATION OF A GALLIUM ARSENIDE MONOLITHIC SAMPLE AND HOLD CIRCUIT by WILLEM G. DURTLER B.Eng. McGill University A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE STUDIES DEPARTMENT OF ELECTRICAL ENGINEERING We accept this thesis as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA June 1986 © Willem G. Durtler 1986 In presenting t h i s thesis i n p a r t i a l f u l f i l m e n t of the requirements for an advanced degree at the University of B r i t i s h Columbia, I agree that the Library s h a l l make i t f r e e l y available for reference and study. I further agree that permission for extensive copying of t h i s thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It i s understood that copying or publication of t h i s thesis for f i n a n c i a l gain s h a l l not be allowed without my written permission. Department of ELECTRICAL ENGINEERING The .University of B r i t i s h Columbia 1956 Main Mall Vancouver, Canada V6T 1Y3 1986 06 12 ABSTRACT This thesis describes work done towards the development of a gallium arsenide monolithic sample-and-hold c i r c u i t . The literature relevant to high-speed electronic sampling is reviewed, and the different types of high-speed sampling circuits are discussed. The requirements of a sampling c i r c u i t for use i n a distributed sampling amplifier are analyzed, and i t is found that the most important requirement is a high input impedance. A c i r c u i t suitable for monolithic integration i s designed and analyzed using the computer program mwSPICE. The different fabrication technologies for gallium arsenide integrated circuits are discussed, with emphasis on the self-aligned gate technologies, which can give reduced parasitic source and drain resistances. The processing steps for the refractory metal self-aligned gate technology developed for this thesis at the University of Br i t i s h Columbia are given in detail. DC measurement procedures for MESFETs and Schottky diodes are given and results are presented for self-aligned gate MESFETs fabricated at UBC. These results indicate that the refractory metal self-aligned gate process developed at UBC should be suitable for the fabrication of the monolithic sample-and-hold c i r c u i t . TABLE OF CONTENTS ABSTRACT i i LIST OF TABLES v LIST OF FIGURES v i ACKNOWLEDGEMENT i x 1 INTRODUCTION 1 1.1 Overview 1 1.2 Requirement f o r high-speed monolithic integrated c i r c u i t s 1 1.3 Elements of monolithic microwave integrated c i r c u i t s 3 1.4 Semiconductor materials f o r MMICs 4 1.5 The sampling a m p l i f i e r concept 7 2 HIGH-SPEED SAMPLING 10 2.1 Sample-and-hold waveforms and d e f i n i t i o n s 10 2.2 Sample-and-hold design considerations 12 2.3 Basic sample-and-hold c i r c u i t s 12 2.4 Sampling switches 15 2.5 Survey of l i t e r a t u r e on sample-and-hold c i r c u i t s 20 2.5.1 Discrete mechanical sampling heads 21 2.5.2 Discrete s o l i d state samplers 22 2.5.3 Monolithic sample-and-hold c i r c u i t s 23 2.5.4 Th e o r e t i c a l analysis and modeling of high-speed sample-and-hold c i r c u i t s 27 3 DESIGN AND SIMULATION 30 3.1 System requirements 30 3.2 Buffer amplifiers 40 3.3 The sampling switch 47 4 PROCESSING TECHNOLOGY FOR GaAs MESFETs AND MMICs 56 4.1 Introduction 56 4.2 Review of GaAs MESFET f a b r i c a t i o n technologies 58 4.2.1 Active layer formation 59 4.2.2 Device i s o l a t i o n 62 4.2.3 Gate formation 65 4.2.4 Ohmic contact formation 71 4.2.5 Passive components 74 4.3 UBC r e f r a c t o r y metal s e l f - a l i g n e d gate MESFET f a b r i c a t i o n technology 77 5 MEASUREMENT TECHNIQUES AND RESULTS 89 5.1 Introduction 89 5.2 Diode measurements 90 5.3 Tr a n s i s t o r Measurements 94 - i i i -6 CONCLUSIONS AND SUGGESTIONS FOR FUTURE WORK 107 REFERENCES 111 APPENDIX A l mwSPICE l i s t i n g f o r transfe r curve analysis 115 A2 mwSPICE l i s t i n g f o r b u f f e r a m p l i f i e r transient response 116 A3 mwSPICE l i s t i n g f o r dual-gate switch transient analysis 117 - i v -LIST OF TABLES TABLE DESCRIPTION PAGE 1. ,1 Components f o r monolithic microwave integrated c i r c u i t s 5 1. .2 Important properties of s i l i c o n and gallium arsenide 6 4, .1 Detailed s e l f - a l i g n e d gate process log 80 5. .1 Ty p i c a l s e l f - a l i g n e d gate MESFET model parameters 105 -V-LIST OF FIGURES FIGURE TITLE PAGE 1.1 Sampling a m p l i f i e r block diagram. 8 2.1 Sample-and-hold waveforms and d e f i n i t i o n s ( a f t e r S t a f f o r d 11 et a l . [13] ). 2.2 Basic sample-and-hold c i r c u i t s : (a) simplest, (b) output 13 buffered, (c) input and output buffered, (d) integrator. 2.3 Multistage sample-and-hold c i r c u i t s : (a) feedback, 16 (b) ground referenced. 2.4 Six-diode sampling switch. 17 2.5 FET sampling switch: (a) n-channel MOSFET, (b) n-channel MESFET. 19 2.6 S i l i c o n monolithic sample-and-hold c i r c u i t ( a f t e r S t a f f o r d 25 et a l . [13] ) . 2.7 GaAs monolithic sampling switch ( a f t e r Saul [17] ). 26 2.8 GaAs monolithic sample-and-hold c i r c u i t ( a f t e r Harrold 28 et a l . [19] ) . 3.1 Block diagram of the sampling a m p l i f i e r showing the c r i t i c a l 31 propagation times. 3.2 Input delay l i n e low frequency equivalent c i r c u i t . 34 3.3 Input dc loss as a function of the number of channels: (a) R i n= 1 kn, (b) R i n= 10 kfl 35 3.4 Input delay l i n e high frequency equivalent c i r c u i t . 36 3.5 Input ac loss as a function of channel p o s i t i o n : (a) R i n= 10 kfi, wCin= 10"2, (b) R i n= 10 kQ, wCin= 10_* 38 3.6 Simulated return loss and transmission loss of the loaded 39 input delay l i n e . 3.7 Monolithic FET buff e r a m p l i f i e r ( a f t e r Hornbuckle et a l . [23] ). 42 3.8 Buffer a m p l i f i e r s i m p l i f i e d low frequency small s i g n a l 43 equivalent c i r c u i t . 3.9 Simulated b u f f e r a m p l i f i e r frequency response. 45 - v i -FIGURE TITLE PAGE 3.10 Simulated b u f f e r a m p l i f i e r transient response. 46 3.11 Single-gate MESFET switch: (a) schematic diagram, (b) ON state 48 equivalent c i r c u i t , (c) OFF state equivalent c i r c u i t . 3.12 Dual-gate MESFET switch: (a) schematic diagram, (b) ON state 51 equivalent c i r c u i t , (c) OFF state equivalent c i r c u i t . 3.13 Simulated single-gate GaAs MESFET switch transient response. 54 3.14 Simulated dual-gate GaAs MESFET switch transient response. 55 4.1 Device i s o l a t i o n methods: (a) s e l e c t i v e ion-implantation, 63 (b) i s o l a t i o n ion-implantation, (c) mesa etching. 4.2 Buried-channel r e f r a c t o r y metal self-aligned-gate process 66 ( a f t e r Yokoyama et a l . [42] ). 4.3 T-structure self-aligned-gate process 68 ( a f t e r Levy et a l . [43] ). 4.4 Sel f - A l i g n e d Implantation of N +-layer Technology ( SAINT ) 70 process ( a f t e r Yamasaki et a l . [45] ). 4.5 Sidewall-assisted pattern inversion process ( a f t e r 72 Hagio et a l . [46] ). 4.6 Airb r i d g e f a b r i c a t i o n process. 76 4.7 UBC r e f r a c t o r y metal self-aligned-gate f a b r i c a t i o n process flowchart. 79 4.8 Sample-and-hold mask layout. 86 4.9 Photomicrograph of sample-and-hold chip. 87 4.10 Scanning e l e c t r o n micrograph of dual gate MESFET. 88 5.1 T y p i c a l capacitance/voltage doping p r o f i l e . 92 5.2 T y p i c a l diode current/voltage p l o t . 93 5.3 Symmetric MESFET model equivalent c i r c u i t ( a f t e r Curtice et a l . [50] ). 95 5.4 Small-gate-length MESFET depletion region. 97 5.5 T y p i c a l p l o t of 7 l D S versus V G S used to determine threshold voltage V T and gain parameter K. 99 - v i i -FIGURE TITLE PAGE 5.6 Measurement setup used to determine Rs and RD. 101 5.7 T y p i c a l end-resistance p l o t giving Rs. 102 5.8 T y p i c a l p l o t of transconductance g m versus V G S. 104 5.9 S e l f - a l i g n e d gate MESFET transfe r curves: ( ) measured, ( • • • ) simulated 105 - v i i i -ACKNOWLEDGEMENT Many people helped i n d i r e c t or i n d i r e c t ways i n the research and preparation of t h i s t h e s i s . In p a r t i c u l a r , I would l i k e to thank Dr. L. Young for h i s encouragement and guidance during a l l stages of my graduate work. Peter Townsley was l a r g e l y responsible f o r the acual device f a b r i c a t i o n . I also g r a t e f u l l y acknowledge the contributions of my fellow graduate students, Kim Tan, Dave Hui, Salam Dindo and Wade Tang, as well as Rod Walker f o r h i s proofreading. F i n a l l y , I would l i k e to thank my colleagues and management at Harris-Farinon Canada, Ltd., of Dorval, Quebec, fo r t h e i r a c t i v e support and encouragement. - i x -CHAPTER 1 INTRODUCTION 1.1 Overview This thesis describes the design and f a b r i c a t i o n of a monolithic, high-speed, sample-and-hold a m p l i f i e r f o r use i n s i g n a l processing a p p l i c a t i o n s . The i n t r o d u c t i o n w i l l discuss the requirements f o r high-speed monolithic c i r c u i t s , the a p p l i c a t i o n of gallium arsenide and the fundamentals of gallium arsenide monolithic microwave integrated c i r c u i t s ( GaAs MMICs ), and the concept of d i s t r i b u t e d sample-and-hold a m p l i f i c a t i o n . Chapter 2 w i l l discuss the t h e o r e t i c a l and p r a c t i c a l aspects of high speed sample-and-hold c i r c u i t s and give an overview of published work i n the f i e l d . In chapter 3 the design of a sample-and-hold a m p l i f i e r s u i t -able f o r use i n a d i s t r i b u t e d a m p l i f i e r w i l l be described and simulation r e s u l t s using the computer program mwSPICE w i l l be given. In chapter 4 the development of a s e l f - a l i g n e d gate GaAs processing technology at the U n i v e r s i t y of B r i t i s h Columbia w i l l be described. Measurement procedures and experimental r e s u l t s w i l l be given i n chapter 5, and f i n a l l y chapter 6 w i l l present conclusions and suggestions for future work. 1.2 Requirement f o r high-speed monolithic integrated c i r c u i t s In the past there has been an evolution to f a s t e r and more complex c i r c u i t s , with c i r c u i t s of a given complexity becoming ever f a s t e r and c i r c u i t s of a given speed becoming ever more complex. At the same time -1-these c i r c u i t s are becoming both cheaper and p h y s i c a l l y smaller i n s i z e . These developments are spurred by the requirement for r e l a t i v e l y cheap, high volume subsystems i n areas such as s i g n a l processing, phased array radar and r e a l time graphics. Phased array radar, for example, uses transmit power amp l i f i e r s , receive low noise a m p l i f i e r s , transmit/receive switches and d i g i t a l l y c o n t r o l l e d phase s h i f t e r s , a l l which must operate at the radar frequency of t y p i c a l l y 8 GHz. In presently a v a i l a b l e systems these functions are implemented using mainly hybrid integrated c i r c u i t technology which i s bulky and expensive due to the s k i l l e d manpower required for assembly and tuning. A l l these subsystems have been demonstrated using monolithic integrated c i r c u i t technology [1,2,3,4], but at present y i e l d seems to be the l i m i t i n g f a ctor. Once a s u i t a b l e high y i e l d technology has been developed i t i s l i k e l y that a l l these functions w i l l be integrated on one chip. Another high volume a p p l i c a t i o n that i s being a c t i v e l y investigated i s 12 GHz D i r e c t Broadcast S a t e l i t e ( DBS ) receivers for the commercial t e l e v i s i o n market. These c i r c u i t s t y p i c a l l y c o n sist of a low noise preamplifier, a l o c a l o s c i l l a t o r , a mixer, a bandpass f i l t e r and an automatic gain c o n t r o l intermediate frequency a m p l i f i e r . A l l these functions have been demonstrated i n monolithic form, amd several papers have presented complete receivers on a chip [5,6]. A very important advantage of monolithic microwave c i r c u i t s over hybrid c i r c u i t s i s that the p a r a s i t i c reactances associated with component i n t e r -connections can be greatly reduced. This considerably increases the maximum atta i n a b l e bandwidth which i s important for instrumentation and e l e c t r o n i c -2-warfare a p p l i c a t i o n s . By incorporating the p a r a s i t i c capacitances of a number of FETs into a transmision l i n e structure, s o - c a l l e d t r a v e l l i n g wave, or d i s t r i b u t e d , amplifiers can achieve bandwidths of a decade or more up to 20 GHz [7]; t h i s performance i s only possible with monolithic c i r c u i t s . The small s i z e and minimal p a r a s i t i c s also allow MMICs to be used well into the millimetre-wave ( 30 - 300 GHz ) region [8]. Up to now only wave-guide c i r c u i t s were usable i n t h i s frequency range. In the d i g i t a l f i e l d there i s a large requirement for very high speed l o g i c f o r such a p p l i c a t i o n s as r e a l time s i g n a l processing and r e a l time graphics. Other uses for high speed d i g i t a l ICs are supercomputers and high data-rate telecommunications modems. At present, GaAs-based SSI and MSI c i r c u i t s are commercially a v a i l a b l e that operate up to about 4 GHz [9] but t h e i r cost i s s t i l l p r o h i b i t i v e l y high. 1.3 Elements of monolithic microwave integrated c i r c u i t s A monolithic microwave integrated c i r c u i t ( MMIC ) can be defined as a c i r c u i t used to perform a given function at frequencies greater than about 1 GHz, where the active and usu a l l y passive elements are f a b r i c a t e d on a sin g l e semiconductor chip. This d e f i n i t i o n allows for c r i t i c a l passive components, such as resonators, or bulky n o n - c r i t i c a l components, such as decoupling capacitors, to be o f f the chip. Active components, such as metal-semiconductor f i e l d e f f e c t t r a n s i s t o r s ( MESFETs ) and Schottky diodes are required to achieve gain, f o r frequency conversion and other nonlinear functions. Passive devices, such -3-as capacitors, inductors, r e s i s t o r s and transmission l i n e s are used f o r bandwidth determination, impedance transformation, b i a s i n g and other l i n e a r functions. The most important elements, t h e i r common uses and, where applicable, t h e i r f a b r i c a t i o n technologies are l i s t e d i n table 1.1. One problem with MMICs that contain many passive elements i s that the chip s i z e can become quite large, a cm2 or more i s not uncommon. This increases the cost and can decrease y i e l d due to breakage, substrate flaws etc. Another p o t e n t i a l disadvantage of MMICs i s that present techniques to tune a c i r c u i t a f t e r f a b r i c a t i o n are rudimentary compared with conventional hybrid c i r c u i t s . Therefore a very c a r e f u l i n i t i a l design i s required using the best possible component models and a design philosophy based on minimum s e n s i t i v i t y to component and processing varations. Computer-aided analysis and design are absolutely e s s e n t i a l f o r most MMIC designs. 1.4 Semiconductor materials f o r MMICs At present both s i l i c o n and gallium arsenide are being used f o r the production of MMICs. S i has the advantages of having lower cost and a well developed and simpler production technology while GaAs has inherently higher speed. The main c h a r a c t e r i s t i c s of the two are l i s t e d i n table 1.2. InP also has p o t e n t i a l as a sui t a b l e semiconductor but has not yet been developed to the extent of S i and GaAS. The low f i e l d e l e c t r o n m o b i l i t y of GaAs i s much higher than that of S i which i s the reason f o r i t s higher speed p o t e n t i a l . However, i t s hole -4-COMPONENT FABRICATION TECHNOLOGY APPROXIMATE VALUE RANGE Capacitors i n t e r d i g i t a t e d metal-insulator-metal < 1 pF 1 - 100 pF Inductors loop shorted high-impedance l i n e multiturn ( with airbridges ) < 10 nH < 10 nH 10 - 100 nH Resistors t h i n f i l m sputtered semiconductor 10 - 10 kO 10 fl - 1 kil Transmission l i n e s m i c r o s t r i p coplanar waveguide 20 - 130 O 40 - 200 O MESFETs and Schottky diodes e p i t a x i a l ion-implanted Table 1.1. Components for monolithic microwave integrated c i r c u i t f a b r i c a t i o n . - 5 -PROPERTY Si GaAs I n t r i n s i c r e s i s t i v i t y , fi-cm D i e l e c t r i c constant E l e c t r o n d r i f t mobility, cm2/V-s Hole d r i f t mobility, cm2/V-s Bandgap, eV C r y s t a l structure L a t t i c e constant, A Density, g/cm3 Linear c o e f f i c i e n t of thermal expansion, K"1 Thermal conductivity, W/K-cm Melting point, °C A l l values s p e c i f i e d at 300 K. 2.3X105 11.9 1500 450 1.12, i n d i r e c t diamond 5.431 10 8 13.1 8500 400 1.42, d i r e c t zincblende 5.653 2.33 5.32 2.6X10"6 1.5 1415 6.86X10"6 0.46 1238 Table 1.2. Important properties of s i l i c o n and gallium arsenide. -6-m o b i l i t y i s lower than that of S i and hence n-channel FETs are used almost e x c l u s i v e l y . GaAs does not have a native oxide with appropriate properties for use with MOS, and other i n s u l a t o r s such as Si 3N A and S i 0 2 have thus f a r given r i s e to very high i n t e r f a c e trap d e n s i t i e s , so Schottky b a r r i e r s rather than MIS structures are used for the FET gates which l i m i t s the usable forward gate voltage to about 0.6 V. The high r e s i s t i v i t y of GaAs even a f t e r processing i s one of the main advantages because i t provides inherent i s o l a t i o n between devices and also allows the f a b r i c a t i o n of r e l a t i v e l y low lo s s transmission l i n e s on chip. At 2 GHz i t s d i e l e c t r i c l o s s i s about 0.008 dB per cm compared to 0.4 dB for S i and 0.001 dB f o r alumina, a common hybrid MIC substrate [10]. The d i r e c t bandgap of GaAs allows i t to be used to make s o l i d state lasers and since i t i s transparent to i n f r a r e d l i g h t i t i s an i d e a l material f o r making integrated opto-electronic devices such as monolithic f i b r e - o p t i c repeaters, although InP may be an even better choice f o r t h i s a p p l i c a t i o n [11]. Although much work remains to be done to develop a s u i t a b l e f a b r i -c a t i o n technology, i t appears that GaAs w i l l be the semiconductor of choice f o r most MMIC designs. 1.5 The sampling a m p l i f i e r concept The work done for t h i s thesis was d i r e c t e d at studying the f e a s i b i l i t y of producing a monolithic version of the sampling a m p l i f i e r developed at the Defense Research Establishment Ottawa ( DREO ) [12]. A block diagram of the -7-Figure 1.1 Sampling a m p l i f i e r block diagram. -8-sampling a m p l i f i e r i s given i n figu r e 1.1 The input t r a v e l s along the input delay l i n e (A) and i s f i n a l l y d i s s i p a t e d i n the input load r e s i s t o r (B). The N input switches (C) are p e r i o d i c a l l y closed to sample the s i g n a l along the input l i n e and the sampled voltage i s stored on capacitors (D). Signal processing, such as i n t h i s case a m p l i f i c a t i o n , occurs i n the video am p l i f i e r s (E), a f t e r which the output switches (F) feed the processed s i g n a l to the output delay l i n e (G). Half the s i g n a l t r a v e l s i n the opposite d i r e c t i o n as the input s i g n a l and i s absorbed by the output load r e s i s t o r (H), the other h a l f i s low pass f i l t e r e d to remove the switching noise and i s a v a i l a b l e at the output. The bandwidth of the sampling a m p l i f i e r i s determined mainly by the width of the sampling pulse which should be made as narrow as possi b l e . The bandwidth required of the video amplifiers i s s l i g h t l y greater than h a l f of the input bandwidth divided by the number of channels. The optimum time delay between adjacent switches i s determined by the maximum input freqency, the number of channels and the time delay of the switch c o n t r o l s i g n a l between adjacent switches, which w i l l be non-zero i n p r a c t i c e . The advantages of the sampling a m p l i f i e r are that low bandwidth ampli-f i e r s can be used to amplify wideband signals and that the design i s inherently redundant so that the f a i l u r e of one sub-amplifier w i l l not cause the f a i l u r e of the complete sampling a m p l i f i e r . -9-CHAPTER 2 HIGH SPEED SAMPLING 2.1 Sample-and-hold waveforms and d e f i n i t i o n s An i d e a l sample-and-hold c i r c u i t i s a c i r c u i t that, i n the sample mode, tracks the input s i g n a l and whose output, on r e c e i p t of a hold command, takes on the value of the input s i g n a l at the instant the command i s received and holds t h i s value u n t i l the next command i s given [13]. In p r a c t i c e c e r t a i n s i g n a l d i s t o r t i o n s and time delays occur that w i l l l i m i t the performance of a sample-and-hold c i r c u i t . Figure 2.1 shows the input, output and con t r o l waveforms with the t y p i c a l l y occurring non-i d e a l i t i e s . A f t e r the hold command i s given a f i n i t e time i s required f o r the switch to open; t h i s i s termed delay time. Pedestal i s the term given to the change i n output voltage when the sampling switch i s opened and Is due to the ca p a c i t i v e d i v i d e r e f f e c t of the hold capacitor and the sampling switch p a r a s i t i c capacitances. S e t t l i n g time i s the time required f o r any transients to die down when the switch i s opened. In the hold mode, the hold capacitor w i l l slowly charge or discharge, depending on s i g n a l p o l a r i t y . The corresponding change i n output voltage i s termed droop rate. When the sample command i s given the time required for the switch to close, the hold capacitor to charge to the input l e v e l and the output s i g n a l to s e t t l e down i s termed a c q u i s i t i o n time. -10-INPUT UJ CO o > SAMPLE SETTLING - TIME — _J DELAY TIME HOLD OUTPUT PEDESTAL F. r DROOP ACQUISITION TIME SAMPLE TIME Figure 2.1 Sample-and-hold waveforms and d e f i n i t i o n s ( a f t e r S t a f f o r d et a l . [13] ). -11-2.2 Sample-and-hold design considerations For a given a p p l i c a t i o n there are two sets of constraints that must be taken into account. The f i r s t i s determined by the external system require-ments and consists of such factors as bandwidth, input and output impedance, gain, power handling c a p a b i l i t y and power consumption, l i n e a r i t y and sampling accuracy. On the other hand, the p h y s i c a l c i r c u i t implementation determines the c i r c u i t complexity and cost and the tradeoffs that w i l l be required i n the system requirements. S p e c i f i c design goals were not given for the d i s t r i b u t e d a m p l i f i e r work done at the U n i v e r s i t y of B r i t i s h Columbia. I t was to run as f a s t as possi b l e , run at a f a i r l y low s i g n a l l e v e l and be s u i t a b l e f o r monolithic i n t e g r a t i o n . Since a large number of switches are connected i n p a r a l l e l along the delay l i n e s the input impedance of each must be high to avoid a s i g n i f i c a n t voltage drop along the l i n e . In order to keep y i e l d as high as possible the c i r c u i t complexity should, at l e a s t i n i t i a l l y , be kept low. 2.3 Basic sample-and-hold c i r c u i t s In p r i n c i p l e , a l l sample-and-hold c i r c u i t s c o n s i s t of a s i g n a l switch and a hold capacitor. Other elements, such as b u f f e r c i r c u i t s , switch drive c i r c u i t s and feedback c i r c u i t s can be added to b e t t e r meet system requirements. The simplest type of sample-and-hold i s simply a switch and capacitor, f i g u r e 2.2a. The disadvantages of t h i s c i r c u i t are that a l l the -12-IN OUT -13-hold capacitor charging current must be supplied by the sampled source, which means that the a c q u i s i t i o n time w i l l be dependent on the source impedance. Conversely, the droop rate w i l l be dependent on the input impedance of subsequent c i r c u i t r y , and, i f t h i s impedance i s inductive, there can be s i g n i f i c a n t r i n g i n g of the sampled s i g n a l , which w i l l increase the s e t t l i n g time. The sample-and-hold performance can be improved by following the hold capacitor with a b u f f e r a m p l i f i e r as shown i n f i g u r e 2.2b. This r e s u l t s i n a consistent, high impedance load and thus a low droop rate. The major disadvantage of t h i s c i r c u i t i s increased'complexity, and the b u f f e r must be properly designed to avoid having i t l i m i t speed performance, cause d i s t o r t i o n or give a dc o f f s e t . The input impedance of t h i s c i r c u i t i s s t i l l not well defined and i s time varying, which can cause problems i n high frequency systems. The next l o g i c a l improvement i s to also put a b u f f e r a m p l i f i e r at the input to i s o l a t e i t from the source as shown i n f i g u r e 2.2c. For the case of a number of switches i n p a r a l l e l a high input impedance i s necessary as was discussed i n section 2.2. The input b u f f e r should also be designed to have a high slew rate to reduce a c q u i s i t i o n time. As i n the case of the previous c i r c u i t , the major disadvantages are increased complexity and the p o s s i b i l i t y of d i s t o r t i o n and dc o f f s e t . Another type of sample-and-hold c i r c u i t i s shown i n f i g u r e 2.2d. Here the output b u f f e r a m p l i f i e r i s configured as an integrator, with the hold capacitor i n the feedback loop. The main advantage of t h i s c i r c u i t i s that the switch i s e s s e n t i a l l y always operating at ground p o t e n t i a l , thus easing -14-the drive requirements and allowing a larger input voltage swing. I t has l i m i t e d high frequency use, however, due to the d i f f i c u l t y of obtaining microwave "op-amp" type a m p l i f i e r s . In c e r t a i n a p p l i c a t i o n s , such as sampling o s c i l l o s c o p e s , i t i s required to have very short a c q u i s i t i o n times but at r e l a t i v e l y low sampling rates. In such cases the more complex multistage sample-and-hold c i r c u i t s of the type shown i n fi g u r e 2.3 are often used. In the c i r c u i t of f i g u r e 2.3a, capacitor C x i s i n i t i a l l y charged up to a small f r a c t i o n , t y p i c a l l y 5%, of i t s steady state value before switch S1 i s opened again. Switch S 2 charges the much la r g e r capacitor C 2 over a longer period of time and the amp l i f i e r gain A and the feedback f a c t o r are chosen to charge both capacitors to the o r i g i n a l input value. In the c i r c u i t of f i g u r e 2.3b, C1 i s s i m i l a r l y charged to a f r a c t i o n of i t s steady state value and the gain A i s chosen to charge the larger capacitor C 2 to the f u l l steady state value. Once t h i s i s achieved S 2 opens and S 3 i s closed to discharge C1 back to ground p o t e n t i a l . 2.4 Sampling switches For the switching element i t s e l f there are two popular configurations. The f i r s t i s the diode r i n g shown i n fi g u r e 2.4. In the OFF state ( switch open ) , the c o n t r o l voltage V c must be le s s than the peak s i g n a l voltage V s i n order to keep diodes D5_6 forward biased and reverse biased. Conversely, i n the ON state V c must be greater than V s. The bias voltage V b i s dependent on the bias r e s i s t o r value and diode ser i e s resistance as well as on the maximum input s i g n a l swing [12]. -15-(a) Figure 2.3 Multistage sample-and-hold circuits: (a) feedback, (b) ground referenced. -16-Vs . IN BIAS 01 02 R BIAS + CONTROL + BIAS D5 1 03 OUT D4 D6 - BIAS - CONTROL Figure 2.4 Six-diode sampling switch. -17-The main advantage of the diode r i n g switch i s that, due to the balanced c o n t r o l drive requirement, the complementary sampling pulses tend to cancel at the input and output ports i f well-matched diodes are used. I t can also handle large input s i g n a l l e v e l s i f the bias and co n t r o l voltages and bias r e s i s t o r s are chosen properly, and can have a high OFF/ON impedance r a t i o . I t s disadvantages are a s i g n i f i c a n t dc power consumption and the requirement f o r a high speed complementary switch current drive, e s p e c i a l l y i f a large number of switches are to be used i n p a r a l l e l . The other popular type of switch uses a f i e l d e f f e c t t r a n s i s t o r as a voltage c o n t r o l l e d r e s i s t o r , f i g u r e 2 .5 . For lower speed a p p l i c a t i o n s , up to a few tens of MHz, a s i l i c o n MOSFET i s most us e f u l since i t s gate cannot be forward biased into conduction as i s p o t e n t i a l l y the case with a JFET or MESFET. Higher speed applications, however, require the f a s t switching speed of a GaAS MESFET. The advantages of a FET switch are that i t s state i s c o n t r o l l e d by a single-ended voltage s i g n a l , thus easing the drive requirements compared to a diode switch, and the n e g l i g i b l e dc power consumption. However, since the switch resistance i s dependent on the gate to channel voltage, and the channel voltage i s s i g n a l l e v e l dependent, a l i m i t a t i o n i s placed on the maximum u s e f u l s i g n a l l e v e l that can be handled. In order to minimize these e f f e c t s the switch c o n t r o l bias and pulse height must be chosen such that the c o n t r o l gate does not become forward biased into conduction at the lowest s i g n a l voltage and that the channel resistance does not become too large at the highest s i g n a l l e v e l since t h i s would cause the a c q u i s i t i o n time to be strongly s i g n a l l e v e l dependent. In p r a c t i c e t h i s l i m i t s the -18-(a) I CONTROL OUT (b) CONTROL Figure 2.5 FET sampling switch: (a) n-channel MOSFET, (b) n-channel MESFET. -19-s i g n a l voltage swing to about 1 v o l t peak-to-peak. Another major advantage of the FET switch i s i t s s i m p l i c i t y . I t i s not required to have matched devices and the p h y s i c a l layout i s less c r i t i c a l than i n the case of the diode switch. The disadvantage of the FET switch i s that the single-ended drive does not give any sample pulse feedthrough c a n c e l l a t i o n . This feedthrough i s e s s e n t i a l l y caused by the gate-source capacitance forming a cap a c i t i v e d i v i d e r with the hold capacitor and i s thus dependent on the r a t i o of the values of these capacitances. I t i s more or less independent of s i g n a l l e v e l and w i l l not be an important f a c t o r i n many ap p l i c a t i o n s . The other disadvantage of the MESFET switch i s the low allowable input voltage swing as discussed previously. 2.5 Survey of l i t e r a t u r e on sample-and-hold c i r c u i t s To determine the state of the a r t of sample-and-hold c i r c u i t s both a computer aided search and a manual search were performed using subject and c i t a t i o n indexes. S u r p r i s i n g l y l i t t l e has been published i n the s c i e n t i f i c l i t e r a t u r e . The most important papers of what has been published w i l l be discussed i n four categories: (a) d i s c r e t e mechanical sampling heads, (b) d i s c r e t e s o l i d state sampling c i r c u i t s , (c) monolithic sampling c i r c u i t s and (d) t h e o r e t i c a l analysis and modeling of high speed sampling c i r c u i t s . -20-2.5.1 Discrete mechanical sampling heads The highest speed e l e c t r o n i c switches are found i n t h i s category. The sampling heads are generally used i n sampling o s c i l l o s c o p e s and since they have been developed by pr i v a t e laboratories f o r use i n commercially a v a i l a b l e t e s t equipment l i t t l e has been published on the actual design procedure. The f i r s t recent paper of i n t e r e s t i s by Grove [14] of Hewlett-Packard. In i t he discussed the design and modelling of a two diode sampler located i n the centre of a d i e l e c t r i c - f i l l e d b i c o n i c a l transmission l i n e . Using a s i m p l i f i e d l i n e a r ( small s i g n a l ) model he obtained an expression fo r the sampler bandwidth, which i s determined by the diode c h a r a c t e r i s t i c s , the sampling pulse width and the transmission l i n e c h a r a c t e r i s t i c s f o r both the s i g n a l and the sampling pulse. The design gave a bandwidth of greater than 15 GHz and s t i l l forms the basis of present day sampling heads and has not been s i g n i f i c a n t l y improved upon. In a more recent paper Riad [15] gave a more rigorous analysis of the HP-1430A sampling head, which has a nominal bandwidth of 12.4 GHz and a nominal pulse risetime of 28 ps. The sampling head i t s e l f i s s i m i l a r i n construction to the one discussed i n [14], with a b i c o n i c a l tapered l i n e and two sampling diodes. The input and output impedance matching structures are more -sophisticated, and feedback i s used to bias the diodes to the previous sampled l e v e l as was discussed i n section 2.3. By doing t h i s the sampling network measures only the diffe r e n c e between consecutive samples, thus improving the dynamic range. The sample pulse i t s e l f i s obtained by -21-r e f l e c t i n g a f a s t risetime voltage step o f f a short c i r c u i t wall i n the c a v i t y . When the leading edge of the step i s r e f l e c t e d o f f the short c i r c u i t i t i s inverted and, upon reaching the diodes, cancels the incoming wave leaving only a narrow pulse whose width i s determined by the round t r i p distance between the diodes and the short c i r c u i t . A f t e r describing the sampler and i t s operation Riad goes on to develop a model of i t which includes the input and output matching networks, the diode layout, construction and bias, and the feedback network. Mechanical sampling heads using d i s c r e t e diodes are the f a s t e s t e l e c t r o n i c samplers cu r r e n t l y a v a i l a b l e , the f a s t e s t having bandwidths of about 18 GHz. Their disadvantage i s t h e i r high cost ( f o r machining and assembling t h e i r components ) and t h e i r r e l a t i v e l y large s i z e . 2.5.2 Discrete s o l i d state samplers In contrast to the mechanical samplers discussed i n the previous section, s o l i d state samplers do not normally have matching networks f o r the input s i g n a l . T y p i c a l l y , a complete sampler w i l l use input and output b u f f e r am p l i f i e r s to i s o l a t e the switch from the external c i r c u i t r y . The input impedance of the a m p l i f i e r s i s u s u a l l y high while the output impedance i s low. The switch can c o n s i s t of e i t h e r a diode bridge or a FET of some sort. In recent work the FET switch has been preferred because of i t s ease of f a b r i c a t i o n and much simpler drive requirements. A representative paper describing the state of the a r t of such disc r e t e -22-sampling c i r c u i t s i s that by Givens [16]. He uses high slew rate monolithic b u f f e r a m p l i f i e r s and d i s c r e t e DMOS FET switches f o r h i s c i r c u i t , which i s p r i m a r i l y intended for a n a l o g - t o - d i g i t a l converter systems. As such, speed i s not as important as accuracy. His design achieves a bandwidth of about 50 MHz f o r a 2 V peak-to-peak input, but with high l i n e a r i t y , low droop rate and low pedestal, which he terms hold-step error. The low pedestal i s achieved by using a charge compensation c i r c u i t to supply the same amount of charge to the hold capacitor as was tr a n s f e r r e d to the switch. The r e s t of the paper describes the tradeoffs involved i n sample-and-hold design and some of the techniques used to measure t h e i r c h a r a c t e r i s t i c s . The advantage of d i s c r e t e s o l i d state samplers i s t h e i r low cost and small s i z e compared to mechanical ones. The disadvantage i s that the i n e v i t a b l e c i r c u i t p a r a s i t i c s w i l l tend to l i m i t the maximum speed to a few GHz, although c i r c u i t s of t h i s bandwidth have not yet been reported i n the l i t e r a t u r e . 2.5.3 Monolithic sample-and-hold c i r c u i t s For large volume app l i c a t i o n s , such as the sampling a m p l i f i e r envisioned i n t h i s project, monolithic c i r c u i t s can be expected to give s u b s t a n t i a l l y reduced cost as well as increased uniformity and p o t e n t i a l l y higher performance. For high speed ap p l i c a t i o n s , GaAs i s the semiconductor of choice due to i t s higher e l e c t r o n m o b i l i ty r e l a t i v e to s i l i c o n . Processing technology i s much less developed f o r GaAs, however, and much work needs to be done before the f u l l p o t e n t i a l of GaAs sample-and-hold c i r c u i t s can be -23-r e a l i z e d . The e a r l i e s t paper describing a monolithic sample-and-hold was by S t a f f o r d et a l . [13] i n 1974. They used s i l i c o n technology and a f a i r l y complex integrator/feedback system to obtain the medium speed, medium performance sample-and-hold c i r c u i t shown i n figu r e 2.6. Although they do not give the speed performance, t h e i r quoted s e t t l i n g time was 1 jus, giving a maximum sampling rate of about 250 kHz. The f i r s t paper describing a monolithic sample-and-hold switch i s by Saul [17] i n 1980. He used a quad r i n g of MESFETs as a switch, but used an external hold capacitor and no buf f e r a m p l i f i e r s , f i g u r e 2.7. Using MESFETs with a 4 fj.m gate length and a 13 pF hold capacitor Saul was able to obtain a maximum sampling rate of 150 MHz. The major l i m i t i n g f a c t o r was the p a r a s i t i c inductance associated with the external capacitor. I t i s therefore reasonable to expect that, using a submicron gate length switch and a 1 or 2 pF monolithic hold capacitor, a sampling rate of at l e a s t an order of magnitude higher can be obtained. In h i s switch design Saul uses a quad r i n g of MESFETs, presumably based on the standard diode r i n g . However, since the MESFETs are not comple-mentary, the main reason f o r using a r i n g ( which i s to reduce sample pulse feedthrough by using a balanced drive ) i s l o s t . What remains i s a complex structure having the same c h a r a c t e r i s t i c s as a sing l e MESFET of the same geometry. A more recent paper describing a GaAs monolithic sample-and-hold c i r c u i t was published by Barta et a l . i n 1983 [18]. They use a t r i p l e - g a t e MESFET switch with an on-chip metal-insulator-metal ( MIM ) capacitor followed by a -24-SUB - IN + IN SWITCH CLAMPS ft A CONTROL HOLD CHARGE CANCEL DEVICE OUT V SWITCHING CIRCUIT Figure 2.6 S i l i c o n monolithic sample-and-hold c i r c u i t ( a f t e r S t a f f o r d et a l . [13] ). -25-+ BIAS OUT CONTROL - BIAS Figure 2.7 GaAs monolithic sampling switch ( after Saul [17] ). -26-feedback b u f f e r a m p l i f i e r to minimize loading e f f e c t s on the performance of the sampler i t s e l f . The use of a t r i p l e - g a t e switch, with the sample pulses applied to the centre gate and the outer gates grounded, was found to s i g n i f i c a n t l y reduce sample pulse feedthrough to the input and output. They reported an o v e r a l l 3dB bandwidth of 1.1 GHz with a maximum sampling rate of 500 MHz. A more complex switch has been reported by Harrold et a l . [19] for use i n a switched capacitor bandpass f i l t e r IC. Their c i r c u i t , shown i n figu r e 2.8, uses drive c i r c u i t r y which allows the gate of the switching FET to track the input s i g n a l , thus a l l e v i a t i n g the input voltage swing l i m i t a t i o n . They reported a maximum switching speed of about 1 GHz. 2.5.4 Th e o r e t i c a l analysis and modeling of high speed sample-and-hold c i r c u i t s A number of papers already discussed i n t h i s s e c t i o n contain an analysis or model of the sampling process. Grove [14] gives a s i m p l i f i e d l i n e a r a n alysis of samplers i n general. Riad [15] gives a thorough model of the HP-1430A sampling head which inludes a nonlinear model f o r the switching diodes. His main objective was to obtain the sampling head step response. Other papers have dealt more with the t h e o r e t i c a l aspects of sampling. Blum [20] investigates the e f f e c t s of aperture time using Fourier analysis. Wollman [21] does a s i m p l i f i e d analysis of the e f f e c t s of nonlinear switch resistance, showing that t h i s w i l l give r i s e to intermodulation d i s t o r t i o n . F i n a l l y , Sonders [22] defines the parameters involved i n the dynamic -27-+ BIAS IN HOLD OUT - BIAS CONTROL Figure 2.8 GaAs monolithic sample-and-hold c i r c u i t ( a f t e r Harrold et a l . [19] ). -28-performance of high speed sample-and-hold c i r c u i t s and gives a transformer bridge technique for the measurement of those parameters. In conclusion, the l i t e r a t u r e published to date provides some idea of the the promise of GaAs high speed sampling c i r c u i t s , although t h i s promise has not yet been r e a l i z e d . The work being done at the U n i v e r s i t y was designed to continue the development of high-speed monolithic sample-and-hold c i r c u i t s , both i n terms of processing and c i r c u i t complexity and i n terms of speed. - 2 9 -CHAPTER 3 DESIGN AND SIMULATION 3.1 System requirements In order to spec i f y the performance requirements of the sampling amplifier subsystems, the system requirements of the sampling a m p l i f i e r i t s e l f must f i r s t be defined. A d e t a i l e d block diagram of the sampling a m p l i f i e r i s shown i n f i g u r e 3.1. The analysis w i l l be divided into three sections: the o v e r a l l system, the input network and the output network. The external parameters of i n t e r e s t f o r the o v e r a l l system are bandwidth, gain,input impedance and output impedance. Secondary c h a r a c t e r i s t i c s are power handling c a p a b i l i t i e s , noise and d i s t o r t i o n c h a r a c t e r i s t i c s . These parameters are determined by several factors such as sampling rate S and sample pulse width W, spacing between adjacent switches, input and output impedances of the switches and gain and bandwidth of the video a m p l i f i e r s . T y p i c a l l y , i n designing such a system one would f i r s t determine the primary parameters: bandwidth B, gain A and system impedance Z 0. The maximum allowable sampling pulse width i s determined by the bandwidth requirement, Wmax. * V2B (3.1) The sampling rate and the number of channels N required f o r complete reconstruction of the sampled s i g n a l are r e l a t e d by -30-Figure 3.1 Block diagram of the sampling a m p l i f i e r showing the c r i t i c a l propagation times. -31-N = B/S (3.2) The time delay between adjacent channels T s i s also dependant on the bandwidth. I t i s given by T s = 1/2B (3.3) In p r a c t i c a l systems there w i l l also be a delay i n the sampling pulse between adjacent channels T p which r e s u l t s i n an e f f e c t i v e s i g n a l delay of T s e =TS ± T p (3.4) depending on whether the sampling pulse i s t r a v e l l i n g i n the same d i r e c t i o n (-) as or opposite to (+) the input s i g n a l . Thus, the bandwidth i s given by B = V2T s e (3.5) The video a m p l i f i e r bandwidth requirement i s B v i d e o > S/2 (3.6) I t would appear that, f o r a given input s i g n a l bandwidth, one could decrease the video bandwidth requirement by increasing the number of channels and decreasing the sampling rate. In p r a c t i c e the number of channels i s l i m i t e d by the loading of the input and output networks on t h e i r -32-respective delay l i n e s . This loading consists of three components, a dc loading due to the r e s i s t i v e component of the input and output impedances, an ac loading which includes the input and output reactances and a per i o d i c loading due to the d i s t r i b u t e d nature of the input and output l i n e s . In the following discussion the loading e f f e c t s on the input l i n e w i l l be analyzed; s i m i l a r e f f e c t s also hold f o r the output l i n e . The low frequency equivalent c i r c u i t of the input l i n e i s shown i n fig u r e 3.2, where R i n i s the input resistance of the sampling c i r c u i t , and R e q = Rin/N (3.7) The loss f o r t h i s c i r c u i t i s given by L i n d c = 201og( 1 + Z0N/2Rin ) dB (3.8) This i s p l o t t e d i n figu r e 3.3 as a function of N f o r Z 0 = 50 0 and R i n = 1 kO and 10 kQ. The ac loading e f f e c t i s s i m i l a r to the dc s i t u a t i o n , but now both the t r a v e l l i n g wave nature of the input s i g n a l and the input capacitance must be taken into account. The equivalent c i r c u i t f o r the ac case i s shown i n fig u r e 3.4. In t h i s case the voltage of the input s i g n a l decreases ( i . e . the l o s s increases ) as the si g n a l t r a v e l s along the transmission l i n e . Assuming that the transmission l i n e i t s e l f has n e g l i g i b l e loss the loss at the Nth sampling c i r c u i t i s given by -33-Who RIN •AA/vV -A/VW 1 1 1 1 (l) (2) (3) (4) (N-1) (N) Figure 3.2 Input delay line low frequency equivalent c i r c u i t . -34-20 10 20 50 100 200 500 1000 NUMBER OF CHANNELS Figure 3.3 Input dc loss as a function of the number of channels: (a) Rin= 1 kfl, (b) Rln- 10 kfl. -35-u 0 -WW- I T R I N HVWVi ' I N rAWn -K-rAAAAn -K-rAA/vVi 1 ( i ) (2) (3) 1 (N) Figure 3.4 Input delay l i n e high frequency equivalent c i r c u i t . -36-Lin..e<N) = 201og( 1 + HNZo|Yin| ) dB (3.9) where Y i n = 1/Rin + jwC i n. This i s p l o t t e d i n fig u r e 3.5 f o r R i n = 10 kQ and uC = IO - 4. The t h i r d form of loading i s due to the p e r i o d i c nature of the sampling c i r c u i t . Internal r e f l e c t i o n s caused by the d i s c o n t i n u i t i e s of the sampling c i r c u i t s can i n t e r f e r e d e s t r u c t i v e l y to give n u l l s i n the tr a n s f e r charac-t e r i s t i c s . This w i l l be most severe when the e l e c t r i c a l length between adjacent channels approaches 90°. The e f f e c t of p e r i o d i c loading on the tra n s f e r c h a r a c t e r i s t i c s may not be as noticeable f o r submultiples of 90° but w i l l s t i l l appear i n the input and output return l o s s , defined as where S l i i s the input (i=l) or output (i=2) r e f l e c t i o n c o e f f i c i e n t . P e r i o d i c loading was simulated using the microwave analysis program Touchstone. A chain of 20 sampling c i r c u i t s connected by l o s s l e s s 50 O transmission l i n e segments was assumed; the sampling c i r c u i t s were modelled as a p a r a l l e l combination of a 10 kfi r e s i s t o r and a 1 pF capacitor, and the transmission l i n e segments were chosen to have an e l e c t r i c a l length of 45° at 2 GHz. The c a l c u l a t e d input return loss and transmission loss are shown i n f i g u r e 3.6, the p e r i o d i c r i p p l e i n the return loss and the n u l l i n the transmission at 4 GHz can be c l e a r l y seen. In order to minimize loading e f f e c t s i t i s c l e a r that the input impedance of the input sampling c i r c u i t s and the output impedance of the output Return Loss = 201og| S i ± | dB (3.10) -37-Figure 3.5 Input ac loss as a function of channel position. (a) Rin= 10 kfl, o>Cin= 10-2, (b) Rin= 10 kfl. WCin=10-* -38-DB[S11] . DB[S2i] LINE LINE 0.0000 LOSS, dB 15.00 1 /S11 \ / Return loss \ A A A A \ Transi nission loss 0.0000 3.000 FREQ-GHZ 6 .000 Figure 3.6 Simulated return loss and transmission loss of the loaded input delay line. -39-sampling c i r c u i t s must be maximized, and that the s i g n a l transmission delay T s must be kept le s s than 90° at the maximum input freqency. The s i t u a t i o n at the output i s s i m i l a r to that discussed f o r the input. I t i s , however, much more d i f f i c u l t to implement wideband, high output impedance amp l i f i e r s than high input impedance a m p l i f i e r s . The s i t u a t i o n i s less c r i t i c a l at the output than at the input since i t i s not necessary to feed a large number of channels from one source. The loss mechanisms are s i m i l a r f o r the input and the output, but to some extent the e f f e c t s w i l l cancel since the channel that has the highest loss at the input w i l l have the lowest loss at the output and v i c e versa. I f the sampling pulse width i s l e s s than the t o t a l time required f o r the sampling pulse to t r a v e l to the adjacent channel, the adjacent switch to open and the output s i g n a l to t r a v e l back to the f i r s t switch, then the output s i g n a l w i l l see the other switches only i n t h e i r high impedance state. Since t h i s i s p r e c i s e l y the condition s p e c i f i e d i n equations 3.1 and 3.5, no output bu f f e r a m p l i f i e r s are required. 3.2 Buffer amplifiers Buffer a m p l i f i e r s at the sample-and-hold inputs have two functions. They can be designed to have a high input impedance to reduce the loading problems discussed i n the previous section, and they can be designed to have a low output impedance to decrease the time required to charge the hold capacitor. In addition, they w i l l also i s o l a t e the s i g n a l l i n e from the sample pulse l i n e . -40-The bu f f e r a m p l i f i e r configuration of fig u r e 3.7 was chosen because of i t s high input impedance and because the feedback of Q2 eases the production uniformity requirements. Amplifiers of t h i s type have been described i n [23] and have shown gains of 10 dB with a 5 GHz bandwidth. A s i m p l i f i e d low frequency small s i g n a l equivalent c i r c u i t of the buffer a m p l i f i e r i s shown i n figu r e 3.8. The FETs are assumed to be i d e a l and have i d e n t i c a l transconductance gsa, zero bias current I 0 and gate capacitance C 0 per u n i t gate width, and WA and IL are the gate width and t o t a l current of Qi. At low frequencies, 13 = ^ + I 2 or W 3I 0 - Wx( I 0 + g mV i n ) + W2( I 0 + ^ ) (3.11) Rearranged, t h i s gives V0ut = (( W3 - W2 - Wx )/W2 }I 0/g m - ( Wx/W2 )V i n (3.12) I f Wx+W2 = W3 there w i l l be no dc o f f s e t and the am p l i f i e r w i l l have a gain of -Wj/Wg independant of t r a n s i s t o r transconductance. The maximum output current i s determined by Q4 and Q5; i f these are chosen to have equal width the a m p l i f i e r w i l l have a symmetrical current drive c a p a b i l i t y of W4I0. W4 cannot be increased i n d e f i n i t e l y , however, because the corresponding increase i n gate capacitance w i l l l i m i t the high frequency response. The diodes are required to keep the gate of Q4 reverse biased when the output voltage i s negative. Since the t r a n s i s t o r s are assumed to be -41-VDD Q3 W=100 jjm r - 1 Q4 I W=100jJm Q2 IN Ql " — i W=49 jJ W=51JJm h SZ 02 OUT Q5 W=100 jJm V ss Figure 3.7 Monolithic FET buf f e r a m p l i f i e r ( a f t e r Hornbuckle et a l . [23] ). -42-OUT Figure 3.8 Buffer amplifier simplified low frequency small signal equivalent c i r c u i t . -43-i d e n t i c a l , the voltage at the gate of Q4 must be equal to V D D/2. The number and area of the diodes are chosen such that the voltage at the source of Q4 i s not greater than about 0.5V r e f e r r e d to the gate at the minimum output voltage. This gives M( V d + W4I0RS ) + | V o u t j m i n | * V D D/2 (3.13) where M i s the number of diodes, V d i s the diode voltage drop and Rs i s the diode s e r i e s resistance. To obtain a more exact idea of the transient and high frequency response c h a r a c t e r i s t i c s of such a buff e r a m p l i f i e r the computer program Microwave-SPICE was used to simulate the amp l i f i e r . The FET and diode model parameters are derived i n chapter 5, and the SPICE program l i s t i n g s are given i n appendix A. Two analyses were performed, one to determine the amp l i f i e r frequency response and one to determine the transient response when d r i v i n g a capac i t i v e load. The frequency response curve f o r a l i g h t l y loaded GaAs FET am p l i f i e r ( R l o a d = 1 kfl ) i s shown i n figu r e 3.9. At low frequencies the am p l i f i e r has a loss of about 0.1 dB, at higher frequencies there i s about 3 dB peaking; t h i s i s caused by the e f f e c t i v e decrease i n negative feedback due to the phase s h i f t i n Q4 and the diodes. The 3 dB bandwidth of the am p l i f i e r i s almost 10 GHz. The simulated transient response i s shown together with the input s i g n a l i n f i g u r e 3.10; the load i n t h i s case i s a 1 pF capacitor. I t can be seen that the am p l i f i e r i s i n v e r t i n g with roughly unity gain; the differe n c e between the p o s i t i v e and negative gain i s caused by the extra resistance -44-- 4 5 -VOUT VIN HEAL REAL 0.0000 5.0E-09 TIME l.OE-OB Figure 3.10 Simulated bu f f e r a m p l i f i e r t r a n s i e n t response. -46-of the diodes i n the sourcing h a l f cycle ( p o s i t i v e output voltage). The r i n g i n g and overshoot are due to the l i m i t e d bandwidth of the a m p l i f i e r . The same a m p l i f i e r with the load increased to 10 pF, and a l l the input times also increased ten times, showed almost no r i n g i n g . 3.3 The sampling switch The advantages of a FET switch over a diode switch were given i n section 2.4. In t h i s s e ction the switching c h a r a c t e r i s t i c s of s i n g l e and dual gate FET switches w i l l be discussed. The s i n g l e gate switch i s shown schematically, with i t s equivalent c i r c u i t , i n f i g u r e 3.11. For a symmetrically designed FET the source and drain terminals are interchangeable; the terms "source" and "drain" are used for reference only, with the switch input considered to be the source. For the small s i g n a l l e v e l s used here the FET w i l l always be operating i n the l i n e a r regime so that the use of a resistance to model the source-drain conduction mechanism i s appropriate. The most important switch c h a r a c t e r i s t i c i n the ON state i s the switch resistance, which should be minimized to minimize a q u i s i t i o n time. Referring to f i g u r e 3.11, i t can be seen that the switch ON resistance i s given by Ron = R s + Rch + RD (3-14) For s e l f - a l i g n e d gate FETs, Rs and RD consist of the ohmic contact resistance, the resistance of the n + layer between the ohmic contact and the -47-Figure 3.11 Single-gate MESFET switch: (a) schematic diagram, (b) ON state equivalent c i r c u i t , (c) OFF state equivalent c i r c u i t . -48-channel, and a short section of channel that i s not modulated by the gate. The channel resistance i s dependant on the gate-to-channel voltage, where fo r small drain and source voltages the channel voltage w i l l be the average of the d r a i n and source voltages. For a uniform doping p r o f i l e and assuming that V s and V D are small and VG=0, the channel resistance can be approximated by [24] 1 R c h - (L/W) { 1 - 7( V b i/V p ) }-i (3.15) qND/ia where V b i i s the b u i l t - i n voltage of the Schottky b a r r i e r , V p i s the pinch-o f f voltage of the FET, given by V p = qNDa2/2e (3.16) and a i s the channel thickness. In order to reduce R c h one can change the geometry of the FET, increase the doping concentration or increase the channel thickness. The l a t t e r two also increase the pinch-off voltage which, aside from lowering the channel resistance, also makes the resistance le s s s e n s i t i v e to v a r i a t i o n s i n channel voltage. In the OFF state the most important c h a r a c t e r i s t i c of the switch i s the value of the gate capacitances C G S and C G D, which must be minimized. Assuming again that V s and V D are small, the two capacitances w i l l be approximately equal and w i l l be given by CGS * CGD « «WL/2a (3.17) -49-Equation 3.17 also assumes that V p » V b i- kT/q and that, i n the OFF state, the gate voltage V G equals the threshold voltage V t. This depletion capacitance model assumes a one-dimensional e l e c t r i c f i e l d d i s t r i b u t i o n under the gate. In r e a l i t y , with the short gate lengths used here, there w i l l be an a d d i t i o n a l f r i n g i n g capacitance to the sides of the depletion region which can be quite s i g n i f i c a n t . This w i l l be e s p e c i a l l y important with s e l f - a l i g n e d gate devices due to the proximity of the n +-regions to the gate. Since t h i s l a t e r a l depletion width cannot vary much with gate bias due to the high doping l e v e l s of the n +-region, the t o t a l gate capacitance w i l l be larger than c a l c u l a t e d by equation 3.17 and be less s e n s i t i v e to gate bias than one would expect using the standard one-dimensional depletion capacitance formulas. I t i s the gate capacitance that produces a sample-and-hold pedestal by forming a capacitance d i v i d e r with the hold capacitor; i t can be reduced by decreasing the width or, to a l e s s e r extent, the length of the gate or by increasing the channel thickness. The use of a d d i t i o n a l gates to i s o l a t e the c o n t r o l s i g n a l from the input and output l i n e s was f i r s t proposed by Barta et a l . [18]. They used a t r i p l e gate FET with the c o n t r o l s i g n a l applied to the centre gate and the two outside gates grounded to give i s o l a t i o n to both the input and the output. In the present case a b u f f e r a m p l i f i e r i s assumed to provide i s o l a t i o n to the input l i n e so that a dual gate FET can be used. The configuration of a dual gate FET used as a switch i s shown i n fi g u r e 3.12. The switch ON resi s t a n c e i s given i n t h i s case by -50-IN IN FL OUT CONTROL CONTROL (a) I DEPLETION o l ° REGION o ° DEPLETION o k o REGION R CH GG -vwv-R CH W W S.I. GaAs (b) i—OUT IN CONTROL S.I. GaAs OUT (c) Figure 3.12 Dual-gate MESFET switch: (a) schematic diagram, (b) ON state equivalent c i r c u i t , (c) OFF state equivalent c i r c u i t . -51-R o n - R S + 2 R c h + RD + ^GG (3.18) where RQQ i s the unmodulated resistance between the gates. Assuming equal spacings between the source and drain and the gates, RQQ w i l l be less than R S and R D because i t does not include a contact resistance component. In the OFF state the source and drain capacitances of the f i r s t FET w i l l be the same as f o r a sing l e gate FET. The second FET w i l l also have capacitances associated with i t which w i l l be larger than the OFF capaci-tances of the f i r s t FET since the gate voltage i s l e s s , and w i l l be e s s e n t i a l l y constant assuming again that the source and drain voltages remain e s s e n t i a l l y at ground p o t e n t i a l . I f a s i n g l e and dual gate switch of the same gate geometries are compared one sees that the ON resistance of the dual gate switch i s about double that of the si n g l e gate switch. The pedestal i s reduced s l i g h t l y f o r the dual gate switch since the t o t a l hold capacitance now includes the gate capacitances of the second FET, while the OFF capacitance of the f i r s t FET remains the same as f o r the sing l e gate case. In p r a c t i c a l a p p lications t h i s e f f e c t i s n e g l i g i b l e since the hold capacitor i s us u a l l y chosen to be much la r g e r than the gate capacitances. The extra channel resistance of the second FET does help smooth the e f f e c t s of pedestal but does not s i g n i f i c a n t l y reduce them, while s i g n i f i c a n t l y increasing hold capacitor charging time. The s i n g l e and dual gate FET switches were simululated using the quadratic GaAs MESFET model on Microwave SPICE, the input l i s t i n g s are given i n appendix A. For comparison purposes the sing l e and dual gate FETs were -52-both taken to have the same gate width of lOO/^ m; the hold capacitor was chosen to be 1 pF i n both cases. The sample pulse width was taken to be 100 ps with a r e p e t i t i o n rate of 100 MHz. The transient response of the single gate switch i s shown i n figure 3.13 and of the dual gate switch i n figure 3.14. I t can be seen that the pedestal shows up as a s l i g h t negative o f f s e t i n the sampled s i g n a l which i s nearly independant of s i g n a l l e v e l , and which i s very s i m i l a r i n magnitude i n both cases. The number of cycles required to reach a steady state hold voltage i s greater f o r the dual gate switch. The dual gate switch also has a high droop rate f o r large negative signals which i s due to conduction of the gate diode of the second FET. In both cases the a q u i s i t i o n time f o r p o s i t i v e signals i s greater than f o r negative signals due to the v a r i a t i o n of R D S with gate voltage. To minimize t h i s e f f e c t , the switch FET pinchoff voltage should be made as large as i s compatible with other external and i n t e r n a l c i r c u i t parameters. 1.000 volts 0.0000 -1.000 0.0000 B.0E-08 TIME 2.0E-07 Figure 3.13 Simulated single-gate GaAs MESFET switch transient response. -54-1.000 volts 0.0000 -1.000 0.0000 B.0E-0B TIME, S 2.0E-07 Figure 3.14 Simulated dual-gate GaAs MESFET switch transient response. -55-CHAPTER 4 PROCESSING TECHNOLOGY FOR GaAs MESFETS and MMICs 4.1 Introduction An important aspect of MMIC f a b r i c a t i o n i s the choice of a sui t a b l e f a b r i c a t i o n technology. In a general MMIC technology the following steps are used: -active layer formation -device i s o l a t i o n -gate formation and f i r s t l e v e l m etalization -ohmic contact formation -passive component formation -passivation and p r o t e c t i o n -backside v i a hole processing. The order may vary depending on the p a r t i c u l a r technology being used and some c i r c u i t s may require a d d i t i o n a l steps while others may omit some. For each step there are several possible technologies a v a i l a b l e ; the choice w i l l depend on the f i n a l use of the MMIC, the equipment a v a i l a b l e and cost considerations. The d i f f e r e n t processing steps w i l l be discussed i n the following sections. The expected reduction i n cost i s one of the main reasons behind the large amount of i n d u s t r i a l research into GaAs MMICs, and the choice of technology d i r e c t l y e f f e c t s the cost i n several ways. The c a p i t a l cost of the equipment, the throughput and the achievable l e v e l of automation d i r e c t l y determine the cost per wafer, and the uniformity of the process -56-across the wafer, and from wafer to wafer, w i l l i n part determine the y i e l d , a higher y i e l d of course giving a lower cost per chip. To some extent the f i n a l use of the MMIC w i l l also determine the processing technology. For example, i f a c i r c u i t i s to be used i n a low si g n a l l e v e l environment i t should be optimized for noise performance. Low noise FETs t y p i c a l l y are biased f a i r l y close to pinch-off and have a r e l a t i v e l y t h i n , l i g h t l y doped channel [25] . In addition, gate p a r a s i t i c resistance must be minimized while p a r a s i t i c source and drain resistances are not as important since the channel i s almost pinched o f f . Thus, important c h a r a c t e r i s t i c s of a low noise technology are i t s a b i l i t y to uniformly and reproducibly produce a th i n , l i g h t l y doped channel and to achieve a low gate resistance. On the other hand, power amplifiers require a r e l a t i v e l y thick, h i g h l y doped channel to give a large pinch-off voltage, allowing a large input voltage swing, and to allow a high current density i n the channel. Gate resistance i s no longer c r i t i c a l but the source and drain resistances should be minimized to reduce power d i s s i p a t i o n and thus improve e f f i c i e n c y and r e l i a b i l i t y . The most c r i t i c a l component i n an MMIC i s the MESFET. This i s because i t involves the most processing steps and because the gate length i s usually the smallest, and thus most d i f f i c u l t to reproduce, dimension on the chip. Section 4.2 gives a review of GaAS MESFET and MMIC f a b r i c a t i o n technologies, while s e c t i o n 4.3 describes i n d e t a i l the s e l f - a l i g n e d gate technology developed at the U n i v e r s i t y of B r i t i s h Columbia for t h i s p r o ject. -57-4.2 Review of GaAs MESFET f a b r i c a t i o n technologies The s t a r t i n g point for a l l GaAs MESFET f a b r i c a t i o n technologies i s high r e s i s t i v i t y semi-insulating ( S.I. ) GaAs. The e a r l i e s t commercially a v a i l a b l e GaAs was grown along the <111> axis using the h o r i z o n t a l Bridgman ( HB ) technique, but HB wafers are i r r e g u l a r l y shaped which reduces y i e l d and i n h i b i t s automated production. The more recent l i q u i d encapsulated Czochralski ( LEC ) technique allows c i r c u l a r wafers to be grown along the <100> axis. HB and e a r l y LEC wafers required chromium i n the gallium arsenide to give the high r e s i s t i v i t y c h a r a c t e r i s t i c s . Chromium pins the bulk Fermi l e v e l approximately midway between the conduction and valence bands, thus g i v i n g the high r e s i s t i v i t y c h a r a c t e r i s t i c s [26]. Recently, improvements i n c r y s t a l growth technology have allowed undoped LEC GaAs to be made which ex h i b i t s high r e s i s t i v i t y without the a d d i t i o n of Cr. I t i s thought that i n t h i s case the Fermi l e v e l i s pinned between the conduction and valence bands by a trapping l e v e l due to a c r y s t a l defect i n which As atoms are located on Ga s i t e s i n the c r y s t a l l a t t i c e , the A s G a a n t i s i t e defect [26]. Regular LEC-grown wafers show a f a i r l y high number of d i s l o c a t i o n s , t y p i c a l l y 10 4 - 10 5 cm"2. Recently, s o - c a l l e d d i s l o c a t i o n free wafers have been produced by doping the GaAs with about 1% In which can reduce the d i s l o c a t i o n density to le s s than 10 cm"2. This apparently increases the f r a g i l i t y of the wafers, however, thus p o t e n t i a l l y reducing y i e l d , and i t i s not yet c l e a r to what extent d i s l o c a t i o n s a f f e c t device performance. -58-4.2.1 Active layer formation Once a wafer type has been selected, MESFETs and MMICs can be fabricated. The f i r s t step, which i s common to a l l processes, i s the formation of an n-doped channel layer on the S.I. GaAs substrate. The most common n-type dopant i s S i , although Se, S and Te are also used. The two methods used to form the n-layer are epitaxy and ion-implantation. In the case of epitaxy, c r y s t a l l i n e GaAs of the desired doping l e v e l i s grown on the s t a r t i n g wafer. Usually a buf f e r layer of high p u r i t y GaAs i s deposited f i r s t , t h i s i s e s p e c i a l l y important i n the case of Cr-doped substrates since Cr has the tendency to migrate into the channel, thus changing the device c h a r a c t e r i s t i c s over time. Once the bu f f e r layer i s grown, the active layer i s deposited to the desired thickness. There are three types of epitaxy that are normally used: l i q u i d phase ( LPE ), vapour phase ( VPE ) and molecular beam ( MBE ). In LPE, the s t a r t i n g wafer i s placed i n a hot s o l u t i o n containing Ga, As and the dopant. The s o l u t i o n i s then cooled and the doped GaAs c r y s t a l i z e s out on to the wafer [27]. In VPE, gases containing compounds of Ga and As are passed over the heated wafer where they react and deposit on to the wafer. In metal-organic chemical vapour deposition ( MOCVD ), organic compounds of Ga and As are used which allow lower temperature formation of the e p i t a x i a l layer [28]. In MBE, which i s the l a t e s t technology, elemental Ga, As and donor ions are deposited on the wafer d i r e c t l y i n a high vacuum environment. Very t h i n l a y e r s , i n the order of a few atomic layers, can be deposited, and each layer can be doped i n d i v i d u a l l y , allowing such devices as Modulation Doped -59-FETs ( MODFETs ) to be f a b r i c a t e d [29]. In ion-implanted formation of the active layer, ions of the dopant species are accelerated i n vacuum and implanted into the GaAs substrate. The doping p r o f i l e that r e s u l t s may be c a l c u l a t e d using a model due to Lindhard, Scharff and Schiott [30] based on the assumption that the target material i s amorphous. When c r y s t a l l i n e materials, such as GaAs, are used the wafer i s t i l t e d and rotated to present a "random equivalent" p r o f i l e to the ion beam [31]. The doping p r o f i l e that i s obtained roughly f i t s a truncated gaussian curve, and with t y p i c a l a c c e l e r a t i n g voltages of 50 to 200 kV the doping peak occurs at between 200 and 1500 A f o r S i into GaAs. I f the random equivalent condition i s not met the implanted ions can channel through the c r y s t a l l a t t i c e r e s u l t i n g i n a deeper implant which tends to be quite nonuniform. This would produce a large v a r i a t i o n of threshold voltage of the MESFETs. In a d d i t i o n to the depth p r o f i l e obtained with ion-implantation there occurs a c e r t a i n amount of l a t e r a l movement known as straggle. In the case of s e l e c t i v e implantation ( see section 4.2.3 ) t h i s w i l l r e s u l t i n a non-abrupt t r a n s i t i o n between the implanted and non-implanted regions. Although the doping p r o f i l e f o r a sing l e implant i s roughly gaussian i n shape i t i s , i n theory, possible to approximate many u s e f u l doping p r o f i l e s by using multiple implants of d i f f e r e n t doses and energies. One can also use p h o t o r e s i s t or other s u i t a b l e materials to block the implant from c e r t a i n areas of the wafer. I t i s thus, f o r example, possible to fa b r i c a t e both low noise and high power FETs on the same chip by using two implant masks. -60-When the GaAs i s implanted the c r y s t a l l a t t i c e i s severely damaged. In order to r e p a i r the damage and also to ac t i v a t e the implant by allowing the implanted ions to locate themselves on Ga s i t e s , the wafer must be heat treated, or annealed. Presently the most common method to do t h i s i s to heat the implanted wafer i n a furnace to about 800 to 850 °C for approximately 20 minutes. A major problem with heat t r e a t i n g GaAs i s that the As s t a r t s to vaporize at temperatures above about 500 °C. This outgassing changes the stoichiometry of the c r y s t a l near the surface and can severely degrade act i v e layer performance. In order to avoid t h i s problem several solutions can be used. The simplest i s to encapsulate the wafer with a temperature-stable d i e l e c t r i c to contain the As during annealing; both S i 3 N 4 and S i 0 2 are commonly used. However, since the thermal c o e f f i c i e n t s of expansion of these materials are not matched to that of GaAs, stresses occur during annealing which reduce the o v e r a l l a c t i v a t i o n and which also r e s u l t i n differences i n performance f o r otherwise i d e n t i c a l FETs aligned along d i f f e r e n t crystalographic axes [32]. In the past years several capless furnace anneal systems have been developed that use an overpressure of As gas near the wafer to prevent outgassing. The As gas i s usu a l l y obtained by pl a c i n g powdered InAs, which gives a higher p a r t i a l pressure than GaAs, i n a s p e c i a l boat which also contains the wafer [33]. Another method of capless annealing uses two GaAs wafers i n face-to-face contact [34]. In theory no other As sources are required but s i g n i f i c a n t outgassing can s t i l l occur near the edges of the wafers, thus reducing -61-y i e l d . Use of proximate contact annealing i n conjunction with As over-pressure has also been reported [35]. Another recent development that has seen much i n t e r e s t i n the l a s t few years i s the s o - c a l l e d r a p i d thermal anneal system [36,37,38]. Here the wafer i s r a p i d l y heated using i n f r a r e d l i g h t , such as that produced by high-i n t e n s i t y tungsten lamps, to temperatures s l i g h t l y higher than those used f o r furnace anneals but f o r durations of a few seconds rather than the 20 minutes or so normally used with furnace anneals. In p r i n c i p l e t h i s r a pid annealing should allow capless anneals to be performed without As over-pressure because the short times involved do not allow s i g n i f i c a n t out-d i f f u s i o n . By the same token chemical reactions with other materials i s minimized, as i s the r e d i s t r i b u t i o n of the implanted ions due to d i f f u s i o n . 4.2.2 Device i s o l a t i o n In a d d i t i o n to the active layer formation by one of the methods described i n the previous s e c t i o n an i s o l a t i o n step must be used so that those parts of the chip that are not required to be e l e c t r i c a l l y a c t i v e become, or remain, semi-insulating. This i s required both to eliminate interactions between t r a n s i s t o r s and to b u i l d high q u a l i t y passive components. There are three ways to achieve i s o l a t i o n : s e l e c t i v e ion-implantation into S.I. GaAs, i s o l a t i o n implantation and mesa etching, see f i g u r e 4.1. With s e l e c t i v e implantation an implant mask i s used to protect those areas of the wafer that are to remain semi-insulating from the ion beam during implant. A f t e r the implant the mask i s stripped o f f leaving the -62-DOPANT IONS \ \ \ \ \ \ \ ii I I J I I I J I I I . I I n j i I * J (a) ISOLATION IONS ^ ^ ^ ^ ^ ^ ^ I T T t . l l is.»i n . i r • • «i.r* n . i i r j 7 \X* X * X v %•%•••« v * x * y X * X \ > x x x J V x X K X X X 1 (b) i I I . I I *.*••* i^»y<|^n,» *»W V'J1 Y«« •< *• • V ** • V *• * V s • V *• • *•* •* • V •* V \* ••_•* • • (0 n-DOPED 6a As S.I. GaAs _ X X X X x* x x XXX x" * X " x » GaAS PHOTORESIST Figure 4.1 Device isolation methods: (a) selective ion-implantation, (b) isolation ion-implantation, (c) mesa etching. -63-desired pattern [39]. An i s o l a t i o n implant must be performed a f t e r the wafer has been annealed. An implant mask i s again used but i n t h i s case i t covers the desired active regions. A high dose, high energy implant i s then performed to damage the c r y s t a l l a t t i c e elsewhere, thus providing the semi-insulating property [40]. Ty p i c a l i s o l a t i o n implant species are protons, boron and oxygen. I s o l a t i o n implants can be used with both s e l e c t i v e and channel implants but are not normally used with e p i t a x i a l wafers because of the high a c c e l e r a t i n g voltages required to penetrate the few microns of the e p i t a x i a l layer. In the case of a mesa etch the active layer i s etched away from that part of the chip that i s to become semi-insulating. Special etchants are used to obtain sloping sidewalls which allow continuous m e t a l i z a t i o n between the mesa and the etched sections [41]. The advantage of s e l e c t i v e implantation and i s o l a t i o n implantation i s that they are completely planar which s i m p l i f i e s interconnect metalization. Sel e c t i v e implantation i s the simpler of the two but there i s some evidence that an i s o l a t i o n implant gives better i s o l a t i o n and reduces backgating [40], which i s the i n t e r a c t i o n of the gate of one t r a n s i s t o r on the I D S c h a r a c t e r i s t i c s of other nearby devices. Backgating i s not so much of a problem f o r MMICs as i t i s for d i g i t a l ICs with t h e i r much higher packing density. The advantage of mesa etching i s that i t can be used with e p i t a x i a l wafers and that i t provides very good i s o l a t i o n . -64-4.2.3 Gate formation The a c t i v e layer formation steps are common to a l l FET processes. The next steps can occur i n two d i f f e r e n t orders, depending on the type of technology being used. In the e p i t a x i a l processes, ohmic contacts are formed f i r s t and the gate deposited l a t e r . In the s o - c a l l e d s e l f - a l i g n e d processes, which a l l use ion-implantation f o r the active layer formation, the gate, or sometimes dummy gate, i s deposited f i r s t and acts as an implant mask f o r a second, high dose, implant which i s used to reduce the source and drain p a r a s i t i c resistances. Since the emphasis f o r the present work has been on s e l f - a l i g n e d gate technologies, gate formation f o r both types of processes w i l l be discussed f i r s t . In p r i n c i p l e , i t should be possible to use a high temperature stable gate material as an implant mask for the n +-implant. The gate must be able to withstand the high temperatures of the annealing cycle without s i g n i f i c a n t degradation or i n t e r a c t i o n with the GaAs channel. I f an implant energy of about 100 keV i s used for the n +-implant, the gate w i l l be i n very close proximity to the n + regions. This w i l l r e s u l t i n a very low breakdown voltage as w e l l as a very high gate f r i n g i n g capacitance. Yokoyama et a l . [42] proposed using a high-energy n + implant to move the doping peak deeper into the substrate and thus further away from the gate; a flow chart of t h e i r process i s shown i n fi g u r e 4.2. Although t h i s does improve the capacitance and breakdown c h a r a c t e r i s t i c s i t also increases the ser i e s resistance because the doping near the surface i s low. The l a t e r a l straggle - 6 5 -\ \ \ \ \ \ UWIIWIIlJUl t t l H t t im. ++ P59 Mi CHANNEL IMPLANT A N N E A L REFRACTORY 6ATE METAL DEPOSITION GATE DEFINITION ETCH n + OHMIC IMPLANT ANNEAL OHMIC CONTACT DEPOSITION ALLOYING SEMI-INSULATING GaAs PHOTORESIST • M.11 i i . i i * ••••• • • 4»r« n-DOPED 6aAs M GATE METALIZATION v +++ +++ n* -DOPED 68A8 OHMIC CONTACT METALIZATION Figure 4.2 Buried-channel r e f r a c t o r y metal self-aligned-gate process ( a f t e r Yokoyama et a l . [42] ). - 6 6 -i s also increased which l i m i t s how short the gate can be made before the source and drain n + regions short out the channel. Levy et a l . [43] found a simple s o l u t i o n to t h i s problem; a flowchart of t h e i r process i s shown i n fi g u r e 4 . 3 . A f t e r the channel implant has been done the whole wafer i s covered with gate metal. A second layer of material i s deposited on top of t h i s and patterned with the gate mask. The bottom ( gate ) metal i s then etched away using a plasma technique, the top metal having been chosen to have a slow r e a c t i o n rate with the plasma species used to etch the gate metal. The wafer i s over-etched to s l i g h t l y undercut the masking la y e r . When the wafer i s now implanted again f o r the ohmic contacts t h i s undercut provides the necessary separation between the n +-regions and the gate. A f t e r implantation the top metal i s removed, u s u a l l y using wet etching techniques, and the wafer i s annealed. Levy used TiW, which i s r a p i d l y etched by fluorine-based plasmas, as the gate metal and A l or Ni as the implant mask. This i s because pure W has poor adhesion to GaAs, and subsequent workers have also used WSi^ [ 4 4 ] , amongst others. The presence of T i , while g r e a t l y improving adhesion, i s thought by some to degrade device performance by re a c t i n g with the GaAs during annealing. The r e f r a c t o r y metal s i l i c i d e s do not s u f f e r from t h i s problem, but both adhesion and Schottky gate c h a r a c t e r i s i c s are very dependent on chemical composition, and they also have a s l i g h t l y higher r e s i s t i v i t y than the m e t a l l i c compounds. The choice of masking layer depends on the required stopping power and the desired ease of production, p o t e n t i a l materials being, amongst others, A l , Ni, Cr and photoresist. Photoresist i s the e a s i e s t to use -67-V Y V Y V V V CHANNEL IMPLANT ¥ V Y Y V Y V ANNEAL REFRACTORY BATE METAL DEPOSITION GATE IMPLANT MASK DEFINITION GATE DEFINITION ETCH (WITH UNDERCUT) n +OHMIC IMPLANT STRIP GATE IMPLANT MASK ANNEAL SEMI-INSULATING GaAs PHOTORESIST GATE IMPLANT MASK n-DOPED GaAs T.W GATE METALIZATION w l + ++J y s\ OHMIC CONTACT DEPOSITION ALLOYING * + + +++ + +++. |T -DOPED GaAs OHMIC CONTACT METALIZATION Figure 4.3 T-structure self-aligned-gate process ( after Levy et a l . [43] ). -68-but, being the l e a s t dense, has the lowest implant stopping power. Ni and Cr have much higher stopping powers but are more d i f f i c u l t to deposit and remove. A l i s e a s i l y evaporated and i s e a s i l y etched i n hydrochloric acid, and has acceptable stopping powers f o r most a p p l i c a t i o n s . A completely d i f f e r e n t approach to s e l f - a l i g n e d gate MESFET f a b r i c a t i o n was taken by Yamasaki et a l . [45]. Their technology, c a l l e d the S e l f - A l i g n e d Implantation of N +-Layer Technology ( SAINT ), i s shown i n f i g u r e 4.4. A f t e r s e l e c t i v e implantation of the channel n region, the wafer i s covered with a multilayer r e s i s t c o n s i s t i n g of PECVD Si 3 N 4 (1500 A), bottom photoresist (8000 A ) , sputtered S i 0 2 (3000 A) and top photoresist. The top photoresist i s patterned for the n + regions and i s used as a mask f o r the fluorine-based reactive ion etch of the Si0 2, a f t e r which the bottom photoresist i s over-etched using an oxygen-based reactive ion etch to obtain an undercut p r o f i l e . The remaining photoresist and S i 0 2 are used as the n + inplant, a f t e r which the wafer i s covered with RF magnetron-sputtered S i 0 2 . The S i 0 2 sidewalls are t h i n compared to the thickness of the f l a t areas and are e a s i l y etched away using buffered HF, followed by the removal of the remaining photoresist. A f t e r annealing, ohmic windows are etched through the S i 0 2 and S i 3 N 4 and ohmic contacts are deposited and alloyed. The l a s t step i s to etch the Si 3N A under the gate using the S i 0 2 as an etchmask, and pattern and deposit the gate metal. The gate length i s determined by the length of the bottom photoresist a f t e r the undercut etch, while the separation between the gate and the n + regions i s determined by the amount of undercut. Another type of s e l f - a l i g n e d technology was reported by Hagio et a l . - 6 9 -V V 11 —IT !«-•• I I J I I I J I I I J I H i l l J " V »J%,.»^ «.,.'^ V-J».V-.»«.<£/ V V V V V V V + + + + g ' ' A 1 | y i V J + + + + + + + + y % • + ++ + CHANNEL IMPLANT DEPOSIT SILICON NITRIDE DEPOSIT BOTTOM PHOTORESIST SPUTTER SILICON 0I0XIDE PATTERN TOP PHOTORESIST FOR n + IMPLANT REACTIVE ION ETCH SILICON DIOXIDE WITH UNDERCUT OF BOTTOM PHOTORESIST n T IMPLANT SPUTTER SECOND LAYER SILICON DIOXIDE ETCH SECONO LAYER SILICON DIOXIDE SIDEWALLS REMOVE REMAINING PHOTORESIST ANNEAL OPEN WINDOWS FOR OHMICS DEPOSIT OHMIC CONTACTS ALLOY ETCH GATE WINDOW THROUGH SILICON NITRIDE DEPOSIT GATE METAL SEMI-INSULATING GaAs PHOTORESIST FIRST LAYER SILICON DIOXIDE SECOND LAYER SILICON DIOXIDE • • • ^  • • • «. V*.. •••• n-DOPED GaAs + + ++ n -DOPED GaAs SILICON NITRIDE OHMIC CONTACT METALIZATION GATE METAL Figure 4 . 4 Self-Aligned Implantation of N+-layer Technology ( SAINT ) process ( after Yamasaki et a l . [45] ). -70-[46], a flowchart of t h e i r process i s shown i n figu r e 4.5. A f t e r channel implantation a dummy S i 0 2 gate i s formed and then covered with plasma-enhanced chemical vapour deposited Si 3N 4. The plasma deposition causes the n i t r i d e to cover the sides of the gates as well as the wafer surface. When the wafer i s then implanted, the n + regions are separated from the dummy gate by the thickness of the n i t r i d e layer. A number of s e l e c t i v e plasma etch steps are then done to expose the GaAs where the dummy gates were located. A n o n - c r i t i c a l photolithography step allows the gate metal to be deposited a f t e r which the the remaining masking layers are removed. As i n the SAINT process, the main advantage of t h i s process i s that the gate need not withstand the high annealing temperatures so that a lower r e s i s t i v i t y gate metal can be used. An advantage of t h i s technology over the SAINT process i s that the separation between the ohmic regions and the gate i s c o n t r o l l e d by a deposition rather than by an undercut etch, deposition being p o t e n t i a l l y more uniform across the wafer. 4.2.4 Ohmic contact formation The source and drain contacts of an FET should be n o n - r e c t i f y i n g and have a s u f f i c i e n t l y low resistance. The no n - r e c t i f y i n g c h a r a c t e r i s t i c i s obtained by having a very high ( >10 1 9 cm"2 ) donor concentration near the metal-semiconductor i n t e r f a c e , allowing the electrons to tunnel through the very narrow depletion region [47]. Ohmic contact resistance consists of two parts: the contact resistance of the in t e r f a c e and the sheet resistance of the semiconductor -71-\ \ \ \ \ \ \ CHANNEL IMPLANT SEMI-INSULATING GaAs n *i.>i n.rr rt'rr n,ir iicvv-jr K» •» • v s • v • v *• • v -v s •! SILICON DIOXIDE DUMMY GATE FORMATION PHOTORESIST PECVD SILICON NITRIDE DEPOSITION AND PATTERNING n r IMPLANTATION ANNEALING NITRIDE ETCH OHMIC CONTACT METALIZATION RESIST COATING RESIST PLASMA ETCH DUMMY GATE REMOVAL SILICON DIOXIDE n-DOPED GaAs ++ + + + + n -DOPED GaAs SILICON NITRIDE OHMIC CONTACT METALIZATION GATE METAL EVAPORATION AND LIFT OFF GATE METAL Figure 4.5 Sidewall-assisted pattern inversion process ( after Hagio et a l . [46] ). -72-between the ohmic area and the channel. Contact resistance i s reduced by increasing the c a r r i e r concentration at the surface, while sheet resistance i s reduced by increasing the c a r r i e r concentration or by e f f e c t i v e l y increasing the thickness of the doped layer. Ohmic contact sheet resistance reduction i s used with both e p i t a x i a l and ion-implanted FETs. E p i t a x i a l FETs use the gate recess technique to etch the channel to the desired t o t a l doping l e v e l . During e p i t a x i a l growth the epi layer i s made th i c k enough to provide the desired low sheet resistance. Since the channel i s etched anyways i t i s also possible to grow a t h i n n +-layer on top of the channel layer to further decrease sheet resistance. Most ion-implanted FETs use a second, high dose implant to decrease the sheet resistance of the ohmic contact areas. This can be accomplished e i t h e r by using a separate implant mask or by using one of the s e l f - a l i g n e d techniques described i n the previous section. The other component of ohmic resistance i s the contact resistance of the i n t e r f a c e between the ohmic metal and the semiconductor. The technique used almost u n i v e r s a l l y with GaAs i s to include a c e r t a i n amount of n-type dopant i n the ohmic contact metal. A f t e r evaporation and l i f t - o f f the ohmic contacts must be a l l o y e d to allow the dopant to d i f f u s e into the surface of the GaAs. Since the d i f f u s i o n depth i s small a very high surface doping concentration can be obtained. The most commonly used procedure i s to evaporate a e u t e c t i c mixture of AuGe ( 88-12% by weight ) which i s a l l o y e d at 400 - 500 °C f o r about 2 minutes. Ni i s often evaporated on top of the AuGe; i t apparently acts -73-as a wetting agent during a l l o y i n g and r e s u l t s i n improved ohmic character-i s t i c s as w e l l as gi v i n g a harder and more durable surface. A f t e r a l l o y i n g another, th i c k e r layer of Au i s often deposited to f a c i l i t a t e wirebonding. During the a l l o y i n g cycle the ohmic metal melts and forms small bumps on the surface of the contact ( see fig u r e 4.10, page 88 ). In general, the l a r g e r these bumps are the poorer the ohmic c h a r a c t e r i s t i c s w i l l be. Kuzuhara et a l . [48] reported an a l t e r n a t i v e technique which does not require an a l l o y i n g temperature above the AuGe e u t e c t i c point and which thus r e s u l t s i n a smooth surface morphology. The high surface donor concentration was obtained by ion-implanting S i at a dose and energy of >7xl0 1 3 cm"2 and 150 keV re s p e c t i v e l y . The implant i s a c t i v a t e d by r a p i d thermal annealing at 1120 °C for 5 seconds using a SiO xN y encapsulant, a f t e r which AuGe-Ni contacts are evaporated and l i f t e d o f f and the wafer i s b r i e f l y heated to 300 °C to activa t e the contact. 4.2.5 Passive components In a d d i t i o n to MESFETs, most MMICs w i l l also require passive components. The d i f f e r e n t types of passive components were b r i e f l y discussed i n section 1.3; t h i s s e c t i o n w i l l discuss the processing steps required to f a b r i c a t e them. Many passive components can be made using e s s e n t i a l l y the same processing steps as used f o r MESFET f a b r i c a t i o n , although often apparently redundant steps are added so as to not compromise FET y i e l d or c h a r a c t e r i s t i c s . There are two a d d i t i o n a l "components" that are often used which require a d d i t i o n a l -74-processing steps; these are airbridges and backside v i a holes. Airbridges are used where low capacitance crossovers are required, such as s p i r a l inductors and large gatelength power FETs. The f a b r i c a t i o n process i s shown i n f i g u r e 4.6. A f i r s t t h i ck layer of photoresist i s patterned to open holes where the a i r b r i d g e w i l l contact the f i r s t l ayer metal. A t h i n layer of metal i s then sputter deposited and a second photoresist layer i s used to define the a i r b r i d g e s . The exposed sputtered metal i s e l e c t r o - p l a t e d with gold to about 1 fim thickness a f t e r which the top photoresist i s removed. The e l e c t r o - p l a t e d gold i s then used as an etch mask to remove the undesired sputtered metal, a f t e r which the f i r s t layer of photoresist i s removed, leaving the f i n a l bridge. V i a holes are used when low inductance microwave grounds are required i n m i c r o s t r i p based designs. A f t e r a l l the topside processing i s done the wafer i s thinned from the backside to the f i n a l thickness, u s u a l l y between 100 and 200 /jm, and the backside i s patterned and etched. Infrared mask align e r s are u s u a l l y used to a l i g n the back to the front. Great care must be taken a f t e r thinning because the t h i n wafers are very f r a g i l e . With the processing steps discussed so f a r , a l l MMIC passive and active components can be f a b r i c a t e d . For most devices a choice of possible technologies e x i s t s with the f i n a l d e c i s i o n being based on c i r c u i t requirements such as tolerance and r e l i a b i l i t y , and production constraints such as a v a i l a b l e equipment and cost. Resistors can be made ei t h e r by sputter depositing a t h i n f i l m r e s i s t i v e material or by using n-doped GaAs. In the l a t t e r case a separate recess etch ( for e p i t a x i a l wafers ) or implant ( f o r ion-implanted wafers ) i s often used to allow independent - 7 5 -I l l l l l l l l l LUTJ l l l l l l l l l l l l i l l l STARTING WAFER WITH FIRST LEVEL METALIZATION PATTERN SUPPORT PHOTORESIST DEPOSIT THIN CONDUCTIVE LAYER PATTERN BRIDGE PHOTORESIST ELECTROPLATE Au BRIDGE CONDUCTOR REMOVE PHOTORESIST ETCH THIN CONDUCTIVE LAYER I 1 GaAs WAFER fflTTJJJ FIRST LEVEL METALIZATION V////A PHOTORESIST THIN CONDUCTIVE GOLD LAYER AIRBRIDGE Figure 4.6 Airbridge fabrication process. -76-optimization of FET channel parameters and r e s i s t o r c h a r a c t e r i s t i c s . The sputtered r e s i s t o r requires s l i g h t l y more processing but can be more accurate and uniform and have a lower temperature c o e f f i c i e n t of resistance than the semiconductor r e s i s t o r , which takes up les s space. Capacitors can be made eit h e r with a planar i n t e r d i g i t a t e d structure or using a metal-insulator-metal ( MIM ) sandwich structure. The i n t e r d i g i t a l capacitor i s more repeatable ( but much harder to model ), easier to make and has a higher y i e l d than the MIM capacitor but i s l i m i t e d i n value to about 1 pF. For larger values an MIM capacitor i s required; sputtered Si0 2 or Ta 20 5 or plasma-deposited S i 3 N 4 are the usual d i e l e c t r i c s and an air b r i d g e i s often used to connect the top plate to the r e s t of the c i r c u i t to reduce the chance of a short c i r c u i t at the edge of the capacitor. Inductors are e i t h e r simulated using a short length of high impedance l i n e or made as a loop inductor. M u l t i t u r n inductors require an airbridge to access the centre of the inductor, or a v i a hole can be used i n the case of shunt elements. Coupled inductors have also been demonstrated using these techniques. 4.3 Refractory metal s e l f - a l i g n e d gate MESFET f a b r i c a t i o n technology The r e f r a c t o r y metal s e l f - a l i g n e d gate MESFET f a b r i c a t i o n technology developed at the U n i v e r s i t y of B r i t i s h Columbia i s c l o s e l y based on that by Levy and Lee [43] and Sadler [35]. The complete process of MESFET f a b r i c a t i o n requires f i v e masks, while a s i x t h mask i s required f o r the MIM capacitor of the sample-and-hold. The UBC process d i f f e r s s i g n i f i c a n t l y i n -77-the wafer cleaning procedures, the photolithography steps and the annealing conditions. There are several other minor modifications such as the use of a plasma etch rather than a reactive ion etch ( RIE ) to undercut the gate mask and the choice of implant dose and energy to obtain depletion mode rather than enhancement mode FETs. A flowchart of the MMIC process i s shown i n fig u r e 4.7; a d e t a i l e d step by step d e s c r i p t i o n follows i n table 4.1. The development of t h i s processing technology i s to a large extent an evolutionary process of t r i a l and error; when a p a r t i c u l a r run does not y i e l d expected r e s u l t s i t i s often d i f f i c u l t to i s o l a t e the step that caused the problem. Although the process described here gives reasonable devices i t i s by no means f u l l y mature. The main steps that could use improvement are discussed below, as are those that are not self-explanatory. Steps 1-2 Wafer cleaning The wafers are received at UBC with both sides polished. The p o l i s h i n g i s done using a combination of chemical and abrasive means. The r e s u l t i n g surface damage, and also possible surface contamination, can cause inconsistent and poor r e s u l t s . Therefore, the surface layers are removed by etching p r i o r to subsequent processing. Step 1 i s used to thoroughly degrease and clean the wafer, immediately thereafter step 2 i s used to etch about 2 pirn from the surface i n a slow and uniform manner. The same etching s o l u t i o n i s also used f o r the r e g i s t r a t i o n mark etch, allowing the etch rate and hence the surface etch depth to be determined from the r e g i s t r a t i o n mark depth and etch time. -78-V V Y Y V V V CHANNEL IMPLANT SEMI-INSULATING GaAs n r T T T n T T J T T T j Y Y Y Y Y Y Y REFRACTORY GATE METAL DEPOSITION GATE IMPLANT MASK DEFINITION GATE DEFINITION ETCH (WITH UNDERCUT) n +OHMIC IMPLANT STRIP GATE IMPLANT MASK ANNEAL PHOTORESIST GATE IMPLANT MASK rrrTTrnTira y s l v •» • Z* v V i V i i i ' n-DOPED GaAs TiW GATE METALIZATION r f F f r s • •••» V + + + ++ OHMIC CONTACT DEPOSITION ALLOYING • :+++. rr -DOPED 6aAs OHMIC CONTACT METALIZATION ure 4.7 UBC refractory metal self-aligned-gate MESFET fabrication process flowchart. -79-TABLE 4.1 DETAILED SELF-ALIGNED GATE PROCESS LOG STEP PROCESS 1 Wafer cleaning 2 Surface etch (=2 /zm) 3 Photoresist deposition 4 R e g i s t r a t i o n mark exposure and develop 5 R e g i s t r a t i o n etch 6 S t r i p photoresist 7 Photoresist deposition 8 Channel exposure 9 Light cleaning etch 10 Channel implant 11 Photoresist s t r i p 12 Light cleaning etch DESCRIPTION * 1% Alconox s o l u t i o n (NaH2P04) , 4 min * DI rinse, 1 min, N 2 blow dry * b o i l i n g acetone, 5 min * b o i l i n g isopropanol, 5 min * 2H 20 2: 5NH40H: 240H20, 27°, 10 min * DI ri n s e , 30 sec * b o i l i n g isopropanol, 5 min * spin-on S1400-30, 4000 rpm, 20 sec * softbake 95°, 25 min, cooldown * 320 ran, 20 mWcnf2, 30 sec * spray develop, 30 sec ( 37 sec i f chlorobenzene treatment used ) * DI ri n s e , 15 sec * 2H 20 2: 5NHA0H: 240H20, 27°, 30 sec * DI ri n s e , 15 sec * b o i l i n g acetone, 5 min * b o i l i n g isopropanol, 5 min * as i n step 3 * as i n step 4 * 1H 20 2: 1NH40H: 240H20, 27°, 3 sec * DI ri n s e , 15 sec * 10% NHA0H, 1 min ( Ga 20 3 removal ) * BHF, 1 min ( As 20 5 removal ) * DI ri n s e , 10 min * N 2 blow dry * 2 9 S i , energy=100 keV, dose=2.5xlO- 1 2cnT 2 * wafer o r i e n t a t i o n : 7° t i l t , 22° r o t a t i o n * b o i l i n g acetone, 10 min * "microstrip", 90°, 5 min * DI ri n s e , hot, 15 sec * b o i l i n g acetone, 5 min * b o i l i n g isopropanol, 5 min * N 2 blow dry * as i n step 9 -80-13 Gate metal deposition TiW, 2000 A * r f sputter deposition, Ar atmosphere, 100 W, 33 mTorr, 22 min 14 Gate metal patterning and exposure 15 Gate implant mask deposition 16 L i f t o f f 17 Gate undercut etch 18 n + patterning and exposure 19 Light cleaning etch 20 N + implant 21 Photoresist s t r i p 22 A l removal 23 Light cleaning etch 24 S i 3 N 4 encapsulent deposition 25 Implant anneal 26 S i 3 N 4 removal 27 S i 3 N 4 p a s s i v a t i o n and capacitor d i e l e c t r i c deposition 28 Ohmic contact patterning and exposure * S1400-30, 4000 rpm, 20 sec * softbake 95°, 25 min, cooldown * immerse i n chlorobenzene, 2.5 min * expose as i n step 4 * evaporate 4400 A A l ( or 3500 A Cr ) * b o i l i n g acetone, gentle a g i t a t i o n * CF 4/0 2 plasma, 100 W, 500 mTorr 120° CF 4 = 200 seem, 0 2 •= 8 seem, 2 min * as i n steps 3-4 * as i n step 9 * 2 8 S i , 100 keV, l x l 0 1 3 c n f 2 * wafer o r i e n t a t i o n as i n step 10 * as i n step 11 * warm cone. HC1, 1 min * as i n step 9 * NH3 plasma preclean, 5 min * plasma deposition, 500 A, 300°, 100 W 1500 mTorr, He = 500 seem, SiH 4 = 550 seem, NH3 =37.6 seem * Minibrute furnace, 825°, 25 min 1 -0/min N 2 atmoshere * 40% HF, 3 min, buffered HF, 1.5 min * DI r i n s e , 10 min * as i n step 24 * as i n step 14 29 L i g h t cleaning etch * as i n step 9 -81-30 Ohmic deposition * 31 L i f t o f f * 32 A l l o y * 33 Ohmic gold and * capacitor top plate patterning and exposure 34 Au deposition * 35 L i f t o f f * evaporate AuGe (88-12%), 2000 A, Ni, 200 A as i n step 16 Minibrute furnace, 425°, 2 min, 1 i/min N 2 atmosphere as i n step 14 evaporate 2000 A Au as i n step 16 -82-Step 6 Photoresist strip A number of d i f f e r e n t techniques are used depending on the d i f f i c u l t y of removal. In most cases b o i l i n g acetone i s s u f f i c i e n t , but a f t e r implants the r e s i s t i s damaged and requires the use of 0 2 plasma or "microstrip" remover. There i s no apparent damage to the GaAs by any of these methods. Step 9 Light cleaning etch I t was found that the device c h a r a c t e r i s t i c s are strongly a f f e c t e d by any surface contamination. The cleaning process used here removes about 50 A from the surface which does not s i g n i f i c a n t l y a l t e r the doping p r o f i l e even a f t e r repeated a p p l i c a t i o n and i s organic contaminant free. I t i s used before each implant and each metal or n i t r i d e deposition. Step 13 Gate metal deposition This step was previously proceded by an i n s i t u Ar sputter etch of the GaAs before deposition. The r e s u l t i n g poor a c t i v a t i o n i s thought to be due to the surface stoichiometry change caused by the l i g h t e r Ga atoms being more e a s i l y sputtered than As. Step 14 Gate metal patterning and exposure A chlorobenzene soak i s used here before developing to remove the solvents from the top layer of photoresist. The r e s u l t i n g harder top layer develops more slowly than the r e s t of the photoresist so that an overhanging r e s i s t p r o f i l e i s obtained. During subsequent metal evapo-r a t i o n t h i s overhang ensures a d i s c o n t i n u i t y between the desired and undesired me t a l i z a t i o n areas which eases l i f t o f f . Step 16 L i f t o f f -83-I f necessary, a b r i e f immersion i n an u l t r a s o n i c bath can a i d l i f t o f f , but i f overdone t h i s can also remove the A l implant metal from the desired areas. Step 25 Anneal O r i g i n a l l y two anneals were done, one a f t e r each implant, but better a c t i v a t i o n was achieved with only one anneal a f t e r the i s o l a t i o n implant. The annealing temperature i s r e l a t i v e l y low compared to conventional furnace anneals to minimize i n t e r a c t i o n s between the TiW and the GaAs. A f a i r b i t of experimentation was done using rapid thermal annealing, and although the best runs gave better a c t i v a t i o n s than the best furnace anneals, the r e s u l t s were not reproducible from run to run. This might be a t t r i b u t a b l e to the use of wafers from d i f f e r e n t suppliers and d i f f e r e n t boules, and since r a p i d thermal annealing seems to be p o t e n t i a l l y superior i t warrants further i n v e s t i g a t i o n . Step 27 S i 3 N 4 p a s s i v a t i o n and capacitor d i e l e c t r i c deposition A separate n i t r i d e layer i s used rather than the annealing cap to minimize the p r o b a b i l i t y of pinhole shorts. Step 32 Ohmic contact a l l o y i n g Some work was done to investigate the use of the r a p i d thermal anneal technique to a l l o y the ohmic contacts. As i n the case of the channel anneal t h i s i s promising but needs more i n v e s t i g a t i o n . The sample-and-hold mask set layout i s shown i n f i g u r e 4.8. To reduce cost, three mask layers were put on each mask so that only one out of three rows on the wafer contains u s e f u l devices. The bottom row of figure 4.8 -84-contains the input b u f f e r amplifier, a dual gate switch, an MIM capacitor and the output b u f f e r a m p l i f i e r . On the top row there are d i s c r e t e single and dual gate t r a n s i s t o r s , a diode and a capacitor f o r t e s t i n g purposes. A photomicrograph of the chip i s shown i n figu r e 4.9, an SEM closeup of a dual gate FET a f t e r removal of the n i t r i d e i s shown i n f i g u r e 4.10. The gate lengths are about 0.5 Lim with about 4 Lira spacing between the gates. The nonuniform texture of the ohmic contacts i s also v i s i b l e . -85-Ed < < E-Ed Eb CO Ed as co Eb Eb 03 Et] t—I E- Eb a. _2 E- 0* o«* Ed a o o i—i o s: a, i—i «C £ U X o E-»—i 3 CO w E-< <c a Ed E-4 O Ed E-_] Ed O EL, Z CO .-. » CO X D a Ed Eb a O Ed CQ i-t Eb E- i-t a, a. Z X Figure 4.8 Sample-and-hold mask layout. -86-Figure 4.9 Photomicrograph of sample-and-hold chip. -87-I 1 5 ym Figure 4.10 Scanning electron micrograph of dual gate MESFET. - 8 8 -CHAPTER 5 MEASUREMENT TECHNIQUES AND RESULTS 5.1 Introduction The measurement of device parameters and performance i s a v i t a l and non-t r i v i a l part of the development of a processing technology [49]. In t h i s chapter the measurement techniques used to evaluate device performance w i l l be discussed and r e s u l t s presented. The measurements used can be divided into two categories, low frequency or s t a t i c measurements which give information about the the i n d i v i d u a l device model parameters, and microwave measurements which give information about the high frequency c h a r a c t e r i s t i c s of the device as a whole. I f measurements and modeling are c a r r i e d out c o r r e c t l y there should be good correspondence between the low frequency and the high frequency r e s u l t s . The emphasis i n t h i s thesis i s on low frequency measurements. The reasons f o r t h i s can be summarized as follows - a v a i l a b i l i t y of t e s t equipment -ease of wafer scale t e s t i n g -ease of i s o l a t i n g device parameters -can be done at d i f f e r e n t points i n the f a b r i c a t i o n process. Two catagories of low frequency measurements can be distinguished. Capa-citance versus voltage ( CV ) measurements can be made of reverse biased Schottky b a r r i e r diodes to obtain doping p r o f i l e s . Current versus voltage ( IV ) measurements can be made of diodes to obtain reverse saturation current, i d e a l i t y f a c t o r and b a r r i e r height, and of t r a n s i s t o r s to obtain -89-saturated current, threshold voltage, transconductance and source and drain resistance. In the following sections the techniques used to make these measurements w i l l be presented. 5.2 Diode measurements The most important a p p l i c a t i o n of diode measurements i s to determine the q u a l i t y of the channel anneal step. This i s p a r t i c u l a r l y important i n a r e f r a c t o r y metal-based s e l f - a l i g n e d gate technology since the gate i s present during the anneal and can p o t e n t i a l l y react with the GaAs. CV measurements using a HP4061A LCR meter c o n t r o l l e d by a HP9816 computer are performed on large area diodes to determine the doping p r o f i l e of the active layer. The doping p r o f i l e ND(W) i s obtained by measuring the capacitance at d i f f e r e n t bias l e v e l s and applying the following formulas. The capacitance per un i t area i s C(V) = e/W(V) (5.1) where W(V) i s the depletion width at bias voltage V, and ND(W) = ( -2/q€ ){ d(l/C 2)/dV }_1 (5.2) This method of obtaining the doping p r o f i l e i s l i m i t e d to a small forward bias on the diode. I f the bias i s increased too much the r e s u l t i n g current makes accurate determination of the capacitance impossible. Accurate -90-determination of the doping p r o f i l e near the surface i s thus not possible with t h i s technique. A t y p i c a l doping p r o f i l e i s shown i n fi g u r e 5.1. with the "best f i t " LSS p r o f i l e c a l c u l a t e d using a program written by David Hui. Diode IV measurements are made using the HP4145A semiconductor parameter analyzer. The parameters of i n t e r e s t are the i d e a l i t y f a c t o r n, the reverse sat u r a t i o n current I 0 , the Schottky b a r r i e r height <j>h and the diode series resistance Rs. The basic diode equation, neglecting Rs, i s I(V) = I 0[ exp( qV/nkT ) - 1 ] (5.3) For V > ~ 3nkT/q the fa c t o r 1 can be neglected, and taking the natural logarithm of both sides and d i f f e r e n t i a t i n g with respect to V gives d ln(I)/dV = qV/nkT + l n ( I 0 ) (5.4) P l o t t i n g l n ( I ) versus V y i e l d s a s t r a i g h t l i n e f o r a l i m i t e d range of V, the slope of which i s proportional to 1/n and the y-intercept of which i s I 0 , which can be used to obtain <f>h from <f>h = ( kT/q )ln( A**T 2S/I 0 ) (5.5) where where A** = 8.4 Acm"2K"2 i s the e f f e c t i v e Richardson constant f o r GaAs and S i s the area of the diode [35]. A t y p i c a l diode IV p l o t obtained with the HP4145A i s shown i n figure 5.2. The analyzer i s programmed to c a l c u l a t e n d i r e c t l y to f a c i l i t a t e measuring a -91-Figure 5.1 Typical capacitance/voltage doping profile. - 9 2 -LNI ) CURSOR ( MARKER (• IF 3400V . 2300V . •296E-03 •491E-03 6.356mA ) •5.940nA ) (mA) 119.71 E-03 48.47 /div -604.4 -.5000 10.00 j 1.000 /div .0000 2500/div ( V) 2.000 1/GRAD j Xintercept| Yinterceptj LINEl! 911EHD3_j 1_. 10_E+00i 666E-03 [ -606E-03 LINE2J 1 " 1 " " " " - ] LNI ( ) 26E-3*LN (ABE (I) ) Figure 5.2 Typical diode current/voltage plot. -93-large number of devices. T y p i c a l l y , n ~ 1.1 for r e f r a c t o r y metal s e l f -aligned gate devices. As the voltage i s increased the l i n e a r dependance of l n ( I ) on V breaks down due to the presence of the p a r a s i t i c s e r i e s resistance Rs. As the voltage i s increased the voltage drop across the resistance dominates the drop across the diode so that a p l o t of I versus V gives another s t r a i g h t l i n e with slope 1/RS. 5.3 T r a n s i s t o r measurements Accurate measurement of t r a n s i s t o r parameters i s important to study the e f f e c t s of changes i n processing steps and to allow r e a l i s t i c modelling of l a r g e r scale c i r c u i t s to be performed. The MESFET model used i n the simulations i n t h i s thesis i s a symmetric square law model, with the gate-source and gate-drain j u n c t i o n e f f e c t s given by a Schottky diode model [50], the general equivalent c i r c u i t i s shown i n fig u r e 5.3. The diode parameters I 0 , n and <j>b can be obtained i n the manner discussed i n s e c t i o n 5.2 Because of the small gate area of microwave t r a n s i s t o r s i t i s not po s s i b l e to d i r e c t l y obtain accurate gate capacitance measurements. Gate capacitances can be measured on s o - c a l l e d f a t FETs which can have gate lengths and widths of 100 firn or more. The zero bias gate capacitance i s measured with the source and drain t i e d together and y i e l d s a depletion capacitance per u n i t area. Since with a s e l f - a l i g n e d gate process the t r a n s i s t o r i s p h y s i c a l l y the same on both the source and the drain side, the -94-Figure 5.3 Symmetric MESFET model equivalent c i r c u i t ( after Curtice et a l . [50] ). -95-zero bias gate-source and gate-drain capacitances should also be the same and can be obtained from the f a t FET values by m u l t i p l y i n g by the gate area. As mentioned i n section 3.3, for small gate length t r a n s i s t o r s there w i l l also be a s i g n i f i c a n t f r i n g i n g capacitance from the edges of the gate; t h i s i s shown schematically i n fi g u r e 5.4, assuming a uniform doping p r o f i l e and ignoring the proximity of the source and drain n + regions [51]. The depletion region i s divided into two regions. Region I i s the one-dimensional region under the gate, the standard depletion capacitance formulas are assumed to hold here. Region II consists of two quarter-c i r c u l a r regions on e i t h e r side of the gate, with radius W, where W i s the depletion width of region I. Then, W = J{ ( 2e/qND )( V b i - V - kT/q ) } cm (5.5) Q = qNDLW + 4qND7rW2 C (5.6) ^ T O T A L " I 5Q/aV | - e( L/W + Tr ) Fern"2 (5.7) Eqation 5.7 gives the t o t a l gate capacitance per u n i t gate width, and, since the t r a n s i s t o r i s assumed to be symmetric, the drain and source components w i l l both be given by C T 0 T A L/2. The zero bias source and drain capacitances required by the model are then given by CGSO = C G D 0 = 7( qN DeL 2/8V b i ) + Tre/2 Fern"1 (5.8) -96-GATE per cm of gate width. The f i r s t term can be obtained from diode or f a t FET data so that no d e t a i l e d knowledge of the doping p r o f i l e i s required. The FET channel current i n the saturation regime can be modelled by I D S " K ( V G S " V T ) 2 ( 1 + A V D S ) ( T A N H « V D S ) ( 5 - 9 ) where V T i s the threshold voltage, and K, A and a depend on the device geometry and semiconductor parameters [47,50]. A t y p i c a l p l o t of , / l D S versus V G S i s shown i n figu r e 5.5. I t f i t s the l i n e a r approximation quite w e l l . V T i s defined as the x-axis intercept of the quadratic region asymptote and K i s given by the square of i t s slope. The v a r i a t i o n of I D S i n the l i n e a r regime i s c o n t r o l l e d by the hyperbolic tangent parameter a. I t can be determined from the slope of I D S for small V D S as A I D S / A V D S a = K-VT2 (5.10) V G S= 0, V D S « V D S_ s a t The channel length modulation parameter A i s often used i n computer simulation programs to account f o r the small slope of I D S versus V D S i n the sat u r a t i o n regime; i t can be evaluated from AI D S/AV D S A = K-VT2 (5.10) v G S= o, v D S> V D S t The measurement of source and drain resistances i s more complicated -98-if A) CURSOR (-2.4200V MARKER (-3.0000V 124.0 E-03 16.6E-03. 2.80E-03, 12.39 /div 1580 -3.440 4300 VG .4 ,300/div ( V) GRAD 1/GRAD Xintercept Yintercept LINE1 32.1E-03 31.1E+00 -2.94E+00 94.3E-03 LINE2 SQBT (/A) - /IS Figure 5.5 Typical plot of J l o s voltage VT and gain parameter K versus V G S used to determine threshold -99-because of the d i f f i c u l t y of i s o l a t i n g the p a r a s i t i c resistances, which are not modulated by the applied gate voltage, and the channel resistance, which i s . The method used i n t h i s thesis was proposed by Lee et a l . [52] and i s shown schematically i n fig u r e 5.6. In t h i s setup the gate i s s l i g h t l y forward biased with respect to the source so that a small gate current flows. At the same time, a constant current source i s used to obtain a small d r a i n current while the drain-source voltage i s monitored as the gate current i s perturbed s l i g h t l y . As the drain current increases the drain side of the gate becomes inc r e a s i n g l y reverse biased and the gate current gets concentrated i n the source side of the channel. The d i f f e r e n t i a l end resistance R e n d i s defined as Rend avD S a i G S (5.12) Ipg—const and i n [52] i t i s shown that, f o r a l i m i t e d range of I D S , t h i s becomes Rend = R s + nkT/qI D S (5.13) Thus, by p l o t t i n g AV D S/AI G S versus 1/I D S and f i n d i n g the y-axis intercept of the l i n e a r p o r t i o n with slope nkT/q one can determine Rs. By reversing the source and d r a i n terminals one can obtain RD. A t y p i c a l p l o t i s shown i n fi g u r e 5.7. -100--101-REND (ft ) CURSOR ( 454E+00 . 30.0E+00. 50.00 E+00 5.000 /div .0000 MARKER [ 454E+0I d . 30.0E+00. ) / / -\ r / f / / / • / / * • .0000 1.500 IDINV .1 500/div ( ) E+03 GRAD 1/GRAD Xintercept Yintercept LINE1 52.6E-03 19.0E.00 -117E+00 6.18E+00 LINE2 REND (O ) - AVDS/AIG IDINV ( ) - 1/ID Figure 5.7 Typical end-resistance plot giving Rs. -102-Another parameter which i s commonly used i s the transconductance defined as a iDS (5.14) Vpg=const I t i s u s u a l l y expressed i n millisiemens per millimeter of gate width. I t i s a small s i g n a l parameter, however, and depends strongly on operating point; i t i s most often measured at V G S = 0 or V G S = +0.8 V. A t y p i c a l p l o t of versus V G S i s shown i n f i g u r e 5.8. For comparison purposes the K-factor defined e a r l i e r i s a more unive r s a l f i g u r e of merit since i t i s not operating point dependant. The model parameters f o r a t y p i c a l recent FET are given i n table 5.1. These parameters are used i n the SPICE simulations of chapter 3. To show the v a l i d i t y of at l e a s t the s t a t i c part of the model, the simulated and measured t r a n s f e r curves of t h i s FET are shown together i n f i g u r e 5.9. -103-(mS) CURSOR ( .OOOOV MARKER ( ,6000V 5.98E+00. 7.17E+00 E+00 6976 /div 0000 -3.440 1 - 1 r i ^ _ . I i . \ i cn I i i j ! ! .... ( i ( ! ! I 1 r ! i ---f-— VG 4300/div 0 .4300 ( V) SQRT if A) - /IS GM (mS) - 1000KAID/AVG Figure 5.8 Typical plot of transconductance g,,, as a function of gate bias. -104-PARAMETER SPICE DESIGNATION VALUE Threshold voltage, V T VTO -1.80 V Hyperbolic tangent parameter, a ALPHA 0 . 8 6 Transconductance parameter, /9 BETA 2 . 6 8 X 1 0 " 3 A/V2 Channel length modulation parameter, A LAMBDA 2xl0" 5 Source resistance, Rg RS 6.17 n Drain resistance, RD RD 20.7 n Gate resistance, R Q RG 3 kfi Zero-bias gate-source capacitance, C G S 0 CGSO 0.28 pF Zero-bias gate-drain capacitance, C G D 0 CGDO 0.28 pF Gate diode ideality factor, n N 2.2 Gate b u i l t - i n potential, ^ b VBI 0.8 V Drain-source capacitance, C D S CDS 0.07 pF Table 5.1. Self-aligned gate MESFET model parameters used in SPICE simulations. -105-EEsof - mwSPICE r- 5/9/BB - 16: IB: 14 - DTA SAGFET . IDS REAL 0.0150 0.0050 — • 1' m • • • < • • ! •« 1 • • • • < L » * • • • _. ,. . . a — • • 0.0000 1.500 VDS 3.000 Figure 5.9 UBC self-aligned gate MESFET transfer curves: ( ) measured, ( • • • ) simulated. -106-CHAPTER 6 CONCLUSIONS AND SUGGESTIONS FOR FUTURE WORK The work done i n t h i s thesis can be divided into two sections. The f i r s t deals with high speed sampling and i t s a p p l i c a t i o n to the sampling amp l i f i e r concept developed at the Defense Research Establishment Ottawa ( DREO ). A l i t e r a t u r e survey was done to determine the state of the a r t for high speed sampling c i r c u i t s . I t was found that the highest speed e l e c t r o n i c sampling i s achieved using s o l i d state mechanical sampling heads used i n sampling o s c i l l o s c o p e s , with bandwidths of about 18 GHz. The highest speed monolithic c i r c u i t s are made with gallium arsenide and have bandwidths of about 2 GHz. Some of the d i f f e r e n t types of sample-and-hold c i r c u i t s were discussed, ranging i n complexity from a single switch and storage capacitor to multistage feedback c i r c u i t s . The important parameters of the two most common types of switch were also investigated. I t was found that the s i x diode r i n g switch can handle the l a r g e s t voltage swing but requires a balanced current switch drive, which can be d i f f i c u l t to obtain i f a number of switches are to be used i n p a r a l l e l at a high sampling rate. The FET switch uses a single-ended voltage drive and i s therefore more sui t e d f o r a p p l i c a t i o n s , such as the sampling a m p l i f i e r , r e q u i r i n g a large number of switches i n p a r a l l e l . High speed switching w i l l require the use of GaAs MESFETs so that the maximum allowable voltage swing w i l l be l i m i t e d to about 0.5 V by the conduction of the forward biased gate diode. The use of a dual-gate MESFET to reduce sample pulse feedthrough, as was reported i n [18], was investigated and found to have minimal e f f e c t i n most p r a c t i c a l a p p l i c a t i o n s . -107-The e f f e c t s of sampling c i r c u i t parameters on the performance of the sampling a m p l i f i e r were investigated i n chapter 3. I t was found that the main f a c t o r determining the number of channels that can be used without introducing excessive loss i s the input impedance of the sampling c i r c u i t s . In order to minimize t h i s l o s s , high input-impedance b u f f e r am p l i f i e r s are required to i s o l a t e the switches from the delay l i n e . The performance of one such a m p l i f i e r was analyzed using a s i m p l i f i e d low frequency model as well as simulated using the computer program Microwave-SPICE. The performance of t h i s a m p l i f i e r should be adequate up to at l e a s t 10 GHz. The other main area of i n v e s t i g a t i o n i n t h i s thesis i s the technologies used i n the manufacture of gallium arsenide monolithic integrated c i r c u i t s . The main components used i n MMICs were discussed, and the most important processing technologies reported i n the l i t e r a t u r e were discussed In some d e t a i l . Much work i s being done to develop s e l f - a l i g n e d gate technologies, which have the advantages of maintaining a planar structure and being p o t e n t i a l l y simpler to manufacture, as well as having improved speed performance due to the reduction of p a r a s i t i c source and drain resistances by reducing the spacing between the gate and the ohmic n + regions. The development of a r e f r a c t o r y metal T-gate s e l f - a l i g n e d gate process technology at the U n i v e r s i t y of B r i t i s h Columbia was presented; i n t h i s process the distance between the gate and the ohmic regions i s determined by the amount of undercut of the gate implant mask. The gate material i t s e l f i s present during the anneal, and much e f f o r t was required to determine the best annealing conditions i n order to obtain adequate a c t i v a t i o n without excessive i n t e r a c t i o n between the titanium-tungsten gate material and the -108-gallium arsenide. Chapter 5 deals with the measurements used to characterize the performance of the Schottky diodes and MESFETs made at UBC. The emphasis i s on dc measurements since i t i s easier to i s o l a t e the various parameters, and the measurements themselves are easier to perform. The measurement methods used to obtain the various model parameters used for computer simulation were given and r e s u l t s given f o r some recently f a b r i c a t e d FETs. The simulation r e s u l t s showed good agreement with the measured values. A t e s t j i g was made to allow measurement of the microwave parameters of one of the b e t t e r FETs at Harris/Farinon i n Montreal, but the FET was damaged i n t r a n s i t to Montreal so that no measurements were poss i b l e . The f a b r i c a t i o n steps used to make di s c r e t e devices are r e a d i l y extended to allow f a b r i c a t i o n of a complete monolithic sample-and-hold c i r c u i t , i n c l u d i n g input and output b u f f e r a m p l i f i e r s , a MESFET sampling switch and a hold capacitor. In the i n i t i a l mask design, the sum of the widths of the input and feedback t r a n s i s t o r s was not chosen to be equal to the width of the current source t r a n s i s t o r . This r e s u l t e d i n a s i g n i f i c a n t dc o f f s e t which caused the output stages to be turned o f f under normal operation, no measurements of a m p l i f i e r performance were therefore p o s s i b l e . Most of the future work w i l l be required i n the processing area. The main areas of i n t e r e s t are the use of r a p i d thermal annealing to anneal the channel and n + implants without using a d i e l e c t r i c annealing cap and with minimum i n t e r a c t i o n between the gate and the gallium arsenide as well as to a l l o y the ohmic contacts. The p h y s i c a l e f f e c t s of the i n t e r a c t i o n between the gate material and the substrate during anneal could also warrant -109-i n v e s t i g a t i o n . The use of the s e l f - a l i g n e d gate processing technology to f a b r i c a t e a complete sample-and-hold c i r c u i t should be attempted. For the sampling a m p l i f i e r , a high sampling rate i s not required so one of the multistage sampling c i r c u i t s discussed i n chapter 2 could be used. The bu f f e r a m p l i f i e r topology discussed i n chapter 3 should be s u i t a b l e i f the gate dimensions are appropriately chosen; the dimensions given i n fi g u r e 3.7 suggested. Given su i t a b l e drive c i r c u i t r y , maximum sampling rates of at l e a s t 1 GHz should be attainable, with sampling times of le s s than 100 ns -110-REFERENCES R.E. Lehmann and D.D. Heston, " X-band monolithic ser i e s feedback LNA," IEEE Trans. Microwave Theory and Techniques, Vol. MTT-33, No.12, Dec. 1985. C. Andricos, I.J. Bahl and E.L. G r i f f i n , " C-band 6-bit monolithic phase s h i f t e r , " IEEE Trans. Microwave Theory and Techniques, Vol. MTT-33, No.12, Dec. 1895. S.D. Bingham, S.D. McCarter and A.M. Pavio, " A miniaturized 6.5-16 GHz monolithic power am p l i f i e r module," IEEE Trans. Microwave Theory and Techniques, Vol. MTT-33, No.12, Dec. 1895. Y. A y a s l i , R.A. Pucel, J.L. Vorhaus and W. Fabian, "A monolithic X-band single-pole, double-throw b i d i r e c t i o n a l GaAs FET switch," 1980 IEEE GaAs IC symposium digest. S. Hori, K. Kamei, K. Shibata, M. Tatematsu, K. Mishima and S. Okiano, " GaAs monolithic MIC's f o r d i r e c t broadcast s a t e l l i t e r e c e i v e r s , " IEEE Trans. Microwave Theory and Techniques, Vol. MTT-31 , No. 12, Dec. 1983. P. Harrop, P. Lesarte and A. C o l l e t , " GaAs integrated a l l - F E T - f r o n t -end at 12 GHz, " 1980 IEEE GaAs IC symposium digest. Y. A y a s l i , L.D. Reynolds, R.L. Mozzi and L.K. Hanes, " 2-20 GHz GaAs t r a v e l l i n g wave power a m p l i f i e r , " IEEE Trans. Microwave Theory and Techniques, V o l . MTT-32, No.3, March 1984. P. Bauhahn, T. Contolatis, J . Abrokwah, C. Chao and C. Seashore, " 94 GHz planar GaAs monolithic balanced mixer," 1984 IEEE microwave and millimeter-wave symposium digest. G.A. Breed, GaAs d i g i t a l ICs promise e x c i t i n g RF a p p l i c a t i o n s , RF Design, A p r i l 1986. ] K.C. Gupta, R. Garg and I.J. Bahl, " M i c r o s t r i p l i n e s and s l o t l i n e s , " Artech House, 1979. ] S.R. Forrest, " Monolithic optoelectronic i n t e g r a t i o n : a new component technology f o r lightwave communications," IEEE Trans. Elecron Devices, Vol. ED-32, No.12, Dec. 1985. ] L.J. Conway and S.L. Bouchard, " The sampling a m p l i f i e r (U)," DREO report No. 863, June, 1982. - I l l -[13] K.R. Staffor d , P.R. Gray and R.A. Blanchard, " A complete monolithic sample/hold a m p l i f i e r , " SC-9, No.6, June 1974. [14] W.M. Grove, " Sampling for osc i l l o s c o p e s and other RF systems: DC through X-band," IEEE Trans. Microwave Theory and Techniques, Vol. MTT-14, No.12, Dec. 1966. [15] S.M. Riad, " Modelling of the HP-1430A feedthrough wideband (28 ps) sampling head," IEEE Trans. Instrumentation and Measurement, Vol. IM-31, No.2, June 1982. [16] S.D. Givens, " Bipolar and DMOS technologies team up to produce a f a s t sample and hold a m p l i f i e r , " IEEE Midcon/80 Conference Record. [17] P.H. Saul, " A GaAs MESFET sample and hold switch," IEEE J . S o l i d State C i r c u i t s , V o l. SC-15, No.3, June 1980. [18] G.S. Barta and A.J. Rode, " GaAs sample and hold IC using a 3-gate MESFET switch," 1982 IEEE GaAs IC Symposium Digest. [19] S.J. Harrold, I.A.W. Jance and J. Mun, " A GaAs switched capacitor f i l t e r , " 1985 IEEE GaAs IC Symposium Digest. [20] A.S. Blum, " Frequency response of f i n i t e aperture sample-and-hold systems, IEEE Trans. Nuclear Science, V ol. NS-30, No.l. Feb. 1983. [21] H. Wollman, " High speed ADC systems for waveform a n a l y s i s , " IEEE Trans. Instrumentation and Measurement, Vol. IM-33, No.3, Sept. 1984. [22] T.M. Sonders, " A bridge c o n t r o l f o r the dynamic c h a r a c t e r i z a t i o n of sample/hold a m p l i f i e r s , " IEEE Trans. Instrumentation and Measurement, Vol. IM-27, No.4, Dec. 1978. [23] D.P. Hornbuckle and R.L. Van Tuyl, " Monolithic GaAs direct-coupled a m p l i f i e r s , " IEEE Trans. Elecron Devices, Vol. ED-28, No.2, Feb. 1981. [24] A. Gopinath and J.B. Rankin, " GaAs FET RF switches," IEEE Trans. Elecron Devices, Vol. ED-32, No.7, Jul y 1985. [25] J.V. DiLorenzo and D.Khandelwal, eds., " GaAs FET p r i n c i p l e s and techniques," Artech House, 1982. [26] C. Kocot and C.A. Sto l t e , " Backgating i n GaAs MESFET's," IEEE Trans. Microwave Theory and Techniques, Vol. MTT-30, No.7, J u l y 1982. [27] A. Markoc and L.F. Eastman, " The growth of uniform submicron GaAs layers by l i q u i d phase epitaxy," J . Electrochem. Soc., Vol. 123, p906, 1976. -112-[28] H.M. Manasevit and W.I. Simpson, " The use of metal-organics i n the preparation of semiconductor materials: I. E p i t a x i a l gallium-V compounds," J . Electrochem. S o c , Vol. 116, pl725, 1969. [29] P.C. Chao, S.C. Palmateer, P.M. Smith, U.K. Mishra, K.H.G. Duh, and J.C.M. Hwang, " Millimeter-wave low noise high e l e c t r o n m o b i l i t y t r a n s i s t o r s , " EDL-6, No.10, Oct.1985. [30] f o r example, see S.K. Ghandi, " VLSI f a b r i c a t i o n p r i n c i p l e s , " John Wiley and Sons, 1983. [31] J . Kasahara, H. Sakurai, T. Suzuki, M. A r a i and N. Watanabe, " The e f f e c t of channeling on the LSI-grade uniformity of GaAs FETs by ion-implantation," 1985 IEEE GaAs IC symposium digest. [32] C P . Lee, R. Zucca and B.M. Welch, " Orientation e f f e c t on planar GaAs Schottky b a r r i e r f i e l d e f f e c t t r a n s i s t o r s , " Appl. Phys. L e t t . , Vol.37, No.3, 1980. [33] K.P. Pande, O.A. Aina, A.A. Lakhani, V.K.R. Nair and J.M. O'Connor, " A s i m p l i f i e d capless annealing of GaAs f o r MESFET a p p l i c a t i o n s , " IEEE Trans. Elecron Devices, Vol. ED-31, No.4, Apr. 1984. [34] B. Molnar, " Close-contact annealing of ion implanted GaAs and InP," Appl. Phys. Lett. , Vol.36, No.11, 1 June 1980. [35] R.A. Sadler, " F a b r i c a t i o n and performance of submicron GaAs MESFET d i g i t a l c i r c u i t s by s e l f - a l i g n e d ion implantation," Ph.D. D i s s e r t a t i o n , C o r n e l l U n i v e r s i t y , Jan. 1984. [36] H. Kanber, R.J. C i p o l l i , W.B. Henderson and J.M. Whelan, " A comparison of r a p i d thermal anealing and c o n t r o l l e d atmosphere annealing of S i -implanted GaAs, J. Appl. Phys., Vol.57, No.10, 15 May 1985. [37] K.S. Seo, S. Dahr and P.K. Battacharya, " High q u a l i t y Si-implanted GaAs a c t i v a t e d by a two-step r a p i d thermal anneal technique," Appl. Phys. L e t t . , Vol.47, No.5, 1 Sept. 1985. [38] T. Ohnishi, Y.Yamaguchi, T. Inada, N. Yokoyama and N. N i s h i , " A p p l i c a t i o n of the lamp annealing method to the n + - l a y e r of WSi x-gate s e l f - a l i g n e d GaAs MESFETs, EDL-5, No.10, Oct. 1984. [39] M.H. Badawi, D.R. Dundobbin and J . Mun, " Se l e c t i v e implantation of GaAs f o r MESFET ap p l i c a t i o n s , " E l e c t r o n i c s L e t t . Vol.10, No.15, [40] D.C. D'Avanzo, " Proton i s o l a t i o n f o r GaAs MESFET's," IEEE Trans. Microwave Theory and Techniques, Vol. MTT-30, No.7, J u l y 1982. -113-[41] f o r example, see R.E. Williams, " GaAs processing techniques," Artech House, 1984. [42] N. Yokoyama, T. Mimura, M. Fukata and H. Ishikawa, " A new s e l f - a l i g n e d source/drain technology f o r ultrahighspeed GaAs MESFET VLSI," ISSCC Tech. Digest, Feb. 1981. [43] H.M. Levy and R.L. Lee, " S e l f - a l i g n e d submicron gate d i g i t a l GaAs integrated c i r c u i t s , " EDL-4, No.4, Apr. 1983. [44] T. Ohnishi, N. Yokoyama, H. Onodera, S. Suzuki and A. Shibatomi, " Characterization of WSix/GaAs Schottky contacts," Appl. Phys. Lett., Vol.43, No.6, 15 Sept 1983. [45] K. Yamasaki, K. Asai, T.Mizitani and K.Kurumada, " S e l f - A l i g n Implantation for N +-layer Technology (SAINT) f o r high-speed GaAs ICs, E l e c t r o n i c s L e t t e r s , Vol.18, No.3, 1982. [46] M. Hagio, S. Katsu, T.Tagaki, M. Kazumura G. Kano, I. Teramoto and H. Mizuno, " A new s e l f - a l i g n technology for low noise GaAs MESFET's -Sidewall-assisted pattern inversion technology-," 1984 IEDM Symposium Digest. [47] for example, see S.M. Sze, " Physics of semiconductor devices," 2nd E d i t i o n , Wiley-Interscience, 1981. [48] M. Kuzuhara, T. Nozaki and H. Kohzu, " Non-alloyed ohmic contacts to Si-implanted GaAs activa t e d using SiO^-capped i n f r a r e d r a p i d thermal annealing," J . Appl. Phys., Vol.58, No.3, 1 Aug. 1985. [49] H. Fukui, " Determination of basic device parameters of a GaAs MESFET," B e l l System Tech. J . , Vol.58, No.3, Mar. 1979. [50] W.R. Curtice and M. Ettenburg, " A nonlinear GaAs FET model f o r use i n the design of output c i r c u i t s f o r power a m p l i f i e r s , " IEEE Trans. Microwave Theory and Techniques, Vol. MTT-33, No.12, Dec. 1985. [51] T. Takada, K. Yokoyama, M. Ida and T. Sudo, " A MESFET v a r i a b l e -capacitance model for GaAS integrated c i r c u i t simulation," IEEE Trans. Microwave Theory and Techniques, Vol. MTT-30, No.5, May 1982. [52] K. Lee, M.S. Shur, A.J. V a l o i s , G.Y. Robinson, X.C. Zhu and A. Van Der Z i e l , " A new technique for the c h a r a c t e r i z a t i o n of "End" resistance i n Modulation-doped FETs," IEEE Trans. Elecron Devices, V o l . ED-31, No.10, Oct. 1984. -114-! name: 468S128E (2,4) ! date: 86 05 07 ! purpose: COMPARE SIMULATED AND MEASURED TRANSFER CURVES ! FOR UBC SELF-ALIGNED GATE GaAs MESFET. CKT S2PA_A1 1 2 0 [MODEL=gasmdl area=l] DEF2P 1 2 SAGFET MODEL gasmdl GAS M0DEL=1 VTO=-1.80 ALPHA=.86 BETA=2.68E-3 LAMBDA=2e-5 + RS=6.17 RD=20.7 CGS0=.28p CGD0=.28p CDS=.07p VBI=0.8 N=2.1 RG=3K SOURCE SAGFET IVS_Vds 2 3 DC=3.0 SAGFET IVS_Vmon 0 3 DC=0 SAGFET IVS_Vgs 1 0 DC =-.4 CONTROL SAGFET DC Vds 0 3.2 Vgs -2 0.5 .5 SPICEOUT SAGFET DC V ( a l l ) I ( a l l ) END Appendix A l . mwSPICE l i s t i n g f o r transf e r curve a n a l y s i s . -115-!buffer amp simulation using GaAsFET model !output t r a n s i e n t analysis dim ckt cap pf res oh S2PA A l 1 2 0 [model=gl area= =5.1] S2PA_A2 7 2 0 [model=gl area= =4.9] S2PA_A3 2 3 4 [model=gl area= =10] S2PA A4 2 3 2 [model=gl area= =10] S2PA_A5 6 7 6 [model=gl area= =10] S1PA Dl 4 5 [model=dl] S1PA_D2 5 7 [model=dl] DEF2P 1 7 AMP MODEL SOURCE Dl D CJO=10p IS=1E-15 N=l.l RS=100 VJ=.8 Gl GAS VT0=-1.8 BETA=2.68E-4 LAMBDA=2E-5 RD=62 RS=62 CGS0=3.If TAU=10p RG=3k ALPHA=.86 VBI=.8 CGD0=3.If CDS=.75f AMP AMP AMP IVS_Vin AMP AMP CONTROL AMP AMP SPICEOUT AMP IVS_Vdd 3 0 DC=4 IVS_Vss 6 0 DC=-2 0 tran=pwl(0 0 .2n 0 CAP_Cload 7 8 c=l RES Rload 8 0 r=50 .4n .5 4.4n .5 4.8n -.5 8.8n -.5 9n 0) tran .In lOn options l i s t node tran v ( l ) v(7) i(cap_cload) Appendix A2. mwSPICE l i s t i n g f o r the b u f f e r a m p l i f i e r transient response. -116-! simulation of a GaAsFET switch dim cap pf res oh CKT S2PA_A1 1 3 2 [MODEL=gl area=10] S2PA_A2 0 4 3 [model=gl area=10] CAP_Chold 4 0 c=l DEF2P 1 4 SWITCH MODEL g l gas VTO=-1.80 LAMBDA=2E-5 BETA=2.68E-4 alpha=.86 + RS=62 RD=62 CGS0=3.If cgdo=3.If VBI=0.8 CDS=.75f SOURCE SWITCH RES_Rin 10 2 r=10 SWITCH IVS_Vin 10 0 tran pwl(0 0 40n 0 41n .5 lOOn .5 102n -.5 150n -.5 151n 0) SWITCH IVS_Vcntrl 1 0 tran pulse(-3 0 .In .In .In .In lOn) CONTROL SWITCH tran lOOp 200n u i c SWITCH i c v(4)=-0 SWITCH OPTIONS NODE ACCT SPICEOUT SWITCH tran v(4) v(10) Appendix A3. mwSPICE l i s t i n g f o r dual-gate switch t r a n s i e n t analysis. -117-

Cite

Citation Scheme:

        

Citations by CSL (citeproc-js)

Usage Statistics

Share

Embed

Customize your widget with the following options, then copy and paste the code below into the HTML of your page to embed this item in your website.
                        
                            <div id="ubcOpenCollectionsWidgetDisplay">
                            <script id="ubcOpenCollectionsWidget"
                            src="{[{embed.src}]}"
                            data-item="{[{embed.item}]}"
                            data-collection="{[{embed.collection}]}"
                            data-metadata="{[{embed.showMetadata}]}"
                            data-width="{[{embed.width}]}"
                            async >
                            </script>
                            </div>
                        
                    
IIIF logo Our image viewer uses the IIIF 2.0 standard. To load this item in other compatible viewers, use this url:
https://iiif.library.ubc.ca/presentation/dsp.831.1-0096908/manifest

Comment

Related Items