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Cascode voltage switch logic circuits Chu, Kan Man 1986

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CASCODE VOLTAGE SWITCH LOGIC C I R C U I T S  by Kan B. Eng. (Hons)  Man Chu  , McGi 11 University,  1984  A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE  REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE  in THE  FACULTY OF GRADUATE STUDIES  DEPARTMENT OF ELECTRICAL ENGINEERING  We a c c e p t to  THE  this  thesis  the required  as conforming standard  UNIVERSITY OF BRITISH COLUMBIA Apr i I 1986 ©  Kan  Man Chu,  1986  In p r e s e n t i n g  this thesis i n partial  f u l f i l m e n t o f the  requirements f o r an advanced degree a t the U n i v e r s i t y o f B r i t i s h Columbia, I agree t h a t the L i b r a r y s h a l l make it  f r e e l y a v a i l a b l e f o r reference  and study.  I further  agree t h a t p e r m i s s i o n f o r e x t e n s i v e copying o f t h i s t h e s i s f o r s c h o l a r l y purposes may be granted by the head o f my department o r by h i s o r her r e p r e s e n t a t i v e s . understood t h a t  Iti s  copying o r p u b l i c a t i o n o f t h i s t h e s i s  f o r f i n a n c i a l gain  s h a l l n o t be allowed without my  permission.  Department o f  ti^C7^icAu  The U n i v e r s i t y o f B r i t i s h 2075 Wesbrook P l a c e Vancouver, Canada V6T 1W5 Date  10  /1Q\  2- A A )  p-6  Columbia  ^ipCy.  written  Abstract Cascode v o l t a g e  switch  (CVS) l o g i c  i s a CMOS c i r c u i t  technique which has p o t e n t i a l advantages NAND/NOR l o g i c  i n terms o f c i r c u i t  power d i s s i p a t i o n a n d l o g i c presents  delay,  flexibility.  over  layout This  two new p r o c e d u r e s f o r c o n s t r u c t i n g  CVS c i r c u i t s  t o p e r f o r m random l o g i c  conventional density,  thesis differential  f u n c t i o n s . The f i r s t  p r o c e d u r e makes u s e o f a K a r n a u g h map a n d t h e s e c o n d procedure  i s a t a b u l a r method b a s e d  approach. Both s t a t i c  on t h e Q u i n e - M c C l u s k e y  and dynamic c i r c u i t  techniques  e m p l o y i n g t h e CVS l o g i c c o n c e p t a r e d i s c u s s e d . and  l a y o u t methods based  on t h e o r e t i c a l g r a p h m o d e l s a r e  presented t o ensure t h ew i r a b i l i t y  o f CVS c i r c u i t s .  NORA CVS m u l t i p l i e r h a s been d e s i g n e d u s i n g technology o f Northern Telecom. and  simulations  Some w i r i n g  indicate that  An 8x8  t h e 3um CMOS  The c h i p m e a s u r e s 4mm by 4mm  i t c a n be r u n a t a t h r o u g h p u t  r a t e o f 50MHz.  ii  Table  of Contents  Abstract  i  List  of f i g u r e s  List  of Tables  iv x  Acknowledgement 1.  2.  xi  Introduction  1  1.1 G e n e r a l  1  background  1 .2 O b j e c t i v e  3  1.3 T h e s i s o u t l i n e  4  T h e o r e t i c a l a s p e c t s o f CVS l o g i c  6  2.1 CVS l o g i c  6  2.1.1  design procedures  SCVS t r e e d e s i g n  6  2.1.2 DCVS t r e e d e s i g n  9  2.1.2.1  Design  by i n t u i t i o n  2.1.2.2 K-map p r o c e d u r e 2.1.2.3 T a b u l a r m e t h o d 2.2 W i r i n g a n d l a y o u t o f CVS t r e e s  3.  10 ..17 25 36  2.2.1  One-dimensional  t r e e l a y o u t method  36  2.2.2  T w o - d i m e n s i o n a l t r e e l a y o u t method  37  2.3 T e s t i n g schemes f o r DCVS c i r c u i t s  42  Circuit  49  t e c h n i q u e s w i t h CVS l o g i c  3.1' s t a t i c c i r c u i t t e c h n i q u e s 3.1.1  49  C o n v e n t i o n a l CVS c i r c u i t s i n NMOS a n d CMOS  3.1.2 D i f f e r e n t i a l  49 s p l i t - l e v e l CMOS l o g i c  3.2 D y n a m i c CVS c i r c u i t t e c h n i q u e s 3.2.1 Domino CMOS l o g i c 3.2.2 NORA CMOS l o g i c  53 57 57 68  iii  3.3 P e r f o r m a n c e c o m p a r i s o n s o f CMOS f u l l 4.  5.  A h i g h s p e e d CVS p i p e l i n e d m u l t i p l i e r  adders  design  77 84  4.1 A l g o r i t h m a n d a r c h i t e c t u r e  84  4.2 C e l l  97  t y p e s and t h e i r  circuits  4.3 P r o c e s s a n d s p e e d c r i t e r i a  106  4.4 S i m u l a t i o n s o f t h e c e l l s  111  4.5 I n p u t a n d o u t p u t c o n s i d e r a t i o n s  121  4.6 F l o o r p l a n a n d c e l l  133  layout  Conclusion  137  REFERENCES  138  APPENDIX A: S P I C E l i s t i n g s full  f o r simulation of  adders  144  APPENDIX B: S P I C E o u t p u t s f o r s i m u l a t i o n o f multiplier  cells  160  APPENDIX C: L a y o u t s o f some m a j o r c e l l s o f t h e multiplier  169  List  of T a b l e s  Table  Page  2.1  Typical l i s t  2.2  T y p i c a l format f o r a 1 0 - l i s t  27  2.3  The  30  2.4  The p r i m e i m p l i c a n t T a b l e 2.3  2.5  The  10-list  f o r m a t f o r t h e t a b u l a r method  of a 3 - b i t magnitude comparator  1 - l i s t and  t a b l e of the 1 0 - l i s t  of 31  i t s m i n i m a l sum  f o r the  magnitude comparator 2.6  The  0-list  and  33  i t s m i n i m a l sum  f o r the  magnitude comparator 3.1  Comparison  of s i m u l a t i o n  d i f f e r e n t t y p e s of f u l l  27  34 results for adders  4.1  A t r u t h t a b l e of the m u l t i p l e x e r a r r a y  4.2  The CVS  d i s t r i b u t i o n of d i f f u s i o n nodes f o r t h e tree i n Fig.4.17  78 89 116  List  of f i g u r e s  Figure  Page  2.1  A typical  2.2(a)  A SCVS c i r c u i t f  SCVS  circuit  structure  7  for the function  = AB'C +AB'D' +AE +F'  ...8  2.2(b)  Another SCVS c i r c u i t  2.3  The s t r u c t u r e o f a D C V S c i r c u i t  2.4  DCVS  exclusive-or  2.5(a)  DCVS  circuit  2.5(b)  Recursive DCVS structure c =g + p c „ n  2.6(a)  i n NMOS  n  n  f o r thefunction  f  8 11  circuits  13  f o r the function c ^ g  1  + PJCQ  1  f o r the function 15  n-1  The D C V S t r e e a n d i t s s y m b o l i c  represen-  tation  2.6(b)  f o r t h e f u n c t i o n P = x . x_ ... x 1 2 n DCVS implementation f o r the function f  1  =  P  1  Y  +  P  2 ' Y  DCVS  2.7(a)  E n c i r c l e m e n t o f t h e K-map f o r t h e c a r r y - o u t of a f u l l  adder  18  DCVS  implementation of the carry-out  full  adder  of a 18  T h e K-map o f F i g . 2 . 7 ( a ) ,  but with  different  encirclements 2.8(b)  20  The D C V S t r e e r e s u l t i n g  from t h e 10-loops o f  Fig.2.8(a) 2.8(c)  6  implementation f o r the function  function  2.8(a)  16  1  2.6(c)  2.7(b)  5  20  The c o m p l e t e D C V S t r e e r e s u l t i n g Fig.2.8(a)  from 20  vi  2.9(a)  K-map f o r t h e f u n c t i o n Q = x' x  1  x' x' x V + 1 2 3 4 t h e 10- a n d  ( x„ + x„ + x ) s h o w i n g 2 3 4  01 - e n c i r c l e m e n t s  ...23  2.9(b)  DCVS c i r c u i t  corresponding t o the 01-loop  23  2.9(c)  The c o m p l e t e  DCVS c i r c u i t  23  2 . 1 0 ( a ) An a l t e r n a t i v e e n c i r c l e m e n t a r r a n g e m e n t f o r t h e K-map o f F i g . 2 . 9 ( a ) 2 . 1 0 ( b ) The c i r c u i t r e s u l t i n g f r o m F i g . 2 . 1 0 ( a ) . Compare t h i s c i r c u i t 2.11  with that  list  26  The s h a r e d DCVS t r e e c i r c u i t to  2.13  24  T h e b a s i c DCVS t r e e s t r u c t u r e a s i t w o u l d d e v e l o p from a t a b u l a r  2.12  i n Fig.2.9(c)  24  the 10-list  The c o m p l e t e  corresponding  o f T a b l e 2.4  DCVS t r e e  32  f o rthe 3-bit  magnitude comparator  35  2 . 1 4 ( a ) A SCVS t r e e f o r t h e c a r r y  look-ahead  function  38  2.14(b) The c o r r e s p o n d i n g E u l e r p a t h  from  Fig.2.14(a)  38  2 . 1 4 ( c ) A 1-D l a y o u t o f t h e c i r c u i t 2 . 1 5 ( a ) A DCVS h a l f a d d e r  i n Fig.2.14(a)  circuit  38 39  2.15(b) The E u l e r p a t h from F i g . 2 . 1 5 ( a )  39  2 . 1 5 ( c ) The l a y o u t o f a h a l f a d d e r  39  2.16  A 2-D l a y o u t o f t h e c i r c u i t  2 . 1 7 ( a ) A DCVS f u l l  adder  i n Fig.2.14(a)  circuit  2 . 1 7 ( b ) A 2-D l a y o u t o f t h e f u l l  43 adder  2.18  A 3 - i n p u t NAND g a t e w i t h i l l e g a l  2.19  An i l l e g a l  43 inputs  s t a t e d e t e c t o r f o r DCVS t r e e s  vii  41  46 46  2.20  A fault  3.1(a)  The g e n e r a l  3.1(b)  A s t a t i c NMOS SCVS c i r c u i t w i t h logic  detection  scheme f o r DCVS c i r c u i t s  s t r u c t u r e o f SCVS c i r c u i t s  47 50  reduced  swing  50  3.2  Another  SCVS c i r c u i t c o n f i g u r a t i o n  i n NMOS  3.3  A static  SCVS c i r c u i t  i n CMOS  51  3.4(a)  A static  DCVS c i r c u i t  i n NMOS  .54  3.4(b)  A s t a t i c DCVS c i r c u i t  i n CMOS  54  3.5  A general  3.6(a)  The i n t e r c o n n e c t i o n  method  o f DSL c i r c u i t s  58  3.6(b)  The i n t e r c o n n e c t i o n  method  o f DCVS c i r c u i t s  58  3.7(a)  A d y n a m i c SCVS g a t e  59  3.7(b)  A d y n a m i c DCVS g a t e  59  3.8  A SCVS domino g a t e w i t h a f e e d b a c k d e v i c e T2  61  3.9  A SCVS domino g a t e w i t h p r e c h a r g e d i n t e r n a l  s t r u c t u r e o f DSL c i r c u i t s  nodes  51  56  61  3 . 1 0 ( a ) A SCVS domino NAND g a t e  64  3 . 1 0 ( b ) A DCVS d o m i n o NAND g a t e  64  3.11  An l a t c h e d d o m i n o c i r c u i t  65  3.12  An e x a m p l e c o n s t r u c t i o n domino  logic  3.13(a) A c l o c k e d  fora glitch-free  block  67  CMOS r e g i s t e r  69  3 . 1 3 ( b ) T h e l a s t s t a g e o f a CVS p i p e l i n e d s e c t i o n 3 . 1 4 ( a ) A N - t y p e RCCMOS r e g i s t e r  69 71  3 . 1 4 ( b ) A P - t y p e RCCMOS r e g i s t e r  71  viii  3 . 1 5 ( a ) A NORA 0 - s e c t i o n  w i t h a SCVS t r e e  71  3 . 1 5 ( b ) A NORA 0 - s e c t i o n  w i t h a DCVS t r e e  71  3.16  The t i m i n g d i a g r a m f o r a 0 ' - s e c t i o n  cascaded  to a 0-section 3.17  A p i p e l i n e d stage which differential  3.18  73 provides  o u t p u t from s i n g l e - e n d e d  inputs  74  A timing constraint a d d i t i o n a l t o Fig.3.16 if  t h e p i p e l i n e d stage i n Fig.3.17 i s used  3.19  A static  CMOS f u l l  adder  3.20  A conventional  3.21  A modified  4.1  The NORA p i p e l i n e scheme a n d i t s t i m i n g  4.2  The a r c h i t e c t u r a l scheme o f a n 8x8  NORA f u l l  NORA f u l l  76 79  adder  81  adder  82  multiplier  86  92  4.3  The c e l l  level  scheme o f a r e c o d e r  4.4  The c e l l  level  scheme o f a m u l t i p l i e r a r r a y  93  4.5  The c e l l  level  scheme o f a c a r r y s a v e a r r a y  94  4.6  The c e l l  level  scheme o f an 1 6 - b i t a d d e r  96  4.7  A recoder  cell  C1 a n d i t s t r u t h t a b l e  99  4.8  The DCVS c i r c u i t s sub  array  f o r t h e f u n c t i o n s 2X. a n d  D  3  4.9  A DCVS c i r c u i t  4.10  outpads ...... The h a l f a d d e r a n d f u l l a d d e r b l o c k s a n d their logical functions  4.11  The b l o c k carry  93  99  t o generate the multiplexed  diagrams and l o g i c a l  look-ahead c e l l s  101 102  functions of 102  ix  4.12  An a l t e r n a t i v e c o n s t r u c t i o n o f c i r c u i t s i n F i g . 2 . 5 ( a ) and (b)  104  4.13(a) A d e l a y stage w i t h s i n g l e - e n d e d o u t p u t  105  4.13(b) A d e l a y s t a g e w i t h complementary o u t p u t s  105  4 . 1 4 ( a ) A lumped model o f a CVS c i r c u i t  108  4 . 1 4 ( b ) A s i m p l i f i e d RC m o d e l o f a CVS c i r c u i t  108  4.15  Contour l i n e s of r e l a t i v e d e v i a t i o n in  Ref .[39]  112  4.16(a) A c a p a c i t i v e model f o r t h e output 4 . 1 6 ( b ) A lumped RC m o d e l f o r t h e o u t p u t 4.17  e{p,-y)  A circuit  example f o r f i n d i n g  load load  112 112.  the c r i t i c a l  discharging path  116  4 . 1 8 ( a ) A NORA s t a g e w i t h s i n g l e - e n d e d o u t p u t  119  4 . 1 8 ( b ) A NORA s t a g e w i t h c o m p l e m e n t a r y o u t p u t s  119  4.19  122  The s t a g e s o f t h e p i p e l i n e d m u l t i p l i e r  4.20(a) A t y p i c a l gate p r o t e c t i o n s t r u c t u r e f o r i n p u t pads 4.20(b) A c r o s s s e c t i o n o f t h e p r o t e c t i o n s t r u c t u r e in  Fig.4.20(a)  4.21  The s c h e m a t i c  4.22  The o u t p u t  124 of a basic c e l l  o f s t a g e #1  (jim) o f t h e  transistors  125  The t h r e e t y p e s o f c o n t a c t p l a c e m e n t i n output pad d e s i g n  4.24  125  s t a g e o f t h e m u l t i p l i e r . The  numbers i n d i c a t e t h e w i d t h s  4.23  124  128  T h e c r o s s s e c t i o n o f a CMOS i n v e r t e r parasitic  t r a n s i s t o r s shown  x  with 131  4.25  The l a t c h - u p modes o f a CMOS d r i v e r  131  4.26  A layout of output pad which h e l p t o prevent latch-up  4.27  132  An a b n o r m a l p o w e r - u p s e q u e n c e f o r a CMOS inverter  134  4.28  The a d d i t i o n o f a n d i o d e  4.29  The f l o o r p l a n o f t h e m u l t i p l i e r  xi  t o prevent  latch-up  ....134 135  Acknowledgement The a u t h o r w i s h e s  t o thank P r o f e s s o r  D a v i d L. P u l f r e y  f o r h i s p a t i e n t s u p e r v i s i o n and h i s v a l u a b l e this  s u g g e s t i o n s on  project. I am a l s o g r a t e f u l t o Tommy L u k a n d G a i v a n Chang f o r  their  e f f o r t s in helping  l a y out p a r t  of the m u l t i p l i e r c h i p  i n t h e c o u r s e of a f o u r t h y e a r u n d e r g r a d u a t e the a u t h o r ' s  project  supervision.  S p e c i a l t h a n k s go t o my p a r e n t s f o r t h e i r throughout  under  this  encouragement  work.  Financial assistance Engineering Research  from the N a t u r a l  Council  o f Canada  acknowledged.  xii  S c i e n c e s and  isgratefully  1  CHAPTER 1 : INTRODUCTION  1.1 GENERAL BACKGROUND  Random as  basic  logic building  building  block  generates  good  While  this  design  traditionally  elements.  approach logic  The  levels  that  a n d power. F u r t h e r m o r e ,  result  in  of  chip  area.  differential  A  new  assure  results,  of a r e a  logic  advantage  i s that each stage  p r o d u c e s good  long  approach  [1]  d e l a y . T h i s type  circuit.  CVS c i r c u i t s  i scalled  one b i n a r y t r e e ,  The  complement  inverter.  and p r o v i d e  of the output  On t h e c o n t r a r y ,  interrelated simultaneously  or both  with only  to  Boolean  c a n be c l a s s i f i e d  consist  variables,  is  margins. i n terms  gates  combine  will  with  into  (DCVS).  logic  tree  within  a t r e e network s w i t c h (CVS)  two t y p e s , SCVS  namely,  logic  t r u e o r complemented  gates  forms o f  output  variable.  v a r i a b l e c a n be o b t a i n e d  t h r o u g h an  DCVS  disjointed  one form o f  cascode  functions  a cascode voltage  (SCVS) a n d d i f f e r e n t i a l  input  noise  of these  of c i r c u i t  single-ended of  simple  h a s power g a i n and  into combinational  a  stacking transistors  this  gates  d e l a y s , h i g h power c o n s u m p t i o n , a n d waste  o f p r o c e s s i n g complex  of  of  large  long chains  p a i r s o f NMOS d e v i c e s  circuit  NAND/NOR  i t i s also excessive  networks capable single  utilizes  logic  gates  binary  t h e t r u e a n d complement  consist  trees, outputs.  which  of  two give  2  The i m p l e m e n t a t i o n o f random l o g i c d e s i g n has  many  advantages  over  the conventional  approach.  The most o b v i o u s a d v a n t a g e  appears  that  DCVS  with  circuits  CVS  logic  NAND/NOR  logic  i s i n device  will  usually  count; i t  require  t r a n s i s t o r s , o f b o t h n- a n d p - t y p e , t h a n t h e two l e v e l implementation  [ 1 ] . Device  redundancy  i snaturally  t h e f u n c t i o n a l power o f t h e d i f f e r e n t i a l SCVS  logic  can  be  r e c e n t example of t h i s large  realised  r e d u c e d by  tree.  i s a large leverage c i r c u i t  i n which  height,  the elimination  f u r t h e r advantages Another flexibility where  of  long ^chains  g e n e r a l advantage that  h a s an  increased  of gates r e s u l t s i n  i s afforded,  o f DCVS i s t h e i n c r e a s e o f l o g i c especially  i n those  some c o m p l e x f u n c t i o n must be i m p l e m e n t e d  arises  through  having  domino c h a i n a r e s i g n a l s signals  which  stack  i n b o t h d e n s i t y , power a n d p e r f o r m a n c e .  A c o n s t r a i n t o f u s i n g CMOS  circuits  to  ensure  that  to  of  a r e a t ground  form  t h e "domino  instances  i n d o m i n o CMOS. a  domino  chain  a l l the inputs to the gate"  type,  p o t e n t i a l during precharge  i.e., [3].If  c h a r g e s may l e a k away f r o m a p r e c h a r g e d n o d e , r e s u l t i n g wrong  signal  propagating  s t a n d a r d domino l o g i c gates  a  number o f d e l a y s t a g e s h a v e been c o m p r e s s e d i n t o a s i n g l e [ 2 ] . A l t h o u g h t h i s CVS c i r c u i t  a  NAND/NOR  i n NMOS t e c h n o l o g y a l s o . A  CVS g a t e  not,  logic  fewer  cannot  be  along  t h e domino  s u f f e r s from t h e f a c t  implemented.  However,  that  chain. inverting  in  Thus, logic  c l o c k e d DCVS p r o v i d e s  3  complementary  outputs  and t h e r e f o r e overcomes t h i s  restriction  [1].  1.2  OBJECTIVE  C a s c o d e v o l t a g e s w i t c h (CVS) logic  i sa newly-proposed  f a m i l y [1]. I t s advantages of reduced  s a v i n g a n d l o w power d i s s i p a t i o n be  logic  t h a t CVS l o g i c w i l l  circuit  these a t t r a c t i v e  new d i r e c t i o n i n  prospects  t h r e e a s p e c t s o f CVS l o g i c a r e e x a m i n e d i n t h i s First,  theoretical  methodology  and  issues  layout  such  u s e s an a l g e b r a i c d e c o m p o s i t i o n logic  approach.  can  However,  t o g i v e more i n s i g h t deserve  special  presented  thesis. circuit  logic  design  and f a c t o r i z a t i o n  implemented  by  method [ 4 ]  technique, and  this  computer-aided  into circuit  attention  behaviour.  i n CVS c e l l  various c i r c u i t  Wiring  and  t h e domino  and  and c e l l  techniques  NORA  here layout  design. A layout style i s compaction.  employing  t h e CVS l o g i c  a r e e v a l u a t e d a n d compared w i t h c o n v e n t i o n a l  Utilizing  design  two o t h e r d e s i g n methods a r e d e v e l o p e d  t o ensure area e f f i c i e n c y  Second, concept  be  as  i n mind,  topology a r e i n v e s t i g a t e d and rendered  u s e f u l t o I C d e s i g n e r s . A r e c e n t CVS  complex  area  h a v e been r e c o g n i z e d a n d i t may  represent a s i g n i f i c a n t  NMOS/CMOS l o g i c d e s i g n . W i t h  delay,  MOS  techniques.  (NO R A c e ) t e c h n i q u e s ,  t h e CVS  4  logic  is  of c i r c u i t Third, is  shown t o be s p e e d and the  shown t o be  pipelined logic,  logic  feasible  8x8  bit  through  be  logic  b l o c k c o n s t r u c t i o n and  1.3  relieved  Cascode V o l t a g e  i n a CMOS design  technology example.  been c o n s t r u c t e d u s i n g  the  foregoing  into  dynamic  d e l a y time  and  design.  circuits,  partitioning,  The  such are  A CVS  theories  a practical  as  shown  logic.  i n t r o d u c e s t h e b a c k g r o u n d and Switch  first  (CVS)  section  a p p r o a c h e s t o CVS other  is  a  logic  current  work  l o g i c . Some a d v a n t a g e s o f CVS  approaches  to  of  Chapter  d e s i g n , one  of  t h e l a y o u t o f CVS  variable  proposes  i s a K a r n a u g h map  on  logic  logic  trees: a  a two-dimensional  alignments  are  two  new  method  and  examples u s i n g  s e c o n d s e c t i o n d i s c u s s e s two  m e t h o d b a s e d on a g r a p h m o d e l and number  Two  t a b u l a r method. S p e c i f i c  p r o c e d u r e s a r e g i v e n . The  the  i n terms  discussed. The  the  families  T H E S I S OUTLINE  C h a p t e r One  are  has  of t r a d i t i o n a l  i n CVS  logic  specific  incorporated  difficulties  be  a  multiplier  design  to  o f CVS  t o d e m o n s t r a t e how  can  logic  flexibility.  implementation  i n order  principles  superior to other  these  different  one-dimensional m e t h o d where  m a x i m i z e d . The  third  5  section presents a testing  scheme u t i l i z i n g  t h e s e l f - t e s t i n g and  f a u l t - s e c u r e p r o p e r t i e s o f DCVS t r e e s . Chapter techniques  Three  summarizes  which could apply t o  charge-sharing  and  comparison  these  of  clock  the  static  CVS  logic.  and dynamic Problems  circuit such  as  skew c o n s t r a i n t s a r e i n v e s t i g a t e d . A  circuit  techniques  i s carried  o u t by  simulations. Chapter pipelined  Four i s devoted  multiplier.  individual cell done  to  ensure  The  to  details  implementations that  each  the  design  of  chip  are presented.  pipeline  stage  of  an  8x8  a r c h i t e c t u r e and Simulations meets  the  c o n s t r a i n t . The p r o b l e m s a s s o c i a t e d w i t h t h e I/O i n t e r f a c e , as  transistor  width/length r a t i o degradation  CVS  are speed such  and l a t c h - u p , a r e  discussed. Conclusions Chapter.  a r e drawn a n d s u g g e s t i o n s a r e made i n t h e l a s t  6  CHAPTER 2 : THEORETICAL ASPECTS OF CVS LOGIC  2.1 CVS LOGIC DESIGN PROCEDURES  2.1.1. SCVS T r e e D e s i g n  A simple consists and  of a d e p l e t i o n load device,  a binary  tree  r e a l i z a t i o n o f a SCVS c i r c u i t  tree  x = ( x  ,...,x  switching  when x i s t h e t r u e  SCVS  from ground  ) i s the  false  f u n c t i o n f ( x ) , a n d node Q i s g r o u n d e d  vector.  Given  a  Boolean  expression,  expression  or  minimal  sum,  corresponding  The  n  1  the  technology  a p a i r of i n v e r t e r b u f f e r s  s u c h t h a t node Q i s d i s c o n n e c t e d  when t h e i n p u t c o n t r o l v e c t o r of  NMOS  ( o r SCVS t r e e ) , a s shown i n F i g . 2 . 1 .  i s designed  vector  in  SCVS  tree  of  a  structure  k i n d o f n e t w o r k c a n be d e s i g n e d u s i n g [4]. F o r example, t h e s w i t c h i n g  which  can  logical  be  a  minterm  function,  i s sought. G e n e r a l l y , factorization  a this  techniques  function  f = AB'C + AB'D' + AE + F' can  be f a c t o r i z e d a s f = A[B'(C+D')+E]+F',  and  i t s corresponding  SCVS  t r e e c a n be r e a l i z e d a s i n e i t h e r  F i g . 2 . 2 ( a ) o r ( b ) . T h e s e c i r c u i t s c a n be because one  shown  to  be  correct  e a c h p o s s i b l e p a t h f r o m node Q t o g r o u n d c o n t r i b u t e s t o  product term i n the e x p r e s s i o n  f o rf.  SINGLE RAIL OR DUAL RAIL CONTROL SIGNALS  ig.2.1 A t y p i c a l  SCVS c i r c u i t  s t r u c t u r e i n NMOS  8  J j  LOAD/BUFFERS  2  1 f •  f• f  ^NOOE Q  <-Ot i  F i g . 2 . 2 ( a ) A SCVS c i r c u i t  f o rthe function  f =AB'C+AB'D'+AE+F'  LOAD/BUFFERS NODE Q  B  X7  F i g . 2 . 2 ( b ) A n o t h e r SCVS c i r c u i t  f o rthe function f  9  The s t r u c t u r e static larger load  full  i n Fig.2.2(a)  CMOS  circuit  technique  is  appropriate  device  and  thus  decrease  CMOS),  the structure  are closer  i s better  and thus reduce  a  the  pull-up  t i m e . However, f o r (such  as  domino  since shared  nodes  the discharging time.  Design  The d e s i g n o f DCVS c i r c u i t s t h a t o f SCVS c i r c u i t s .  d e s i g n o f DCVS t r e e s i s a n identification  rise  to  precharging  i n Fig.2.2(b)  t o t h e ground  2.1.2 DCVS T r e e  require  the  when  u s e d . The n o d e s w i t h  shared p a r a s i t i c capacitance are c l o s e r  dynamic t e c h n i q u e s which  than  i s more  i s c o n s i d e r a b l y more  difficult  The o n l y e x i s t i n g p r o c e d u r e algebraic  technique  based  on  o f s u b - e x p r e s s i o n s common t o two o r more  functions  [ 4 ] . The d e c o m p o s i t i o n  involved  in  t h i s approach  and  factorization  f o rthe the  Boolean  techniques  a r e q u i t e m a t h e m a t i c a l . As s u c h , t h e  method d o e s n o t p r o v i d e t h e i n s i g h t  into circuit  behaviour  which  i s o f t e n important f o r IC d e s i g n e r s . S e c t i o n ( l ) which to  approach  some  f o l l o w s s u g g e s t s a few  of  the design problems.  i n t r o d u c e two o t h e r methods, w h i c h a r e practical The  first  Karnaugh  than  described  procedure map.  This  much  intuitive  methods  S e c t i o n s ( 2 ) and (3) simpler  and  more  i n [ 4 ] , f o r c o n s t r u c t i n g DCVS t r e e s .  utilizes  the  hand-processing  pictorial method  nature  of  the  i s shown t o be an  10  efficient  approach  functions  of  complexity  up  of  to to  realizing five  K-maps  or  suddenly  low d e v i c e - c o u n t c i r c u i t s f o r  six  variables.  increases  However,  when more t h a n  v a r i a b l e s a r e c o n s i d e r e d . A c c o r d i n g l y , a second procedure has  a  uniform  d e v e l o p e d . The  five which  p r o c e d u r a l c o m p l e x i t y f o r n - v a r i a b l e s , has method i s t a b u l a r  form of the Quine-McCluskey Note  the  that a unique,  i n nature  and  is  a  been  modified  method [ 7 ] .  one-to-one  correspondence  between  a  B o o l e a n e x p r e s s i o n a n d a DCVS t r e e s t r u c t u r e d o e s n o t e x i s t [ 6 ] . Thus, the above structures given  design  to  procedures  can  realize a particular  produce  logic  several  tree  operation. Also for a  s t r u c t u r e , some o f t h e i n p u t v a r i a b l e s may  be  allowed  to  permutate. The implement  two DCVS d e s i g n p r o c e d u r e s p r o p o s e d h e r e c a n be u s e d any  Boolean f u n c t i o n , p r o v i d e d the a p p r o p r i a t e  t a b l e s a r e known. E x a m p l e s investigated  in  this  of  thesis  c o m p a r a t o r s and m u l t i p l i e r  2.1.2.1 D e s i g n by  Differential  CMOS  designs  include  adder  which cells,  have  to  truth been  magnitude  circuits.  Intuition  cascode  p u s h - p u l l l o a d , and a p a i r  switch c i r c u i t s  usually consist  of i n t e r r e l a t e d b i n a r y d e c i s i o n  ( o r DCVS t r e e s ) , a s shown i n F i g . 2 . 3 .  of  a  trees  11  PUSH-PULL  LOAD  OUTPUTS *1  DCVS DUAL RAIL CONTROL SIGNALS Xn  ^GND  Fig.2.3  The s t r u c t u r e  of  a DCVS  circuit  TREE  12  The DCVS t r e e i s p r o p e r l y d e s i g n e d 1.  When t h e i n p u t v e c t o r x = ( x  such t h a t :  ,  x  1 vector  of  the  disconnected  switching  When  x=  (  x  path x  4  1 reverse  function  by  ) i s the false vector  of Q ( x ) , the  trying  this  circuit  can  be  easily  a l l the p o s s i b l e combinations of t h e input the  circuit  by  observing  s e t o f u n i q u e p a t h s f r o m n o d e s Q a n d Q* t o t h e g r o u n d . The  x'^  x'^  +  expression  t o node Q" c o r r e s p o n d s t o  x^ w h i c h i s e q u a l  Q'(x) = x ^  Sometimes intuition, a  is  e x a m p l e i s a 2-way e x c l u s i v e - o r DCVS g a t e shown i n  set of paths attached i  Q  n  v e c t o r s . H o w e v e r , we c a n a l s o v e r i f y  x  Q ( x ) , node  through the t r e e ;  F i g . 2 . 4 ( a ) . The f u n c t i o n a l i t y o f  the  true  holds.  A simple  verified  i s the  f r o m g r o u n d a n d node Q' i s c o n n e c t e d t o g r o u n d  by a u n i q u e c o n d u c t i n g 2.  ) n  the  x'^  DCVS  nature.  c a n be b u i l t  Fig.2.4(a)  with  another  expression  t o Q ( x ) , w h i l e f o r node Q t h e  j 2 * X  tree  For  Fig.2.4(b))  equal  x  e s p e c i a l l y f o r those  recursive  general  +  the  can  constructed  e a s i l y by  kinds of Boolean f u n c t i o n s  instance,  by r e p l a c i n g 2-way  be  XOR  a  3-way  the tree.  x  2  XOR ,  x'  tree 2  (see  pair  Fig.2.4(c)  s t r u c t u r e f o r a n n-way XOR t r e e , w i t h a s t a c k i n g  t o n.  with  in  shows a height  13  LOAD  ( c ) n-way XOR  gate  F i g . 2 . 4 DCVS e x c l u s i v e - o r  circuits  14  Another  interesting  recursive nature  a r i s e s i n the  Given a r e c u r s i v e c  n we c o n s t r u c t vector  Boolean  carry  look-ahead  functions  with  circuit  [5],  expression  + p c ( f o r n=1 , 2 , 3 , . . . ) , n n n-1 a c i r c u i t t o h a v e c a n d c' a s o u t p u t s , n n to  n  9  of  = g  equal (  example  ' 'n 9  9  1  with  input  ' 'l ' 9  n ' 'n 1 ' 'l ' 0 ' 'o First o f a l l , t h e f u n c t i o n c = g + p c„ c a n be r e a l i z e d a s 1 1 M O the c i r c u i t i n F i g . 2 . 5 ( a ) , and i s t h e b a s i c circuit f o r the P  P  P  P  C  C  K  y  recursion. for  c  n  Fig.2.5(b)  shows a g e n e r a l  , with a stacking height  For  Boolean  expressions  and  function P =  i t s symbolic  Fig.2.6(a) complex  t h e DCVS t r e e n e t w o r k s .  ••••  representation the  x n  ?  t  n  e  corresponding  a r e shown i n  Consider structure  Fig.2.6(a).  Using  b a s i c b u i l d i n g b l o c k , we c a n c o n s t r u c t  more  functions f  where P  as  t o 2n+1.  c o n s i s t i n g o f o n l y a few p r o d u c t  terms, i t i s easy t o c o n s t r u c t a simple  equal  s t r u c t u r e of the c i r c u i t  1  literals.  1  = P y + P„ y" a n d f = P + P„ , .1 2 2 1 2  ,  1  1  a r e two d i f f e r e n t p r o d u c t t e r m s , Their  respectively.  structures  are  shown  in  and  y,  y'  are  F i g . 2 . 6 ( b ) and (c)  F i g . 2 . 5 ( a ) DCVS c i r c u i t  f o rthe function  c  = g  + P  1  LOAO  BLOCK (n-i) — _ r  I  BLOCK (n)  J . F i g . 2 . 5 ( b ) R e c u r s i v e DCVS s t r u c t u r e c  n  =  9n  +  Pn n - 1 c  f o rthe function  16  P  P  >  HE  F i g . 2 . 6 ( a ) The DCVS t r e e a n d i t s s y m b o l i c r e p r e s e n t a t i o n f o r t h e f u n c t i o n P *= x x .... x 1  2  1  F i g . 2 . 6 ( b ) DCVS i m p l e m e n t ation f o rthe function f  i =  p  iy  +  p  2 y'  n  Ik! F i g . 2 . 6 ( c ) DCVS i m p l e m e n t ation forthe function f  2 - 1 P  +  P  2  17  K-Map  2.1.2.2  The for  Procedure  input  variable  o f a DCVS t r e e i s r e p r e s e n t e d by x. ,  i =1,2,...,n. A l i t e r a l  x'.  . A  x'.  / P.  1  cube  i sa variable  i s a s e t P of l i t e r a l s  x^ such  or  i t s negation  t h a t x. eP i m p l i e s i  l  In  a  Karnaugh  map o f n v a r i a b l e s , t h e r e a r e 2 ° c e l l s , o f  w h i c h each r e p r e s e n t s a cube c o n s i s t i n g Cells  t h a t c o n t a i n 1's a r e c a l l e d  1-cells  A 1 - l o o p t h a t e n c i r c l e s two a d j a c e n t with  one  original  less  literal  1-cell  rectangular  of e x a c t l y  (similarly,  1-cells  get  a  0-loop).  1-loops, each c o n s i s t i n g of 2  combining  new  1-loops express  Suppose  Before  two  1 - c e l l s , are adjacent  1  c u b e s , s a y Cx  and  retangular 1-loop c o n s i s t i n g  of 2  Cx'  ,  +1  1 - c e l l s by  i n t r o d u c i n g t h e K-map a l g o r i t h m , we g i v e an  demonstrate 1  some x^+x 2  of 2  x  the 3  ideas,  +x„x  carry-out f u n c t i o n of a f u l l  3  1  i . e . given  cube  C  (which  i s the  form  of the  adder), construct the corresponding  e n c i r c l e d p r o p e r l y t o form respectively.  example  t h e Boolean  DCVS t r e e . The K-map i s shown i n F i g . 2 . 7 ( a ) . The 1 - a n d  0-cells  cube  f o rthe 0-loops).  function Q = x  are  a  that  t h e t w o 1 - l o o p s , a n d t h e new 1 - l o o p e x p r e s s e s  (similarly  to  0-cells).  expresses  1  we  literals.  than each of t h e cubes r e p r e s e n t i n g t h e  (similarly,-  on a K-map. I f t h e s e  n  the minimal  cover  0-loops  f o r t h e 1- and  18  Fig.2.7(a) Encirclement of a f u l l adder  o f t h e K-map f o r t h e c a r r y - o u t f u n c t i o n  x hc  p^Vx;  2  x h 3  XfHlJ^ ^TptXl ^X3  ~5  1-tree  Fig.2.7(b)  DCVS  implementation  5  0-tree  of the carry-out of a f u l l  adder  19  Fig.2.7(b) tree  illustrates  attached  called  to  node  the resulting  Q'  the 1-tree. S i m i l a r l y ,  0-cells  DCVS  tree  pair.  i s d e r i v e d from t h e 1 - c e l l s the 0-tree  i s derived  The  and i s  from  the  a n d i s a t t a c h e d t o node Q. N o t e t h a t t h e 1- a n d 0 - t r e e s  are d i s j o i n t e d separately.  b e c a u s e t h e 1-  and  T h i s DCVS c i r c u i t  0-cells  have  been  requires ten N-devices  grouped  to realize  t h e f u n c t i o n Q. The  K-map  disjointed  1-  commonality "shared"  procedure and  0-trees.  between t h e s e  (1-cell)  e x i s t , then  cells  the  minimization  the  cube  of  device  x^P  two o r more a d j a c e n t  0-loop,  1-loop,  (10-loop)  01-cells  a d d e d , we r e v i s i t  a  simultaneously  individual  c a n be  formed  (10-cells). the previous  example.  has three types of e n c i r c l e m e n t s ,  and  t o t h e 10-loops  and  t o t h e cube P i s d e f i n e d as a  types. A 01-loop  K-map shown i n F i g . 2 . 8 ( a )  10-loop.  i sfirst  t h e n more b r a n c h e s c o r r e s p o n d i n g added  maximum  r e p r e s e n t i n g t h e cube x ^  corresponding  these concepts  corresponding  are  allows  ( 0 1 - c e l l ) . These 0 1 - c e l l s o r 1 0 - c e l l s a c t as  With  and  (0-cell)  o f two d i f f e r e n t  namely,  c o n s t r u c t t h e two  two t r e e s t o be e x p l o r e d ; f r o m t h i s a  representing  the c e l l  by e n c i r c l i n g  The  also  just  developed.  Suppose a 1 - c e l l  10-cell  It  tree structure leading to the  c o u n t c a n be  0-cell  d o e s more t h a n  The  "shared"  tree  constructed (Fig.2.8(b)),  to the  1-loop  and  0-loop  t o f o r m a c o m p l e t e DCVS t r e e ( F i g . 2 . 8 ( c ) ) . N o t e t h a t  20  x x 2  3  00  0  1  h  01  11  10  1 1  I 10-loop i  F i g . 2 . 8 ( a ) The K-map o f F i g . 2 . 7 ( a ) , b u t w i t h enc i r c l e m e n t s  F i g . 2 . 8 ( b ) The DCVS t r e e r e s u l t i n g f r o m t h e 10loops of Fig.2.8(a)  different  F i g . 2 . 8 ( c ) The c o m p l e t e DCVS t r e e r e s u l t i n g from F i g . 2 . 8 ( a )  21  only  eight  N-devices  fewer than t h e  disjointed  number o f s t a c k e d  1.  are  r e q u i r e d , w h i c h i s two d e v i c e s  tree  i n Fig.2.7(b).  l e v e l s increases  steps:  I d e n t i f y four  cells  different  Find  a  types  1-cells,  minimal  of  in  tree  the  bottom w i t h magnitude construct size  tree  first.  associated  in  the  branches of  i  i n ascending  with  top pair node  of  are always connected From  the  prime  order.  t o loops  control  to  of  are  Q, a n d x'^ a s s o c i a t e d w i t h node i  and  x  i  Q'. x ^  together.  implicants  of  a l l the 10-cells, find a may  share  t h e branches w i t h t h e t r e e i n s t e p ( 2 ) . C o n t r a r i l y  step(2),  associated  Always  of smaller  inputs  m i n i m a l c o v e r such t h a t t h e t r e e so c o n s t r u c t e d some  x^  a r e a r r a n g e d from t o p t o  branches corresponding  The  The v a r i a b l e s  The s o u r c e s o f t h e t r a n s i s t o r s w i t h g a t e i n p u t s x  3.  K-map,  cover f o r a l l the 0 1 - c e l l s . Construct the t o t h i s minimal cover.  of  the  0 1 - c e l l s and 1 0 - c e l l s .  tree corresponding each  However,  to three.  The K-map p r o c e d u r e c o n s i s t s o f f o u r  namely, 0 - c e l l s , 2.  now  the  top pair  of  w i t h node Q, a n d x  control  inputs  a s s o c i a t e d w i t h node  a r e x'^ Q'.  1 4.  F i n d a minimal cover f o r the remaining  0 - c e l l s and 1 - c e l l s .  While c o n s t r u c t i n g the t r e e , always look t r e e b r a n c h e s . The r o o t o f t h e 0 - t r e e t o node Q (node Q ' ) .  f o r t h e s h a r i n g of  (1-tree)  i s connected  22  The a b o v e p r o c e d u r e may c r e a t e if  x  i'  s  a  r  permutated  e  (e.g.  interchanged).  A l s o , t h e r e may  minimal cover,  and t o share t r e e  As  an  example,  Fig.2.9(a), structure the  given  different  be  a  and several  4-variable  ways  to  choose  K-map  as  shown  different  Fig.2.10(b).  way  leads  to  step  (3)  of  encircling  a  different  source  of F i g . 2 . 9 ( c ) of t h e c i r c u i t For  capacitances  level  generates  see  minimally i n  i n some o f t h e t r e e  the  with  numerous  indicates that the c i r c u i t performance t o that  i n Fig.2.10(b).  may  w i t h more t h a n a b o u t s i x s t a c k e d be  reduced  because  d i s c h a r g i n g the p a r a s i t i c d r a i n and source of  transistors.  So,  s i x or  less  of  for circuits  levels,  charging  capacitances  s p e e d , i t may be b e t t e r t o b r e a k u p c o m p l i c a t e d of  a s shown i n  structure,  with  would have s u p e r i o r e l e c t r i c a l  performance  circuits  skipped  f e a t u r e , combined  associated  and d r a i n c o n n e c t i o n s ,  a DCVS c i r c u i t  chains  K-map,  tree  increased. This undesirable  large parasitic  shared  the  Note t h a t t h e 1 0 - c e l l s a r e not covered  is  in  0 - c e l l s and 1 - c e l l s .  t h i s m a n i f e s t a t i o n , and thus t h e stack branches  a  (1) and (2) g e n e r a t e s t h e t r e e  i n Fig.2.9(b). Further, applying  Fig.2.10(a),  long  variables are  c o m p l e t e DCVS t r e e i n F i g . 2 . 9 ( c ) . S t e p ( 4 ) h a s b e e n  A  the  x^  structures  branches.  a p p l i c a t i o n of steps  b e c a u s e t h e r e a r e no r e m a i n i n g  the  tree  and  through  r e q u i r i n g high  logic  v a r i a b l e s . I n such c a s e s ,  into  DCVS  t h e K-map  x, x Vaa 2  oo 01 11 101-loOp;  10 X  2 3 4 X  X  F i g . 2 . 9 ( a ) K-map f o r t h e f u n c t i o n Q = x ' x ' x ' x ' + x ( *2 3 4 ) s h o w i n g t h e 10- a n d 0 1 - e n c i r c l e m e n t s 1  +  x  +  2  3  4  x  1  F i g . 2 . 9 ( b ) DCVS c i r c u i t corresponding t o the 01-loop  F i g . 2 . 9 ( c ) The c o m p l e t e DCVS circuit  24  X  4 10  00 01 1 1 00 v 1 / 1)  11  01  0  0  0  11  1  1  1  10  F i g . 2 . 1 0 ( a ) An a l t e r n a t i v e K-map o f F i g . 2 . 9 ( a )  fo\  V e n c i r c l e m e n t arrangement f o r  the  F i g . 2 . 1 0 ( b ) The c i r c u i t r e s u l t i n g f r o m F i g . 2 . 1 0 ( a ) . Compare this c i r c u i t with that in Fig.2.9(c)  25  design  p r o c e d u r e may  2.1.2.3 T a b u l a r  The  prove p a r t i c u l a r l y u s e f u l .  Method  tabular  method d e s c r i b e d  M c C l u s k e y method [7] minimal  covering  fields,  of  set.  namely; the  finding A  h e r e makes use prime  list  implicants  i t s decimal  input vector  ( x  x  index  r e p r e s e n t a t i o n on  (number o f  start with a 0- l i s t  (list  another  two  mechanism 01- c e l l s  1-list  (list  1's  the  containing  lists,  a  analogous  from the  to  using a modified  1.  0-cells  from the  records  ) of t h e  n  with  Similarly,  the  right The  order  of  f u n c t i o n ) , and  lists,  and  a of  the  0-list,  we  We a  generate  01-list.  The  10-cells  and  K-map  1-list,  approach. 10-list  Quine- McCluskey procedure r e s u l t s  and in a  Fig.2.11.  f u n c t i o n Q.  increasing  a 0-list  on  two  representation).  two  in  1 - l i s t which c o n t a i n s a l l x  their  (see T a b l e 2.1).  generation  t a b u l a r p r o c e d u r e c o n s i s t s of  Draw a  )  of the  10-list  the  1 - c e l l s and  DCVS t r e e s t r u c t u r e shown i n The  1's  From t h e s e  is  and  i n an a s c e n d i n g  c o n t a i n i n g O's).  S e l e c t i o n of m i n i m a l c o v e r s 01-list  left  in their binary  namely;  Quine-  n  input v e c t o r s are grouped i n t o records their  the  c o n v e n t i o n a l l y c o n s i s t s of 1  and  of  index  five  steps:  the  true  The i  list  vectors  (  i s subdivided  from  which c o n t a i n s a l l the  top  to  x^ into  bottom.  false vectors  of  26  I I I  L_ TREE  I  DERIVED |  I F R O M 1 - LIST |  I  1  TREE DERIVED FROM 01 - L I S T  _ J  TREE DERIVED  I I  FROM 10 - LIST  | FROM  TREE DERIVED 0 - LIST  _L  I  \ 7  F i g . 2 . 1 1 T h e b a s i c DCVS t r e e s t r u c t u r e a s i t w o u l d from a t a b u l a r l i s t  develop  27  DEC1WI REPRESENTATION  l i n n VECTOR  O F M 1P U 1 VECTOR  X, x - • • x ?  e.g. 1  0  0  1  4  1  0  0  3  0  1  1  6  1  1  0  n  > RECORD  RECORD j>i  o o o e o  T a b l e 2.1 T y p i c a l  list  f  O O  0 o  e  format f o r the t a b u l a r  OECIrR REPRESENTATO IN REDUCED N IPUT VECTOR OF REDUCED W I UT VECTOR e.g. 1  0  1  2  1  0  3  1  1  o  O  0 0  0 0  T a b l e 2.2 T y p i c a l  > RECORD  RECORD J>i  format f o r a 1 0 - l i s t  method  28  Q i s d r a w n . The r e c o r d w i t h 2.  index  i i s notated  F o r i = 1 t o n: I n t h e 1 - l i s t , e a c h row s t a r t i n g w i t h x i  is  compared  0-list.  with  the  rows  I f the reduced vector  i  = 1 within  within  ( x  ,  record  x  )  2 rows and  is  of  the  10-list  is slightly  shown i n T a b l e 2.2. The v a r i a b l e x  the  two  i  t o the  1-list  10-list.  d i f f e r e n t and i s  i s no l o n g e r  required.  t h e 1 - l i s t , e a c h row s t a r t i n g w i t h x^ = 0 w i t h i n  i i s compared w i t h 0- l i s t . the  Similarly,  the  rows  within  record  i f the reduced vector  two rows i s t h e same, c h e c k t h e s e  row  entry to the 0 1 - l i s t .  same a s t h a t o f t h e Apply  the  The  column of  of  corresponding Apply  the  tree  method  of  branches  conventional  set f o r the  1- l i s t .  Construct  the  x  ) of n  and  add  a  i s the  finding  and 0 1 - l i s t .  and l o o k when  t r e e s . Thus, a "shared"  covering  of  format of the 0 1 - l i s t  s e t f o r e a c h o f t h e two l i s t s  dominance p r o c e d u r e s ,  sharing  record  10-list.  Quine-McCluskey  minimal covering  i+1  ( x_ ,..., 2  two rows  i m p l i c a n t s t o t h e rows i n t h e 1 0 - l i s t  5.  of  For i = 0 to n - l : In  4.  i - 1 of the  two r o w s i n t h e  r e s p e c t i v e l y and a d d a row e n t r y  format  record  n  t h e same, t h e n c h e c k t h e s e  0-list  The  3.  as r e c o r d i .  procedure  unchecked the  trees  rows  by  prime Select a row  and  f o r a maximum amount constructing  the  tree i s b u i l t . of s e l e c t i n g a minimal in  the  corresponding  0-list  and  t o these  two  29  minimal  sums, b y a d d i n g more b r a n c h e s  t o t h e "shared"  T h u s , a DCVS t r e e s t r u c t u r e o f t h e f o r m shown  in  tree.  Fig.2.11  materialises. As an e x a m p l e , c o n s i d e r t h e d e s i g n comparator  by  the  tabular  b i n a r y n u m b e r s , A= A^ A^ A  method.  of  a  The  3-bit  circuit  a n d B=  ,  magnitude  c o m p a r e s two  and  gives  an  o u t p u t Q=1 w h e n e v e r A>B. We a s s i g n t h e v a r i a b l e s (  X  equal t o (  Note:  a  1  , X  2  ,  X  , X  3  4  , X  5  , X  6  3 ' 3 ' 2 ' 2 ' 1 ' 1 different assignment will A  B  A  B  A  B  )  K  lead  to a different  tree  structure. By 1-list (2)  step  (1)  (totalling  of  the  procedure,  28 r o w s ) , a n d t h e 0 - l i s t  i s performed,  a  10-list  A p p l i c a t i o n of  step  (3)  generated.  By  step  (4), a  Table  i s derived  2.4  implicants  actually  tree  i s illustrated  of  the  1-list  we r e a d i l y  from  form  that  prime the  tree  2.3 i s d r a w n .  01-list  can  be  10-list,  a minimal  and  these  prime  c o v e r i n g s e t . The " s h a r e d "  i n F i g . 2 . 1 2 . By s t e p ( 5 ) , t h e u n c h e c k e d rows  and  method  i s illustrated  no  step  i m p l i c a n t t a b l e a s shown i n  0-list  result  i n Tables  r e s p e c t i v e l y . Their corresponding minimal Quine-McCluskey  (36 r o w s ) . A f t e r  a s shown i n T a b l e  indicates  tabulate the  are  also  i n Fig.2.13.  2.5  and  2.6  sums w o r k e d o u t by t h e  i n d i c a t e d . The c o m p l e t e  DCVS  30  DECira REPRESENTATION  REDUCED INPUT VECTOR  OF REDUCED INPUT VECTOR  *5  Table  2.3  The  0  0 0 0 0 0  1  0 0 1 0 0 0 0 0 0 1  5 6 12 3 24 18  0 0 0 0 1 1  0 0 1 0 1 0  1 1 1 0 0 0  0 1 0 1 0 1  1 0 0 1 0 0  7 13 25 26  0 0 1 1  0 1 1 1  1 1 0 0  1 0 0 1  1 1 1 0  15 27 30  0 1 1 1 1 1 1 0 1 1 1 1 1 1 0  10-list  of  a  3-bit  magnitude comparator  31  DECIMAL RtPHESENTmiW PRIME IMPLICflNT N  5 x  2  X  3  x  *i  *i  x„  J 3  *i *2  Table  2.4  x  3  5 6 ? 12 13 15 18  25 26 2? 30  X  X X  5 -<6 J  J  x  M  6  x  *5  *i  *2  0 1 3  X  x„ x  '  5 X  B  x  6  X  X  X  X  X  X  X  X  X  X X  X  X  X  X  X  X  x 4 ;  X X  x  The prime  implicant  X  table  of  the  10-list  X  of  X  X  Table  2.3  F i g . 2 . 1 2 The s h a r e d DCVS t r e e c i r c u i t 1 0 - l i s t of Table 2.4  corresponding to  the  OECMRL REPRESENTATION  INPUT VECTOR  OF INPUT VECTOR *1  x  3  X  4  x  5  x  6  0 0  0 0  0 0 1 0  1 0 0 0  9 10 40 34  0 0 1 1  0 0 0 0  1 1 1 0  0 0 0 0  0 1 0 1  1 0 0 0  11 14 41 42  0 0 1 1  0 0 0 0  1 1 1 1  0 1 0 0  1 1 0 1  1 0 1 0  43 46  1 0 1 0  1 8  HIN1MRL sun =  X  2 * 3  X  5*6  +  W E  T a b l e 2.5 T h e 1 - l i s t a n d i t s m i n i m a l comparator  1 0 1 1 1 1 1 0 X ' ) 6  + x'  2  X  3  X ' 4  sum f o r t h e m a g n i t u d e  OEIlrWL ftHiUtNlMtOI  WW TECTOR  «r imn ncroR  *2 5 * x  x  x  5 B x  16  0 1 0 0 0 0  20 1? MB  0 1 0 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0  21 28 19 52 19  0 0 0 0 1 1  1 1 1 1 1 1  0 0 1 0 0 0  1 1 1 0 1 0  0 1 0 1 0 0  1 0 0 1 0 1  29 23 53 54 60 51  0 0 1 1 1 1  1 1 1 1 1 1  1 0 0 8 1 0  1 1 1 1 1 0  0 1 0 1 0 1  1 1 1 0 0 1  31 61 55  0 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 I 1  63  1 1  22  1 1 1 1  niNiim. sun = *2 yi *2*3*1  T a b l e 2.6 T h e 0 - l i s t a n d i t s m i n i m a l comparator  sum f o r t h e m a g n i t u d e  35  F i g . 2 . 1 3 The c o m p l e t e DCVS t r e e comparator  f o r the 3-bit  magnitude  36  2.2  WIRING AND  The  L A Y O U T OF C V S  high  functional  circuit  technique  circuit  layouts  being the  wirable.  tree  Several  layout  We a  first  CVS  AND-OR  and  circuit.  model of  the  However,  realize  This  optimal  circuit  of  and  designing  an a  designers densities here  between  trees.  one-dimensional  in  has  been  static  transistors  n-sided  p-sided  SCVS  trees  the  discussed  method  of  with  cascode to  find  while  still  to  compact  Method  linear,  connections  high  are  Layout  a  for  bussing  realized  consists  these  approaches  Tree  achievable  challenge  facilitate  networks  graph  density a  consider  series/parallel  side  which  One-Dimensional  2.2.1  for  poses  TREES  graph graph  requires  layout  used  to  CMOS  by  [8],  The  style layout  means  of  original  representing  the  N-MOS  for  the  P-MOS  side.  only  the  n-sided  graph  model.  Given  a  SCVS  transistors  and  connections  of  adjacent  in  the  corresponding and  hence  Euler  tree  they  graph  gates  i.e.  are  in  model,  in then  physically  them by a  edges  connected  transistors  connect  path,  network,  a  sequence  in  a  the it  drawn  manner  edges  corresponding according  circuit. is  If  possible  adjacent  diffusion of  are  to  positions  area. that  two  If  of  all  the  edges place  there  contains  to  an  exists the  to  are the  array an edges  37  of the can  g r a p h m o d e l , t h e n a l l t h e d r a i n and  be  chained  then the have  by  g r a p h can  Euler  d i f f u s i o n areas.  be  In  corresponds to a chain other  such  chains  f o r a SCVS t r e e can graph  E u l e r p a t h as The  be  several  latter  f o u n d by  Euler  path,  subgraphs  case,  path  separated  from  a r e a . Thus, a compact  layout  that  each  which  Euler  transistors  by a s e p a r a t i o n  i s no  regions  is  decomposing  the  corresponding  adjacent  i n ( b ) , and  same c o n c e p t c a n  linear  s m a l l CVS circuits  be  used to  a  Euler method  trees adjacent  with  layout  some  In  only  in  (b)  be  to  are  to each other.  For  DCVS  arrange  two two  shown i n  chosen.  s u i t a b l e f o r l a y i n g out constructing  s u c h as t r e e m a c r o s , c o m p u t e r - a s s i s t e d ,  l a y o u t methods s h o u l d  simple  which c o n t a i n s  order  a  in (c).  s t r a i g h t l i n e w i r i n g as  paths is  is illustrated  h a l f adder c e l l  (Fig.2.15(a)).  arrays  the  one-dimensional  i t s layout  Consider  DCVS t r e e s  Fig.2.15(c),  the  e x a m p l e , a SCVS t r e e shown i n F i g . 2 . 1 4 ( a ) has  networks.  adjacent  2.2.2  of  the  source  m o d e l i n t o a minimum number o f E u l e r p a t h s t h a t c o v e r  graph model. For  tree  If there  decomposed i n t o  paths.  the  The a  few  larger  two-dimensional  used [ 6 ] .  Two-Dimensional Tree Layout Method  SCVS c i r c u i t s , orderings  of  e s p e c i a l l y those with  transistors,  are  more  series/parallel naturally  realized  (SP) as  38  C  D  E  B  F  G A  B-  POLY / METAL DIFFUSION  <7Gnd Fig.2.14(c)  A  1-D  layout  of  the  circuit  in  Fig.2.14(a)  F i g . 2 . 1 5 ( c ) The l a y o u t o f a h a l f  adder  40  two-dimensional  layouts  than  linear,  one-dimensional  layouts  [ 9 ] , The t r a n s i s t o r s w h i c h c o n n e c t t o g r o u n d a r e p l a c e d bottom  row  of  the  t r e e . T r a n s i s t o r s connected i n s e r i e s  t h o s e i n t h e b o t t o m row a r e p l a c e d above the  on t h e  the connecting  on t h e s e c o n d  row,  directly  t r a n s i s t o r . This process i s repeated  t o p row c o n n e c t e d  to  the  devices  until  i s reached.  The  internal  tree  increases  t h e number o f m e t a l w i r i n g t r a c k s a v a i l a b l e f o r m a k i n g  global  connections  load  with  tree connections.  may be made i n d i f f u s i o n b e c a u s e i t  E s p e c i a l l y i n l a r g e c o l l e c t i o n s o f SCVS  t r e e s r e q u i r i n g a l a r g e number o f e x t e r n a l c o n n e c t i o n s , of  t h e use  metal t o perform i n t e r n a l w i r i n g produces congestion  f o r the  i n t e r - t r e e w i r i n g , w h i c h must n e c e s s a r i l y be made i n m e t a l . example  layout  of  the  tree  F i g . 2 . 1 6 . I t i s w e l l known transistors  may  additional  in  i s kept  degradation  diffusion  interconnection  of  to  a  reasonable  length,  the  c a n be more t h a n o f f s e t by t h e i n c r e a s e  density. Another  arranging  approach  carefully  Straight-line  i s to the  together. penalties  When  inter-tree  individual  wires  sharing  tree  In  order  common i n p u t s  must t a k e j o g s  i n terms o f w i r e  result.  ease  c o n n e c t i o n s by structure  w i r i n g b e t w e e n common v a r i a b l e s i n a d j a c e n t  i s encouraged, and t r e e s  may  i n Fig.2.14(a) i s i l l u s t r a t e d i n  h a v e an i m p a c t on p e r f o r m a n c e . H o w e v e r , i f t h e  diffusion  performance  that  An  length and  to  encourage  should  be  t o make c o n n e c t i o n s , overall  layout  v a r i a b l e bussing,  [6]. trees kept large  porosity shared  F i g . 2 . 1 6 A 2-D  l a y o u t of the c i r c u i t  i n Fig.2.14(a  42  variables (rail),  of  trees  are  p r e f e r e n t i a l l y placed  e.g.  the  v a r i a b l e A on  Fig.2.17(b).  The  set  by  interchanging  the  same  of a l l o w e d  level  by  to  other  maximizing  v a r i a b l e s of This An  the  2.3  the  logical  layout  functions  TESTING SCHEMES FOR  that,  with  IC c a n  be  operation can  and  [ 1 0 ] . The  of a f u l l  be  Level-Sensitive  row in  i s generated  variables  within  sliding  variables  to  optimal  structure  is  adder c e l l  {A,B,C} a r e  SCVS t r e e  shared  layout.  shown i n F i g . 2 . 1 7 .  symmetric  thus swapping v a r i a b l e s  i n both  in  g r o u p i n g of common v a r i a b l e s  of  different in adjacent  layout.  DCVS C I R C U I T S  design p r a c t i c e s are  threaded together  to s h i f t  layout  number o f a l i g n m e n t s b e t w e e n  some a d d i t i o n a l c i r c u i t r y ,  switch  the  same  trees.  and  This  Most s t r u c t u r e d  IC  the  f u r t h e r compacts the  s i g n a l can  tree  s e t of v a r i a b l e s  i s allowed.  trees  of  m e t h o d i s s u i t a b l e f o r b o t h DCVS and  that  rails  rail  tree configurations  columns,  the  neighbouring  example i s the  Note  top  symmetric v a r i a b l e s , s w i t c h i n g  unoccupied l e v e l s within chosen  the  i n the  into a  built  upon t h e  concept  a l l memory e l e m e n t s i n  shift  register.  A  an  control  t h e memory e l e m e n t s f r o m t h e i r n o r m a l modes o f r e g i s t e r mode. T h e n , t h e  frozen Scan  and Design  shifted (LSSD)  current  out is  IBM's  for  s t a t e of  the  examination.  discipline  for  SUM'  SUM  F i g . 2 . 1 7 ( a ) A DCVS f u l l  F i g . 2 . 1 7 ( b ) A 2-D  adder  circuit  layout of the f u l l  adder  44  structured to  design  shift  into  "Level-sensitive" logic  fort e s t a b i l i t y .  depth,  or  out  "Scan" r e f e r s t o t h e  of  any  r e f e r s t o c o n s t r a i n t s on  and  the  handling  of  element i n t h e design i s t h e " s h i f t has  state  will  exploiting circuit the  clocked  a  information  of  r e g i s t e r l a t c h " (SRL),  which  may p r o v i d e  due t o power g l i t c h e s o r a l p h a  A DCVS t r e e p r o d u c e s (called  scheme f o r  o f DCVS t r e e s  [ 1 2 ] , A DCVS  outputs  both stuck-at  [11],  different  of o n - l i n e  complementary  testability  and dynamic f a u l t  differential  paths  from  This  coverage  two  nodes  Q a n d Q b a r , r e s p e c t i v e l y , a n d r e p r e s e n t e d by a n o r d e r e d  two  paths  to  (1,0) o r (0,1).  cause  the  output  to  I t i s known t h a t a n y s i n g l e change  detection  i sa clear  tree. This  one  of  an i l l e g a l  as  space)  failure  (0,0) or  may  a  i s so c a l l e d the s e l f - t e s t i n g property  A DCVS t r e e a l s o h a s a f a u l t - s e c u r e input  (1,1)  [12].  s t a t e a t t h e o u t p u t o f any  i n d i c a t i o n of t h e presence of  shown t h a t a s i n g l e i l l e g a l  of  s t a t e f r o m one l e g a l s t a t e t o an  (non-code space) s t a t e such the  only  ground i s a c t i v e , p r o d u c i n g a l e g a l (code  output  tree  to  particles).  (Q,Q')) t o g r o u n d . U n d e r f a u l t - f r e e o p e r a t i o n ,  Thus,  due  f o r every t r e e .  pair  illegal  excitation, A key  considerably  has t h e unique property  network.  circuitry.  the s e l f - t e s t i n g property  presence  (e.g.,  describe  the  circuit  r e c e n t l y been i m p l e m e n t e d i n DCVS l o g i c We  of  ability  fault  o f DCVS t r e e s .  property.  to a functioning  i n the  It  can  be  tree can only  45  cause  the  output  [12].  illegal  are  input.  An  Fig.2.18. outputs  and  such  small to  y  of  in  (Q,Q')  is  region  of  debug in  of  the  DCVS  the  read  equal  chip  the  be  number  grid  than  when  only  test  data  which  flag  signal.  pseudo-random otherwise) sequence  using needs is  be  stored  causes  that  this to  design,  to a  be  be  increased  the  is  located. LSSD  sent  since  or  in the  the  latches  the  error  exclusive-or  off  and  no  to  down  the  and  search  is  decreased  valuable  of  The  square system  testing, chip  and  is  root  is  more  and  the  the  error over  (compressed of  suit  x  additional  enhancement  to  for  latched  the  length  a  corresponding  pattern  the  within is  number  considerable  on-chip  at  This  the  data  scheme  traditional  self-testing,  n e e d be may  points  shown  pulled  located  this  Note  an is  Fig.2.20.  error  for  flag"  be  the  and  be  other  (1,1).  in  and  An  chip.  required  observable  shown  excited,  the  "error  to  at  an  illegal  detector  only  can  in  its  is  increase  detector  correct  the  gate  than  can  if  of  state  or  inputs  output  NAND  rather  faults  chip.  its  legal  illegal  or  process  output  independent  (0,0)  is  registers  This  the  The  to  of  3-input  state  allows  off  of  is  trees,  illegal  whole to  one  boundaries,  the  both  locations  a  placing  illegal  correct  output  using  an  have  the  Fig.2.19.  which  serially pairs  The  scheme  faults  the  block  shown  help  and  that  either  can  produce  internal  observability.  A  tree  Therefore,  logical  whenever  produce  example  of  circuit  to  A DCVS  state,  inputs  of  tree  the  or  testing  testing  needs  Q'=l  0=0  I  O  Jf-B-I  (— C=0  \7  F i g . 2 . 1 8 A 3 - i n p u t NAND g a t e w i t h  illegal  inputs  HI ERRFLAG G  h  0'  >-  TEST  aocK  F i g . 2 . 1 9 An i l l e g a l  state detector  f o r DCVS t r e e s  47  SHIFT REGISTERS ;  S/fl  fK  —*  A — 3 NODE  —*  —5  —J  —J  —5  —) r  Fig.2.20 A  as  fault  detection  "^SCAN OUT  n  scheme f o r  DCVS  circuits  48  w i t h no m o d i f i c a t i o n t o t h e  circuit  needed.  49  CHAPTER 3 : C I R C U I T TECHNIQUES WITH CVS LOGIC  3.1  STATIC C I R C U I T TECHNIQUES  3.1.1. C o n v e n t i o n a l  For in  CVS C i r c u i t s  single-ended c i r c u i t s ,  Fig.3.l(a).  A  complex  i n NMOS a n d CMOS  the general concept  function  [ 2 ] i s shown  r e a l i z e d by t h e SCVS t r e e  p r o d u c e s a weak s i g n a l on node Q, w h i c h c a n be s t r e n g t h e n e d dedicated  sense  amplifier/buffer.  d e p l e t i o n N-device, NMOS  inverter  (Fig.3.1(b)). associated and  c a n be a  a n d t h e s e n s e a m p . / b u f f e r c a n be a  cascaded  with  Because  of  This  large  c a n be a c c o m p l i s h e d , at  5V,  When, t h e t r e e  at  f  logic  at  usually  improvement node  Q i s  f o r e x a m p l e , by r e d u c i n g  so  that  less  c o n f i g u r a t i o n [13]  charge  i s  i s shown i n  n e t w o r k i s a n open c i r c u i t ,  t r a n s i s t o r T1,  i n c r e a s i n g through  output  swing  ratio  on t h e c a p a c i t a n c e s o f t h e t r e e n e t w o r k .  p u l l e d high through T1  capacitances  i f thelogic  A slightly different circuit Fig.3.2.  pull-up/pull-down  t h e SCVS t r e e n e t w o r k , p e r f o r m a n c e  t o 3V w h i l e k e e p i n g V d d  manipulated  suitable the  power s a v i n g s c a n r e s u l t  decreased. Vcc  The c u r r e n t s o u r c e  pair  with  by a  w i t h t h e d r i v e on  i t s connection  t o output  node Q i s transistor  f . Feedback  t o t h e d e p l e t i o n - t y p e t r a n s i s t o r T1 m a i n t a i n s h i g h . When t h e t r e e n e t w o r k c o n d u c t s ,  t o a low v o l t a g e l e v e l ,  turning off  transistor  from  node  Q  node Q i s p u l l e d T2. Thus, t h e  5 0  Vcc Q  CURRENT  SENSE AMP.  SOURCE (1)  AND BUFFER  NODE Q  BUFFER •» f  \  SCVS TREE  X7  F i g . 3 . l ( a ) The g e n e r a l s t r u c t u r e  Vdd=5V  Vcc=3V  ic  \  o f SCVS c i r c u i t s  HI  -» f  K7  iSCVS TREE  Fig.3.1(b) A s t a t i c  NMOS SCVS c i r c u i t w i t h r e d u c e d l o g i c  swing  51  Tl  T2  ^S  3  \  SCVS TREE  F i g . 3 . 2 A n o t h e r SCVS c i r c u i t  H u  1  T  2  i n NMOS  > n  \  configuration  12  SCVS TREE  Fig.3.3 A s t a t i c  SCVS c i r c u i t  i n CMOS  52  voltage T3  w h i c h c a u s e s t h e v o l t a g e on o u t p u t f  low. f  on node f r i s e s v i a i n v e r t e r 1 1 , t u r n i n g  The a c t i o n i s r e g e n e r a t i v e  on  transistor  t o decrease t o a l o g i c  t h r o u g h t h e feedback from  output  t o t r a n s i s t o r T1. The  CMOS  general  technology  scheme i n F i g . 3 . 1 ( a )  c a n a l s o be i m p l e m e n t e d i n  ( s e e F i g . 3 . 3 ) . The c u r r e n t  source  i s a P-device  whose g a t e i s a t g r o u n d . I n v e r t e r 11 a c t s a s a CMOS b u f f e r whose transfer sensing drive  characteristics  may  o f node Q. T2 a c t s a s on  node  Q  and  s t a t e , when Q i s l o w ,  be a  adjusted  current  assisting  to  provide  booster  early  raising  i n thep u l l - u p . During  T1 i s p r o v i d i n g a DC c u r r e n t  the steady  i n order  to  s t a r t t h e p u l l - u p a c t i o n . T2 i s o f f s i n c e node f i s h i g h . Node Q rises  (SCVS t r e e o p e n ) , s l o w l y a t f i r s t , u n t i l  t h e o u t p u t o f 11  g o e s l o w a n d t u r n s on T 2 . In d e s i g n i n g the  t r u e a n d t h e c o m p l e m e n t f o r m o f t h e f u n c t i o n ; g e n e r a l l y , one  form w i l l levels for  SCVS t r e e s , i t i s a d v a n t a g e o u s t o l o o k a t b o t h  be e a s i e r t o i m p l e m e n t . The f o r m t h a t  of  The  low  level  and  current  important static  will  d e s i r e d o u t p u t c a n be t a k e n  b u f f e r . Note t h a t a l l t h e s t a t i c direct  fewer  current  source  result  in a  faster  simply  from the  s t a c k i n g c a n be p o w e r e d w i t h a h i g h e r  t h e same l o g i c  circuit.  contains  to  for high  ground,  frequency  SCVS  although operation.  circuit this  designs would  other  have  a  n o t be v e r y  I f c i r c u i t s c o n s u m i n g no  power a r e r e q u i r e d , CMOS DCVS d e s i g n  i s the solution.  53  Static NMOS  or  DCVS  CMOS  circuits  technology  respectively.  a r e commonly i m p l e m e n t e d i n e i t h e r as  shown  L e t us c o n s i d e r  family  (Fig.3.4(b)).  either  node  Q  or  only  Depending  i n Fig.3.4(a) the d i f f e r e n t i a l  on  Vdd  and  thelatch  over  conventional  P-MOS d e v i c e s . pull-up  Q' i s p u l l e d down by t h e DCVS t r e e  network.  rise  times.  smaller  and  3.1.2  static  CMOS c i r c u i t s w i t h  F i r s t , t h e use o f  of the f u l l  loading  i stypically  t h a n CMOS c i r c u i t s  Because  proposed  Split-Level  advantages  stacked  N-MOS a n d  P-transistors results  as  i n shorter  c a n be t w o o r t h r e e  CMOS c i r c u i t . T h i r d ,  input  a f a c t o r o f two o r t h r e e  times gate times  r e q u i r e complementary N-channel only  CMOS L o g i c  stack  o f t h e t r e e network, to  1  current  t o be d r i v e n , s i n c e t h e i n p u t s d r i v e  of the high  none o f t h e s e Split-Level  that  Q  devices.  Differential  capacitance  unstacked  i n load and b u f f e r c i r c u i t r y  P-channel devices  o u t p u t s Q,  form o f c i r c u i t has three  that  t h e NMOS t r e e  to static  trees are free of d i r e c t  Second, t h earea r e q u i r e d  than  capacitance smaller  sets. This  devices  logic  inputs,  g r o u n d . The l o g i c  after  CMOS  (b)  the d i f f e r e n t i a l  R e g e n e r a t i v e a c t i o n s e t s t h e PMOS l a t c h of  and  reduce  of N-devices and large a  few  the output delay  has b e t t e r ( D S L ) CMOS  performance Logic  techniques  time than  parasitic have  [14],[15]. the  c i r c u i t technique  been  However,  Differential [ 1 6 ] . The DSL  Fig.3.4(b) A  static  DCVS c i r c u i t  i n CMOS  55  circuit the  i s shown i n F i g . 3 . 5 .  same a s Two  i n DCVS, b u t  nodes  Q  and  where V t h nodes  the  N - t r a n s i s t o r s T3  reference voltage  and  see  goes  up  problems can  node Q'  i s a t 2.5V,  capability be  and  considered  be  Vth,  interconnection the  line  internal  low  problem,  result when  is initially  is fully  T2  is  logic  nodes  the  will  t h e s i z e s o f T1  Although  i s equal  on.  to a  current voltage  Node Q'  is  body  effect  t o 0.8V  on  For  example,  and  i t  is  l e v e l t h a t w o u l d have a p p e a r e d  of  i t  partially  size  of  decrease  i n l o n g e r d e l a y . Thus, a  the  o f f . The  seen w i t h t h i s t e c h n i q u e .  reduction  to  process,  at  i s i n c u t o f f mode.  then  p r o b l e m i s due Vth  N-device,  current to i t s high  t o 5V b e c a u s e T1  the  node f . A l t h o u g h this  the  from i t s low  u n t i l T3  Two  alleviates  the  S u p p o s e node Q i s p u l l e d down f r o m 2.5V  possible to destroy on  s w i n g on  f a s t , b e c a u s e T4  r a i s e d up t o 2.5V  if  I f VREF i s s e t t o Vdd/2 +  t h e l o a d c i r c u i t r y , and  switches  s t a t e very f  swing  been  tree i t s e l f .  node  connected to a  a r e c l a m p e d a t V d d / 2 . S p e e d i m p r o v e m e n t has  t h e t r e e and  on  with t h e i r gates  the  between  l e v e l , T1  tree i s  then  by a s m a l l e r l o g i c  drive  T4  Fig.3.5.  achieved  low  logic  (VREF) a r e a d d e d t o r e d u c e t h e l o g i c  Q',  Q'  the  load i s different.  i s the t h r e s h o l d v o l t a g e of  Q and  of the  In t h i s technique  and  T2  the  P-device  the output tradeoff  drive should  are chosen. Another  existing  i n the Northern  s i m u l a t i o n s show t h a t i t i s n e c e s s a r y  in  T3  and  T4.  T e l e c o m 3jim CMOS t o s e t VREF  equal  56  F i g . 3 . 5 A g e n e r a l s t r u c t u r e o f DSL  circuits  57  t o 4.2V i n o r d e r Also  t o clamp e i t h e r o f t h e nodes Q o r Q  t h e clamped l o g i c  t h e DCVS t r e e DSL  swing i s s e n s i t i v e t o the stack  swing,  DCVS c i r c u i t s due t o t h e h a l f  which r e s u l t s i n a reduction  circuit,  version  DSL  i s about twice  circuits, to  their  tree  Simulations  t h e reduced l o g i c  In  a  interconnection  stage  i t s f o l l o w i n g stage,  t h e DSL  order  to  is  kept  and long and  l o a d c i r c u i t r y . F i g . 3 . 6 ( a ) and (b) compare t h e method  of  DSL  with  that  of  DSL c i r c u i t s may be f o u n d t o be u s e f u l  metallization  full  s w i n g a t node Q a n d Q' i n  of the previous  of  of  3.3, i n d i c a t e t h a t  a s f a s t a s a DCVS v e r s i o n .  network  logic  l i n e s a r e d r a w n b e t w e e n t h e open d r a i n o u t p u t s  associated  circuits.  i n Section  the load c i r c u i t r y  the  interconnect  of  rail-to-rail  by two t i m e s o f t h e c h a r g e s  i n the c i r c u i t .  discussed  advantage  close  l e v e l of  f o r a f i x e d VREF.  n e e d e d t o be m a n i p u l a t e d  take  2.5V.  c i r c u i t s w o u l d be e x p e c t e d t o be a b o u t two t i m e s f a s t e r  than standard  adder  to  1  standard  DCVS  i fa  two-level  scheme ( F i g . 3 . 7 )  involves  scheme i s a v a i l a b l e .  3.2 DYNAMIC CVS C I R C U I T TECHNIQUES  3.2.1  Domino CMOS L o g i c  The  basic  precharging  dynamic  CVS  circuit  t h e d y n a m i c o u t p u t node ( o r n o d e s  in  the  case  of  58  OPEN DRAIN OUTPUTS  Vdtj/2 SWING IN THESE LONG INTERCONNECT LINES  n \ \  i DSL ! UUO .J  F i l l Vdd SMIN6 HERE  F i g . 3 . 6 ( a ) The i n t e r c o n n e c t i o n  F i g . 3 . 6 ( b ) The i n t e r c o n n e c t i o n  method o f DSL c i r c u i t s  m e t h o d o f DCVS  circuits  59  \ CLOCK  I SCVS TREE  i  F i g . 3 . 7 ( a ) A dynamic  SCVS  gate  F i g . 3 . 7 ( b ) A dynamic DCVS  gate  CLOCK  60  DCVS) t o a h i g h l o g i c ground  level  is  level,  while  the  path  precharge,  the path  t o Vdd  phase. At  the  the  be p u l l e d  output  down.  circuits  to  will  There  generally  either are  have  dynamic  completion  the s t a t e of  f l o a t a t the h i g h l e v e l  serious  problems  several logic  gates  or  because  have s t a b i l i z e d .  be  a p p r o a c h i s t o use The  important  transition  the  gates.  s o l v e d by a d d i n g However,  the domino c i r c u i t p r o p e r t y of a  from precharge  a  circuit.  utilization of  This  of the f u l l  a SCVS d o m i n o g a t e  simplifies  circuit  is  at  c h a r g e s h a r i n g [ 1 7 ] . An  a l l gates  clocking  in  example  i s shown i n F i g . 3 . 8 . The  the  circuit.  node Q,  dynamic output  Q  o n l y the b u f f e r ouput f i s f e d T2  P - t r a n s i s t o r which s e r v e s as the feedback level  means  i n h e r e n t s p e e d o f t h e g a t e s . An  of  logic  by  the  permits  to  high  that  and  b u f f e r 11, and  gates  inputs  technique.  domino  goes t o the s t a t i c other  in  practical  to. e v a l u a t i o n i s a c c o m p l i s h e d  greatly  will  more c l o c k  more  o f a s i n g l e c l o c k edge a p p l i e d s i m u l t a n e o u s l y t o the  the  i n s e r i e s and,  be a c t i v a t e d u n t i l i t s  T h i s problem can  the  useful  t h e d y n a m i c a p p r o a c h , no g a t e c a n  phases t o synchronize  the  i s t u r n e d o f f by a c l o c k and  t o g r o u n d i s t u r n e d o n . T h e n , d e p e n d i n g on  inputs,  path  t u r n e d o f f . Changing of i n p u t s t o the  g a t e must o c c u r d u r i n g t h i s p r e c h a r g e of  current  is  a  high  impedance  device to restore  where c h a r g e s  may  e x a m p l e o f t h i s phenomenon  be  l o s t due  follows.  the to  61  F i g . 3 . 8 A SCVS d o m i n o g a t e w i t h a f e e d b a c k  F i g . 3 . 9 A SCVS d o m i n o g a t e w i t h p r e c h a r g e d  d e v i c e T2  internal  nodes  62  During output  t h e p r e c h a r g e p h a s e , node Q  node  the  Q,  would  be  E t o F was  in  that  goes h i g h , and charge  input p a t t e r n of the  at  h i g h , no  cycle.  c y c l e , i n p u t A and i n p u t s E and  F  node Q i s s h a r e d  If  internal  remain  at  a  device  the output.  This g l i t c h  magnitude  exceeds  a  but can  The  of the  glitch  has  critical  be d e t e r m i n e d by node c a p a c i t a n c e s For Fig.3.9  level,  to  failure,  namely,  that  the  its  of  the  magnitude  be done by  networks,  a  t o be c o n n e c t e d t o Vdd  on d u r i n g  limiting can  gate.  c h a n g e a s shown i n a  through a N-device which i s only  t h e p r e c h a r g e p h a s e . The  which i s s t i l l  of  of a l l i n t e r n a l  at the b u f f e r circuit  at  if  i n each t r e e , which, i n t u r n ,  t o the capacitance  the  via  logic  value,  D  l o s s i s recovered  only  node  Q  N3  the c l o c k e d N-device which i s d i s c h a r g e d  of  low  t h e w o r s t c a s e r a t i o o f t h e sum  tree  inputs B to  e l i m i n a t e s g l i t c h e s a l t o g e t h e r . E a c h i n t e r n a l node o f  t r e e has turned  large  evaluation  N2,  t o be c o n t r o l l e d . T h i s c a n  t h e maximum number o f d e v i c e s  charge  during that time a g l i t c h occurs lead  of  and  t h r e s h o l d v o l t a g e o f an N d e v i c e . T h e r e f o r e , the  one  nodes, except  the  the  N2  previous  w i t h t h e u n c h a r g e d n o d e s N1  a v o l t a g e d r o p a t node Q. T2,  one  and  and  lead to a  during  any  thus causing feedback  T1  z e r o , and  c h a r g e d . T h i s c o n d i t i o n may  s h a r i n g problem i n the next phase  the  p h a s e . I f , f o r e x a m p l e , i n p u t A was  i n p u t s B t o D and  node  via  f i s f o r c e d down. W h e t h e r i n t e r n a l n o d e s N1  a r e c h a r g e d o r n o t d e p e n d s on evaluation  i s charged  exceptions  p r e c h a r g e d t h r o u g h T l and  are  t h e d r a i n node  t o ground i n each  63  c y c l e . This c o n f i g u r a t i o n guarantees precharged feedback  to  t h a t a l l i n t e r n a l nodes a r e  V d d - V t h , s o t h a t t h e r e i s no c h a r g e  d e v i c e T2 i n F i g . 3 . 8  i s t h u s no l o n g e r n e c e s s a r y .  A l t h o u g h t h e two s t a b i l i z i n g m e t h o d s h a v e been u s i n g SCVS d o m i n o c i r c u i t r y , circuitry. l e s s than feedback  We  they a r e a l s o  find that generally,  15 N - d e v i c e s , t h e f i r s t  applicable  to  DCVS  f o r s m a l l CVS c i r c u i t s  with  method w h i c h  requires a  o f SCVS d o m i n o g a t e s i s t h a t o n l y  i s available,  and  i t s complement  cannot  b e c a u s e o f t h e n o n - i n v e r s i o n p r o p e r t y o f t h e domino DCVS  domino  problem a  gate  has  been proposed  tree  network  has s l i g h t l y  exclusive-or  gate  as  l a r g e as would  i n SCVS l o g i c in  be o b t a i n e d logic.  l a r g e r d e v i c e count  result  of a  The  logic  cases, than i t s  i n the case of  (see S e c t i o n 2.1.2.1).  w o r s t c a s e , t h e DCVS t r e e n e t w o r k  true  a s a way t o a l l e v i a t e t h e  SCVS c o u n t e r p a r t , e . g . o n l y two more N - d e v i c e s  twice  single  the  by p r o v i d i n g c o m p l e m e n t a r y o u t p u t s [ 1 4 ] . I n some  DCVS  n-way  demonstrated  device i s s u f f i c i e n t .  The l i m i t a t i o n output  s h a r i n g . The  a  However, i n t h e  function  i f t h e f u n c t i o n was  can  be  implemented  t r e e s . One o b v i o u s e x a m p l e i s t h e NAND g a t e  shown  Fig.3.10. An a l t e r n a t i v e m e t h o d o f  generating  using  single-ended logic  called  l a t c h e d domino ( l d o m i n o ) l o g i c  shown  in  differential  t r e e s has been p r o p o s e d  outputs  i n a technique  [ 1 8 ] . An l d o m i n o  gate  is  F i g 3 . 1 1 . The c r o s s - c o u p l e d d e v i c e s T1 a n d T2 f o r m an  F i g . 3 . 1 0 ( b ) A DCVS domino NAND g a t e  65  Fig.3.11  An l a t c h e d  domino  circuit  66  unbalanced  latch/sense  amplifier  together  with  feedback  T3 a n d T 4 , w h i c h a l s o a c t a s l o a d d e v i c e s . D u r i n g phase  (0  i s high),  tree, the  latch  discharged.  However,  such  i f the logic  that  node  level.  Note  tree discharges  to  therefore  discharge  drive  stage  of  property  logic  node N2,  stays  0), o t h e r w i s e  latched,  used together reduce  the  i t  at the  a  should glitch  N1.  ina circuit circuit  area  Ldomino  c a n o n l y be a p p l i e d  and  gates  can  b u t c a n n o t be d r i v e n d i r e c t l y by  i s t o be  SCVS  u s i n g o n l y one o f t h e speed  node  i n a s e r i e s o f domino g a t e s ,  o f domino l o g i c  The  of  domino g a t e s ,  domino g a t e s . T h i s t e c h n i q u e  to  the  i fthe glitch-free  preserved.  DCVS f o r m s o f d o m i n o l o g i c  t o enhance t h e l o g i c with respect  approaches  first  flexibility  to a circuit  alone,  c a n be  while  and  implemented  retaining  the  a d v a n t a g e . A l s o , o p t i m i z a t i o n methods [ 1 9 ] o f e l i m i n a t i n g  domino  logic  incorporating  .redundancy the  are  three types  found  to  block  i s shown i n F i g . 3 . 1 2 .  gate with single-ended logic  block.  be  o f domino c i r c u i t s  l o g i c d e s i g n . An e x a m p l e c o n s t r u c t i o n f o r a  the  always  a p p e a r a t o u t p u t Q', o r e v e n c o m p l e t e f a i l u r e may o c c u r due  the accidental  logic  is  t h a t t h e i n p u t g a t e s o f t h e SCVS t r e e  s t a b i l i s e d u r i n g t h e p r e c h a r g e p h a s e (0= will  by t h e l o g i c  N1  o v e r p o w e r s t h e u n b a l a n c e d l a t c h a n d node N1 s t i l l high  the evaluation  i f node N2 i s n o t d i s c h a r g e d  i s designed  devices  helpful  for  i n t o a random  glitch-free  domino  N o t i c e t h a t t h e l a t c h e d domino  i n p u t s c a n o n l y be a t t h e f i r s t  DCVS d o m i n o g a t e s a c c e p t  stage  differential  of  inputs  67  LATCH  U  LATCH  PBEOWSE EVALUATE  I  f  1_F  GLITCH-FREE DOMINO L06IC BLOCK  i  LATCHED  K  6 6'  ^  DCVS  "T^joCVS  H  K'  t  REIISTER; SCVS  Oi  SCVS  REHSTER j  LATCHED  i  H' n  SCVS  F i g . 3 . 1 2 An e x a m p l e c o n s t r u c t i o n logic block  for a glitch-free  domino  68  only,  while  inputs  or both.  3.2.2  SCVS  NORA CMOS  NORA (NO  gates  RAce)  CMOS  pipelined  the  consists  flexibility.  The  and  large  consume  technique  will  availiability almost  the  stage  techniques  logic  p-logic  as  structures.  Using  p-logic  cause long circuits gates  output buffers by  form logic  delay  times  i n t h e NORA  because  s i g n a l s . A CVS p i p e l i n e d  t h e domino  replaced  CVS  In i t s o r i g i n a l  g a t e s t o enhance  gates usually  areas.  of i n v e r s i o n same  [20] a r e suitable f o r  o f n- a n d p - l o g i c  eliminate  Fig.3.12, but with last  or single-ended  Logic  implementing structure  c a n have d i f f e r e n t i a l  of the  section  i s  CVS l o g i c b l o c k d e s c r i b e d i n i n t h e dynamic  Clocked  CMOS  gates  (CCMOS)  of the registers  (Fig.3.13). The that  race-free  the latched  precharge  properties information  s i g n a l s o r by i n p u t  o f NORA p i p e l i n e d should  or  low-low c l o c k  be  require  altered  by t h e  v a r i a t i o n s . F u t h e r m o r e , i t c a n be  shown t h a t , a f t e r t h e e v a l u a t i o n pipelined-section  not  sections  p h a s e , a p r o p e r l y - d e s i g n e d NORA  keeps i t s output r e s u l t s i n s p i t e of h i g h - h i g h overlaps  (clock  desirable  because  the control  difficult,  especially for high  skew) [ 2 0 ] , of speed  clock  This skew  circuits  property  is  i s extremely with  unmatched  69  ^  FEEDBACK TRANSISTOR  FROM OOMINO GATES  CCMOS RE6ISTER  F i g . 3 . 1 3 ( b ) The l a s t  s t a g e o f a CVS p i p e l i n e d  section  70  clock  loads or a d i s t r i b u t e d clock. Depending  on  the  types of c i r c u i t  t h a t p r e c e d e t h e CCMOS  r e g i s t e r , t h e f o u r - t r a n s i s t o r CCMOS c i r c u i t may be r e d u c e d t o three-transistor  circuit.  When  the  register  N - t y p e d y n a m i c l o g i c ( s u c h a s a CVS l o g i c shown  in  F i g . 3 . 1 4 ( a ) i s u s e d . The v e r s i o n  is  block),  p r e c e d e d by the  version  shown i n F i g . 3 . 1 4 ( b )  i s u s e d when p r e c e d e d by P - t y p e d y n a m i c l o g i c . The a d v a n t a g e the  Reduced  Clocked  significant The  two  increase  i n conductance of the c r i t i c a l  t r a n s i s t o r s i n series that  disadvantage  constraint For allow  of  path.  t u r n on when t h e p r e c h a r g e d  RCCMOS i s t h a t  on t h e c l o c k  delay  to  one  transistor.  now t h e r e i s an a d d i t i o n a l  skew, a s i s d i s c u s s e d  later.  a h e a v i l y p i p e l i n e d s t r u c t u r e , speed c o n s i d e r a t i o n s  only  section.  one In  dynamic order  dynamic g a t e d e l a y , exploited.  to  gate  to  evaluate  be  present  containing  a  a complex f u n c t i o n  t h e l o g i c power o f CVS  0-sections  in  a  SCVS  circuits  phases,  i . e . , c h a n g i n g 0 t o 0'  obtained. In the following discussion,  within  one  should  be  a n d a DCVS g a t e a r e  stage  shown  in  i n p u t s , a 0' only  the  i s either  SCVS  the  -section i s pipelined  F i g . 3 . 1 5 ( a ) i s c o n s i d e r e d . The a r g u m e n t s  a p p l y t o t h e DCVS s t a g e . D u r i n g t h e e v a l u a t i o n N1  may  pipelined  shown i n F i g s . 3 . 1 5 ( a ) a n d ( b ) r e s p e c t i v e l y . By i n t e r c h a n g i n g clock  of  CMOS (RCCMOS) o v e r CCMOS r e g i s t e r s i s t h e  s t a t e changes t o another s t a t e a r e reduced The  a  still  p h a s e (0=1), node  f l o a t i n g o r d i s c h a r g e d d e p e n d i n g on t h e i n p u t s .  The  71  F i g . 3 . 1 5 ( a ) A NORA 0 - s e c t i o n w i t h a SCVS t r e e  F i g . 3 . 1 5 ( b ) A NORA 0 - s e c t i o n w i t h a DCVS t r e e  72  RCCMOS  register  i s a c t i n g as a c l o c k e d i n v e r t e r , and t h e output  c a n be e i t h e r h i g h o r l o w . D u r i n g t h e p r e c h a r g e p h a s e (0=0), t h e ground  path of the r e g i s t e r  i s blocked. I f the output  from the p r e v i o u s e v a l u a t i o n i s h i g h , then t h e output to  be  h i g h . I f t h e output i s low ( i . e . ,  no  charges  can  be  added  through  0 - s e c t i o n , the output changes f r e e l y latched at the f a l l i n g  when  T2.  0  0'  a  0  i s h i g h and t h e o u t p u t o f t h e f i r s t  stage  turns  low  for a and  skew.  is  Fig.3.16  0'  i s high.  the  s t a g e changes  that t h i s constraint  of  i s independent  I n some s i t u a t i o n s , output  needed. Such a c i r c u i t  but  Thus,  the  case from the might  overlap  must be l e s s t h a n t h e t i m e e q u i v a l e n t  t o a dynamic gate d e l a y ( t y p i c a l l y a  differential  from  on t o o e a r l y , a n d t h e d y n a m i c o u t p u t  b e t w e e n h i g h 0 a n d h i g h 0'  tree  Thus  i s n o t y e t l o w . The i n p u t t r a n s i s t o r  a c c i d e n t a l l y d i s c h a r g e because  SCVS  be  - s e c t i o n cascaded t o a 0 - s e c t i o n , w i t h the relevant  low t o h i g h b u t 0' second  been  edge o f 0.  c l o c k i n g d i a g r a m . The o v e r l a p c o n s t r a i n t a r i s e s when  to  i s high  Now we e x a m i n e t h e c o n s t r a i n t on t h e c l o c k shows  continues  node N1 h a s n e v e r  d i s c h a r g e d ) a n d T1 i s o n , t h e n t h e o u t p u t c o n t i n u e s because  resulting  a  few  of the clock  pipelined requires  (0-section)  nanoseconds).  stage  frequency.  that  single-ended  Notice  provides  a  i n p u t s may be  i s shown i n F i g . 3 . 1 7 . I f t h e  i s open d u r i n g t h e e v a l u a t i o n p h a s e (0=1), t h e n n o d e s  N1 a n d Q a r e h i g h a n d n o d e s N2 a n d Q' a r e l o w . O t h e r w i s e  i f node  73  i i ,  !  ! EVALUATION  f °  FOR STAGE #i+l  i Vi | OVERLAP i  \  EVALUATION  ™  STAGE #i  TINE  ' CONTRAINT  F i g . 3 . 1 6 The t i m i n g d i a g r a m f o r a 0 ' - s e c t i o n 0-section  cascaded t o a  74  Fig.3.17 A p i p e l i n e d stage which provides d i f f e r e n t i a l from s i n g l e - e n d e d i n p u t s  output  75  N1  i s d i s c h a r g e d , t h e n n o d e s N2  changes  to  low.  During  the  and Q'  c h a n g e t o h i g h and node Q  p r e c h a r g e p h a s e (0=0,  d i s c h a r g i n g p a t h o f t h e N - t y p e RCCMOS r e g i s t e r node  N1  is  and Q r e m a i n  However  i f node N1  that  Now  at  high  and  output  a n d T2 w i l l  we  is  similar  -section  shown i n F i g . 3 . 1 6 . The  should  be  p a t h t h r o u g h node Q  Thus,  we  have  l a t c h e d d u r i n g the  i s connected  precharged  on may  cause  f r e q u e n c y . To  This  next  the  the  first  stage  and  constraint  being  i s more t h a n  momentarily  an  i s a l s o independent supply  inverter within a 0-section.  N2  charging path  e r r o n e o u s c h a r g i n g o f o u t p u t node Q, low 0'  other  d a n g e r a r i s e s when 0  i s n o t h i g h y e t . Nodes N1  remove t h i s c o n s t r a i n t , we  t h r o u g h an  on  low r e s p e c t i v e l y . The  o v e r l a p t i m e b e t w e e n low 0 and delay.  the  h o l d s . However,  constraint  ( F i g . 3 . 1 8 ) . The  t o h i g h and  the output r e g i s t e r of  to  of  c o n s t r a i n t that the c l o c k o v e r l a p  clock  c h a n g e s f r o m h i g h t o low and 0'  0-clock  off.  l e s s than a dynamic gate d e l a y s t i l l  should f u r t h e r analyse the  (II)  respectively.  t o t h e p r e v i o u s a n a l y s i s f o r t h e SCVS  circuit  turned  then  t u r n o u r a t t e n t i o n a t t h e c l o c k skew c o n s t r a i n t  0'  of  If  phase.  c a s e when o u t p u t Q'  are  levels  information i s correctly  The  output  low  remain  this circuit.  we  blocked.  i s not d i s c h a r g e d a t the p r e v i o u s e v a l u a t i o n  p h a s e , t r a n s i s t o r s T1  precharge  is  d i s c h a r g e d at the p r e c e d i n g e v a l u a t i o n phase,  n o d e s Q'  shown  0'=1), t h e  0'  i f the inverter  of the using  clock the  76  '  o  •  1  /  L  I  I  t  0  I OVERLAP I TIME CONTRAINT  Fig.3.18 A timing c o n s t r a i n t a d d i t i o n a l l i n e d stage i n Fig.3.17 i s used  to Fig.3.16  i f the pipe  77  3.3  PERFORMANCE COMPARISONS OF CMOS F U L L ADDERS  Having various  discussed general  CVS  performance circuits.  circuit of  The  issues i n  techniques,  these  circuits  evaluation  the  implementation  i t i s important with  presented  (described  i n Sections  4.3  use  include  those  t e c h n i q u e s , namely, f u l l  implemented  are  listings  and outputs a r e given  A  summarized  modified  results  circuit  Fig.3.19.  f o r the  by  NORA  i n Table  and  signal  static  DCVS  static  a n d one t o g e n e r a t e  full  CMOS one  i n t h e SUM c i r c u i t  other  delay  circuit  NORA.  The  a d d e r i s shown i n to  generate  has t h e h i g h e s t stack  the  possible static  full  CMOS  f r o m t h e c o m p l e m e n t a r y i n p u t s . The f u l l  level  t h e worst  i s relatively  fast  implementations  because t h e complemented o u t p u t s a r e o b t a i n e d t h r o u g h gate  circuit  t h e c a r r y o u t s i g n a l . The 3-way  d e l a y time of t h e adder. T h i s c i r c u i t with  adders  i n A p p e n d i x A.  l a r g e s t p a r a s i t i c c a p a c i t a n c e , and thus determines  compared  we  3.1. Some o f t h e S P I C E i n p u t  Two s u b c i r c u i t s a r e i d e n t i f i e d ,  e x c l u s i v e - o r gate  case  i n d i g i t a l hardware,  CMOS, DCVS a n d DSL, a n d d y n a m i c  t e c h n i q u e s , n a m e l y , NORA,  and  Since the f u l l  i t a s a v e h i c l e f o r o u r c o m p a r i s o n p u r p o s e . The f u l l  simulated  sum  on S P I C E  T e l e c o m 3nm CMOS  and 4.4).  a d d e r i s t h e most common b u i l d i n g b l o c k  conventional  i s based  s i m u l a t i o n s with the parameters of t h e Northern process  t o compare t h e  t h e more here  of  only  one  CMOS a d d e r i s  X ^ P R O P E R T Y  C I R C U 1 T X T E C H N I O U E \ S T A T I C F U L L  CMOS  S T A T I C DCVS S T A T I C DSL  NORA  M O D I F I E D NORA DCVS NORA DCVS DOMINO  INPUT  GRTE  CRPRC1TRNCE  (FF)  OUTPUT  LORD  CRPRCITRNCE  (FF)  ft OF P-  y  DEV1CE5  / 1 /  / OF N-  UDR5T  CRSE  DELAY  TIME  (ns>  DEVICES  155  50  15/15  19  85  50  4/15  20  85  60  4/19  13  110  150  12/10  15  45  150  8/20  12  85  150  12/26  9  85  150  12/22  8  T a b l e 3.1 C o m p a r i s o n o f s i m u l a t i o n r e s u l t s f o r d i f f e r e n t types o f f u l l adders  79  Fig.3.19 A s t a t i c  CMOS f u l l  adder  80  found  to  adder,  b u t t o have a l a r g e r  and  to  almost  have  need  t h e same d e l a y a s t h e s t a t i c  more  (*2 t i m e s )  devices.  input  DCVS ( F i g . 3 . 4 ( b ) ) gate  The DSL ( F i g . 3 . 5 ) a d d e r  t h e same i n p u t g a t e c a p a c i t a n c e a n d c i r c u i t  DCVS a d d e r  o f f e r s a 35% i n c r e a s e i n performance.  full  implemented  adder  k i n d s o f CMOS s t a t i c The blocks large  which has  area  as the  Apparently, the  i n DSL i s t h e f a s t e s t amongst t h e v a r i o u s adders.  c o n v e n t i o n a l NORA a d d e r  with  serial  i s shown i n F i g . 3 . 2 0 . T h i s c i r c u i t  n-  and  p-logic  i s c h a r a c t e r i z e d by a  i n p u t g a t e c a p a c i t a n c e because o f t h e wide t r a n s i s t o r s  the p - l o g i c of  capacitance  in  b l o c k , a n d a s l o w s p e e d due t o t h e u s e o f t w o l e v e l s  gate d e l a y and because h a l f o f  the logic  i s performed  by  p-transistors. A m o d i f i e d NORA a d d e r very  special  3-way  XOR  [ 2 2 ] shown  i n Fig.3.21  contains  g a t e t o g e n e r a t e t h e sum s i g n a l .  a  This  circuit  h a s two t i m e s s m a l l e r i n p u t g a t e c a p a c i t a n c e a n d i s 20%  faster  than  accidential  the s e r i a l  F o r example,  i s possible  under  down.  similar  threshold  i s that certain  i f A=0, B=1 a n d C=1, t h e g a t e o f T14  s o u r c e o f T15) and t h e g a t e o f T15 ( o r s o u r c e  pulled at  a d d e r . The d i s a d v a n t a g e  d i s c h a r g e due t o r a c e s  conditions. (or  NORA  of  T14) a r e  I f t h e d r a i n n o d e s o f T7 a n d T10 d o n o t p u l l  r a t e s so that a v o l t a g e d i f f e r e n c e  of  more  down  than  a  i s d e v e l o p e d a c r o s s t h e g a t e n o d e s o f T14 a n d T15, t h e  d r a i n node o f  T13  discharges  accidentally.  This  requires  a  Fig.3.20 A conventional  NORA f u l l  adder  ML*  Fig.3.21  A m o d i f i e d NORA f u l l  adder  83  careful that  sizing the  o f t h e t r a n s i s t o r s a l o n g t h e d i s c h a r g i n g paths so  conductance  to  ground  and  the capacitive  a s s o c i a t e d w i t h e a c h o f t h e p u l l , down p a t h s process  control  and  detailed  e x t r a c t i o n a r e needed i f t h i s  i s equal.  simulation  circuit  through  i s to  be  A  load tight  circuit  successfully  implemented. The  DCVS NORA ( F i g . 3 . 1 5 ( b ) ) a d d e r h a s  capacitance  and  delay  time  although  t h e a r e a consumed  better,  compared  flexibility  to  than  smaller  the  i s larger.  the modified  This  NORA,  circuit  i s also  i n terms o f c i r c u i t  due t o t h e c o m p l e m e n t a r y o u t p u t s , a n d r e l i a b i l i t y a s  i ssimilar only  gate  t h e c o n v e n t i o n a l NORA a d d e r ,  a c c i d e n t a l d i s c h a r g e c a n n o t o c c u r . The DCVS d o m i n o adder  input  t o t h e DCVS NORA a d d e r i n e v e r y  kind of f u l l  domino c h a i n w i t h o u t  adder c i r c u i t  causing race  (Fig.3.10(b))  aspect.  It is  w h i c h c a n be i n c l u d e d i n a  problems.  84  CHAPTER 4 : A HIGH SPEED CVS P I P E L I N E D M U L T I P L I E R DESIGN  4.1  ALGORITHM AND ARCHITECTURE  B o t h GaAs MESFET a n d S i b i p o l a r t e c h n o l o g i e s currently  to realize  multipliers  extremely  fast  i n high-performance ICs s t i l l  some  applications,  but  a  attractive level  for  throughput  i n CMOS a r e because  of  rate  very  and  useful.  The  of  i s t h e number  i n a u n i t time i n t e r v a l . Latency  i s broadly segments  of  successive  logic  technology  is  frequently  machine. tasks  Bandwidth t h a t c a n be  i s the length of  time  t o perform a s i n g l e task. A p i p e l i n e d a r i t h m e t i c unit defined as a c o l l e c t i o n or  of hardware r e s o u r c e s  s e c t i o n s , which a r e organized  l i n e or p i p e l i n e with synchronized flow  critical  technologies.  (or,  required  In  signal  pipelined  l a t e n c y a r e two f i g u r e s o f m e r i t  rate)  as  power d i s s i p a t i o n a n d h i g h e r  a  executed  i s not  CMOS  u s e d t o d e t e r m i n e t h e c o m p u t i n g power o f throughput  digital  i s required,  of i n t e g r a t i o n compared w i t h o t h e r Bandwidth  such  o f CMOS c i r c u i t  real-time  where l a t e n c y  i t s lower  used  h a s t o be d e m o n s t r a t e d .  example  o r image p r o c e s s i n g ,  high  structures  circuits  [ 2 3 ] , [ 2 4 ] . However, t h e f e a s i b i l i t y  design  processing  logic  a r e being  subdivided  as a l i n e a r  t i m i n g c o n t r o l , such  t a s k s c a n be s i m u l t a n e o u s l y  s e c t i o n s of t h e p i p e l i n e .  called assembly that  a  e x e c u t e d by t h e  85  To d e s i g n an 8 - b i t p i p e l i n e d building  blocks  shown  multiplier,  i n Fig.3.15  subdivide the m u l t i p l i e r  and  the basic  3.17  were  i n t o k s e c t i o n s , and each  NORA  used.  section  We has  t h e maximum l a t e n c y e q u a l t o T . I t i s c o n s t r u c t e d by a l t e r n a t i n g 0 a n d 0' 0'=O,  - s e c t i o n s as i l l u s t r a t e d  the 0-sections  are  0 ' - s e c t i o n s a r e precharged.  i n Fig.4.1.  F o r phase  0=1  i n t h e e v a l u a t i o n phase w h i l e t h e 0'-section  The  outputs  are held  by t h e RCCMOS r e g i s t e r s . T h e n , f o r p h a s e 0=0 0'=1, t h e  constant  0 ' - s e c t i o n s a r e i n t h e e v a l u a t i o n phase and t h e 0 - s e c t i o n s precharged.  Now  the 0'-section  p r e v i o u s phase, a r e h e l d  outputs,  constant  evaluated  i n such  a  way  are  i n the that  the  0 ' - s e c t i o n s c a n u s e t h e i n f o r m a t i o n t o compute t h e c o r r e s p o n d i n g results.  I n t h i s way, t h e r e i s a c o m p l e t e flow of information st th from t h e 1 stage t o t h e k s t a g e a f t e r a d u r a t i o n o f k * r . The  throughput latency  rate of the pipeline  i sthe inverse  of  t h e maximum  T per s e c t i o n , not of the l a t e n c y or d u r a t i o n k*r of the  entire pipeline. Therefore, the increase i n the pipeline (number o f s e c t i o n s ) d o e s n o t a f f e c t t h e t h r o u g h p u t A number o f a l g o r i t h m s h a v e multipliers.  Cellular  Tri-section,  Bi-section  advantageous  because  cells  and  generally  possess require  been  developed  array multipliers and  they  the  use  regularity large  length  rate. for parallel  [25] such as P e z a r i s ' ,  Baugh-Wooley  scheme  are  o n l y a few t y p e s o f f u l l  adder  i n structure.  amounts  of  p r o h i b i t i v e when t h e o p e r a n d s a r e more t h a n  However,  hardware 16 b i t s .  and The  they become Dadda  f -SECTION  INPUTS  STAGE #1  AL  f -SECTION  ^-SECTION PRECHMK)  STAGE #2  I*'-SECTION  r  j -SECTION  fcV*UMTIO*  PRECHMK)  1  •'-SECTION CVMJMTIM  -SECTION o o  STAGE IK  • •  jf-SECTION m E V O K ) 1 / j -SECTION FOR QOO K]  TINE  o  OUTPUTS  F i g . 4 . 1 The NORA p i p e l i n e  scheme a n d i t s t i m i n g  87  scheme and 0 ( l o g N)  the delay  schemes a r e speedup  Wallace (N  tree  i s the  [26]  can  number o f b i t s ) ;  r a r e l y used i n m o n o l i t h i c  they  can  significant  give  enough  interconnections  for  to  and  attain  small  N  i s not the  more  algorithm  multiplier  is  been c h o s e n f o r our  Modified  of  generating  products to the technique  increases  and  array  (CSA)  A brief given  sum  two;  a  a n-1  and  a  pipelined  and  of c o u r s e ,  numbers  adding  previous  reducing  algorithm  n-bit binary  partial  results.  t h e number o f  t h i s reduces the  number  partial  of  the hardware  This  carry  required  time.  the d e t a i l e d proof  c o m p l e m e n t m u l t i p l i c a n d and =  a l l  summary o f t h e q u a t e r n a r y  below, without  A  of by  stages,  the m u l t i p l i c a t i o n  [27]  8-bit  p a r t i a l p r o d u c t s and  speed  p r o d u c t s by a f a c t o r o f save  n  shifted  be  difficult  (or Quaternary) Booth's  [ 2 9 ] . T r a d i t i o n a l l y , m u l t i p l i c a t i o n o f two consists  to  [28].  t h a t has  the  the  s t r u c t u r e . Other  newly proposed s t r u c t u r e s i n c l u d e Luk's m u l t i p l i e r  The  tree  because  considered  i r r e g u l a r i t y of the  p i p e l i n e d Dadda m u l t i p l i e r  theoretical  however, these  multipliers,  justify  the  a  ...  multiplier  a  n-2  a 1  Booth's a l g o r i t h m [30]. Let be  equal  [29]  the n - b i t  is 2's  to  , 0  and B=  b  b ... n-1 n-2 respectively. From t h e  b  b 1 0 bits of  multiplier  B,  we  obtain  the  88  Booth's recoded w . = b 3  where  digit . 2 -1  j=0,1,2...  is either times  0, ±1  the  +  2  3  D  . - 2 * b„. 2:+1  ( n - 2 ) / 2 and  b  =0.  o r ±2. E a c h p a r t i a l  N o t e t h a t t h e v a l u e of  product  multiplicand A shifted left  the product  i s given  p-z . : (  n  2 , /  3=0  When  is  formed  from  2*j b i t s . More  are  An  V *A* 2 . 2 j  3  operands  0,  octal ±1,  with  p r o c e s s o p e r a n d s w i t h up t o  more t h a n  16 b i t s a r e c o n c e r n e d ,  Booth's a l g o r i t h m r e q u i r e s p a r t i a l  ±2,  multiplication hardware and times  significant For  the  times  three  poses  overall  ±2  quaternary can and  speed  a d v a n t a g e and  be  resolved  shifting  the  elements  and  an  into  products that  Although  The extra  multiplication area  saving are  by add  a  multiplication  basic  operations bits.  structure  operation  at  product  perform  PP^  All  the  where  only  the  least  8-bit m u l t i p l i e r . Table  t h e r e l a t i o n s h i p b e t w e e n t h e m u l t i p l i c a n d A=  a partial  should  two  multiplicand  s i g n i f i c a n t b i t a r e r e q u i r e d . F o r an  and  problems.  an be  multiplicand.  Booth's a l g o r i t h m , the  p r o d u c t s c a n be g e n e r a t e d  multiplexing  shows  the  may  16  [31].  complementing partial  ±4,  t i m e a r e needed t o p r e c a l c u l a t e t h i s  the  t i m e s ±1,  ±3, times  three,  w_.  formally,  o c t a l or even h i g h e r o r d e r v e r s i o n of Booth's a l g o r i t h m used.  w.  by  This algorithm should e f f i c i e n t l y bits.  ,  a^ a^  ...  4.1 a^  = pp;? p p ^ ... pp;? . Apparently, we 8 7 0 an e x t r a a d d i t i o n t o t a k e i n t o a c c o u n t t h e a d d e r  RE COOED DIGIT J M  SIGNED TO. REPRESENTATION OF wj  0  000  +1  001  -1  101  +2  010  -2  110  PARTIAL PRODUCT PP PPe  PP  0  0  7  J  e  7 ?  ?  9  6  9  9  6  9  5  9  9  6  8  ?  9  1  r 8  i Q  0  6  7  i 9  0  J  0  0  9  4  9  5  9  4  9  4  9  3  9  i  >  5  5  > 9  4  addj PP  ppi  PPe  9  9  Q  ?  J  3 i 5 2  0 9  3  0  2  9  0  0  0  0  1  8 8  1  8  i  > 8  PPJ  2  2  1  8  0  0  B  1  1  i  9  8  j  T a b l e 4.1 A t r u t h t a b l e o f t h e m u l t i p l e x e r  0  9  9  array  90  operation  on t h e LSB b i t . H o w e v e r , i t i s p o s s i b l e  operation carry  by s i m p l y  look-ahead  using  a common c a r r y  2's  approaches  to  solve  approach i s c a l l e d some  complex  result  the  complement  a  product,  t h e " s i g n p r o p a g a t e " method,  possible The  which  first  requires  t o i m p l e m e n t . We c h o o s e t h e s e c o n d  t h e " s i g n g e n e r a t e " method [ 3 2 ] . The s i g n b i t o f  c a n be w r i t t e n 0 * „i * I. _ 2 8 i=8 5  S = pp  T h e r e a r e two  problem of sign e x t e n s i o n .  decoding l o g i c  approach c a l l e d  o  as 1 15 i + p p * £. 2 8 1=10 o  m n  2 ^ y  It  and  n i n t h b i t o f e a c h p a r t i a l p r o d u c t , i . e . , t h e s i g n b i t pp^ , 8  o u g h t t o e x t e n d a l l t h e way t o t h e l e f t .  the  technique  this  (CLA) a t t h e b o t t o m o f t h e a r r a y .  In order t o generate the c o r r e c t the  save  to delay  c a n be p r o v e d  that  S = - PP  0 ^ 8 * 2 8  + - pp  1 8  V  * 2  8  10  15 1=12  i  3 ^ P P  8  15 i=14  i  2 , 12 3 ^ 14 + - pp * 2 + - pp * 2 8  9 + 2 +  8  2  11  +2  13  +2  ^15  ^8 +2  w h e r e - PPg =1" PPg The a b o v e e q u a t i o n c a n be i n t e r p r e t e d a s : 1. 2.  Complement t h e n i n t h b i t ( p p ^ ) o f e a c h p a r t i a l p r o d u c t . 8 Add 1 t o t h e l e f t o f t h e s i g n b i t o f e a c h p a r t i a l p r o d u c t .  3.  Add  1 t o the n i n t h b i t of the f i n a l  product.  91  The a r c h i t e c t u r a l Fig.4.2. and  The r e c o d e r  generates Wj  digit  scheme o f an 8 - b i t m u l t i p l i e r  i s shown i n  b l o c k e x a m i n e s e a c h t h r e e - b i t g r o u p o f B's  t h e a p p r o p r i a t e w_. 's s i m u l t a n e o u s l y . The  is  represented  recoded  as a s i g n e d magnitude s t r i n g  ( sub^ ,  2X. , 1X. ) , w h i c h c o n s t i t u t e s t h e a c t u a l c o n t r o l s i g n a l s o f t h e multiplexers.  The m u l t i p l e x e r s p e r f o r m  0,±1,±2 o p e r a t i o n s a n d t h e reduced last  t o two o p e r a n d s t h r o u g h  stage  look-ahead  The c a r r y s a v e  level. five  input b i t s order.  scheme b e c a u s e a cascaded 3-level the  of  array  full  requires  the may  same be  (5,3)-counter  formed  and  (CSA).  as  a  The  carry  The c e l l  carry  are  save  level array  three  adders.  order  cell  which  We c a n r e d u c e t h e a r r a y a r e used i n the  k i n d of adder which to  two  advantageous is  levels  probably  output  first reduces  bits  of  t o use the 2 - l e v e l faster  than  two  a d d e r s i f i m p l e m e n t e d i n CVS l o g i c . H o w e v e r , t h e  scheme i s more e f f i c i e n t  t o t a l delay  product.  i f two ( 5 , 3 ) - c o u n t e r s  It  such  times  i n F i g s . 4 . 3 , 4.4 a n d 4.5 r e s p e c t i v e l y .  A (5,3)-counter i s a s p e c i a l  different  adder,  multiplexers  of h a l f adders and f u l l  o n l y two l e v e l s ,  products  t h e c a r r y save a r r a y  adder, which g i v e s the f i n a l  blocks are i l l u s t r a t e d  consist  partial  i s a two-operand p a r a l l e l  schemes f o r t h e r e c o d e r s ,  to  four  the m u l t i p l i c a t i o n  i n the aspect  of  partitioning  i n t o e q u a l amounts o f d e l a y a t e a c h l e v e l .  i s always important  i n a pipelined design.  This  92  A a 3  3  RECOOERS  7 6- O 8  a  MULTIPLEXERS  (Wj)  7 6  0  (PP^.addj)  j=0.1.2.3  j-0.1.2.3  1* CARRY SAVE ARRAY  ^> l5 l4-" Q n  n  n  16-BIT ADDER  O p p  Fig.4.2  The a r c h i t e c t u r a l  scheme o f  p  15 14" 0  v  r  an  8x8  r  r  multiplier  CI w  CI CI CI  F i g . 4 . 3 The c e l l  8  7  8  6  level  a  5  8  4  scheme o f a r e c o d e r  3  3  LruriJriJrLrUri  T  C3  a  2  a  i  3  0 SUb.  4 C3 H C3 H C3 HC3  C3 H C 3 HC3 C3J-C3J  .j  PP*  PP*  PP*  PP*  PP*  PP*  array  PPj  PP*  (C2)  addj  PP SAME STRUCTURE FOR j-0.1.2. 3  Fig.4.4  The c e l l  level  scheme o f a m u l t i p l e x e r  array  94  95  Three  types  of  structure  are  commonly  used  in  high  p e r f o r m a n c e p a r a l l e l a d d e r d e s i g n . They a r e 2 - b i t l o o k - a h e a d PARADD scheme) [ 3 3 ] , 4 - b i t l o o k - a h e a d solver these of  [35]  structure.  The  [ 3 4 ] , and  number o f c e l l  the  levels  p a r a l l e l a d d e r s a r e 9, 5 a n d 6 r e s p e c t i v e l y ,  16-bit  operands  (N=16).  structure.  This  requiring half  is  primarily  than  the  recurrence  r e q u i r e d by  f o r the  The 4 - b i t l o o k - a h e a d  a l w a y s f a s t e r and r e q u i r e s l e s s a r e a  (or  case  structure i s  2-bit  look-ahead  due t o t h e 4 - b i t s t r u c t u r e o n l y  the l e v e l s of the 2 - b i t s t r u c t u r e w i t h l e s s  than  t w i c e t h e d e l a y t i m e p e r l e v e l . The number o f l e v e l s r e q u i r e d by the recurrence approach.  s o l v e r s i s a b o u t t h e same a s t h e 4 - b i t  A problem of the recurrence  f a n o u t N/2 a s w e l l a s t h e l o n g w i r e s travel  N/2  bits)  equal  a  difficulty  amount ' o f  implementation. with  its cell  lower  order  s o l v e r s i s the worst  (the longest  in  different  in partitioning  delay  for  Therefore,  each  bits  level  scheme shown i n  bits  are  Fig.4.6.  computed t h r o u g h  available  a l s o ) . This combination full  c a r r y look-ahead  in  the 4 - b i t look-ahead  level  are  paths.  at  an  to  causes  This  our  case  has  the t o t a l delay  does n o t i n t r o d u c e a d d i t i o n a l d e l a y s t a g e s operand  wire  t o be d r i v e n by a s i n g l e d e v i c e . T h i s  l a r g e v a r i a t i o n s of d e l a y time introduce  look-ahead  will  i n t o an  pipelined  adder i s chosen, Notice  that  the  the r i p p l e c a r r y . This s i n c e t h e lower  earlier  time  order  (see Fig.4.5  r e q u i r e s l e s s hardware, a s compared t o a implementation.  "l5 "15  N  "  " » "13  V^"l!  *U  "ll"llV* T»  N  "V  M  8  ^ 6  ?  "  »5  5  "< * " , V , N  N  3  11,1.,  ^  I HR  HR  HB  HR  HR  HR  HR  HR  HR  HR  HR  HR  I T T T T T T T T T T TIf) T% Tg T"8 T8 T T T~l T5 " r '? ? *f> "G _  P  15 ,  \< 1*  P  5  9  .3  1, ,2 1, '„  % 1l  9  r  FR  3  r  5  %  P  A 9  8  P  8  *?  4  6  P  G  9  5 "  FR  5  Ffl 99  99,  9P„  9P. Ffl  CP  J  C5  "\2 9  1P?B  \  %  fi  5, 5  D  *v P *  1 C8  c?  C5  13  C  1  P  .13  .15  FTT P. 15 r  P. 14  CO  ll  . 1 1B  C  C5  13  1?  P  P. IB  C8  II  CP  T I T 9  —  8  ?  CR  t.  11-BIT OWJT inrXHFHD HTfCR  F i g . 4 . 6 The c e l l  ?  4* P  I  C5  9  T T T T P.. II  *v P  -BIT CRRRY RIPPLE RDOER c  r r P  I2  09  I?  *v P 5  l e v e l scheme o f a n 1 6 - b i t  adder  F  »  97  4 . 2 C E L L TYPES AND THEIR C I R C U I T S  With defined CVS  t h e f u n c t i o n s and c o n n e c t i o n s between i n d i v i d u a l i n S e c t i o n 4.1 a n d F i g . 4 . 3 - 4 . 6 ,  transistor-level  procedures  implementation  described  i n Chapter  d e s i g n i n g t h e CVS l o g i c a l the  DCVS  tree,  our  multiplier  single-ended are  output  for  Two  each  exceptions  tree  loads i l l u s t r a t e d  clocked  tree.  Suppose  structure.  In  we  each  when  only  these  need  to  cases,  Similarly, from  node  i s by ' p r u n i n g '  f r o m node  Q,  each c e l l The  every  time  we  been  unmarked t r a n s i s t o r s a r e d e l e t e d from t h e t r e e .  Now,  we w i l l  searching  starts  d i s c u s s t h e DCVS t r e e d e s i g n s f o r  of our m u l t i p l i e r . recoder  cell  CI  has  b,.. 23-1  multiplier  a  we mark t h e t r a n s i s t o r s  f o r p r e s e r v i n g t h e o u t p u t Q', p a t h Q'.  the  p r e s e r v e o n l y t h e open d r a i n  p o s s i b l e path t o ground,  the  a  outputs  w h i c h a r e c o n t a i n e d i n t h i s p a t h . A f t e r a l l t h e p a t h s have traversed,  for  i n F i g s . 3 . 1 5 ( a ) a n d 3.17 a r e u s e d .  o u t p u t Q o f a DCVS t r e e . S t a r t i n g traverse  load  i n most p a r t s o f  are  A s i m p l e method o f o b t a i n i n g a SCVS t r e e DCVS  The  are extremely useful i n  t r e e n e t w o r k s . The  The  cell.  i s r e q u i r e d , o r when d i f f e r e n t i a l  n e e d e d f r o m a SCVS  clocked  our task i s t o design a  shown i n F i g . 3 . 1 5 ( b ) , i s u s e d design.  cells  B arranged  i n 3-bit groups,  ,  b . 2]  and  b .  (the  2]+1  see Fig.4.3) as i n p u t s  98  and  w. = ( s u b . , 2 X . , 1 X . ) a s o u t p u t s . 3 3 3 D  the c e l l are  The b l o c k  a n d i t s t r u t h t a b l e a r e shown i n F i g . 4 . 7 .  three  logical  f u n c t i o n s t o be e v a l u a t e d ,  o f t h r e e d i f f e r e n t CVS t r e e s . The r e l a t i o n  the  be  recognized,  exclusive-or  tree  and  implemented  structure  shown  in  Because cell  of  there  consists  1X.= b . 3  easily  diagram  + b . can  2 ] - 1  using  2}  the  Fig.2.4(a).  DCVS  The K-map  p r o c e d u r e i n S e c t i o n 2 . 1 . 2 . 2 i s u s e d t o i m p l e m e n t t h e sub_. a n d 2 X . f u n c t i o n s , a n d t h e i r CVS t r e e s a r e shown i n F i g . 4 . 8 . 3  Now we c o n s i d e r Table  cells.  From  4 . 1 , we o b s e r v e t h a t t h e f o l l o w i n g B o o l e a n r e l a t i o n s  hold:  for  the design  j = 1 t o 4,  of the m u l t i p l e x e r  i = 0 t o 8:  add . = sub . pp. = [ ( I X . • a . ) + ( i D i where a The f i r s t  -1  • a.  2X.  3  t  1-1  ) ] © sub.  3  = s u b . a n d a„ = " 0 " 3  8  Boolean f u n c t i o n add. i s evaluated  by  the  cell  C2.  3  This  cell  register cell  C3  i s very  and  i s identical  ( o r delay element) that w i l l evaluates  this circuit simple  simple  the  be  discussed  second Boolean f u n c t i o n p p  c a n be d e s i g n e d  using  a  3  1  1  -  I  and P' = (  I X ' . + a'. )• ( 3  1  2X'  . + a'. 3  1  later. 3  five-variable  i n t u i t i v e approach i s p r e f e r r e d . L e t P= 1 X . • a . + 2 X . • a . , 3  to thepipelined  -  1  ).  .  The  Although  K-map,  a  CI  Ban 0 0 0 0 1 1 1 1  2Xj lXj  F i g . 4 . 7 A recoder c e l l  Fig.4.8  The  DCVS c i r c u i t s  C1  B«-» so, 2Xi lXj 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 0 1 0 1 1 0 1 0 0 0  0 0 1 1 0 0 1 1  and  f o r the  i t s truth table  f u n c t i o n s 2 X J and  sub  100  The  s e r i e s / p a r a l l e l networks c o r r e s p o n d i n g t o f u n c t i o n P and  are  shown i n F i g . 4 . 9 .  pp?  , we e m p l o y t h e 2-way e x c l u s i v e - o r  and  replace  In order  to construct  P'  t h e DCVS n e t w o r k f o r  c o n f i g u r a t i o n of  Fig.2.4,  ( x' ) by s u b . ( s u b ' . ) a n d t r a n s i s t o r x„ 1 1 3 3 2 ( x ' ^ ) by n e t w o r k P ( P ' ) r e s p e c t i v e l y , a s shown i n F i g . 4 . 9 . The  adder  carry  save a r r a y  (FA) c e l l s . T h e i r  shown  i n Fig.4.10.  logical  For  block  The  the carry  and  generate  DCVS  "propagate"  GG  form  of  the  in  Chapter  Two  c  disadvantage 9 stack  (P's)  "generate"  are obtained  C's  The  C4,  + p n  carry  from  these  generate  and  block  diagrams  and  logical  C 5 , C6 a n d C7 a r e i l l u s t r a t e d i n function  c n  i s recursive  and  i s in  , w h e r e n £ 1. A DCVS s t r u c t u r e n-1  function  i s shown i n F i g . 2 . 5 . stack  l e v e l s f o r n=4), and t h i s a f f e c t s  the  By a p p l y i n g  through the  the block  o f t h i s t r e e network i s t h e h i g h  significantly.  signals  s t a g e i s a row o f C8 c e l l s w h i c h a r e  gates.  = g  which implements t h i s  the  c a r r y p r o p a g a t e GP. The c e l l s C 5 , C6  Note t h a t t h e l o g i c of  adder,  out  cells  n  (eg.  discussed  C4 ( s e e F i g . 4 . 6 ) e v a l u a t e s  the carry  actually exclusive-or  Fig.4.11.  been  signals  and t h e block  C7 c o m p u t e  functions  functions are  networks corresponding t o these  look-ahead  p r o p a g a t e s i g n a l s . The l a s t  the  diagrams and l o g i c a l  (HA) a n d f u l l  2.6(a) and 2 . 7 ( b ) ) .  h a l f a d d e r s . The c e l l  and  c o n s i s t s o f h a l f adder  f u n c t i o n s have a l r e a d y  (Fig.2.4,  (G's)  input x  However, t h e height  2n+1  performance  the s e r i e s / p a r a l l e l decomposition as  101  NETWORK P  NETWORK_P'  ixHI  H i  IF-  i g . 4 . 9 A DCVS c i r c u i t  t o generate  8  i-i  themultiplexed  outputs  A B C  Cout S S= A 0 B  s= AeBec  C t = AB  Cout= AB+BC+CA  ou  F i g . 4 . 1 0 The h a l f a d d e r a n d f u l l logical functions  *P4 «A H  adder blocks  *A  li-  11 11 11  es "-Co  C4  1  and t h e i r  1  G6, GPj  *A  1AJJL C6  *2h  1 1 1 1 11 -Co  C7  -Co  T  c  C3  2  V  WiVi'.V.'i '!  F i g . 4 . 1 1 The b l o c k d i a g r a m s a n d l o g i c a l look-ahead c e l l s  1  functions of carry  103  shown n+1,  i n Fig.4.12,  t h e s t a c k h e i g h t o f t h e DCVS t r e e r e d u c e s t o  w i t h t h e same number o f t r a n s i s t o r s r e q u i r e d . T h i s  of  thec i r c u i t  former  which has almost  version,  is  desirable  half  version  of the stack height of the  in  our  high  performance  application. In the  order t o synchronize  pipeline,  between l o g i c a l can in  be  s e r i e s slow  down t h e c h a r g e - u p  a r e sometimes needed shown i n  Fig.3.13(a)  smaller  input  i n 5ns  by  the  input  gate  limit  l o a d . Dynamic d e l a y  capacitance  the c i r c u i t  gate  consequently  the stages  a n d ( b ) c a n d r i v e l a r g e l o a d s w i t h a few  c a p a c i t a n c e of 15fF. A 60fF which  and  of d r i v i n g a l a r g e output  r e g i s t e r . F o r example, a 200fF high  stages  b l o c k s . The CCMOS r e g i s t e r  shown i n F i g . 4 . 1 3 ( a )  times  delay  signals properly i n  u s e d a s a d e l a y e l e m e n t . H o w e v e r , t h e two P - t r a n s i s t o r s  capability as  additional  the propagating  compared  l o a d c a n be of  t o t h e CCMOS  driven  Fig.4.13(a)  to with  a  logic  an i n p u t  l o a d d r i v e n by a CCMOS r e g i s t e r , f o r  capacitance  i s four times  that of the  dynamic d e l a y s t a g e , r e q u i r e s a l s o 5ns t o r e a c h a l o g i c  high.  c,  c,  9  9  I«;HC  BLOCK (1)  ]]K  .IF  cJC*  c t°  c \  »  BLOCK (N)  i BLOCK (N-l)j  L4i]---u4J ^  F i g . 4 . 1 2 An a l t e r n a t i v e i n Fig.2.5(a) and (b)  ^7  construction  of c i r c u i t s  iq.4.13(b) A d e l a y stage w i t h complementary  outputs  106  4 . 3 PROCESS AND SPEED C R I T E R I A  The  process  CMOS p r o c e s s Ottawa,  [36]  Canada.  Sum p r o c e s s design  chosen of  f o r our m u l t i p l i e r  Northern  This process  which has  been  Telecom  design  i s t h e 3*im  Electronics  (NTE) o f  i s t h e scaled-down v e r s i o n of the  commonly  c o m m u n i t y . Some o f t h e d e s i g n  used  by  the  university  rules are identical  t o the  5nm p r o c e s s , w h i l e o t h e r s a r e s i m p l i f i e d . The p r o c e s s features 16 —3 p-type wells ( N «5x 10 cm ) on t h e n - t y p e s u b s t r a t e 15 -3 ( N »5x 10 cm ), a p o l y s i l i c o n layer with gate oxide d t h i c k n e s s o f .05Mm, a n d a s i n g l e l a y e r o f m e t a l l i z a t i o n . a  x  The  process  i s q u i t e c o n v e n t i o n a l a n d by no means t h e most  advanced process  o f t h e t i m e . Some a d v a n c e d p r o c e s s e s  minimum f e a t u r e  size  polysilicon  down  (polysilicon  to clad  below  1.5MH.  with  Also,  metal)  r e s i s t a n c e may be u s e d t o r e d u c e t h e p o l y  line  delay.  interconnection  i t i s o f t e n a d v a n t a g e o u s t o h a v e two  s e p a r a b l e n- a n d p - w e l l s , s o t h a t d o p i n g  i n one  adjusted  possibly  doping reduces  independently  level  silicided  w i t h much s m a l l e r  sheet  Furthermore,  shrink the  of  i n thep-well.  the other, The  lower  well  c a n be  lowering the  doping  i n the p-well  t h e j u n c t i o n capacitance of t h e source  and t h e d r a i n of  t h e n - c h a n n e l t r a n s i s t o r . T h i s w o u l d be v e r y d e s i r a b l e f o r performance source  CVS  logic  because  of  t h e l a r g e shared  capacitances associated with the tree  networks.  high  d r a i n and  107  Circuit and  performance  the c i r c u i t  techniques used.  m e r i t of t h e c i r c u i t comparison of  A convenient  i s the i n v e r t e r  oscillator.  We  The  3um  f o r b o t h . The  and  as  the  to separate  the  with  level  by  2  inverter  pull-down  stage  speed  a  ring  transistor  p e r i o d of o s c i l l a t i o n  per  for  ring oscillator  r e s p e c t i v e l y , and m i n i n u m l e n g t h  delay  the  process  determined  w i d t h o f t h e p u l l - u p and  3/xm  31ns,  of  technology  f i g u r e of m e r i t f o r the  delay  [37]  a r e 5.4um a n d are used  that  have s i m u l a t e d a s e v e n - s t a g e  u s i n g the SPICE program parameters.  I t i s necessary  t e c h n i q u e from  purposes.  a process  d e p e n d s on b o t h t h e p r o c e s s  model  transistors channels  i s found  is  by  of  to  about  be  2.2ns  ( = 3 l n s / ( 2 * 7 ) ) a t 27°C. Ideally a circuit redesign In  design  adjusting  the  ideal  circuit  width  shown  N1  i s high N1  depends  a s an  is  Node  that  a  in  the  on  same  ratio  This condition the  major  i s used.  w o u l d p r o b a b l y h a v e t o be r e d o n e  s i t u a t i o n w o u l d be t h a t  improve  often  circuit  such  of t h e b u f f e r t r a n s i s t o r s  process are scaled-down. it  be  i s n o t r e q u i r e d when a d i f f e r e n t CMOS p r o c e s s  our d e s i g n , l o a d matching  further  should  process.  the  i n each c e l l .  performance  of  as the dimensions i s hard to Consider  example. A lumped model f o r  A the  i n the  fulfill  and  the dynamic  speed  by  CVS  considerations  i n F i g . 4 . 1 4 ( a ) . Suppose i n i t i a l l y  t h e v o l t a g e o f node  ( 5 V ) , w h i l e b o t h o f n o d e s N2  N3  is  t r a n s i s t o r T1  and  are  a l l o w e d t o d i s c h a r g e t h r o u g h t h e CVS i s t u r n e d on. F i n a l l y  node N3  is  low  (0V).  t r e e and  charged  to  thus Vdd  LUMPED RC MOOEL OF CVS TREE  F i g . 4 . 1 4 ( a ) A l u m p e d m o d e l o f a CVS c i r c u i t  c  lnt* o c  . 4 . 1 4 ( b ) A s i m p l i f i e d RC m o d e l o f a CVS c i r c u i t  109  t h r o u g h t h e i n t e r c o n n e c t l i n e . The t o t a l is  determined  simplified  convenient equivalent  delay  by t h e RC t i m e c o n s t a n t o f t h e CVS t r e e , p l u s t h e  RC t i m e c o n s t a n t o f t h e t o t a l o u t p u t A  gate propagation  RC  model  for calculation resistance  as  load.  shown  purposes.  and  i n Fig.4.14(b)  i s more  and C are the cvs cvs c a p a c i t a n c e o f t h e CVS t r e e .  total  R  R. a n d C. are the resistance and c a p a c i t a n c e of t h e int int interconnect line. R i s t h e o n - r e s i s t a n c e of t h e d r i v i n g o t r a n s i s t o r and C i s t h e output c a p a c i t i v e l o a d ( e g . i n p u t gate o of next stage). A c c o r d i n g t o MOS scaling laws [ 3 8 ] , the o n - r e s i s t a n c e of t r a n s i s t o r s  and R ) cannot be scaled. o cvs i s s c a l e d l i n e a r l y , and t h u s t h e d e l a y t h r o u g h t h e  However, C tree  ( R  CV s (the product R  through  C ) can cvs cvs interconnect path,  the  be  scaled  especially  down.  leads  necessarily dimensions The  to  i m p r o v e i n t h e same  ratio  i n the process are scaled  that  not  scale.  t h e c o n c l u s i o n t h a t c i r c u i t p e r f o r m a n c e may n o t  d e l a y t h r o u g h t h e CVS t r e e  two-thirds  delay  the poly l i n e , i s  d o m i n a t e d by t h e t i m e c o n s t a n t R. C. which does int i n t This  The  of  the  total  as  that  by  which  the  down. is  typically  one-half  to  gate d e l a y . T h i s i s the general  c o n c l u s i o n w h i c h c a n be  drawn  cells  T h i s c a n a l s o be shown by t h e f o l l o w i n g  in  our  design.  from  n u m e r i c a l example. C o n s i d e r a f u l l connected  to  a  60fF  load  simulations  adder c e l l  of  whose  different  output  is  t h r o u g h a 500Mm minimum w i d t h p o l y  110  l i n e . The c a p a c i t a n c e o f e a c h d i f f u s i o n of a t r a n s i s t o r regions  in  region  i s e s t i m a t e d t o be 4 0 f F , a n d t h e r e a r e  the  DCVS  tree.  The  conductance  d e s i g n e d t o be e q u i v a l e n t t o t h e c o n d u c t a n c e n-device.  Suppose  the  conductance  a l s o equal t o that of a minimum-size and  (drain or source)  of  of  respectively  [ 3 6 ] . We  such  the tree i s  a  minimum-size  of the d r i v i n g p-device i s N-device.  The  c a p a c i t a n c e of t h e p o l y l i n e a r e approximated  .22fF/mn  20  carry  out  resistance  a s I0fi/um a n d  the  following  calculation: R  cvs  C  = R  = L/[WM C (Vdd-Vth)] ~3.5kfi o ox = 40fF*20 =800fF  cvs R. =l0£i/nm * 500um = 5kfi int C. =.22fF/Mm * 500Mm = 1 l 0 f F int C = 60fF o H e n c e , we g e t R  C = 3 . 5 k n * 8 0 0 f F = 2.8ns cvs cvs ( R + R. ) * ( C. + C ) = 8.5kO*9l0fF o int int o We s e e  that  two-thirds  the that  time of  constant  the  total  of time  the  CVS  constant.  ~1.4ns  tree  is  about  This ratio i s  p r e d i c t e d by d e t a i l e d S P I C E s i m u l a t i o n s , a l t h o u g h t h e i n d i v i d u a l d e l a y t i m e s a r e f o u n d t o be a b o u t s i m p l e RC t i m e c o n s t a n t s .  d o u b l e t h o s e c a l c u l a t e d by t h e  111  4.4  SIMULATIONS OF  This  THE  section  CELLS  discusses  transistors within a cell The  multiplier  is  the  techniques  t o meet a c e r t a i n  intended  to operate  that  precharging  t i m e and  e v a l u a t i o n time  of  the d e t a i l s of s i z i n g  the t r a n s i s t o r s  in a cell  d i s c u s s the m o d e l l i n g  of t h e o u t p u t  load  characteristic There  are  CVS  gate  10ns.  (on-resistance=  must  Before  R^  r a t e of have  going  d e s i g n , we  l o a d i n g of a  the  requirement.  at a throughput  implies  capacitive  NORA  sizing  speed  50MHz. T h i s  Suppose a t r a n s i s t o r  each  of  a  into first  cell.  )  is  driving  a  C  t h r o u g h a d i s p e r s i v e l i n e o f l e n g t h -1, w i t h o r e s i s t a n c e r and c a p a c i t a n c e c per u n i t l e n g t h . o o  three  models of p r o p a g a t i o n  time along a wire t o  be  considered: 1.  Synchronous model - the p r o p a g a t i o n  2.  C a p a c i t i v e model - the p r o p a g a t i o n  time  i s constant.  r e q u i r e s 0(1) time. 2 3. D i f f u s i o n model - the p r o p a g a t i o n r e q u i r e 0( 1 ) time. Define parameters 7=cl/ C and p = r l / R . A c r i t e r i o n which o o been d e s c r i b e d model solving  for  i n Ref.  [ 2 9 ] may  simulation  the c l a s s i c a l  be  purposes.  used  to  choose  This c r i t e r i o n  with a  p r o p e r l y c h o s e n b o u n d a r y c o n d i t i o n s . The  result  F i g . 4 . 1 5 . The  relative  actual  delay  from  the  c(p,7) delay  is R*  the C  (1+7+p)  suitable  i s derived  transmission l i n e equation  variable  a  has  set  from of  i s summarized i n  in  deviation an  of  idealized  112  F i g . 4 . 1 5 Contour l i n e s  of r e l a t i v e  deviation  e(p,i)  i n Ref.[39]  HI  HI HI  i  5  ri  Fig.4.16(a) A capacitive model f o r t h e output l o a d  in F i g . 4 . 1 6 ( b ) A lumped model f o r t h e output  i  Co  RC load  113  c a p a c i t i v e m o d e l . I f (p y)  lies  t  realm, Note  the c a p a c i t i v e output that  (p,7)  model  a c o r r e c t i o n term  model t o t a k e account lies  (Fig.4.16(b)) Here  (Fig.4.16(a))  may  be  used.  r l C /R i s added t o t h e c a p a c i t i v e o o interconnect  diffusion  realm,  line the  resistance. lumped  If  RC  model  the e q u i v a l e n t  output  i s more a p p r o p r i a t e .  is  capacitance  of the  i n " the  i n the s y n c h r o n o u s or c a p a c i t i v e  an  example  i s determined.  to The  show  how  f o l l o w i n g data  l=500Mm, r=lOfi/Mm, c=.22fF/um ( p o l y =60fF, R =3.5kO o o p=rl/ R = 10*500/3500 » 1.43 o 7=cl/ C = .22*500/60 ^ 1.83 o (P,T) l i e s i n t h e c a p a c i t i v e r e g i o n  i s given: line)  C  Because  c a p a c i t i v e model can C  out  = C  be  = C  used.  o o  +  (c + r * C  + ,39tF/w  model  for  equal  SPICE  to c + r* C  which determines 1  in  0  )*1  * 500Mm  255fF choose  simulations  e q u i v a l e n t c a p a c i t a n c e c' p e r u n i t  on  0  u s e f u l parameters which help to  load  is  / R  + c'*l  - 60fF  Two  the  d+p+7)  o  = C  =  (see F i g . 4 . 1 5 ) ,  / R  q  are  the c'  l e n g t h of  and  proper 1  output .  The  max interconnect  line  . T h i s i s the p r o p o r t i o n a l constant  the dependence of e q u i v a l e n t  t h e c a p a c i t i v e m o d e l . To d e t e r m i n e  capacitance  c o  u  t  t h e maximum l e n g t h  1 14  1  max holds,  of  interconnect  we  line  under p/y  draw a s t r a i g h t l i n e  point which i n t e r s e c t s with  the  L  i s equal t o the s m a l l e r max p R / r at t h i s point, o In the  s i m u l a t i o n s of  which in  the  c a p a c i t i v e model  Fig.4.15  and  boundary of the d i f f u s i o n  of  the  two  y  values  i n d i v i d u a l c e l l s of  C  the  with  long wires  (eg. c l o c k l i n e ,  power  h e a v i l y d i s t r i b u t e d c a p a c i t i v e l o a d i s the  the  realm. /c  o  and  multiplier,  the c a p a c i t i v e output model i s g e n e r a l l y v a l i d . Only of e x c e e d i n g l y  mark  i n the  case  supply  line)  l u m p e d RC  model  used. Now gate. to  we  t u r n t o the  As m e n t i o n e d i n S e c t i o n  the  discharging delay  o u t p u t b u f f e r . We buffer  allot  4.3,  the  o f t h e CVS  6ns  total  transistors in a gate delay  is  t r e e p l u s the delay  t o t h e CVS  tree delay  and  4ns  CVS due  of  the  to  the  delay.  An CVS  problem of s i z i n g  initial  tree  such  discharging  the  equivalent  is  the  same  N-transistor.  connected  contained  in  t o s i z e the  that  path  minimum-size serially  g u e s s w o u l d be  For  as  of t h i s approach i s t o  keep  in  c o n d u c t a n c e o f any the  requires  a  path each  of  with  (see  a four  transistor  I2^tm ( = 4*3MITI) w i d e . The R  the  single  conductance  example,  transistors  t h a t p a t h t o be  transistors  advantage  Fig.4.14(b))  constant  CVS  irrespective w i t h H,  and  of i s not  the  tree height  H.  If C  s t r o n g l y d e p e n d e n t on  CVS  the  increases  linearily  transistor  width,  115  then the t r e e delay we  keep  the  h a s a l i n e a r d e p e n d e n c e on H.  individual  transistor  width  Otherwise  constant,  R  i f also  cvs increases  l i n e a r i l y w i t h H and t h e t r e e d e l a y  dependence  on  conducting path  H  [ 4 0 ] , Sometimes  p a t h h a s t h e same l e v e l  with a smaller  without  affecting  After  the  stack  transistor  the  discharge  requirement  there  CVS  of  inputs  This  inspecting  using  the  discharging  not every  of s t a c k s . I n such cases, the smaller  the  6ns. In order  tree,  task  that  we  and  may  find  tree  transistors  we  indeed  t o f i n d out the worst  t r y a l l the out  should  delay  their  i s quite formidable  possible  corresponding  because  i s t o f i n d out t h e c r i t i c a l  usually  discharging  t h e CVS t r e e s t r u c t u r e . The c i r c u i t  input  combinations  which  turn  on  paths  i s simulated  these  critical  paths.  The c r i t i c a l paths  tree  a r e many p o s s i b l e i n p u t c o m b i n a t i o n s . A b e t t e r method a n d  t h e p r o p e r method by  of  the  times.  quadratic  s i z e s h a v e been a s s i g n e d ,  meets  combinations  CVS  a  the performance.  t h r o u g h SPICE s i m u l a t i o n s  of  a  l e v e l can contain  verify  time delay  in  has  associated  discharging paths are with  the  those  largest parasitic  tree  conducting  capacitances.  make t h e e s t i m a t i o n e a s i e r , we assume t h a t t h e s o u r c e a n d of a t r a n s i s t o r have e q u a l  junction capacitance  a d i f f u s i o n node. F o r example, g i v e n as  shown  i n Fig.4.17, i t s c r i t i c a l  drain  a n d we c a l l  a c a r r y look-ahead  To  both  circuit  d i s c h a r g i n g path i s sought.  1 16  TO CLOCKED LOAD  GND NODE (DRAIN OF A CLOCKED N-OEVICE) Fig.4.17 A c i r c u i t path  example f o r f i n d i n g  \wjfl8ER OF \0IFFUSIW \W0ES PATH  n.  STflCK LEVEL 1 2 3 4  flBCD 2  3  3  ABE  3  3  2  RF  3  2  G  2  T a b l e 4.2 The d i s t r i b u t i o n in Fig.4.17  the c r i t i c a l  of d i f f u s i o n  2  discharging  TOTAL 1 OF DIFFUSION NODES III A PATH  10 8 5 2  n o d e s f o r t h e CVS t r e e  1 17  We  assign  path  starting  shared has  stack  to discharge Table  level  from t h e  capacitance  node. in  the  drain  at  of  the  stack l e v e l  through  bottom  transistor.  The  i (£1) i n a p a r t i c u l a r  path  4.2 s u m m a r i z e s t h e d i s t r i b u t i o n  i t has  paths.  the highest  The  case  simulation, By o b s e r v i n g  should  In  some c a s e s  critical  i t i s hard  i f one  path  than  the  other  eliminate  the  discharging paths simulation 1.  P  t o determine which  path  has a s m a l l e r t o t a l  path.  . Path  P  2.  2  is  more  height  (taller  f o r the simulation to r u l e s may be a p p l i e d  Suppose less  t h e r e a r e two critical  (thus  have  a b o u t t h e same t o t a l number o f d i f f u s i o n  2  nodes but t h e s t a c k h e i g h t P  paths.  is  number o f d i f f u s i o n  stack  It i s left  i n the  i s n o t needed) i f :  and 1  tree delay.  non-critical and  the  the worst case t r e e  d e t e r m i n e t h e w o r s t c a s e p a t h . Some g e n e r a l to  ABCD  t o c a r r y out the worst  output • of  nodes ( l e s s h e a v i l y branched) but h i g h e r tree)  is  s e t i n p u t s A t o D h i g h and E t o G  t h e open d r a i n  e v a l u a t i o n p h a s e , we c a n f i n d  path  nodes  s t a c k l e v e l number a n d t h e l a r g e s t  number o f d i f f u s i o n n o d e s . I n o r d e r  low.  of d i f f u s i o n  critical  total  we  nodes of t h e  a s e r i e s of i t r a n s i s t o r s t o the ground  the d i f f e r e n t conducting  because  numbers t o t h e s h a r e d  of P  is  larger  than  that  of  '  or, P  a n d P 'have a b o u t t h e same s t a c k h e i g h t b u t  l a r g e r t o t a l number o f d i f f u s i o n  nodes,  has a  118  3.  or,  P  and 2  1  P„ h a v e a b o u t t h e same s t a c k h e i g h t  and t o t a l  number o f d i f f u s i o n n o d e s b u t P^ h a s a l a r g e r p r o p o r t i o n o f diffusion  nodes  located at a higher  stack  l e v e l than  that  o f t h e m u l t i p l i e r , we f i n d  that  o f P„ . 2  After the  s i m u l a t i n g each c e l l  longest  tree delay  occurs  i n c e l l s C4 a n d  FA.  They  barely  meet t h e 6ns r e q u i r e m e n t , e v e n i f t h e e q u i v a l e n t  resistance  R  of t h e t r e e i s s e t t o t h a t  N-device.  Some  examples of c e l l The  of  a  minimum-size  simulations are given  next task  i s t o size the load devices  such  drive the required capacitive loading to a logic  the  4ns time  the  load  circuitry  . shown  T r a n s i s t o r T6 i s t h e d i s c h a r g i n g d e v i c e the  widest  transistor  P-device T l i s designed such internal  that high  they within  nodes  of  the  that  tree  to  in  and s h o u l d  Fig.4.18(a). be  i n t h e t r e e . The i t can 5V  charge  within  at  precharging up  10ns  least  N1  wide  f o r the various c e l l s  i n order  to give  p r e c h a r g e c u r r e n t . I f T1 i s t o o s m a l l , node N1 may n o t to  5V  after  to  of  charge  C  phase.  sharing,  through out  evaluation  of  sufficient rise  up  10ns. T h i s w i l l d e c r e a s e t h e a l l o w a n c e f o r v o l t a g e  d r o p a t N1 due discharging  and  during the  p r e c h a r g e p h a s e . From s i m u l a t i o n r e s u l t s , T l i s i n t h e r a n g e 12-18MII»  s  slot.  Consider  b i g as  v  i n A p p e n d i x B.  can  as  c  T4  and and  also  slow  T5 d u r i n g  down  the  the following  119  F i g . 4 . 1 8 ( a ) A NORA s t a g e w i t h s i n g l e - e n d e d o u t p u t  F i g . 4 . 1 8 ( b ) A NORA s t a g e w i t h c o m p l e m e n t a r y  outputs  120  A s u i t a b l e s i z e f o r t h e f e e d b a c k t r a n s i s t o r T2 i s most  of  4.2V  due  the  cells.  to  I f T2 i s t o o s m a l l , t h e n N1 may d r o p b e l o w  charge  non-conducting.  sharing  Since  a c c i d e n t i a l charging  3*im f o r  even  though  the  tree  is  V t h f o r T3 i s e q u a l t o 0.8V, i t may c a u s e  of C  t h r o u g h T 3 . I f T2 i s t o o l a r g e  and  out provides  a  discharge  o f N1 d u r i n g  The  significant  sizes  high  C  during  w i d e T4 a n d T5 w i l l speed  of  typical C about  Q u t  out  i t may s l o w down t h e  when t h e t r e e  i s conducting. that  f r o m 5V t o b e l o w 0.3V i n 10ns i f N1 out t h e e v a l u a t i o n phase. However, e x c e s s i v e l y have a  i f N1  negative  effect  changes t o low d u r i n g  on  the  charge-up.  evaluation. For a  e q u a l t o l 5 0 f F , a s u i t a b l e w i d t h f o r T4 a n d  T5  is  6um. The  T3  C  evaluation  current,  o f T4 a n d T5 a r e e q u a l a n d a r e c h o s e n s u c h  they can discharge stays  pull-up  will  s i z e o f T3 i s c h o s e n s u c h t h a t when N1 c h a n g e s t o l o w , provide  enough  within  4 n s . From s i m u l a t i o n  about  three  or  four  current  t o c h a r g e up  c  t o u f c  r e s u l t s , t h e w i d t h o f T3  times  that  o  a b o v e 4V should  o f T4 o r T 5 . N o t e t h a t  be even  though C  i s n o t c h a r g e d up t o a f u l l 5V ( s a y , 4V) d u r i n g the out e v a l u a t i o n phase, C w i l l u l t i m a t e l y r i s e up t o 5V i n t h e n e x t out p r e c h a r g e p h a s e b e c a u s e N1 i s n o t l i k e l y high  immediately  t h r o u g h T3.  and  thus  some  t o change from  residual  current  low will  to flow  121  Consider Fig.4.18(b).  another The  type  widths  of  OV  are equal t o 5V  phase.  and  i n 10ns A width  load  o f t r a n s i s t o r s T7  i n a s i m i l a r manner t o t h o s e T11  clocked  o f T1  and  and  T6.  provided of  N4  stays  low  T13  The  are chosen such t h a t they  as are  in  determined  s i z e s o f T10  can  during  18-21MIII i s n e e d e d f o r T10  shown  and  charge  and from  c Q  u  t  the  evaluation  T11,  if C  is out  about  l 5 0 f F . The  to  N5  when  T12  t o be  same a s , to four  N3  three the  s i z e s o f T8  i s discharged. times  The with  t o the  pads  at  t o t h e odd  d i s c u s s the  o f a d i g i t a l MOS gate  r e q u i r e the  t h e s i z e o f T8  width  N3  size  of  t o be  the  r a t i o o f T8/T9 i s s e t  buffer's  sensitivity  and  T9  may  to  the  be c h o s e n  to  OUTPUT CONSIDERATIONS  even s t a g e s ,  We  The  we  from  N3.  one  electrode,  i s divided into  end  a r e numbered f r o m one  supplied  and  A s m a l l e r s i z e o f T8  pipelined multiplier  input  stages  or T11.  l o a d i n g a t node  INPUT AND  determine the delay  Generally  to i n c r e a s e the  v o l t a g e d r o p i n N3.  4.5  T12  smaller than,  s i z e o f T10  i n order  reduce the  and  and  14 d y n a m i c  outpads at the other  t o f o u r t e e n . The  clock  s t a g e s , w h i l e t h e c l o c k l i n e 0' as  shown i n  i n p u t pad  end.  The  0  is  line  i s supplied  Fig.4.19. design  integrated c i r c u i t , have  stages  first.  The  which are  t o be p r o t e c t e d a g a i n s t  input  terminals  connected  to  a  t h e damage w h i c h  input pads U's.B's)  stags #1  •tagt  stage  f  # 3  2  stags #14  dock pad  f  F i g . 4 . 1 9 The  s t a g e s of  the  pipelined  multiplier  output pads P's  123  c o u l d be c a u s e d by e l e c t r o s t a t i c d i s c h a r g e s . B e c a u s e o f t h e v e r y high  i n p u t i m p e d a n c e o f an MOS  gate,  electric  a c c u m u l a t e d on t h e i n p u t g a t e a n d g e n e r a t e in  the gate  oxide;  permanently  t h i s gate  damaged.  A  gate  break  down  protection  ( F i g . 4 . 2 0 ( a ) ) c o n s i s t s b a s i c a l l y of a p a i r of diodes which  can  input  sink  large  be field  and  be  structure (D1 arid D2)  c u r r e n t s i f the voltage of the o f f - c h i p  i s o u t s i d e t h e range of Vdd  d i s t r i b u t e d diodes  may  a high e l e c t r i c  o x i d e may t h u s typical  charges  designed  and  Gnd,  to attenuate  and  a  series  of  t h e c u r r e n t and v o l t a g e  supplied t o the gate. The  cross-section  o f t h e p r o t e c t i o n s t r u c t u r e i s shown i n  F i g . 4 . 2 0 ( b ) . D i o d e D1 i s c o n s t r u c t e d by h a v i n g t h e n - s u b s t r a t e . N o t e t h a t a p+ d i f f u s i o n n e a r D1 t o c o l l e c t Similarly, The  t h e l a r g e amount  D2 i s f o r m e d by h a v i n g  adjacent  n+  diffusions  of  a p+ d i f f u s i o n i n  f i x e d a t Gnd i s p l a c e d holes  emitted  a n+ d i f f u s i o n  fixed  at  Vdd  by  D1.  i n the p-well.  act  as  electron  collectors. Pipeline single logic order  input  stage  #1 c o n s i s t s o f i n p u t d r i v e r s  signals to differential  stage. Transmission to  basic c e l l The precharged,  latch  the  of stage  gates  data  which  convert  s i g n a l s f o r t h e next  DCVS  are placed at the input l i n e s i n  when  i t i s v a l i d . The s c h e m a t i c  of a  #1 i s shown i n F i g . 4 . 2 1 .  transmission and t h e gate  gate  is  c l o s e d (0=0)  when t h e s t a g e i s  v o l t a g e o f T1 i s a l l o w e d  to  vary  with  124  A7£ « OFF CMP DMT  Fig.4.20(a)  DS ITRB IUTED oj ores  BATE DMT  A t y p i c a l g a t e p r o t e c t i o n s t r u c t u r e f o r i n p u t pads  Fig.4.20(b) A cross s e c t i o n of the p r o t e c t i o n in Fig.4.20(a)  structure  Fig.4.21  r  INPUT FfiON STAGE #13  The s c h e m a t i c of a b a s i c c e l l of s t a g e  — i r * i  ,  I  «jf200  H  750 ^  r  ML  4 0  #1  :  0FF CHIP OUTPUT (lOpF LOAD)  240  STAGE #14  OUTPUT PAD  F i g . 4 . 2 2 The o u t p u t s t a g e of t h e m u l t i p l i e r . The numbers i n d i c a t e t h e w i d t h s (um) of t h e t r a n s i s t o r s  126  the  i n p u t v o l t a g e . The i n p u t v o l t a g e  e v a l u a t i o n phase b e g i n s . electric  set-up  charges  time i s equal  With  a  The i n p u t s i g n a l  at  t h e gate  t o thedelay  standard  current  CMOS i n t e r f a c e , t h e i n p u t  such t h a t Q and Q  i.e.  stage  gate  voltage  logic  levels,  c a n be e v a l u a t e d  1  gate  logic  #1,  (=2ns). swing i s  i s  designed  enough d i s c h a r g i n g  w i t h i n 10ns.  I f the  o f T1 c a n o n l y go u p t o 3V, a s i n t h e c a s e o f TTL then v a l i d outputs  evaluation  t i m e o f 10ns.  f o r by i n c r e a s i n g t h e w i d t h According  Q a n d Q' may n o t be o b t a i n e d i n  H o w e v e r , t h i s c o u l d be c o m p e n s a t e d  of T1.  t o simulation r e s u l t s , a width  needed i f t h e gate v o l t a g e 5V. T h u s , s t a g e  the internal  of thehigh logic  i n c r e a s e of 60% i s level  i s 3V i n s t e a d  #1 p e r f o r m s t h e a d d i t i o n a l f u n c t i o n o f l e v e l  s h i f t i n g , and can convert for  form  o f T1. Note t h a t t h e input  s u c h t h a t a g a t e v o l t a g e o f 5V o n T1 p r o v i d e s  of  stablize  i sstored i nthe  of a transmission  f r o m 0 t o 5V. S u p p o s e t h e d r i v e r ,  an  to  t h e t r a n s m i s s i o n g a t e o p e n s (0=1), i . e . , a t t h e t i m e t h e  before  of  i s required  a TTL i n p u t s i g n a l t o a  circuit,  CMOS  o r r e s t o r e a b a d CMOS i n p u t  signal signal  (with voltage  lower  t h a n n o r m a l ) t o a good o n e .  Now  turn  o u r a t t e n t i o n t o t h e o u t p u t p a d d e s i g n . The  we  traditional  output pad u s u a l l y c o n t a i n s  w i t h an i n c r e a s i n g s i z e an  inverter  r a t i o o f 3 t o 4. The d e l a y  output pad i s g e n e r a l l y  multiplier,  three  about  t h i s output pad delay  15-25ns. will  drivers  time f o r such  For our p i p e l i n e d  be l o n g e r  than the delay  127  of  each  internal  stage.  A  new  arrangement  n e c e s s a r y . Our d e s i g n h a s o n l y one l a r g e i n v e r t e r pad,  a n d s a c r i f i c e s an e x t r a p i p e l i n e  the gate sized  l o a d of the output  such  stage  is  therefore  i n the  output  ( s t a g e #14) t o d r i v e  p a d ( F i g . 4 . 2 2 ) . The t r a n s i s t o r s  t h a t the d e l a y s of stage  #14 a n d t h e o u t p u t  are  pad a r e  e q u a l t o 10ns. Large  transistors  w i t h l a r g e v a l u e s -of w i d t h / l e n g t h  are r e q u i r e d i n the output transistors  are  d r i v e r and pad d e s i g n . G a t e s of t h e s e  usually arranged  i n t h e form  o f a meander w i t h  d r a i n a n d s o u r c e c o n t a c t s p l a c e d i n one o f t h r e e d i f f e r e n t as  illustrated  in  Fig.4.23.  The  transistor  in  resistances  the l a y o u t of simple  are  minimized.  Fig.4.23(b)  placement  of  may  contacts  To r e d u c e  be  causes  r a t i o of t h e meander-type t r a n s i s t o r , i s much l o w e r  t h a n t h e W/L  used.  ways,  Fig.4.23(a)  o c c u p i e s t h e l a r g e s t area of t h e t h r e e , a l t h o u g h t h e source drain  ratio  the area  and  occupied,  Unfortunately,  this  a d e g r a d a t i o n o f t h e W/L  i . e . , t h e a c t u a l W/L  ratio  v a l u e e s t i m a t e d from t h e t r a n s i s t o r ' s  layout [41]. The  W/L  r a t i o degradation of the t r a n s i s t o r  i s due t o t h e d i s t r i b u t e d regions. causes  The  drop  position-dependent  gate-source problem  voltage  regions  r e s i s t a n c e of  of  the  of  source  Fig.4.23(b) and  a l o n g t h e source and d r a i n biassing  the  of  transistor.  the The  drain regions  drain-source most  a p p e a r s t o be t h e d i f f e r e n c e s i n g a t e / s o u r c e  and  important v o l t a g e and  DRAIN CONTACTS  ORAIN CONTACTS  ORAIN CONTACTS  ////////////////////////A  [  '4 6ATE  SOURCE CONTACTS  (a)  ^GATE >///////////< SOURCE CONTACTS  (b)  I  I  ^GATE 2  SOURCE CONTACTS  (c)  F i g . 4 . 2 3 The t h r e e t y p e s o f c o n t a c t p l a c e m e n t i n o u t p u t pad d e s i g n  to CO  129  the  l o c a l values  values  of s o u r c e / s u b s t r a t e  o f t h r e s h o l d v o l t a g e . The  remote from the source of  the  voltage, begins transistor  to saturate,  still  operates  t h e r e f o r e has  lower  and  nonuniformly  whereas  the  the  current  the source The output  layout  pad  as  design  voltages  still  local  remain  p a r t s of t h e c h a n n e l  problem  transistor,  of  degradation  is  placed  of  the  threshold  distributed  a  decrease  that are  along  the  source  drivers.  paths  are  by  close  remote  than  This  the  was the  penalty as  drain  of from  chosen f o r W/L  ratio  in area.  possible  to  resistance  to  The the  the c o n t r i b u t i o n of because  The the  c o n t a c t s as b e f o r e .  is  voltage  the drop  r e s i s t a n c e i s " a m p l i f i e d " by i t s  gate/source  I n a b u l k CMOS  formed  small  distributed  distributed  is  a  the  resistance.  problem  alleviates  important  t h r e s h o l d and  output  i n Fig.4.23(c)  as  drain  far less  distributed  only  leaving the  source  the  with  are  while  contribution  Another  illustrated  i n t h i s work, and  contacts  e f f e c t on  part  contact.  degradation source  gate-to-source  other  the t r a n s i s t o r gate, causing  i n those  value  i n the t r i o d e r e g i o n . Even though a l l  gate/source along  a higher  v a l u e of t h e  p a r t s of t h e t r a n s i s t o r a p p r o a c h s a t u r a t i o n , the voltages  local  p a r t of the t r a n s i s t o r w h i c h i s  c o n t a c t , and  t h r e s h o l d v o l t a g e and  voltage which a f f e c t  voltages.  latch-up process  parasitic  w h i c h may the  lateral  occur  p-n-p-n pnp  i n the  (or  transistors  SCR) and  130  vertical  npn  transistors,  CMOS i n v e r t e r i n F i g . 4 . 2 4 . different  modes:  as  shown i n t h e c r o s s - s e c t i o n o f a  The i n v e r t e r c a n l a t c h  ( a ) f r o m V d d t o Gnd,  node a n d ( c ) f r o m t h e o u t p u t node will and  be j  (b)from  t o Gnd  t r i g g e r e d when j u n c t i o n s  i sreversed region  drive  f o r t h e npn t r a n s i s t o r o p e r a t i n g  electrons current nature  p^  sweeps  emitted  from  region  j  lateral  holes  biased, emitted  sufficient  i n thea c t i v e  mode.  i n turn, provide  f o r t h e pnp t r a n s i s t o r . T h i s a c t i o n i s r e g e n e r a t i v e  help prevent pnp  base  t h e p r o b l e m , we width  reduce t h e r e s i s t a n c e s R design,  (decrease  base The base in  can e i t h e r  i s p l a c e d about  R . w latch-up. Another  away f r o m t h e  f a r e n o u g h away f r o m c o n s t r a i n t s , t h e n one  t h a t no p a r t o f a n e m i t t i n g j u n c t i o n i s p h y s i c a l l y  from a s u b s t r a t e o r p - w e l l c o n t a c t  and  l50Mm  i n b e t w e e n i s u s e d t o accommodate t h e m e t a l  t h e N - t r a n s i s t o r , f o r example, due t o a r e a  distant  the  t h e PNP t r a n s i s t o r g a i n ) o r  I f t h e P - t r a n s i s t o r c a n n o t be p l a c e d  ensure  increase  and R . I n t h e case o f t h e output pad s w  the P-transistor  p - w e l l and t h earea  must  of  and p r o v i d e s  n^ w i l l ,  Latch-up  and causes f a i l u r e of t h e i n v e r t e r .  To  pad.  across  three  Vdd t o t h e output  a r e forward  amount  from  in  (Fig.4.25).  and j  b i a s e d . The l a r g e  up  A  layout  shown  i n Fig.4.26  p o t e n t i a l cause of latch-up  i s due t o an improper power-up sequence  i n order may  t o reduce R  s help t o prevent  i n p - w e l l CMOS d e v i c e s [42],  Suppose  a  CMOS  131  F i g . 4 . 2 4 The c r o s s s e c t i o n t r a n s i s t o r s shown  o f a CMOS i n v e r t e r  vdd  PI M  Nl  Nl  parasitic  OUTPUT Vdd  Vdd  9  1 M  with  J  9  - J m  —  1  J3  OUTPUT  M  F i g . 4 . 2 5 T h e l a t c h - u p modes o f a CMOS d r i v e r  SUBSTRATE CONTACTS SOURCE CONTACTS  SUBSTRATE CONTACTS SATE INPUT  DRAIN CONTACTS  ADDITIONAL RONS Of CONTACTS  OUTPUT  P-MEU CONTACTS  ML  SOURCE CONTACTS P-NELL CONTACTS  Fig.4.26  A layout of output  P-MEU.  pad which h e l p t o prevent  latch-up  to to  133  i n v e r t e r d r i v e r i s f e d by an  abnormal power-up  sequence,  V  (see F i g . 4 . 2 7 ) .  the beginning  is raised out p o w e r - u p , when V  b e f o r e Vdd is first  At  r a i s e d , base d r i v e i s  where of  supplied  to  out the  lateral  pnp,  t u r n i n g i t on  T h i s t e n d s t o t u r n on supply  base  raised,  i t may  The  the v e r t i c a l  d r i v e to the tend  (see the model i n F i g . 4 . 2 5 ( c ) ) . also,  l a t e r a l pnp.  to s u s t a i n the  remedy i s t o add  npn  a diode,  At  latch-up as  for  low  latch-up  useful  TC  boards  input  are  located  t h e c l o c k s i g n a l s 0 and clock busses i s halved  reason, busses.  sets  thus reducing The  (see  is  Fig.4.25(a)) so  that  t o t h e Vdd  l i n e which i s  thus reducing  the p o t e n t i a l  technique  is  especially "hot  on.  CELL LAYOUTS  p l a c e d at the opposite  Two  t h e p o i n t when Vdd  removed w h i l e power i s  f l o o r p l a n of the m u l t i p l i e r  pads  reduced.  This  help  c o n t a i n i n g CMOS c h i p s h a v e t o be  i . e . , i n s e r t e d and  4 . 6 FLOOR PLAN AND  The  the b e g i n n i n g ,  being . t r i g g e r e d .  where  pluggable",  at  will  shown i n F i g . 4 . 2 8 ,  c u r r e n t c a n n o t f l o w b a c k f r o m r e g i o n n^ momentarily  which  layouts  a t one  e d g e . Two 0', and  of  of  are  i n p u t pads a r e used f o r each  of  flow through  the v o l t a g e drop across and noise some  The  edge w h i l e t h e o u t p u t p a d s  so t h a t the c u r r e n t  Vdd the  i s shown i n F i g . 4 . 2 9 .  Gnd  the busses i s  pads a r e used f o r a  coupling  the  through  the  similar power  o f t h e m a j o r c e l l s a r e shown i n  g.4.27 An a b n o r m a l p o w e r - u p s e q u e n c e  F i g . 4 . 2 8 The a d d i t i o n  f o r a CMOS i n v e r t e r  o f an d i o d e t o p r e v e n t  latch-up  135  3D  8-BIT B's  8-BIT A's  I  INPUT PADS AND ORIVERS RECOOERS AND DRIVERS GnJ Gnj  MULTIPLEXER RON MULTIPLEXER ROW VdJ  MULTIPLEXER ROW MULTIPLEXER ROW  5-81T_ RIPFLE VdJ CARFY  ii-BIT CARRY LOOK-AHEAD  ADDER"  ADDER OUTPUT PADS AND DRIVERS  t  to  16-BIT P's  F i g . 4 . 2 9 The f l o o r  plan of the m u l t i p l i e r  136  Appendix  C.  The  whole  c h i p w i t h p a d s m e a s u r e s 4mm  will  be m o u n t e d i n a 4 0 - p i n p a c k a g e . The d e s i g n was  the  Canadian  Microelectronics  Northern Telecom,  in January  Corp,  1986.  the  silicon  by 4mm  and  submitted to broker for  137  CHAPTER 5 : CONCLUSION  The  new  CMOS  circuit  technique  of cascode voltage  switch  l o g i c h a s been e x a m i n e d i n t h i s t h e s i s . The f e a t u r e s o f design,  circuit  wirability  discussed  i n thecontext of  the various  conventional  CMOS t e c h n i q u e s ,  forms  static  implementation.  split  of  i.e.full  v i a SPICE s i m u l a t i o n s of a f u l l  that thed i f f e r e n t i a l  layout  have  been  o f b o t h ' s t a t i c and dynamic o p e r a t i o n . A  comparison  made  and c i r c u i t  circuit  level  CVS  logic  with  more  CMOS a n d NORA, h a s  adder c i r c u i t .  form of  CVS  F o r dynamic c i r c u i t r y  been  I t i s shown  i s the fastest  t h e DCVS c i r c u i t i s  fastest. The  major  c o n t r i b u t i o n o f t h e work i s t h e p o s t u l a t i o n a n d  d e v e l o p m e n t o f two n o v e l [43].  One m e t h o d  suitable  procedures f o r thedesign  i s b a s e d on K a r n a u g h m a p p i n g t e c h n i q u e s  f o r c i r c u i t s whose B o o l e a n f u n c t i o n s  variables  need  t o be e v a l u a t e d .  Q u i n e - M c C l u s k e y t a b u l a r method, suitable  o f CVS  f o r any  number  s i m p l e r a n d more i n s i g h t f u l  The o t h e r  of  and i s  s i x or  less  m e t h o d , b a s e d on t h e  i s more t e d i o u s t o a p p l y  of v a r i a b l e s . Both these t h a n CVS d e s i g n  trees  but i s  methods a r e  methods  previously  published. The n o v e l d e s i g n layout  an  m e t h o d s h a v e been u s e d i n t h i s  8x8 p i p e l i n e d m u l t i p l i e r .  that the m u l t i p l i e r w i l l  thesis  to  SPICE s i m u l a t i o n s i n d i c a t e  r u n a t 50MHz. T h e  multiplier  chip  i s  138  being  f a b r i c a t e d a t Northern Telecom, Ottawa. The  cascode  voltage  switch  logic  advantages over a l l other conventional term  of  performance.  difficult the  because of the l a r g e  irregular  area e f f i c i e n t regular  However,  tree and  architecture  with  MOS  c e r t a i n l y has  logic  circuit  families  up t h e c i r c u i t s may  number o f d u a l s i g n a l  structures. fast  wiring  family  lines  I t i s recommended t h a t , have  repeated c e l l s  to  be  in be and  i f both  implemented,  s h o u l d be s o u g h t .  a  139  REFERENCES  1.  L.G.Heller A  and W . R . G r i f f i n , "Cascode V o l t a g e S w i t c h  Differential  CMOS  Logic  Family",  Proc.  IEEE  "Random  Logic  Design U t i l i z i n g  Logic: ISSCC,  p p . 1 6 - 1 7 , 1984. 2.  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C o n f . on C i r c u i t s a n d  Computers, pp.147-50, 1982. 34.  G.A.Blaaum, D i g i t a l Englewood C l i f f s ,  35.  R.P.Brent  System  Implementation,  Prentice-Hall:  N J , C h a p . 2 , 1976.  a n d H.T.Kung,  "A  Regular  Layout f o r P a r a l l e l  A d d e r s " , I E E E T r a n s , on Comp., v o l . C - 3 1 , 2 6 0 - 4 , 1 9 8 2 . 36.  G . P u u k i l a , "CMC G u i d e  f o r Designers  Using  the Northern  143  Telecom  37.  CMOS3  S i m u l a t i o n o f MOS  Using  S . L i u , "The  SPICE2," E l e c t o n i c s Research  and  I EE P r o c ,  v o l . 130, and  and  L.Conway,  vol.SC-17,  "Layout  and  M.Syrzycki, MOS  v o l . 132,  A.H.Taber,  K.M.Chu  "A  Transistor 13-6,  Processes  Critique  of  to  VLSI  Related  I/V  1982. Systems,  Deformations  Characteristics",  of IEE  1985.  "Circuit IBM  696-702,  Introduction  M.Maly  5296-8,  UC  1983.  F.P.Preparata,  1980.  Latch-up",  43.  94-104,  Addison-Wesley, pp.22-3,  Meander-type  42.  Laboratory,  Speed i n VLSI Models of C o m p u t a t i o n " , IEEE J o u r n a l  of S o l i d - S t a t e C i r c u i t s ,  Proc,  Integrated  S . L . P a r t r i d g e , " C o m p a r i s o n o f MOS  G . B i l a r d i , M.Pracchi  C.Mead  Canadian  1980.  H.E.Oldham  Network  41.  IC85-6,  A . V l a d i m i r e s c u and  for VLSI",  40.  No.  1985.  Berkeley,  39.  Report  Microelectronics Corporation,  Circuits  38.  Process",  Technique  Technical  to  Disclosure  Help  Prevent  Bulletin,  CMOS  vol.26,  1984. and  Differential  D.L.Pulfrey,  Cascode V o l t a g e  of S o l i d - S t a t e C i r c u i t s ,  "Design  Procedures  Switch C i r c u i t s " ,  accepted  for  IEEE J o u r n a l  for publication,  1986.  144  Appendix A : SPICE  In t h i s three  listings  f o r the s i m u l a t i o n of f u l l  a p p e n d i x , the SPICE  different  full  adders  i n p u t and are  parameters of the N o r t h e r n Telecom the UBC  simulations. computing  The p r o g r a m s  facility.  shown. 3um  output The  adders  listings level  2 MOSFET  CMOS p r o c e s s a r e u s e d  a r e r u n on t h e MTS  of  in  system of the  Listing of -0SL1 at 22:03:44 on APR 9, 1986 for CCId'KCHU 1 2 3 4 S 6 7 8 9 10 11 12 13 14 13 16 17 18 19 20 21 22 23 24 29 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 4S 46 47 48 49 50 51 52 S3 54 55 56 57 58  Page  1»»««*«»04-09-86 ******** SPICE 20.1 (150CT80) ••••••••22:03:23***** "DIFFERENTIAL SPLIT LEVEL FULL ADDER (SUM CIRCUIT)  0*«  INPUT LISTING  TEMPERATURE •  27.000 DEO C  .OPTIONS ITL4«1000 ITL5-0 LIMPTS-300 • ML1 14 2 1 1 PDEV2 L«3U W*12U A0-71.3P AS-66.2P + P0-38.4U PS-37.2U NRS"0.61 NRD-0.55 ML2 15 3 1 1 PDEV2 L-3U W-12U AD-71.3P AS-66.2P + PD-38.4U PS-37.2U NRS-0.61 NRD-0.55 MLS 14 16 3 O NDEV2 L"3U W-12U AD-71.3P AS-71.3P • PD-38.4U PS-38.4U NRS*0.55 NRO-0.55 ML4 15 16 2 0 NDEV2 L-3U W-12U A0-71.3P AS-71.3P • P0-38.4U PS-38.4U NRS-0.5S NRD-0.55 CL1 14 0 35F CL2 15 0 35F * M1 3 4 10 0 NDEV2 L-3U W-12U AO-121.7P AS-S4.0P • P0-3O.4U PS"21U NRS-.38 NRD-1.14 M2 2 5 10 0 NDEV2 L-3U W-12U AD-71.3P AS-54.0P + PD-38.4U PS"21U NRS-.38 NRD-0.43 M3 3 5 11 O NDEV2 L-3U W-12U AD-71.3P AS-54.0P • PD-3B.4U PS*21U NRS-.3B NRO-0.43 M4 2 4 11 O N0EV2 L-3U W-12U AD-71.3P AS-54.0P • P0-38.4U PS-21U NRS-.38 NRO-0.43 MS 10 7 12 0 NDEV2 L-3U W-12U A0-S4.0P AS-121.7P • PD-21U PS-50.4U NRS-1.14 NRD-.38 M6 10 6 13 0 NDEV2 L-3U W-12U AD»54.0P AS-71.3P + PD-21U PS-38.4U NRS-0.43 NRD-.38 M7 11 6 12 O NDEV2 L-3U H-12U A0-54.OP AS-54.0P • P0-21U PS-21U NRS-.38 NRD*.38 M8 11 7 13 0 NDEV2 L"3U W-12U AD-54.0P AS"54.0P + P0-21U PS"21U NRS-.38 NRD-.38 M9 12 9 O O NDEV2 L-3U W>12U A0-54.OP AS-71.3P • P0-21U PS-38.4U NRS-0.43 NR0-.38 M10 13 8 O 0 NDEV2 L-3U W-12U A0-S4.OP AS-71.3P • P0-21U PS-38.4U NRS-0.43 NRD-0.38 CI 2 0 10F C2 3 O 10F • VDD 1 0 OC S VREF 16 O DC 4.3 VA 8 0 PWL(0 S 25NS 5 29NS 0 45NS 0 49NS S) VAN 9 O PWL(0 5 ENS S 10NS O 25NS O 29NS 5 45NS 5 49NS O) VB 6 0 PWHO 5 6NS 5 10NS O) VBN 7 O DC 5 VC 4 0 DC 5 VCN 5 0 PWL(0 5 6NS 5 10NS 0) * .MODEL PDEV2 PM0S(LEVEL-2 VT0--O.8 KP-5E-6 GAMMA-O.6 PHI-0.6 • LAMBDA-0.03 PB-0.6 CGS0-2.5E-10 CGDO-2.5E-10 CGB0-5.E-10 • RSH-80 CJ"1.5E-4 MJ-0.6 COSW-4.E-10 MJSW-0.6 JS-1.0E-5  01  9 C  O 3  ro  O v>  0>  a a »  •b  Listing of -DSL 1 at 12.-39.-9S on APR 7, 1986 for CCId-KCHU 99 60 61 62 63 64 69 66 67 6B 69 70 71 72 73 74 79 76 77 78 79 60 81 82 83 84 89 86 B7 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 1 10 111 112 1 13 1 14 1 15 1 16  Page  • T0X-9.E-8 NSUB-3.E15 XJ«5.E-7 LD-2.SE-7 U0-250 • VMAX-0.7E9) .MODEL N0EV2 NM0S(LEVEL-2 VT0-0.7 KP-16E-6 SAMMA-1.1 PH1-0.6 • LAM8DA-0.01 PB-0.7 CGS0-3.E-10 CGD0-3.E-10 CGB0-9.E-10 • RSH-2S CJ-4.4E-4 MJ-0.5 CJSW-4.E-10 MJSW-0.3 JS-1.E-9 • T0X-9.E-8 NSUB-1.7E16 XJ-6.E-7 LD-3.5E-7 UO-775 • VMAX-1.E5) .MODEL P0EV3 PM0S(LEVEL-3 VTO--O.B KP-5E-6 GAMMA«0.6 PHt-0.6 • PB"0.6 CGS0-2.5E-1O CGD0-2.5E-1O CGB0"5.E-1O • RSH-BO CJ-1.5E-4 MvJ-0.6 CJSW-4.E-10 MJSH-0.6 JS-1.0E-9 • T0X-5.E-8 NSUB-S.E19 XJ-5.E-7 LD-2.5E-7 U0-25O • VMAX-0.7E5 THETA-0.13 KAPPA-1.0 ETA-0.3) .MODEL NDEV3 NMOSUEVEL-3 VTO-0.7 KP-16E-6 OAMMA-1.1 PHI-0.6 • PB-0.7 CGS0-3.E-10 CGDD-3.E-10 CGBO-5.E-10 • RSH-25 CJ-4.4E-4 MJ'0.5 CJSW-4.E-10 MdSW-0.3 JS-1.E-9 • T0X-9.E-B NSUB-1.7E16 XJ-6.E-7 LD-3.5E-7 UO-775 • VMAX-1.E5 THETA-0.11 KAPPA-1.0 ETA-0.05) • .WIDTH OUT-80 .IC V(2)-.3 V(3)-0.3 V(10)-2 V O O - . 2 V<12)-.1 V(13)-.1 . TRAN . 5NS 60NS UK .PLOT TRAN V(2) V(3) V(I4) V(1S) (0,5) .END ........04-07-86 ••*••••• SPICE 20.1 (1S0CT80) ••••••••11:44:13****« OOSL 3-XDR TREE WIDTH-12U 0«**«  MOSFET MODEL PARAMETERS  TEMPERATURE -  27.000 DEG C  .......................................................................  0  OTVPE OLEVEL OVTO OKP OGAMMA OPHI OLAMBOA OPB OCGSO OCGDO OCGBO ORSH OCd OMd OCOSW OMJSW OOS OTOX ONSUB OX J OLD OUO OVMAX  PDEV2 PMOS 2.000 -0.800 9.OOE-06 0.600 0.600 3.OOE-02 0.600 2.90E-10 2.50E-10 9.OOE-10 BO. 000 4. 50E-04 0.600 4.OOE-10 0.600 1 .OOE-05 9.OOE-08 5.00E*15 5-OOE-07 2.50E-07 250.000 7.00E*04  NDEV2 NMOS 2.000 0.700 1 60E-05 1 . 100 0.600 1 OOE-02 0.700 3 OOE-10 3.00E-10 5 OOE-10 25.0O0 4 40E-04 0.500 4 OOE-10 0.300 1 OOE-05 5 OOE-08 1 TOE*16 6 OOE-07 3 50E-07 775.000 1 00E*05  PDEV3 PMOS 3.000 -0.800 S 00E-O6 0.600 O.60O 00 0.600 2 50E-10 2 50E-10 5 OOE-10 80.000 1 50E-04 0.600 4 OOE-10 0.600 1 OOE-05 S.00E-08 5 00E*15 5 OOE-07 2 50E-07 250.OOO 7 O0E*04  NDEV3 NMOS 3.000 0.700 1 60E-05 1 . 100 0.600 00 0.700 3 OOE-10 3 OOE-IO 5 OOE-10 25.000 4 40E-04 0.500 4 OOE-10 0.300 1 00E-05 5 OOE-08 1 70E+16 6 OOE-07 3 50E -07 775.000 1 00E+05  2  Listing of -0SL1 at 12:35:53 on APR 117 IIS 119 120 121 122 123 124 123 126 127 128 129 130 131 132 133 134 133 136 137 138 139 140 141 142 143 144 14S 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174  OTHETA OETA OKAPPA  0.0 0.0  7. 19B6 for CC1d«KCHU 0.130 0.300 1.000  0.0  0.200  0.0 0.200  Page  0.110 0.050 1.000  11:44:13*  ODSL 3-XOR TREE WIDTH*12U 0*«*»  TEMPERATURE •  TRANSIENT ANALYSIS  OLEQEND: • V(2) •; V(3) • ; V(14) $: V(1S) ;  X  TIME  x(.*.$)  00  3 OOOE-10 1 O00E-09 1 3O0E-09 2 OOOE-09 2 500E-09 3 OOOE-09 3 500E-09 4 OOOE-09 4 500E-09 5 OOOE-09 3 500E-09 6 OOOE-09 6 5O0E-09 7 000E-09 7 SOOE-09 8 OOOE-09 8 300E-09 9 OOOE-09 9 5O0E-09 f O00E-08 1 050E-08 1 100E-08 1 150E-08 1 200E-0B 1 250E-08 1 30OE-08 1 350E-0B 1 400E-08 1 450E-08 1 500E-08 1 550E-08 1 60OE-0B 1 650E-08 1 700E-08  V(2)  —  0.0  2 203E+00 1 453E*00 1.258E+00 1. 136E*00 1.060E*00 9 990E-01 9 621E-01 9 292E-01 9 O68E-01 8 850E-01 8 719E-01 8 588E-01 8 486E-01 8 004E-01 7 716E-01 7 644E-01 7 614E-01 7 767E-01 8 023E-01 8 434E-01 8 697E-01 9 O33E-01 9 25BE-01 9 3B2E-01 9 410E-01 9 433E-01 9 307E-01 9 180E-01 9 018E-01 8 835E-01 B 636E-01 8 3B3E-01 8 .131E-01 7.873E-01 7.615E-01  1.250E*00 X  . X X. X . X X X X . X X X X X X X . X X X . J .  *+  X •» X X -» X •» X $X X X X X X $• X X "  2.3O0E+0O X  $•  %m  * • . $ « • +. $ " * + $ • • .• $ * . +$ ' .* * • .$ • • .» + * .* • • $ + • * • • $. +  • •  t.  * .  * *  -  .  3.7S0E+00 5.0O0E*OO  3  Listing of -05L1 at 12:39:55 on APR 7. 1986 fop CCId-KCHU 179 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232  1 790E-08 1 8O0E-O8 1 850E-08 1 90OE-08 1 950E-08 2 OOOE-08 2 O50E-08 2 100E-08 2 150E-O8 2 2OOE-08 2 250E-O8 2 3O0E-O8 2 350E-08 3 400E-08 2 450E-08 2 5O0E-O8 2 550E-08 2 600E-08 2 650E-08 2 700E-08 2 750E-O8 2 800E-08 2 B50E-08 2 900E-08 2 950E-08 3 OOOE-08 3 0S0E-08 3 10OE-08 3 150E-08 3 200E-08 3 250E-08 3 3OOE-08 3 350E-08 3 4O0E-0B 3 450E-08 3 5O0E-O8 3 550E-08 3 600E-0B 3 650E-08 3 7O0E-O8 3.750E-08 3 BOOE-08 3 B50E-08 3 9OOE-08 3 950E-08 OOOE-08 4 4 050E-08 4 10OE-08 4 150E-08 4 2O0E-O8 4 250E-08 4 300E-08 4 350E-08 4 400E-OB 4 450E-08 4 500E-08 4 550E-0B 4 600E-08  7.356E-01 . 7.094E-01 . 6.834E-01 . 6 600E-01 . 6 366E-01 . 6 149E-01 . 5 941E-01 . 9 741E-01 . 9 S64E-01 . 9 388E-01 . 9 231E-01 . 9 O79E-01 . 4 937E-01 . 4 808E-01 . 4 679E-01 . 563E-01 . 4 4 427E-01 . . 4 297E-01 225E-01 . 4 4 196E-01 . 4 229E-01 . 4 348E-01 . 4 471E-01 . 4 780E-01 . 5 248E-01 . 9 B59E-01 . 6 601E-01 . 7 366E-01 . 8 203E-01 . 9 085E-O1 . 9 977E-01 . 1 090E+00 . 1 183E+00 . 1 277E*00 . 1 371E+00 . 1 464E+O0 . 1 554E+O0 . 1 644E400 . 1 728E+00 . 1 811E+00 . 1 868E+00 . 1 909E*0O . 1 950E+00 . 1 991E*00 . 2 033E+00 . 2 067E*00 . 2 099E400 . 2 130E+00 . 2 157E+00 . 2 184E+00 . 2 207E*O0 . 2 230E+00 . 2 25OE+0O . 2 269E+0O . 2 288E*00 . 2 305E*00 . 2 322E*00 . 2 337E*0O .  * $. • « . * $ . * * • * * $ • $ • * • $  Page •  + + +  • * • •  • •  • m  + + +  *• f$  m • • •  • $ • $ • $ • • • • • • * *  •  • »  • •  » * $ $ $ $ $ $  •  +.  • • $t * •  +  •  • »  4  $  • •  •  •  •  .X  •  •  •$  *  4  X  • •  t  • « 4  •  •  4  • • • • •• * * • ft • *  t  4  m  4  m  4  m .  •  • . m  4  •  4-  •  4  •  •  •  4  •  4  •  4-  •  4  •  .  .  «  •  "  •  4  •  •  S  • 4  4  •  4  $ . * $ . • *.•  *  ft ft • * • * ft ft ft ft • ft  t  %  $  $  .  f  $  f t  % % % % % %  $ $  *  Listing of -0SL1 at 12:39:59 on APR T. 1986 for CCId-KCHU 233 234 239 236 237 238 239 240 241 242 243 244 245 246 247 248 249 290 251 252 253 254 235 256 257 258 259 260 261 262 263 264 265 266 267  44 690E-08 700E-08 4 750E-08 4 800E-08 4 850E-0B 4 900E-08 4 950E-O8 3 O00E-O8 S 050E-08 5 100E-08 5 130E-08 5 2O0E-O8 5 250E-08 5.300E-08 5 350E-08 3 400E-08 3 450E-08 9 5O0E-O8 3 550E-O8 3 600E-08 5 650E-08 3 700E-08 3 750E-08 9 8O0E-O8 5 850E-O8 9 9O0E-08 5.950E-08 6 000E-08 Y 0 0  2 33BE*00 . 2 335E*00 . 2 273E«00 . 2 195E*00 . 2 055E+0O . 1 B85E«00 . 1 692E*00 . 1 543E*00 . 1 433E*00 . 1 368E+00 . 1 317E*00 . 1 289E*00 . 1 269E+00 . 1 254E*00 . 1 246E*00 . 1 238E*00 . 1 234E*O0 . 1 230E*OO . 1 218E*00 . 1 203E+00 . 1 182E*00 . 1 I45E*00 . 1 109E+00 . 1 064E*00 . 1 017E*00 . 9 714E-01 . 9 272E-01 . 8 830E-01 .  JOB CONCLUDED TOTAL JOB TIME  • •  Page  + • • * * • • • • • • • • • * • • . • + » . • • ». • * •  • •  •  X • • •.  • + +  • $ •  • *  • •  **  *  • . $• • . * * . $ • . $ •  .t t  0.0  + •  X. .  Listing of -CV4 at 22:05:31 on APR 9. 1986 for CC1d«KCHU 1 2 3 4 5 6 7  8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 23 26 27 28 29 30 31 32 33 34 33 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58  Page  1  1"««««»04-09-86 •••••»•* SPICE 2G.1 (150CT80) ••••••••22 :05: 19«"*« OSTATIC OCVS FULL ADDER (SUM CIRCUIT) <>••*•  INPUT LISTING  TEMPERATURE •  27.000 DEG C  Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  .OPTIONS ITL4-1000 ITL5«0 LIMPTS-300 • ML 1 7 8 1 1 P0EV2 L-3U W«9U AD-49.7P AS-46.4P * PD-32.4U PS-31.2U NRS«0.67 NRO'0.61 ML2 8 7 11 PDEV2 L-3U V"9U AD>49.7P AS-46.4P • PD-32.4U PS-31.2U NRS-0.67 NRD'0.61 • Ml 8 13 10 O NDEV2 L-3U W-12U AD-58.7P AS-58.7P • PD"38.4U PS-38.4U NRS«0.52 NRD'0.52 M2 7 13 9 0 N0EV2 L"3U W-12U AD-S8.7P AS-S8.7P • PD-38.4U PS"38.4U NRS»0.52 NRD«0.S2 M3 8 14 9 0 NDEV2 L-3U W>12U AD'58.7P AS-58.7P * PD-38.4U PS-38.4U NRS'0.52 NRD-0.52 M4 7 14 10 O N0EV2 L"3U W-12U AD-58.7P AS-58.7P + PD-38.4U PS-38.4U NRS".52 NRD-0.52 MS 10 15 12 O NDEV2 L-3U W«12U AD-58.7P AS-58.7P + P0-3B.4U PS'38.4U NRS"0 52 NRD..52 M6 9 15 11 O NDEV2 L-3U W-12U AD-58.7P AS"5B.7P • PD-38.4U PS-38.4U NRS'0.52 NR0..52 M7 10 16 11 O NDEV2 L-3U W-12U AD«58.7P AS"58.7P • P0-38.4U PS-38.4U NRS-.52 NRD-.52 MS 9 16 12 0 NDEV2 L'3U W-12U AD'58.7P AS-58.7P • PD-38.4U PS-38.4U NRS-.52 NRD',52 M9 11 17 O O N0EV2 L-3U W-12U A0-58.7P AS-9S.4P + PD-38.4U PS*37.2U NRS>0.52 NR0-.58 M10 12 18 0 O NDEV2 L-3U W-12U AD-S8.7P AS-55.4P • PD-3B.4U PS-37.2U NRS>0.52 NRD'0.58 CL1 7 O 60F CL2 8 O 60F •  VDD 1 0 DC 3 VA 13 O DC 3 VAN 14 O PWL(0 3 9NS 3 11NS 0) VB 13 0 DC 3 VBN 16 O PHL(0 3 9NS 5 11NS 0) VC 17 O PWL(0 3 34NS 5 36NS O) VCN 18 0 PWL(0 5 9NS 5 11NS O 34NS 0 36NS 3) • .MODEL P0EV2 PM0S(LEVEL-2 VTO'-O.B KP-5E-6 QAMMA-0.6 PHI-0.6 • LAMBDA-0.03 PB-0.6 CGS0-2.5E-1O CG00"2.5E-10 CGBO'S.E-10 + RSH-80 CU-1.5E-4 Md-0.6 CJSW-4.E-10 MJSW-0.6 JS«1.0E-5 + T0X-5.E-8 NSUB-5.E15 XJ-5.E-7 LD-2.5E-7 UO-250 + VMAX-0.7E5) .MOOEL NDEV2 NM0S(LEVEL-2 VT0-0.7 KP-16E-6 GAMMA"1.1 PHI-0.6 + LAM8DA=0.01 PB-0.7 CGS0"3.E-10 CGD0-3.E-1O CGB0«5.E-10 + RSH=25 CJ»4.4E-4 MJ-O.S CJSV-4.E-10 MdSW'0.3 JS"1.E-5 + T0X-5.E-8 NSUB-1.7E16 X0"6.E-7 LD-3.5E-7 UO-775 + VMAX'I.ES)  1 0  g c M J> |J. Q 3 ° rt 3" * m  rr 01 "* O 2  S MI  C £  01 Q. g* ™  — Ol °  Listing of -CV4 at 12:33:33 on APR 7, 1986 for CCId-KCHU 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 73 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 1 10 111 112 113 1 14 115 116  Page  .MODEL PDEV3 PMDSUEVEL-3 VTO—0.8 KP-5E-6 GAMMA"0.6 PHI-0.6 • PB-0.6 CGS0«2.5E-I0 CGO0-2.3E-1O CGBO-S.E-IO • RSH-80 Cd-I.SE-4 Md-0.6 C0SW-4.E-1O MdSW-0.6 JS-1.0E-5 • T0X-5.E-8 NSUB-5.E1S Xd-S.E-7 LD-2.SE-7 UO-250 • VMAX-0.7E3 THETA-0.13 KAPPA-1.0 ETA-0.3) .MODEL NDEV3 NM0S(LEVEL-3 VTO-0.7 KP-16E-6 GAMMA"1.1 PHI-0.6 • PB-0.7 CGS0-3.E-10 CGOO-3.E-10 CGB0-3.E-10 • RSH-2S CJ-4.4E-4 MJ-0.5 C.JSW-4.E-10 MJSW-0.3 JS-1.E-5 • T0X-5.E-B NSUB-1.7E16 XJ-6.E-7 LD-3.5E-7 UO-775 • VMAX-1.E5 THETA-0.11 KAPPA-1.0 ETA-0.05) « .WIDTH OUT"80 .IC V(7)-.4 V(8)-.4 • V(9)-.3 V(10)-.3 V(11)-.2 V(12)-.2 • V(1)-3 .TRAN .5N5 TONS UIC .PLOT TRAN V(7) V(8) (0,3) . END ..«*». 4-07-86 •••••••* SPICE 2G.1 (130CT80) •••••••»12:27:19-  1>  0  OCVSL 3-WAY EXCLUSIVE-OR WIDTH-12U  <)••••  MOSFET MODEL PARAMETERS  TEMPERATURE •  0»»««« NDEV3 NDEV2 PDEV3 PDEV2 NMOS NMOS PMOS OTYPE PMOS 3.000 OLEVEL 2.000 3.000 2.000 OVTO 0.700 -0.800 0. 700 -0.800 OKP 3.COE-06 1.60E-05 S.OOE-06 1.60E-05 OGAMMA 0.600 1 . 1O0 0.600 1. 100 OPHI 0.600 0.600 0.600 0.600 OLAMBDA 3.OOE-02 1.OOE-02 0.0 0.0 OPB 0.600 0.700 0.600 0.700 OCGSO 2.S0E-10 3.OOE-10 2.50E-10 3.OOE-10 OCGOO 2.50E-10 3.OOE-10 2.30E-10 3.OOE-10 OCGBO 5.OOE-10 5.OOE-10 3.OOE-10 5.OOE-10 ORSH 80.000 25.OOO 80.000 25.OOO OCJ 1.50E-04 4.40E-04 1.50E-04 4.40E-04 OMJ 0.600 0.600 O.SOO 0.500 OCJSW 4.OOE-10 4.OOE-10 4.OOE-10 4.OOE-10 OMJSW 0.600 0.600 0.300 0.300 OJS 1.OOE-05 1.OOE-05 1.OOE-05 1.OOE-05 OTOX 3.OOE-08 5. OOE-08 3.OOE-08 5. OOE-08 ONSUB 5.00E+15 1.70E*16 5.00E+15 1.70E*16 OX J 5. OOE-07 6.O0E-07 5.OOE-07 6. OOE-07 OLD 2.50E-07 3.50E-07 2.50E-07 3.50E-07 OUO 250. OOO 775.000 250.000 775.000 OVMAX 7.00E+04 1 .OOE+05 7.00E+04 1,O0E*O5 OTHETA 0.0 O. 130 O. 1 10 0.0 OETA 0.0 0.300 0.050 0.0 OKAPPA 0.200 1 .000 1 .000 0.200 ......."04-07-86 *•• SPICE 2G.1 (150CTB0) *  27.000 DEG C  Listing of -CV4 at 12:35:32 on APR 7. 1986 for CCId-KCHU 11? 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174  Page  3  OCVSL 3-MY EXCLUSIVE-OR WIDTH-12U 0**»»  TRANSIENT ANALYSIS  TEMPERATURE •  OLEQEND: • . V(7) V(8)  •:  X  TIME  xc*)  00  5 OOOE-IO 1 OOOE-09 1 5O0E-09 2 OOOE-09 3 500E-09 3 OOOE-09 3 500E-09 4 OOOE-09 4 500E-09 5 000E-09 5 500E-09 6 OOOE-09 6 500E-09 7 OOOE-09 7 S00E-O9 8 OOOE-09 8 500E-09 9 OOOE-09 9 SOOE-09 1 OOOE-08 1 050E-08 1 1O0E-O8 1 150E-O8 1 200E-08 1 250E-08 1 3O0E-O8 1 3S0E-O8 1 400E-08 1 450E-08 1 500E-08 1 550E-08 1 600E-08 1 650E-O8 1 700E-08 1 7S0E-08 1 800E-08 1 850E-08 1 900E-0B 1 9S0E-08 2 OOOE-08 2.050E-08  V(7)  0.0  1. 250E+00  7.118E-01 . X 1.278E+O0 . X 1 . 165E*00 . X. 1.044E+00 . X . 9.539E-01 . X 8.792E-01 . X 8.293E-01 . X 7.910E-01 . X 7.526E-01 . X 7.336E-01 . X 7.173E-01 . X 7.017E-01 . X 6.947E-01 . X 6.878E-01 . X 6.819E-01 . X 6.789E-01 . X 6.759E-01 . X 6.737E-01 . X 6.724E-01 . X 5.795E-01 . X 5.192E-01 . X 3.040E-01 . X 5.480E-01 . X 6.177E-01 . X 6.760E-01 . X * + 7.161E-01 . 7.390E-01 . • • . 7.619E-01 . • + 7.549E-01 . 7.442E-01 . • .+ 7.317E-01 . 7.002E-01 . » . 6.687E-01 . • 6.340E-01 . * 5.915E-01 . 5.490E-01 . * 5.057E-01 . 4.6I4E-01 . * 4.172E-01 . 3.7S9E-01 . 3.359E-01 . 2.95BE-01 . *  2 .500E+00  .  +  +  3.7SOE+00 S.OOOE+OO  •  +  +. + K)  Page  Listing of -CV4 at 12:38:32 on APR 7. 1986 for CCId'KCHU 179 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232  * 2 100E-08 2 623E-01 • 2 150E-08 2 296E-01 * 2 200E-08 1 976E-01 * 2 250E-08 1 726E-01 • 2.300E-08 1 475E-01 . * 2.350E-08 1 2S0E-01 2 400E-08 1 086E-01 . * 2 450E-O8 9 228E-02 . * 2.500E-08 7 8E9E-02 2 550E-08 6 798E-02 2 600E-08 5 T2TE-02 . * 2.650E-08 4 917E-02 . * 2 700E-08 4 224E-02 2.750E-08 3 531E-02 2 800E-08 3.056E-02 2 B50E-08 2 608E-02 2 900E-08 2 174E-02 2 950E-08 1 889E-02 3 OOOE-08 1 603E-02 3 050E-08 1 390E-O2 3 100E-08 1 177E-02 3 150E-0B 1 005E-02 3 200E-08 8 663E-03 3 250E-08 7 628E-03 3 300E-08 6 992E-03 3 350E-08 5 735E-03 3 400E-08 4 958E-03 3 450E-O8 8 55IE-03 3 SOOE-08 -2 011E-03 3 550E-08 -1 968E-02 3 600E-08 -4 117E-02 3 65OE-08 -6 266E-02 3 700E-08 -7 B57E-02 3 750E-OB -B 874E-02 3 800E-08 -9 356E-02 3 850E-08 -9 256E-02 3 900E-08 -8 339E-02 3 950E-08 -6 724E-02 4 OOOE-08 -4 877E-02 4 050E-08 -1 990E-02 4 100E-08 8 978E-03 * 4 150E-0B 4 284E-02 * 4 2O0E-08 8 046E-02 .« 4 250E-08 1 184E-OI . * 4 3OOE-08 1 652E-01 . * 4 350E-08 2 121E-01 * * 4 400E-08 2 638E-01 * 4 450E-08 3 205E-01 * 4 500E-08 3 771E-01 * 4 5S0E-08 4 414E-01 * 4 60OE-O8 5 090E-01 * 4 650E-08 5 767E-01 * 4 700E-0B 6 551E-01 • 4 750E-08 7 349E-01 4 800E-08 8 159E-01 4 B50E-O8 9 091E-01 4.900E-08 1.002E*00 4 950E-08 1.1OOE*0O  4  + +. . +  + + •  • •  +  + . •.  *.  •  •  + * + + + +  +  •  +  •. • , + . + •  + . + .• •  + * +, *+ .  <J1  L'lstlng of -CV4 at 12:35:32 on APR T, 1986 for CC1d-KCHU 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 231 252 233 254 255 256 257 258 259 260 261 262 263 264 363 266 267 268 269 270 271 272 273 274 273 276 277 278 279 280 281 282  B OOOE-08 5 050E-08 3 tOOE-08 3 150E-08 3 200E-08 3 250E-08 3 300E-08 3 350E-08 3 400E-08 3 450E-08 3 500E-08 3 550E-08 5 600E-08 3 650E-08 3 7O0E-O8 5 750E-08 5 80OE-08 3 850E-0B 3 900E-08 3 950E-08 6 OOOE-08 6 050E-08 6 1O0E-08 6 150E-08 6 200E-08 6 250E-08 6 300E-OB 6 350E-0B 6 4O0E-08 6 450E-08 6 SOOE-08 6 550E-0B 6 600E-08 6 650E-08 6 700E-08 6 750E-08 6 BOOE-08 6 B50E-08 6 900E-08 6 950E-08 7 OOOE-08 V O 0 O  1 208E+00 1 317E+00 1 434E*O0 * 1 S59E+00 1 685E+00 + 1 825E+00 • 1 972E+O0 2 118E+00 + 2 282E+00 + 2 449E*0O + 2 616E+00 • 2 795E+00 • 2 974E+00 3 152E+00 • 3 327E+00 • 3 502E+00 3 676E+00 3 847E+00 . • 4 018E+00 4 155E+00 . • 4 276E+00 .+ 4 397E+00 .* 4 4B0E+00 .+ 4 559E+00 . + 4 635E+00 .+ 4 682E+00 .• 4 729E+00 4 770E+00 + 4 797E+00 + 4 B25E+00 + 4 B47E+00 + 4 864E+00 * 4 881E+00 + 4 893E+00 + 4 9O3E+0O • 4 913E+O0 + 4 920E+00 • 4 927E+00 • 4 934E+00 • 4 939E+00 + 4 944E+00 +  JOB CONCLUDED TOTAL JOB TIME JOB CONCLUDED TOTAL JOB TIME  Page  • *  • • •  •  •  •  •  •  •  •  *  •  *  * • * *  • • •  .  0.0 0.0  155  01  o  a.  S i m u l a t i o n o f t h e domino DCVS f u l l  (c  m n  Oi  anD.nD.ifio.vi  d  3 *9  •  • N O O IP U> n < N I D • o or 3 O < Z  •  O  • O  • <p • D I fl0 ) _ _ . O n n a u a » O Z O Z D tt D • O 3 3 Z < p> a in *» to t > -9 3 •» 3 to „ 2 ^ .,- , • i O *  •zo  <M  N tp I D <  o • aZ  0 ) •> *» I O or • H O I Z o z <:  3 w :  CM * (P * 3 • :_ n O n o n Z n z n z n z n z n z • « • • • • » • • » -i 3 JWJifl J CM D JCM 3 J DC JM DJ3J3 N : CM  >  u.  3  »  ft  z  CM  > o >  c  iono • o i  J CM U J  > • O . to a•  a o o  o  in z in  tP • V  CM ">  *b  • 3 « ) m pj in ) a i oc Z -J 2 : CM C - >  U J "•or) i rs Q m 2 •* Z u>; I H Z - ") a. a  O 3 • •» in •» |p - 4 o * • » CM * » CD CM I - CM CM • » C M • » P ) t P * » ( P C O C M P - C M C M f M CMOl^r (P ( 0 ^ •9 CM CM P J p> co <p m »- •» l e o R r i n v n i t n * • • n i t i to i s O O O O O O O Q O ••- a CM o. P I a •» a.ina.tpar-aeoaoia*-D.*-o.  o •* 8  -m>  I  16  •*i  CM  o  adder  ,=°=  • in pC D • • tn o oo m H in i in i i o o O D • D • O O • <D D t < a o tr o or < o a < c 2 < z < z a 3 z ; CM 3 3 Z CM CM * CM CM 3 c I CM »- m CM u cn •  * 6 • < • * i 3 tn i n o : ? ! • Z D .  CO CM  inmin > in w • D O M  « Q • < O D < O or or a 3 Z Z 3 Z CM « IT  CM **• CM  <  II  Q a CM Z  3  CM II  CM  it in > m  i in x O3O 6* »• * a • 3 II CO II • 3 m 3 tn P I tn n tn tn co  i  « 3 3 trt CO tn 3 t n a i or co a n a » a -J I i 2 - J 2 • 2a -«J Z t Z J Z -J • R -J 3 -I 3 - J 3 3 CM T J CM ' P i •» •» • » CM - 0 > > • CM • > • CM • > * UJ ui C O > CD > co U J a> CO U J I 1 CO U J CO o p n U J n u n o n z P) Q C • • a • 2 « ^ Z i in z in tn o : co n o. co o. a O a o a * 2 u o O CM > tn mo 3 3 3 O 3 03 a O a • 9 CO ro •» •»  1 »- * "  nconco^eD*«eo'--cointxi*-s(Pco<-co  a> o o  1  a z  a  z  Q  * 0>  • ^ • C O ^ P J ^ C O ^ C O  cn  P  J  ^  P  )  n ^ p i  I • • • O • • O • O D N O » O N D * - 0 0 ) 0 - D O ) o, a a D . o. a. a • ^ c M n - « t n i p t » - » m  a u. u.  oo  3 m in  co CM P J  •. •»- n • CO »r 0 ' - Q . O a a. o o. *- n ' - - i - J  Page  Listing of -D0CVS4 at 12:36:17 on APR 7, 1986 for CCId-KCHU 99 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 g 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 1 12 113 114 1 15 116  VDO 1 0 DC 9 VCLK 2 0 PWL(0 0 14NS O 16NS 5 29NS 5 3INS 0 44NS 0 46N5 5) VA 13 O DC 9 VAN 14 0 DC 0 VB 19 O DC 9 VBN 16 0 DC 0 VC 17 O PWL(0 9 42NS 9 44NS O) VCN 18 O PWL(0 0 42NS O 44NS 5) • .MODEL PDEV2 PM0S(LEVEL-2 VT0»-0.8 KP-5E-6 GAMMA-0.6 PHI-0.6 • LAMBDA-0.03 PB-0.6 CGS0-2.5E-10 CGD0-2.5E-10 CGB0-5.E-1O • RSH-80 CJ-1.5E-4 MJ-0.6 CJSW-4.E-10 MJSW-0.6 JS-1.0E-5 • T0X-9.E-8 NSUB-9.E19 XJ-9.E-7 LD"2.5E-7 U0-25O • VMAX-0.7E3) .MODEL NDEV2 NMOSUEVEL-2 VTO-0.7 KP>16E-6 GAMMA"1.1 PHI-0.6 • LAMBDA'0.01 PB-0.7 CGS0-3.E-1O CGD0-3.E-10 CGB0-5.E-10 • RSH-25 CJ-4.4E-4 MJ-0.5 CJSW-4.E-10 MJSW-0.3 JS-1.E-5 • T0X-5.E-B NSUB-1.7E16 XJ-6.E-7 LD-3.5E-7 U0-775 * VMAX-1.E5) .MODEL PDEV3 PM0S(LEVEL-3 VT0--0.8 KP-5E-6 GAMMA"0.6 PHI-0.6 • PB-0.6 CGS0-2.5E-1O CG00-2.3E-1O CGB0-5.E-10 • RSH-80 Cd-1.SE-4 Md-0.6 CdSW-4.E-10 MJSW-0.6 JS-1.0E.-5 • T0X-5.E-8 NSUB-5.E13 XJ-5.E-7 LD-2.5E-7 U0-250 • VMAX-0.7E9 THETA-O.13 KAPPA-1.0 ETA-0.3) .MODEL NDEV3 NM0S(LEVEL«3 VTO-0.7 KP-16E-6 GAMMA-1.1 PHI-0.6 + PB-0.7 CGS0-3.E-10 CGD0-3.E-10 CGB0-5.E-10 • RSH-25 CJ-4.4E-4 MJ-O.S CJSW-4.E-10 MJSW-0.3 JS-1.E-5 * T0X-5.E-B NSUB-1.7E16 XJ-6.E-7 L0-3.5E-7 U0-775 • VMAX-1.E5 THETA-O. 11 KAPPA-1.0 ETA-0.05) • .WIDTH OUT-80 .IC V(4)-.2 V(3)-4.9 V(6)-.1 V(9)-4.8 V(7)-.4 V(8)-.4 • V(9)«.3 V(10)-.3 V(11)-.2 V(12)-.2 * V(19)-.1 V(1)-9 V(2)-0 .TRAN .9NS 60NS UIC .PLOT TRAN V(4) V(3) V(7) V(8) V(2) (0.9) .END . . . . . . . . 0 4 . 0 7 8 5 ........ SPICE 2G.1 (1S0CT80) ••••••••12:30:52***««  G  ODOMINO CVSL 3-WAY EXCLUSIVE-OR WIDTH.12U <»••••  MOSPET MODEL PARAMETERS  TEMPERATURE •  »......«».»...  0  OTYPE OLEVEL OVTO OKP OGAMMA OPHI OLAMBDA OPB OCGSO  PDEV2 NDEV2 PDEV3 NDEV3 PMOS NMOS PMOS NMOS 2.000 2.000 3.000 3.000 -0.800 0.700 -0.800 0.700 5 :00E-06 1.60E-05 5 00E-O6 1.60E-05 0.600 1 . 1O0 0.6OO 1. 100 0.600 0.600 0.60O 0.600 3.OOE-02 1.OOE-02 0..0 0.0 0.600 0.700 0.600 0.700 2.50E-10 3.00E-10 2.50E-10 3.00E-10  27.000 DEO C  2  Listing of -D0CV54 at 12:36:17 on APR 7, 1966 for CCId-KCHU 117 118 119 120 121 122 123 124 12S 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 133 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174  OCGDO OCGBO ORSH OCJ OMJ OCJSW OMJSW OJS OTOX ONSUB OXJ OLD OUO OVMAX OTHETA OETA OKAPPA OOONINO  2 50E-10 3 OOE-10 3 OOE-IO 5 OOE-10 80.000 25.000 1 50E-04 4 40E-04 0.600 0.500 4 OOE-IO 4 OOE-10 0.600 0.300 1 00E-05 1 00E-05 5 OOE-08 3 OOE-08 5 00E+15 1 70E+16 5 OOE-07 6 OOE-07 2 50E-07 3 SOE-07 250.000 775.OOO 7 OOE+04 1.OOE+05 0.0 0.0 0.0 0.0 0.200 0.200  2.50E-10 5.OOE-10 80.000 1.50E-04 0.600 4.OOE-10 0.600 1.00E-05 5.OOE-08 5.00E+15 5.OOE-07 2.50E-07 250.OOO 7.00E+04 0.130 0.300 1.000  Page  3.OOE-10 5.OOE-10 25.000 4.40E-04 0.500 4.OOE-10 0.300 1.00E-05 5.OOE-08 1.70E+16 6.OOE-07 3.50E-07 775.000 1.00E+05 0.110 0.050 1.000  12:30:S2*****  CVSL 3-WAY EXCLUSIVE-OR WIDTH*12U  0**>*  TRANSIENT ANALYSIS  TEMPERATURE •  27.000 DEG C  OLEGEND: • +; •; *: 0: X :  V(4) V(3) V(7) V(8) V(2) TIME  V(4)  X(»*-$0) 00 3 000E-10 1 OOOE-09 1 50OE-O9 2 OOOE-09 2 300E-09 3 OOOE-09 3 SO0E-O9 4 OOOE-09 4 S00E-09 S OOOE-09 3 500E-09 6 OOOE-09 6 500E-09 7 OOOE-09 7 500E-09 8 OOOE-09 8 500E -09 9 O0OE-O9 9 5O0E-O9  1.250E+O0 2.034E-01 0 • 7.532E-01 0 1 .061E+0O0 1.245E+00 0 1.336E+00 0 1.4O2E+0O 0 1.442E+0O 0 1.465E+O0 0 1.480E+00 0 1.492E+00 0 1 .504E+000 1.515E+00 0 1 .525E+000 1.S35E+00 0 1 .540E+OO0 1.545E+00 0 1.549E+00 0 1.552E+00 0 1.555E+00 0 1.5S7E+CO 0  $•  •  2.300E*00  . * • . $ • $ • .$ . • * *  • •  * * * * * *  •  *  •  *  3.730E+00 5.OOOE+00 •  • $ •  $ •  '. t  •  .* •  $-  X  X X X «$ X •* . -$ . X . -$.  3  Pags  Listing of -D0CVS4 at 12:36:17 on *PR 7, 1986 fop CC1d-KCHU 173 176 177 178 179 180 181 182 183 184 183 186 187 188 189 190 191 192 193 194 199 196 197 198 199 200 201 202 203 204 209 206 207 208 209 210 211 212 213 214 213 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232  1. OOOE-08 1.05OE-O8 1 1OOE-08 1 150E-08 1 200E-08 1 250E-08 1.300E-08 1 350E-08 1 40OE-O8 1 450E-08 1 S00E-08 1 350E-08 1 600E-08 1 650E-08 1 700E-08 1 750E-08 1.800E-08 1 850E-08 1 900E-08 1 950E-08 2 OOOE-08 2 050E-O8 2 100E-08 2 150E-08 2 200E-08 2 250E-08 2 3O0E-O8 2 350E-08 2 400E-08 2 450E-08 2 5O0E-08 2 550E-0B 2 600E-08 2 650E-08 2 7O0E-O8 2 750E-08 2 BOOE-08 2 850E-08 2 900E-08 2 950E-08 3 OOOE-08 3.050E-08 3 100E-08 3 150E-08 3 2O0E-O8 3 250E-08 3 300E-08 3 350E-08 3 4O0E-08 3 450E-08 3 5O0E-08 3 550E-08 3 600E-08 3 650E-08 3 700E-0B 3 750E-08 3 SOOE -08 3.850E-08  • 1 3S9E+00 0 • 1 561E+00 0 • 1 S62E+00 0 * 1 564E+0O 0 • 1 965E+00 0 • 1 566E+O0 0 * 1 567E+00 0 * 1 567E+00 0 * 1 568E+00 0 1 575E+00 0 * 1 568E+00 * * 1 471E+O0 1 271E*00 • 9 98OE-01 • 7 606E-01 • 9 701E-01 • 4 259E-01 * 3 205E-01 2 777E-01 * + 2 610E-01 * . • 3 311E-01 4 244E-01 • + . • 5 856E-01 7 862E-01 X • * . » 1 071E+00 1 413E+00 + .• • 1 807E+00 • -. * 2 260E+00 2 711E+00 • • 3 125E+00 3 539E+00 a 3 864E+00 .+ • 4 143E+00 .+ 4 383E+00 .+ 4 510E+00 . + • 4 636E+0O • • 4 728E+O0 • 4 813E-KXJ • m 4 B81E+00 • 4 913E+O0 + a 4 942E+00 • a 4 973E+O0 + • 0 a 5 0O7E+O0 X a 5 030E+00 X .a 5 034E+00 X a 5 02BE+00 X a 5 021E+00 X a 5 012E+00 X 5 001E+00 X 4 990E+00 X 4 980E+00 X 4 970E+00 X 4 960E+00 X 4 949E+00 X 4 937E*00 X 4 920E+00 X 4 902E+O0 X 4 883E+O0 X  •t. •*.  •*. X. X. X. X. X. X. «$  0  •  •  •  • « .  *  .  •  .  •  • . .•  0  r  •  • .  •  0 • "X • $0 10  $t o 0 $ 0 $ 0 * 0 * 0 t 0 S 0 S 0 * 0 % 0 » 0  t  o t o t o t o • t o • t o •to •tX 0 0 t« 0 t*0 t •. t *. t • t * t * t • t* t«X X X X X X  •t •t •t •t •t  4  l i s t i n g of -D0CVS4 at 12:36:17 on APR 7. (966 for CCId-KCHU 233 234 233 236 237 238 239 240 241 242 243 244 243 246 247 248 249 230 251 232 253 254 255 256 257 258 259 260 261 262 263 264 263 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282  3 9 OOE-08 3 950E-08 4 OOOE-08 4 0S0E-08 4 1O0E-08 4 150E-08 4 2 OOE-08 4 250E-08 4 300E-08 4 350E-08 4 400E-08 4 450E-08 4 500E-08 4 550E-08 4 600E-08 4 650E-08 4 7O0E-08 4 750E-08 4 8OOE-08 4 850E-08 4 900E-08 4 950E-08 3 OOOE-08 3 O50E-O8 5 10OE-08 3 150E-08 3 2 OOE-08 3 250E-08 3 300E-08 3 350E-08 3 4O0E-08 5 450E-08 5 5O0E-08 5 550E-08 3 6OOE-08 9 650E-OB 3 7O0E-O8 3 750E-O8 3 800E-08 3 850E-08 5 9O0E-O8 3 950E-08 6 OOOE-08 Y 0 0  Paga  3  4 863E+00 X • • % m • % 4 B43E+0O X 4 829E+00 X • * $ 4 815E+O0 X •+ t 4 804E+O0 X 4 794E+00 X •• • 4 785E+00 X X $ 4 77BE+00 X X % 4 772E+00 X 4 766E+00 X 4 761E+00 X 4 761E+00 • 0 4 747E+00 * 0 4 662E+00 * () * •. 4 416E+00 . • • »0 3 B95E+00 • . 0 3 539E+0O • 0 • 3 089E+00 • »0 • 2 652E+00 X 0 2 232E+00 * • o 1 841E+O0 • t • 0 * 1 317E+00 • 0 . • * 1 223E+O0 • 0 • t 9 844E-01 .• 0 • . $ 7 937E-01 . • 0 • . *. 6 341E-01 0 • • * 4 885E-01 0 3 959E-01 • 0 • + . • 3 034E-01 • 0 • •. « 2 434E-01 • .X • 0 1 912E-01 . * 0 * • 1 503E-01 . * • 0 t. +. .+ 1 212E-01 .* • 0 * . 9 334E-02 .• 0 $ . . • 7 73BE-02 .• 0 * • 6 I42E-02 • + • 0 $ S 022E-02 • > o 4 117E-02 • + • 0 s 3 319E-02 * •• 0 % t 2 7B4E-02 X 0 2 248E-02 • X 0 $ 1 909E-02 « $ 0 1 594E-02 • » " +0  JOB CONCLUDED TOTAL JOB TIME  0.0  10  160  A p p e n d i x B : SPICE o u t p u t s f o r s i m u l a t i o n s of m u l t i p l i e r  In cells  this  appendix,  are presented.  some o u t p u t w a v e f o r m s o f t h e m u l t i p l i e r  The  SPICE  Metheus  workstation.  The  obtained  through  layout  parameters the  the  cells  input  simulations listings  extractor.  are  run  on  the  of the programs a r e The  level  2  MOSFET  o f t h e N o r t h e r n T e l e c o m 3um CMOS p r o c e s s a r e u s e d i n  simulations.  Output waveforms o f a r e c o d e r  CIRCUIT: RECOO  DATE: TUE APR  8 0B:13:28 1986 ( F i l e : recod)  TIME  GROUP 1 : V(subn) V(_sub)_ . V( xn2 )  V(x2)  V(xnl)  V U U _ V m kl_) V(bml)  162  Output waveforms o f a m u l t i p l e x e r  CIRCUIT: HUXR  DflTt: lilt APR  5.24-  6 25:51:30 19Hb ( F i l e : muxa)  1  4.71-  ^  \  / /  /  \ \ \ \  4.173.64-  i i i  \  3.11-  ; \  2.57-  i \ \ \ \ \  2.04-  i i i i i  \ i \ i \ >  1.510.97-  / \ /  R 41  0 1  0~0n  '  5.0n  GROUP 1: VCppl)  10.0n  15.00  V(ppnl) V ( C l k l )  20.0n V(lx)  25.0n  30 0n  35.00  \  40.'0n  45.0n  50.0n TIME  163  Output waveforms o f a c a r r y  CIRCUIT: CL5  DRTE: UED RPR  9 00:48:59 1986 ( r i l e :  look-ahead  cell  ct5)  TIME GROUP 1: V(c?)  V(_cn2)_ VCClkl) V ( w l ) C  164  Output waveforms o f a f u l l  CIRCUIT: FA DATE: SftT APR 5 21:35:16  1586 ( f i l e :  adder  FA)  TIME GROUP 1 : VCcar)  V(_cBrn) V(suw)  V(sumn) VCClki) V(_c)  165  Output waveforms of a h a l f  CIRCUIT: HH  adder  UHTt: HON FEB IP 23:51:10 1986 ( F i l e : HFD  TIME  GROUP 1: V( car ) V(_cBrn_) V(sum) V( sumn ) V(Clkl ) V( b )  \  166  O u t p u t w a v e f o r m o f an i n p u t d r i v e r  CIRCUIT: INLflT  DATE: SRT JHN 25 20:38:21 1985 ( F i l e :  cell  inlet)  TIME  GROUP 1: V( tnp) V(_ouO V ( n l )  V(n2)  V(Clk)  167  Output waveform of an o u t p u t d r i v e r  CIRCUIT: DUTDR  DRTb: HON FEB 17 21:50:11 19B6 ( F i l e :  cell  outdr)  TIME  GROUP 1: V( inp) V(_out_) V ( n l )  V(Clk)  168  O u t p u t w a v e f o r m o f an o u t p u t  pad  169  Appendix C : Layouts  In shown.  this  o f some m a j o r c e l l s  appendix,  t h e l a y o u t s o f some i m p o r t a n t  The d e s i g n r u l e s u s e d a r e t h o s e  3um  CMOS p r o c e s s . The f o l l o w i n g  all  the layouts:  Metal  Contact c u t  of the m u l t i p l i e r  layer  P-well  cells  f o r the Northern  are  Telecom  r e p r e s e n t a t i o n i s used  in  170  Layout of a recoder  cell  171  L a y o u t of a m u l t i p l e x e r  cell  172  Layout of a c a r r y  look-ahead  cell  173  Layout of a f u l l  adder  174  Layout of a h a l f  adder  175  L a y o u t o f an i n p u t d r i v e r  cell  177  L a y o u t o f an o u t p u t  pad  178  L a y o u t o f an i n p u t  pad  

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